1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 #include "dc_dmub_srv.h" 53 #include "dce/dmub_hw_lock_mgr.h" 54 #include "hw_sequencer.h" 55 #include "inc/link_dpcd.h" 56 #include "dpcd_defs.h" 57 #include "inc/link_enc_cfg.h" 58 #include "link_hwss.h" 59 60 #define DC_LOGGER_INIT(logger) 61 62 #define CTX \ 63 hws->ctx 64 #define REG(reg)\ 65 hws->regs->reg 66 67 #undef FN 68 #define FN(reg_name, field_name) \ 69 hws->shifts->field_name, hws->masks->field_name 70 71 static int find_free_gsl_group(const struct dc *dc) 72 { 73 if (dc->res_pool->gsl_groups.gsl_0 == 0) 74 return 1; 75 if (dc->res_pool->gsl_groups.gsl_1 == 0) 76 return 2; 77 if (dc->res_pool->gsl_groups.gsl_2 == 0) 78 return 3; 79 80 return 0; 81 } 82 83 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 84 * This is only used to lock pipes in pipe splitting case with immediate flip 85 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 86 * so we get tearing with freesync since we cannot flip multiple pipes 87 * atomically. 88 * We use GSL for this: 89 * - immediate flip: find first available GSL group if not already assigned 90 * program gsl with that group, set current OTG as master 91 * and always us 0x4 = AND of flip_ready from all pipes 92 * - vsync flip: disable GSL if used 93 * 94 * Groups in stream_res are stored as +1 from HW registers, i.e. 95 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 96 * Using a magic value like -1 would require tracking all inits/resets 97 */ 98 static void dcn20_setup_gsl_group_as_lock( 99 const struct dc *dc, 100 struct pipe_ctx *pipe_ctx, 101 bool enable) 102 { 103 struct gsl_params gsl; 104 int group_idx; 105 106 memset(&gsl, 0, sizeof(struct gsl_params)); 107 108 if (enable) { 109 /* return if group already assigned since GSL was set up 110 * for vsync flip, we would unassign so it can't be "left over" 111 */ 112 if (pipe_ctx->stream_res.gsl_group > 0) 113 return; 114 115 group_idx = find_free_gsl_group(dc); 116 ASSERT(group_idx != 0); 117 pipe_ctx->stream_res.gsl_group = group_idx; 118 119 /* set gsl group reg field and mark resource used */ 120 switch (group_idx) { 121 case 1: 122 gsl.gsl0_en = 1; 123 dc->res_pool->gsl_groups.gsl_0 = 1; 124 break; 125 case 2: 126 gsl.gsl1_en = 1; 127 dc->res_pool->gsl_groups.gsl_1 = 1; 128 break; 129 case 3: 130 gsl.gsl2_en = 1; 131 dc->res_pool->gsl_groups.gsl_2 = 1; 132 break; 133 default: 134 BREAK_TO_DEBUGGER(); 135 return; // invalid case 136 } 137 gsl.gsl_master_en = 1; 138 } else { 139 group_idx = pipe_ctx->stream_res.gsl_group; 140 if (group_idx == 0) 141 return; // if not in use, just return 142 143 pipe_ctx->stream_res.gsl_group = 0; 144 145 /* unset gsl group reg field and mark resource free */ 146 switch (group_idx) { 147 case 1: 148 gsl.gsl0_en = 0; 149 dc->res_pool->gsl_groups.gsl_0 = 0; 150 break; 151 case 2: 152 gsl.gsl1_en = 0; 153 dc->res_pool->gsl_groups.gsl_1 = 0; 154 break; 155 case 3: 156 gsl.gsl2_en = 0; 157 dc->res_pool->gsl_groups.gsl_2 = 0; 158 break; 159 default: 160 BREAK_TO_DEBUGGER(); 161 return; 162 } 163 gsl.gsl_master_en = 0; 164 } 165 166 /* at this point we want to program whether it's to enable or disable */ 167 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 169 pipe_ctx->stream_res.tg->funcs->set_gsl( 170 pipe_ctx->stream_res.tg, 171 &gsl); 172 173 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 174 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 175 } else 176 BREAK_TO_DEBUGGER(); 177 } 178 179 void dcn20_set_flip_control_gsl( 180 struct pipe_ctx *pipe_ctx, 181 bool flip_immediate) 182 { 183 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 185 pipe_ctx->plane_res.hubp, flip_immediate); 186 187 } 188 189 void dcn20_enable_power_gating_plane( 190 struct dce_hwseq *hws, 191 bool enable) 192 { 193 bool force_on = true; /* disable power gating */ 194 195 if (enable) 196 force_on = false; 197 198 /* DCHUBP0/1/2/3/4/5 */ 199 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 200 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 201 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 202 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 203 if (REG(DOMAIN8_PG_CONFIG)) 204 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 205 if (REG(DOMAIN10_PG_CONFIG)) 206 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 207 208 /* DPP0/1/2/3/4/5 */ 209 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 210 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 211 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 212 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 213 if (REG(DOMAIN9_PG_CONFIG)) 214 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 215 if (REG(DOMAIN11_PG_CONFIG)) 216 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 217 218 /* DCS0/1/2/3/4/5 */ 219 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 220 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 221 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 222 if (REG(DOMAIN19_PG_CONFIG)) 223 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 224 if (REG(DOMAIN20_PG_CONFIG)) 225 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 226 if (REG(DOMAIN21_PG_CONFIG)) 227 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 228 } 229 230 void dcn20_dccg_init(struct dce_hwseq *hws) 231 { 232 /* 233 * set MICROSECOND_TIME_BASE_DIV 234 * 100Mhz refclk -> 0x120264 235 * 27Mhz refclk -> 0x12021b 236 * 48Mhz refclk -> 0x120230 237 * 238 */ 239 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 240 241 /* 242 * set MILLISECOND_TIME_BASE_DIV 243 * 100Mhz refclk -> 0x1186a0 244 * 27Mhz refclk -> 0x106978 245 * 48Mhz refclk -> 0x10bb80 246 * 247 */ 248 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 249 250 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 251 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 252 } 253 254 void dcn20_disable_vga( 255 struct dce_hwseq *hws) 256 { 257 REG_WRITE(D1VGA_CONTROL, 0); 258 REG_WRITE(D2VGA_CONTROL, 0); 259 REG_WRITE(D3VGA_CONTROL, 0); 260 REG_WRITE(D4VGA_CONTROL, 0); 261 REG_WRITE(D5VGA_CONTROL, 0); 262 REG_WRITE(D6VGA_CONTROL, 0); 263 } 264 265 void dcn20_program_triple_buffer( 266 const struct dc *dc, 267 struct pipe_ctx *pipe_ctx, 268 bool enable_triple_buffer) 269 { 270 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 271 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 272 pipe_ctx->plane_res.hubp, 273 enable_triple_buffer); 274 } 275 } 276 277 /* Blank pixel data during initialization */ 278 void dcn20_init_blank( 279 struct dc *dc, 280 struct timing_generator *tg) 281 { 282 struct dce_hwseq *hws = dc->hwseq; 283 enum dc_color_space color_space; 284 struct tg_color black_color = {0}; 285 struct output_pixel_processor *opp = NULL; 286 struct output_pixel_processor *bottom_opp = NULL; 287 uint32_t num_opps, opp_id_src0, opp_id_src1; 288 uint32_t otg_active_width, otg_active_height; 289 290 /* program opp dpg blank color */ 291 color_space = COLOR_SPACE_SRGB; 292 color_space_to_black_color(dc, color_space, &black_color); 293 294 /* get the OTG active size */ 295 tg->funcs->get_otg_active_size(tg, 296 &otg_active_width, 297 &otg_active_height); 298 299 /* get the OPTC source */ 300 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 301 302 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 303 ASSERT(false); 304 return; 305 } 306 opp = dc->res_pool->opps[opp_id_src0]; 307 308 if (num_opps == 2) { 309 otg_active_width = otg_active_width / 2; 310 311 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 312 ASSERT(false); 313 return; 314 } 315 bottom_opp = dc->res_pool->opps[opp_id_src1]; 316 } 317 318 opp->funcs->opp_set_disp_pattern_generator( 319 opp, 320 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 321 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 322 COLOR_DEPTH_UNDEFINED, 323 &black_color, 324 otg_active_width, 325 otg_active_height, 326 0); 327 328 if (num_opps == 2) { 329 bottom_opp->funcs->opp_set_disp_pattern_generator( 330 bottom_opp, 331 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 332 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 333 COLOR_DEPTH_UNDEFINED, 334 &black_color, 335 otg_active_width, 336 otg_active_height, 337 0); 338 } 339 340 hws->funcs.wait_for_blank_complete(opp); 341 } 342 343 void dcn20_dsc_pg_control( 344 struct dce_hwseq *hws, 345 unsigned int dsc_inst, 346 bool power_on) 347 { 348 uint32_t power_gate = power_on ? 0 : 1; 349 uint32_t pwr_status = power_on ? 0 : 2; 350 uint32_t org_ip_request_cntl = 0; 351 352 if (hws->ctx->dc->debug.disable_dsc_power_gate) 353 return; 354 355 if (REG(DOMAIN16_PG_CONFIG) == 0) 356 return; 357 358 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 359 if (org_ip_request_cntl == 0) 360 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 361 362 switch (dsc_inst) { 363 case 0: /* DSC0 */ 364 REG_UPDATE(DOMAIN16_PG_CONFIG, 365 DOMAIN16_POWER_GATE, power_gate); 366 367 REG_WAIT(DOMAIN16_PG_STATUS, 368 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 369 1, 1000); 370 break; 371 case 1: /* DSC1 */ 372 REG_UPDATE(DOMAIN17_PG_CONFIG, 373 DOMAIN17_POWER_GATE, power_gate); 374 375 REG_WAIT(DOMAIN17_PG_STATUS, 376 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 377 1, 1000); 378 break; 379 case 2: /* DSC2 */ 380 REG_UPDATE(DOMAIN18_PG_CONFIG, 381 DOMAIN18_POWER_GATE, power_gate); 382 383 REG_WAIT(DOMAIN18_PG_STATUS, 384 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 385 1, 1000); 386 break; 387 case 3: /* DSC3 */ 388 REG_UPDATE(DOMAIN19_PG_CONFIG, 389 DOMAIN19_POWER_GATE, power_gate); 390 391 REG_WAIT(DOMAIN19_PG_STATUS, 392 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 393 1, 1000); 394 break; 395 case 4: /* DSC4 */ 396 REG_UPDATE(DOMAIN20_PG_CONFIG, 397 DOMAIN20_POWER_GATE, power_gate); 398 399 REG_WAIT(DOMAIN20_PG_STATUS, 400 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 401 1, 1000); 402 break; 403 case 5: /* DSC5 */ 404 REG_UPDATE(DOMAIN21_PG_CONFIG, 405 DOMAIN21_POWER_GATE, power_gate); 406 407 REG_WAIT(DOMAIN21_PG_STATUS, 408 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 409 1, 1000); 410 break; 411 default: 412 BREAK_TO_DEBUGGER(); 413 break; 414 } 415 416 if (org_ip_request_cntl == 0) 417 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 418 } 419 420 void dcn20_dpp_pg_control( 421 struct dce_hwseq *hws, 422 unsigned int dpp_inst, 423 bool power_on) 424 { 425 uint32_t power_gate = power_on ? 0 : 1; 426 uint32_t pwr_status = power_on ? 0 : 2; 427 428 if (hws->ctx->dc->debug.disable_dpp_power_gate) 429 return; 430 if (REG(DOMAIN1_PG_CONFIG) == 0) 431 return; 432 433 switch (dpp_inst) { 434 case 0: /* DPP0 */ 435 REG_UPDATE(DOMAIN1_PG_CONFIG, 436 DOMAIN1_POWER_GATE, power_gate); 437 438 REG_WAIT(DOMAIN1_PG_STATUS, 439 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 440 1, 1000); 441 break; 442 case 1: /* DPP1 */ 443 REG_UPDATE(DOMAIN3_PG_CONFIG, 444 DOMAIN3_POWER_GATE, power_gate); 445 446 REG_WAIT(DOMAIN3_PG_STATUS, 447 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 448 1, 1000); 449 break; 450 case 2: /* DPP2 */ 451 REG_UPDATE(DOMAIN5_PG_CONFIG, 452 DOMAIN5_POWER_GATE, power_gate); 453 454 REG_WAIT(DOMAIN5_PG_STATUS, 455 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 456 1, 1000); 457 break; 458 case 3: /* DPP3 */ 459 REG_UPDATE(DOMAIN7_PG_CONFIG, 460 DOMAIN7_POWER_GATE, power_gate); 461 462 REG_WAIT(DOMAIN7_PG_STATUS, 463 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 464 1, 1000); 465 break; 466 case 4: /* DPP4 */ 467 REG_UPDATE(DOMAIN9_PG_CONFIG, 468 DOMAIN9_POWER_GATE, power_gate); 469 470 REG_WAIT(DOMAIN9_PG_STATUS, 471 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 472 1, 1000); 473 break; 474 case 5: /* DPP5 */ 475 /* 476 * Do not power gate DPP5, should be left at HW default, power on permanently. 477 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 478 * reset. 479 * REG_UPDATE(DOMAIN11_PG_CONFIG, 480 * DOMAIN11_POWER_GATE, power_gate); 481 * 482 * REG_WAIT(DOMAIN11_PG_STATUS, 483 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 484 * 1, 1000); 485 */ 486 break; 487 default: 488 BREAK_TO_DEBUGGER(); 489 break; 490 } 491 } 492 493 494 void dcn20_hubp_pg_control( 495 struct dce_hwseq *hws, 496 unsigned int hubp_inst, 497 bool power_on) 498 { 499 uint32_t power_gate = power_on ? 0 : 1; 500 uint32_t pwr_status = power_on ? 0 : 2; 501 502 if (hws->ctx->dc->debug.disable_hubp_power_gate) 503 return; 504 if (REG(DOMAIN0_PG_CONFIG) == 0) 505 return; 506 507 switch (hubp_inst) { 508 case 0: /* DCHUBP0 */ 509 REG_UPDATE(DOMAIN0_PG_CONFIG, 510 DOMAIN0_POWER_GATE, power_gate); 511 512 REG_WAIT(DOMAIN0_PG_STATUS, 513 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 514 1, 1000); 515 break; 516 case 1: /* DCHUBP1 */ 517 REG_UPDATE(DOMAIN2_PG_CONFIG, 518 DOMAIN2_POWER_GATE, power_gate); 519 520 REG_WAIT(DOMAIN2_PG_STATUS, 521 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 522 1, 1000); 523 break; 524 case 2: /* DCHUBP2 */ 525 REG_UPDATE(DOMAIN4_PG_CONFIG, 526 DOMAIN4_POWER_GATE, power_gate); 527 528 REG_WAIT(DOMAIN4_PG_STATUS, 529 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 530 1, 1000); 531 break; 532 case 3: /* DCHUBP3 */ 533 REG_UPDATE(DOMAIN6_PG_CONFIG, 534 DOMAIN6_POWER_GATE, power_gate); 535 536 REG_WAIT(DOMAIN6_PG_STATUS, 537 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 538 1, 1000); 539 break; 540 case 4: /* DCHUBP4 */ 541 REG_UPDATE(DOMAIN8_PG_CONFIG, 542 DOMAIN8_POWER_GATE, power_gate); 543 544 REG_WAIT(DOMAIN8_PG_STATUS, 545 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 546 1, 1000); 547 break; 548 case 5: /* DCHUBP5 */ 549 /* 550 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 551 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 552 * reset. 553 * REG_UPDATE(DOMAIN10_PG_CONFIG, 554 * DOMAIN10_POWER_GATE, power_gate); 555 * 556 * REG_WAIT(DOMAIN10_PG_STATUS, 557 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 558 * 1, 1000); 559 */ 560 break; 561 default: 562 BREAK_TO_DEBUGGER(); 563 break; 564 } 565 } 566 567 568 /* disable HW used by plane. 569 * note: cannot disable until disconnect is complete 570 */ 571 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 572 { 573 struct dce_hwseq *hws = dc->hwseq; 574 struct hubp *hubp = pipe_ctx->plane_res.hubp; 575 struct dpp *dpp = pipe_ctx->plane_res.dpp; 576 577 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 578 579 /* In flip immediate with pipe splitting case GSL is used for 580 * synchronization so we must disable it when the plane is disabled. 581 */ 582 if (pipe_ctx->stream_res.gsl_group != 0) 583 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 584 585 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 586 587 hubp->funcs->hubp_clk_cntl(hubp, false); 588 589 dpp->funcs->dpp_dppclk_control(dpp, false, false); 590 591 hubp->power_gated = true; 592 593 hws->funcs.plane_atomic_power_down(dc, 594 pipe_ctx->plane_res.dpp, 595 pipe_ctx->plane_res.hubp); 596 597 pipe_ctx->stream = NULL; 598 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 599 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 600 pipe_ctx->top_pipe = NULL; 601 pipe_ctx->bottom_pipe = NULL; 602 pipe_ctx->plane_state = NULL; 603 } 604 605 606 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 607 { 608 DC_LOGGER_INIT(dc->ctx->logger); 609 610 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 611 return; 612 613 dcn20_plane_atomic_disable(dc, pipe_ctx); 614 615 DC_LOG_DC("Power down front end %d\n", 616 pipe_ctx->pipe_idx); 617 } 618 619 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 620 { 621 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 622 } 623 624 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 625 int opp_cnt) 626 { 627 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 628 int flow_ctrl_cnt; 629 630 if (opp_cnt >= 2) 631 hblank_halved = true; 632 633 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 634 stream->timing.h_border_left - 635 stream->timing.h_border_right; 636 637 if (hblank_halved) 638 flow_ctrl_cnt /= 2; 639 640 /* ODM combine 4:1 case */ 641 if (opp_cnt == 4) 642 flow_ctrl_cnt /= 2; 643 644 return flow_ctrl_cnt; 645 } 646 647 enum dc_status dcn20_enable_stream_timing( 648 struct pipe_ctx *pipe_ctx, 649 struct dc_state *context, 650 struct dc *dc) 651 { 652 struct dce_hwseq *hws = dc->hwseq; 653 struct dc_stream_state *stream = pipe_ctx->stream; 654 struct drr_params params = {0}; 655 unsigned int event_triggers = 0; 656 struct pipe_ctx *odm_pipe; 657 int opp_cnt = 1; 658 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 659 bool interlace = stream->timing.flags.INTERLACE; 660 int i; 661 struct mpc_dwb_flow_control flow_control; 662 struct mpc *mpc = dc->res_pool->mpc; 663 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 664 unsigned int k1_div = PIXEL_RATE_DIV_NA; 665 unsigned int k2_div = PIXEL_RATE_DIV_NA; 666 667 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 668 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 669 670 dc->res_pool->dccg->funcs->set_pixel_rate_div( 671 dc->res_pool->dccg, 672 pipe_ctx->stream_res.tg->inst, 673 k1_div, k2_div); 674 } 675 /* by upper caller loop, pipe0 is parent pipe and be called first. 676 * back end is set up by for pipe0. Other children pipe share back end 677 * with pipe 0. No program is needed. 678 */ 679 if (pipe_ctx->top_pipe != NULL) 680 return DC_OK; 681 682 /* TODO check if timing_changed, disable stream if timing changed */ 683 684 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 685 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 686 opp_cnt++; 687 } 688 689 if (opp_cnt > 1) 690 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 691 pipe_ctx->stream_res.tg, 692 opp_inst, opp_cnt, 693 &pipe_ctx->stream->timing); 694 695 /* HW program guide assume display already disable 696 * by unplug sequence. OTG assume stop. 697 */ 698 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 699 700 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 701 pipe_ctx->clock_source, 702 &pipe_ctx->stream_res.pix_clk_params, 703 dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), 704 &pipe_ctx->pll_settings)) { 705 BREAK_TO_DEBUGGER(); 706 return DC_ERROR_UNEXPECTED; 707 } 708 709 if (dc_is_hdmi_tmds_signal(stream->signal)) { 710 stream->link->phy_state.symclk_ref_cnts.otg = 1; 711 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 712 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 713 else 714 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 715 } 716 717 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 718 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 719 720 pipe_ctx->stream_res.tg->funcs->program_timing( 721 pipe_ctx->stream_res.tg, 722 &stream->timing, 723 pipe_ctx->pipe_dlg_param.vready_offset, 724 pipe_ctx->pipe_dlg_param.vstartup_start, 725 pipe_ctx->pipe_dlg_param.vupdate_offset, 726 pipe_ctx->pipe_dlg_param.vupdate_width, 727 pipe_ctx->stream->signal, 728 true); 729 730 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 731 flow_control.flow_ctrl_mode = 0; 732 flow_control.flow_ctrl_cnt0 = 0x80; 733 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 734 if (mpc->funcs->set_out_rate_control) { 735 for (i = 0; i < opp_cnt; ++i) { 736 mpc->funcs->set_out_rate_control( 737 mpc, opp_inst[i], 738 true, 739 rate_control_2x_pclk, 740 &flow_control); 741 } 742 } 743 744 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 745 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 746 odm_pipe->stream_res.opp, 747 true); 748 749 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 750 pipe_ctx->stream_res.opp, 751 true); 752 753 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 754 755 /* VTG is within DCHUB command block. DCFCLK is always on */ 756 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 757 BREAK_TO_DEBUGGER(); 758 return DC_ERROR_UNEXPECTED; 759 } 760 761 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 762 763 params.vertical_total_min = stream->adjust.v_total_min; 764 params.vertical_total_max = stream->adjust.v_total_max; 765 params.vertical_total_mid = stream->adjust.v_total_mid; 766 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 767 if (pipe_ctx->stream_res.tg->funcs->set_drr) 768 pipe_ctx->stream_res.tg->funcs->set_drr( 769 pipe_ctx->stream_res.tg, ¶ms); 770 771 // DRR should set trigger event to monitor surface update event 772 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 773 event_triggers = 0x80; 774 /* Event triggers and num frames initialized for DRR, but can be 775 * later updated for PSR use. Note DRR trigger events are generated 776 * regardless of whether num frames met. 777 */ 778 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 779 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 780 pipe_ctx->stream_res.tg, event_triggers, 2); 781 782 /* TODO program crtc source select for non-virtual signal*/ 783 /* TODO program FMT */ 784 /* TODO setup link_enc */ 785 /* TODO set stream attributes */ 786 /* TODO program audio */ 787 /* TODO enable stream if timing changed */ 788 /* TODO unblank stream if DP */ 789 790 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 791 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 792 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 793 } 794 return DC_OK; 795 } 796 797 void dcn20_program_output_csc(struct dc *dc, 798 struct pipe_ctx *pipe_ctx, 799 enum dc_color_space colorspace, 800 uint16_t *matrix, 801 int opp_id) 802 { 803 struct mpc *mpc = dc->res_pool->mpc; 804 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 805 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 806 807 if (mpc->funcs->power_on_mpc_mem_pwr) 808 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 809 810 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 811 if (mpc->funcs->set_output_csc != NULL) 812 mpc->funcs->set_output_csc(mpc, 813 opp_id, 814 matrix, 815 ocsc_mode); 816 } else { 817 if (mpc->funcs->set_ocsc_default != NULL) 818 mpc->funcs->set_ocsc_default(mpc, 819 opp_id, 820 colorspace, 821 ocsc_mode); 822 } 823 } 824 825 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 826 const struct dc_stream_state *stream) 827 { 828 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 829 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 830 struct pwl_params *params = NULL; 831 /* 832 * program OGAM only for the top pipe 833 * if there is a pipe split then fix diagnostic is required: 834 * how to pass OGAM parameter for stream. 835 * if programming for all pipes is required then remove condition 836 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 837 */ 838 if (mpc->funcs->power_on_mpc_mem_pwr) 839 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 840 if (pipe_ctx->top_pipe == NULL 841 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 842 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 843 params = &stream->out_transfer_func->pwl; 844 else if (pipe_ctx->stream->out_transfer_func->type == 845 TF_TYPE_DISTRIBUTED_POINTS && 846 cm_helper_translate_curve_to_hw_format( 847 stream->out_transfer_func, 848 &mpc->blender_params, false)) 849 params = &mpc->blender_params; 850 /* 851 * there is no ROM 852 */ 853 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 854 BREAK_TO_DEBUGGER(); 855 } 856 /* 857 * if above if is not executed then 'params' equal to 0 and set in bypass 858 */ 859 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 860 861 return true; 862 } 863 864 bool dcn20_set_blend_lut( 865 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 866 { 867 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 868 bool result = true; 869 struct pwl_params *blend_lut = NULL; 870 871 if (plane_state->blend_tf) { 872 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 873 blend_lut = &plane_state->blend_tf->pwl; 874 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 875 cm_helper_translate_curve_to_hw_format( 876 plane_state->blend_tf, 877 &dpp_base->regamma_params, false); 878 blend_lut = &dpp_base->regamma_params; 879 } 880 } 881 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 882 883 return result; 884 } 885 886 bool dcn20_set_shaper_3dlut( 887 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 888 { 889 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 890 bool result = true; 891 struct pwl_params *shaper_lut = NULL; 892 893 if (plane_state->in_shaper_func) { 894 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 895 shaper_lut = &plane_state->in_shaper_func->pwl; 896 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 897 cm_helper_translate_curve_to_hw_format( 898 plane_state->in_shaper_func, 899 &dpp_base->shaper_params, true); 900 shaper_lut = &dpp_base->shaper_params; 901 } 902 } 903 904 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 905 if (plane_state->lut3d_func && 906 plane_state->lut3d_func->state.bits.initialized == 1) 907 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 908 &plane_state->lut3d_func->lut_3d); 909 else 910 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 911 912 return result; 913 } 914 915 bool dcn20_set_input_transfer_func(struct dc *dc, 916 struct pipe_ctx *pipe_ctx, 917 const struct dc_plane_state *plane_state) 918 { 919 struct dce_hwseq *hws = dc->hwseq; 920 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 921 const struct dc_transfer_func *tf = NULL; 922 bool result = true; 923 bool use_degamma_ram = false; 924 925 if (dpp_base == NULL || plane_state == NULL) 926 return false; 927 928 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 929 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 930 931 if (plane_state->in_transfer_func) 932 tf = plane_state->in_transfer_func; 933 934 935 if (tf == NULL) { 936 dpp_base->funcs->dpp_set_degamma(dpp_base, 937 IPP_DEGAMMA_MODE_BYPASS); 938 return true; 939 } 940 941 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 942 use_degamma_ram = true; 943 944 if (use_degamma_ram == true) { 945 if (tf->type == TF_TYPE_HWPWL) 946 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 947 &tf->pwl); 948 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 949 cm_helper_translate_curve_to_degamma_hw_format(tf, 950 &dpp_base->degamma_params); 951 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 952 &dpp_base->degamma_params); 953 } 954 return true; 955 } 956 /* handle here the optimized cases when de-gamma ROM could be used. 957 * 958 */ 959 if (tf->type == TF_TYPE_PREDEFINED) { 960 switch (tf->tf) { 961 case TRANSFER_FUNCTION_SRGB: 962 dpp_base->funcs->dpp_set_degamma(dpp_base, 963 IPP_DEGAMMA_MODE_HW_sRGB); 964 break; 965 case TRANSFER_FUNCTION_BT709: 966 dpp_base->funcs->dpp_set_degamma(dpp_base, 967 IPP_DEGAMMA_MODE_HW_xvYCC); 968 break; 969 case TRANSFER_FUNCTION_LINEAR: 970 dpp_base->funcs->dpp_set_degamma(dpp_base, 971 IPP_DEGAMMA_MODE_BYPASS); 972 break; 973 case TRANSFER_FUNCTION_PQ: 974 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 975 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 976 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 977 result = true; 978 break; 979 default: 980 result = false; 981 break; 982 } 983 } else if (tf->type == TF_TYPE_BYPASS) 984 dpp_base->funcs->dpp_set_degamma(dpp_base, 985 IPP_DEGAMMA_MODE_BYPASS); 986 else { 987 /* 988 * if we are here, we did not handle correctly. 989 * fix is required for this use case 990 */ 991 BREAK_TO_DEBUGGER(); 992 dpp_base->funcs->dpp_set_degamma(dpp_base, 993 IPP_DEGAMMA_MODE_BYPASS); 994 } 995 996 return result; 997 } 998 999 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1000 { 1001 struct pipe_ctx *odm_pipe; 1002 int opp_cnt = 1; 1003 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 1004 1005 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1006 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 1007 opp_cnt++; 1008 } 1009 1010 if (opp_cnt > 1) 1011 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1012 pipe_ctx->stream_res.tg, 1013 opp_inst, opp_cnt, 1014 &pipe_ctx->stream->timing); 1015 else 1016 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1017 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1018 } 1019 1020 void dcn20_blank_pixel_data( 1021 struct dc *dc, 1022 struct pipe_ctx *pipe_ctx, 1023 bool blank) 1024 { 1025 struct tg_color black_color = {0}; 1026 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1027 struct dc_stream_state *stream = pipe_ctx->stream; 1028 enum dc_color_space color_space = stream->output_color_space; 1029 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1030 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1031 struct pipe_ctx *odm_pipe; 1032 int odm_cnt = 1; 1033 1034 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1035 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1036 1037 if (stream->link->test_pattern_enabled) 1038 return; 1039 1040 /* get opp dpg blank color */ 1041 color_space_to_black_color(dc, color_space, &black_color); 1042 1043 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1044 odm_cnt++; 1045 1046 width = width / odm_cnt; 1047 1048 if (blank) { 1049 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1050 1051 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1052 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1053 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1054 } 1055 } else { 1056 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1057 } 1058 1059 dc->hwss.set_disp_pattern_generator(dc, 1060 pipe_ctx, 1061 test_pattern, 1062 test_pattern_color_space, 1063 stream->timing.display_color_depth, 1064 &black_color, 1065 width, 1066 height, 1067 0); 1068 1069 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1070 dc->hwss.set_disp_pattern_generator(dc, 1071 odm_pipe, 1072 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1073 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1074 test_pattern_color_space, 1075 stream->timing.display_color_depth, 1076 &black_color, 1077 width, 1078 height, 1079 0); 1080 } 1081 1082 if (!blank) 1083 if (stream_res->abm) { 1084 dc->hwss.set_pipe(pipe_ctx); 1085 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1086 } 1087 } 1088 1089 1090 static void dcn20_power_on_plane( 1091 struct dce_hwseq *hws, 1092 struct pipe_ctx *pipe_ctx) 1093 { 1094 DC_LOGGER_INIT(hws->ctx->logger); 1095 if (REG(DC_IP_REQUEST_CNTL)) { 1096 REG_SET(DC_IP_REQUEST_CNTL, 0, 1097 IP_REQUEST_EN, 1); 1098 1099 if (hws->funcs.dpp_pg_control) 1100 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1101 1102 if (hws->funcs.hubp_pg_control) 1103 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1104 1105 REG_SET(DC_IP_REQUEST_CNTL, 0, 1106 IP_REQUEST_EN, 0); 1107 DC_LOG_DEBUG( 1108 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1109 } 1110 } 1111 1112 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1113 struct dc_state *context) 1114 { 1115 //if (dc->debug.sanity_checks) { 1116 // dcn10_verify_allow_pstate_change_high(dc); 1117 //} 1118 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1119 1120 /* enable DCFCLK current DCHUB */ 1121 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1122 1123 /* initialize HUBP on power up */ 1124 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1125 1126 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1127 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1128 pipe_ctx->stream_res.opp, 1129 true); 1130 1131 /* TODO: enable/disable in dm as per update type. 1132 if (plane_state) { 1133 DC_LOG_DC(dc->ctx->logger, 1134 "Pipe:%d 0x%x: addr hi:0x%x, " 1135 "addr low:0x%x, " 1136 "src: %d, %d, %d," 1137 " %d; dst: %d, %d, %d, %d;\n", 1138 pipe_ctx->pipe_idx, 1139 plane_state, 1140 plane_state->address.grph.addr.high_part, 1141 plane_state->address.grph.addr.low_part, 1142 plane_state->src_rect.x, 1143 plane_state->src_rect.y, 1144 plane_state->src_rect.width, 1145 plane_state->src_rect.height, 1146 plane_state->dst_rect.x, 1147 plane_state->dst_rect.y, 1148 plane_state->dst_rect.width, 1149 plane_state->dst_rect.height); 1150 1151 DC_LOG_DC(dc->ctx->logger, 1152 "Pipe %d: width, height, x, y format:%d\n" 1153 "viewport:%d, %d, %d, %d\n" 1154 "recout: %d, %d, %d, %d\n", 1155 pipe_ctx->pipe_idx, 1156 plane_state->format, 1157 pipe_ctx->plane_res.scl_data.viewport.width, 1158 pipe_ctx->plane_res.scl_data.viewport.height, 1159 pipe_ctx->plane_res.scl_data.viewport.x, 1160 pipe_ctx->plane_res.scl_data.viewport.y, 1161 pipe_ctx->plane_res.scl_data.recout.width, 1162 pipe_ctx->plane_res.scl_data.recout.height, 1163 pipe_ctx->plane_res.scl_data.recout.x, 1164 pipe_ctx->plane_res.scl_data.recout.y); 1165 print_rq_dlg_ttu(dc, pipe_ctx); 1166 } 1167 */ 1168 if (dc->vm_pa_config.valid) { 1169 struct vm_system_aperture_param apt; 1170 1171 apt.sys_default.quad_part = 0; 1172 1173 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1174 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1175 1176 // Program system aperture settings 1177 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1178 } 1179 1180 if (!pipe_ctx->top_pipe 1181 && pipe_ctx->plane_state 1182 && pipe_ctx->plane_state->flip_int_enabled 1183 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1185 1186 // if (dc->debug.sanity_checks) { 1187 // dcn10_verify_allow_pstate_change_high(dc); 1188 // } 1189 } 1190 1191 void dcn20_pipe_control_lock( 1192 struct dc *dc, 1193 struct pipe_ctx *pipe, 1194 bool lock) 1195 { 1196 struct pipe_ctx *temp_pipe; 1197 bool flip_immediate = false; 1198 1199 /* use TG master update lock to lock everything on the TG 1200 * therefore only top pipe need to lock 1201 */ 1202 if (!pipe || pipe->top_pipe) 1203 return; 1204 1205 if (pipe->plane_state != NULL) 1206 flip_immediate = pipe->plane_state->flip_immediate; 1207 1208 if (pipe->stream_res.gsl_group > 0) { 1209 temp_pipe = pipe->bottom_pipe; 1210 while (!flip_immediate && temp_pipe) { 1211 if (temp_pipe->plane_state != NULL) 1212 flip_immediate = temp_pipe->plane_state->flip_immediate; 1213 temp_pipe = temp_pipe->bottom_pipe; 1214 } 1215 } 1216 1217 if (flip_immediate && lock) { 1218 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1219 int i; 1220 1221 temp_pipe = pipe; 1222 while (temp_pipe) { 1223 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1224 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1225 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1226 break; 1227 udelay(1); 1228 } 1229 1230 /* no reason it should take this long for immediate flips */ 1231 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1232 } 1233 temp_pipe = temp_pipe->bottom_pipe; 1234 } 1235 } 1236 1237 /* In flip immediate and pipe splitting case, we need to use GSL 1238 * for synchronization. Only do setup on locking and on flip type change. 1239 */ 1240 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1241 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1242 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1243 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1244 1245 if (pipe->plane_state != NULL) 1246 flip_immediate = pipe->plane_state->flip_immediate; 1247 1248 temp_pipe = pipe->bottom_pipe; 1249 while (flip_immediate && temp_pipe) { 1250 if (temp_pipe->plane_state != NULL) 1251 flip_immediate = temp_pipe->plane_state->flip_immediate; 1252 temp_pipe = temp_pipe->bottom_pipe; 1253 } 1254 1255 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1256 !flip_immediate) 1257 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1258 1259 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1260 union dmub_hw_lock_flags hw_locks = { 0 }; 1261 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1262 1263 hw_locks.bits.lock_pipe = 1; 1264 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1265 1266 if (pipe->plane_state != NULL) 1267 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1268 1269 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1270 lock, 1271 &hw_locks, 1272 &inst_flags); 1273 } else if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 1274 union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; 1275 hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; 1276 hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; 1277 hw_lock_cmd.bits.lock_pipe = 1; 1278 hw_lock_cmd.bits.otg_inst = pipe->stream_res.tg->inst; 1279 hw_lock_cmd.bits.lock = lock; 1280 if (!lock) 1281 hw_lock_cmd.bits.should_release = 1; 1282 dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); 1283 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1284 if (lock) 1285 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1286 else 1287 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1288 } else { 1289 if (lock) 1290 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1291 else 1292 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1293 } 1294 } 1295 1296 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1297 { 1298 new_pipe->update_flags.raw = 0; 1299 1300 /* Exit on unchanged, unused pipe */ 1301 if (!old_pipe->plane_state && !new_pipe->plane_state) 1302 return; 1303 /* Detect pipe enable/disable */ 1304 if (!old_pipe->plane_state && new_pipe->plane_state) { 1305 new_pipe->update_flags.bits.enable = 1; 1306 new_pipe->update_flags.bits.mpcc = 1; 1307 new_pipe->update_flags.bits.dppclk = 1; 1308 new_pipe->update_flags.bits.hubp_interdependent = 1; 1309 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1310 new_pipe->update_flags.bits.gamut_remap = 1; 1311 new_pipe->update_flags.bits.scaler = 1; 1312 new_pipe->update_flags.bits.viewport = 1; 1313 new_pipe->update_flags.bits.det_size = 1; 1314 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1315 new_pipe->update_flags.bits.odm = 1; 1316 new_pipe->update_flags.bits.global_sync = 1; 1317 } 1318 return; 1319 } 1320 1321 /* For SubVP we need to unconditionally enable because any phantom pipes are 1322 * always removed then newly added for every full updates whenever SubVP is in use. 1323 * The remove-add sequence of the phantom pipe always results in the pipe 1324 * being blanked in enable_stream_timing (DPG). 1325 */ 1326 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 1327 new_pipe->update_flags.bits.enable = 1; 1328 1329 /* Phantom pipes are effectively disabled, if the pipe was previously phantom 1330 * we have to enable 1331 */ 1332 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom && 1333 new_pipe->plane_state && !new_pipe->plane_state->is_phantom) 1334 new_pipe->update_flags.bits.enable = 1; 1335 1336 if (old_pipe->plane_state && !new_pipe->plane_state) { 1337 new_pipe->update_flags.bits.disable = 1; 1338 return; 1339 } 1340 1341 /* Detect plane change */ 1342 if (old_pipe->plane_state != new_pipe->plane_state) { 1343 new_pipe->update_flags.bits.plane_changed = true; 1344 } 1345 1346 /* Detect top pipe only changes */ 1347 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1348 /* Detect odm changes */ 1349 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1350 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1351 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1352 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1353 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1354 new_pipe->update_flags.bits.odm = 1; 1355 1356 /* Detect global sync changes */ 1357 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1358 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1359 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1360 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1361 new_pipe->update_flags.bits.global_sync = 1; 1362 } 1363 1364 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1365 new_pipe->update_flags.bits.det_size = 1; 1366 1367 /* 1368 * Detect opp / tg change, only set on change, not on enable 1369 * Assume mpcc inst = pipe index, if not this code needs to be updated 1370 * since mpcc is what is affected by these. In fact all of our sequence 1371 * makes this assumption at the moment with how hubp reset is matched to 1372 * same index mpcc reset. 1373 */ 1374 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1375 new_pipe->update_flags.bits.opp_changed = 1; 1376 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1377 new_pipe->update_flags.bits.tg_changed = 1; 1378 1379 /* 1380 * Detect mpcc blending changes, only dpp inst and opp matter here, 1381 * mpccs getting removed/inserted update connected ones during their own 1382 * programming 1383 */ 1384 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1385 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1386 new_pipe->update_flags.bits.mpcc = 1; 1387 1388 /* Detect dppclk change */ 1389 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1390 new_pipe->update_flags.bits.dppclk = 1; 1391 1392 /* Check for scl update */ 1393 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1394 new_pipe->update_flags.bits.scaler = 1; 1395 /* Check for vp update */ 1396 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1397 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1398 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1399 new_pipe->update_flags.bits.viewport = 1; 1400 1401 /* Detect dlg/ttu/rq updates */ 1402 { 1403 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1404 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1405 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1406 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1407 1408 /* Detect pipe interdependent updates */ 1409 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1410 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1411 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1412 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1413 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1414 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1415 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1416 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1417 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1418 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1419 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1420 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1421 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1422 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1423 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1424 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1425 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1426 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1427 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1428 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1429 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1430 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1431 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1432 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1433 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1434 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1435 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1436 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1437 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1438 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1439 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1440 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1441 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1442 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1443 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1444 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1445 new_pipe->update_flags.bits.hubp_interdependent = 1; 1446 } 1447 /* Detect any other updates to ttu/rq/dlg */ 1448 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1449 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1450 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1451 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1452 } 1453 } 1454 1455 static void dcn20_update_dchubp_dpp( 1456 struct dc *dc, 1457 struct pipe_ctx *pipe_ctx, 1458 struct dc_state *context) 1459 { 1460 struct dce_hwseq *hws = dc->hwseq; 1461 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1462 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1463 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1464 struct dccg *dccg = dc->res_pool->dccg; 1465 bool viewport_changed = false; 1466 1467 if (pipe_ctx->update_flags.bits.dppclk) 1468 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1469 1470 if (pipe_ctx->update_flags.bits.enable) 1471 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 1472 1473 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1474 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1475 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1476 */ 1477 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1478 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1479 1480 hubp->funcs->hubp_setup( 1481 hubp, 1482 &pipe_ctx->dlg_regs, 1483 &pipe_ctx->ttu_regs, 1484 &pipe_ctx->rq_regs, 1485 &pipe_ctx->pipe_dlg_param); 1486 1487 if (hubp->funcs->set_unbounded_requesting) 1488 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1489 } 1490 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1491 hubp->funcs->hubp_setup_interdependent( 1492 hubp, 1493 &pipe_ctx->dlg_regs, 1494 &pipe_ctx->ttu_regs); 1495 1496 if (pipe_ctx->update_flags.bits.enable || 1497 pipe_ctx->update_flags.bits.plane_changed || 1498 plane_state->update_flags.bits.bpp_change || 1499 plane_state->update_flags.bits.input_csc_change || 1500 plane_state->update_flags.bits.color_space_change || 1501 plane_state->update_flags.bits.coeff_reduction_change) { 1502 struct dc_bias_and_scale bns_params = {0}; 1503 1504 // program the input csc 1505 dpp->funcs->dpp_setup(dpp, 1506 plane_state->format, 1507 EXPANSION_MODE_ZERO, 1508 plane_state->input_csc_color_matrix, 1509 plane_state->color_space, 1510 NULL); 1511 1512 if (dpp->funcs->dpp_program_bias_and_scale) { 1513 //TODO :for CNVC set scale and bias registers if necessary 1514 build_prescale_params(&bns_params, plane_state); 1515 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1516 } 1517 } 1518 1519 if (pipe_ctx->update_flags.bits.mpcc 1520 || pipe_ctx->update_flags.bits.plane_changed 1521 || plane_state->update_flags.bits.global_alpha_change 1522 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1523 // MPCC inst is equal to pipe index in practice 1524 int mpcc_inst = hubp->inst; 1525 int opp_inst; 1526 int opp_count = dc->res_pool->pipe_count; 1527 1528 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1529 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1530 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1531 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1532 break; 1533 } 1534 } 1535 hws->funcs.update_mpcc(dc, pipe_ctx); 1536 } 1537 1538 if (pipe_ctx->update_flags.bits.scaler || 1539 plane_state->update_flags.bits.scaling_change || 1540 plane_state->update_flags.bits.position_change || 1541 plane_state->update_flags.bits.per_pixel_alpha_change || 1542 pipe_ctx->stream->update_flags.bits.scaling) { 1543 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1544 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1545 /* scaler configuration */ 1546 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1547 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1548 } 1549 1550 if (pipe_ctx->update_flags.bits.viewport || 1551 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1552 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1553 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1554 1555 hubp->funcs->mem_program_viewport( 1556 hubp, 1557 &pipe_ctx->plane_res.scl_data.viewport, 1558 &pipe_ctx->plane_res.scl_data.viewport_c); 1559 viewport_changed = true; 1560 } 1561 1562 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1563 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1564 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1565 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1566 dc->hwss.set_cursor_position(pipe_ctx); 1567 dc->hwss.set_cursor_attribute(pipe_ctx); 1568 1569 if (dc->hwss.set_cursor_sdr_white_level) 1570 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1571 } 1572 1573 /* Any updates are handled in dc interface, just need 1574 * to apply existing for plane enable / opp change */ 1575 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1576 || pipe_ctx->update_flags.bits.plane_changed 1577 || pipe_ctx->stream->update_flags.bits.gamut_remap 1578 || pipe_ctx->stream->update_flags.bits.out_csc) { 1579 /* dpp/cm gamut remap*/ 1580 dc->hwss.program_gamut_remap(pipe_ctx); 1581 1582 /*call the dcn2 method which uses mpc csc*/ 1583 dc->hwss.program_output_csc(dc, 1584 pipe_ctx, 1585 pipe_ctx->stream->output_color_space, 1586 pipe_ctx->stream->csc_color_matrix.matrix, 1587 hubp->opp_id); 1588 } 1589 1590 if (pipe_ctx->update_flags.bits.enable || 1591 pipe_ctx->update_flags.bits.plane_changed || 1592 pipe_ctx->update_flags.bits.opp_changed || 1593 plane_state->update_flags.bits.pixel_format_change || 1594 plane_state->update_flags.bits.horizontal_mirror_change || 1595 plane_state->update_flags.bits.rotation_change || 1596 plane_state->update_flags.bits.swizzle_change || 1597 plane_state->update_flags.bits.dcc_change || 1598 plane_state->update_flags.bits.bpp_change || 1599 plane_state->update_flags.bits.scaling_change || 1600 plane_state->update_flags.bits.plane_size_change) { 1601 struct plane_size size = plane_state->plane_size; 1602 1603 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1604 hubp->funcs->hubp_program_surface_config( 1605 hubp, 1606 plane_state->format, 1607 &plane_state->tiling_info, 1608 &size, 1609 plane_state->rotation, 1610 &plane_state->dcc, 1611 plane_state->horizontal_mirror, 1612 0); 1613 hubp->power_gated = false; 1614 } 1615 1616 if (pipe_ctx->update_flags.bits.enable || 1617 pipe_ctx->update_flags.bits.plane_changed || 1618 plane_state->update_flags.bits.addr_update) 1619 hws->funcs.update_plane_addr(dc, pipe_ctx); 1620 1621 if (pipe_ctx->update_flags.bits.enable) 1622 hubp->funcs->set_blank(hubp, false); 1623 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1624 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1625 && hubp->funcs->phantom_hubp_post_enable) 1626 hubp->funcs->phantom_hubp_post_enable(hubp); 1627 } 1628 1629 1630 static void dcn20_program_pipe( 1631 struct dc *dc, 1632 struct pipe_ctx *pipe_ctx, 1633 struct dc_state *context) 1634 { 1635 struct dce_hwseq *hws = dc->hwseq; 1636 /* Only need to unblank on top pipe */ 1637 1638 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1639 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1640 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1641 1642 /* Only update TG on top pipe */ 1643 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1644 && !pipe_ctx->prev_odm_pipe) { 1645 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1646 pipe_ctx->stream_res.tg, 1647 pipe_ctx->pipe_dlg_param.vready_offset, 1648 pipe_ctx->pipe_dlg_param.vstartup_start, 1649 pipe_ctx->pipe_dlg_param.vupdate_offset, 1650 pipe_ctx->pipe_dlg_param.vupdate_width); 1651 1652 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1653 pipe_ctx->stream_res.tg->funcs->wait_for_state( 1654 pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1655 pipe_ctx->stream_res.tg->funcs->wait_for_state( 1656 pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1657 } 1658 1659 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1660 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1661 1662 if (hws->funcs.setup_vupdate_interrupt) 1663 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1664 } 1665 1666 if (pipe_ctx->update_flags.bits.odm) 1667 hws->funcs.update_odm(dc, context, pipe_ctx); 1668 1669 if (pipe_ctx->update_flags.bits.enable) { 1670 dcn20_enable_plane(dc, pipe_ctx, context); 1671 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1672 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1673 } 1674 1675 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1676 dc->res_pool->hubbub->funcs->program_det_size( 1677 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1678 1679 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1680 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1681 1682 if (pipe_ctx->update_flags.bits.enable 1683 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1684 hws->funcs.set_hdr_multiplier(pipe_ctx); 1685 1686 if (pipe_ctx->update_flags.bits.enable || 1687 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1688 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1689 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1690 1691 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1692 * only do gamma programming for powering on, internal memcmp to avoid 1693 * updating on slave planes 1694 */ 1695 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1696 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1697 1698 /* If the pipe has been enabled or has a different opp, we 1699 * should reprogram the fmt. This deals with cases where 1700 * interation between mpc and odm combine on different streams 1701 * causes a different pipe to be chosen to odm combine with. 1702 */ 1703 if (pipe_ctx->update_flags.bits.enable 1704 || pipe_ctx->update_flags.bits.opp_changed) { 1705 1706 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1707 pipe_ctx->stream_res.opp, 1708 COLOR_SPACE_YCBCR601, 1709 pipe_ctx->stream->timing.display_color_depth, 1710 pipe_ctx->stream->signal); 1711 1712 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1713 pipe_ctx->stream_res.opp, 1714 &pipe_ctx->stream->bit_depth_params, 1715 &pipe_ctx->stream->clamping); 1716 } 1717 } 1718 1719 void dcn20_program_front_end_for_ctx( 1720 struct dc *dc, 1721 struct dc_state *context) 1722 { 1723 int i; 1724 struct dce_hwseq *hws = dc->hwseq; 1725 DC_LOGGER_INIT(dc->ctx->logger); 1726 1727 /* Carry over GSL groups in case the context is changing. */ 1728 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1729 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1730 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1731 1732 if (pipe_ctx->stream == old_pipe_ctx->stream) 1733 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group; 1734 } 1735 1736 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1737 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1738 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1739 1740 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1741 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1742 /*turn off triple buffer for full update*/ 1743 dc->hwss.program_triplebuffer( 1744 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1745 } 1746 } 1747 } 1748 1749 /* Set pipe update flags and lock pipes */ 1750 for (i = 0; i < dc->res_pool->pipe_count; i++) 1751 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1752 &context->res_ctx.pipe_ctx[i]); 1753 1754 /* OTG blank before disabling all front ends */ 1755 for (i = 0; i < dc->res_pool->pipe_count; i++) 1756 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1757 && !context->res_ctx.pipe_ctx[i].top_pipe 1758 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1759 && context->res_ctx.pipe_ctx[i].stream) 1760 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1761 1762 1763 /* Disconnect mpcc */ 1764 for (i = 0; i < dc->res_pool->pipe_count; i++) 1765 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1766 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1767 struct hubbub *hubbub = dc->res_pool->hubbub; 1768 1769 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom 1770 * then we want to do the programming here (effectively it's being disabled). If we do 1771 * the programming later the DET won't be updated until the OTG for the phantom pipe is 1772 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with 1773 * DET allocation. 1774 */ 1775 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || 1776 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom))) 1777 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1778 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1779 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1780 } 1781 1782 /* 1783 * Program all updated pipes, order matters for mpcc setup. Start with 1784 * top pipe and program all pipes that follow in order 1785 */ 1786 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1787 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1788 1789 if (pipe->plane_state && !pipe->top_pipe) { 1790 while (pipe) { 1791 if (hws->funcs.program_pipe) 1792 hws->funcs.program_pipe(dc, pipe, context); 1793 else { 1794 /* Don't program phantom pipes in the regular front end programming sequence. 1795 * There is an MPO transition case where a pipe being used by a video plane is 1796 * transitioned directly to be a phantom pipe when closing the MPO video. However 1797 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away), 1798 * but the MPO still exists until the double buffered update of the main pipe so we 1799 * will get a frame of underflow if the phantom pipe is programmed here. 1800 */ 1801 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) 1802 dcn20_program_pipe(dc, pipe, context); 1803 } 1804 1805 pipe = pipe->bottom_pipe; 1806 } 1807 } 1808 /* Program secondary blending tree and writeback pipes */ 1809 pipe = &context->res_ctx.pipe_ctx[i]; 1810 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1811 && pipe->stream && pipe->stream->num_wb_info > 0 1812 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1813 || pipe->stream->update_flags.raw) 1814 && hws->funcs.program_all_writeback_pipes_in_tree) 1815 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1816 1817 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1818 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1819 !pipe->top_pipe && 1820 pipe->stream && 1821 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1822 dc->current_state->stream_status[0].plane_count == 1 && 1823 context->stream_status[0].plane_count > 1) { 1824 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1825 } 1826 } 1827 } 1828 1829 void dcn20_post_unlock_program_front_end( 1830 struct dc *dc, 1831 struct dc_state *context) 1832 { 1833 int i; 1834 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1835 struct dce_hwseq *hwseq = dc->hwseq; 1836 1837 DC_LOGGER_INIT(dc->ctx->logger); 1838 1839 for (i = 0; i < dc->res_pool->pipe_count; i++) 1840 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1841 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1842 1843 /* 1844 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1845 * part of the enable operation otherwise, DM may request an immediate flip which 1846 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1847 * is unsupported on DCN. 1848 */ 1849 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1850 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1851 // Don't check flip pending on phantom pipes 1852 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && 1853 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1854 struct hubp *hubp = pipe->plane_res.hubp; 1855 int j = 0; 1856 1857 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1858 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1859 mdelay(1); 1860 } 1861 } 1862 1863 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1864 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1865 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1866 1867 /* If an active, non-phantom pipe is being transitioned into a phantom 1868 * pipe, wait for the double buffer update to complete first before we do 1869 * phantom pipe programming (HUBP_VTG_SEL updates right away so that can 1870 * cause issues). 1871 */ 1872 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM && 1873 old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1874 old_pipe->stream_res.tg->funcs->wait_for_state( 1875 old_pipe->stream_res.tg, 1876 CRTC_STATE_VBLANK); 1877 old_pipe->stream_res.tg->funcs->wait_for_state( 1878 old_pipe->stream_res.tg, 1879 CRTC_STATE_VACTIVE); 1880 } 1881 } 1882 1883 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1884 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1885 1886 if (pipe->plane_state && !pipe->top_pipe) { 1887 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition 1888 * case (if a pipe being used for a video plane transitions to a phantom pipe, it 1889 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end 1890 * programming sequence). 1891 */ 1892 while (pipe) { 1893 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1894 if (dc->hwss.update_phantom_vp_position) 1895 dc->hwss.update_phantom_vp_position(dc, context, pipe); 1896 dcn20_program_pipe(dc, pipe, context); 1897 } 1898 pipe = pipe->bottom_pipe; 1899 } 1900 } 1901 } 1902 1903 /* Only program the MALL registers after all the main and phantom pipes 1904 * are done programming. 1905 */ 1906 if (hwseq->funcs.program_mall_pipe_config) 1907 hwseq->funcs.program_mall_pipe_config(dc, context); 1908 1909 /* WA to apply WM setting*/ 1910 if (hwseq->wa.DEGVIDCN21) 1911 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1912 1913 1914 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1915 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1916 1917 if (dc->current_state->stream_status[0].plane_count == 1 && 1918 context->stream_status[0].plane_count > 1) { 1919 1920 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1921 1922 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1923 1924 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1925 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1926 } 1927 } 1928 } 1929 1930 void dcn20_prepare_bandwidth( 1931 struct dc *dc, 1932 struct dc_state *context) 1933 { 1934 struct hubbub *hubbub = dc->res_pool->hubbub; 1935 unsigned int compbuf_size_kb = 0; 1936 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; 1937 unsigned int i; 1938 1939 dc->clk_mgr->funcs->update_clocks( 1940 dc->clk_mgr, 1941 context, 1942 false); 1943 1944 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1945 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1946 1947 // At optimize don't restore the original watermark value 1948 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 1949 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 1950 break; 1951 } 1952 } 1953 1954 /* program dchubbub watermarks */ 1955 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 1956 &context->bw_ctx.bw.dcn.watermarks, 1957 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1958 false); 1959 1960 // Restore the real watermark so we can commit the value to DMCUB 1961 // DMCUB uses the "original" watermark value in SubVP MCLK switch 1962 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; 1963 1964 /* decrease compbuf size */ 1965 if (hubbub->funcs->program_compbuf_size) { 1966 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) 1967 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 1968 else 1969 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 1970 1971 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 1972 } 1973 } 1974 1975 void dcn20_optimize_bandwidth( 1976 struct dc *dc, 1977 struct dc_state *context) 1978 { 1979 struct hubbub *hubbub = dc->res_pool->hubbub; 1980 int i; 1981 1982 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1983 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1984 1985 // At optimize don't need to restore the original watermark value 1986 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 1987 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 1988 break; 1989 } 1990 } 1991 1992 /* program dchubbub watermarks */ 1993 hubbub->funcs->program_watermarks(hubbub, 1994 &context->bw_ctx.bw.dcn.watermarks, 1995 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1996 true); 1997 1998 if (dc->clk_mgr->dc_mode_softmax_enabled) 1999 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 2000 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 2001 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 2002 2003 /* increase compbuf size */ 2004 if (hubbub->funcs->program_compbuf_size) 2005 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 2006 2007 dc->clk_mgr->funcs->update_clocks( 2008 dc->clk_mgr, 2009 context, 2010 true); 2011 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 2012 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 2013 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2014 2015 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 2016 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 2017 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 2018 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 2019 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start); 2020 } 2021 } 2022 } 2023 2024 bool dcn20_update_bandwidth( 2025 struct dc *dc, 2026 struct dc_state *context) 2027 { 2028 int i; 2029 struct dce_hwseq *hws = dc->hwseq; 2030 2031 /* recalculate DML parameters */ 2032 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 2033 return false; 2034 2035 /* apply updated bandwidth parameters */ 2036 dc->hwss.prepare_bandwidth(dc, context); 2037 2038 /* update hubp configs for all pipes */ 2039 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2040 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2041 2042 if (pipe_ctx->plane_state == NULL) 2043 continue; 2044 2045 if (pipe_ctx->top_pipe == NULL) { 2046 bool blank = !is_pipe_tree_visible(pipe_ctx); 2047 2048 pipe_ctx->stream_res.tg->funcs->program_global_sync( 2049 pipe_ctx->stream_res.tg, 2050 pipe_ctx->pipe_dlg_param.vready_offset, 2051 pipe_ctx->pipe_dlg_param.vstartup_start, 2052 pipe_ctx->pipe_dlg_param.vupdate_offset, 2053 pipe_ctx->pipe_dlg_param.vupdate_width); 2054 2055 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 2056 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 2057 2058 if (pipe_ctx->prev_odm_pipe == NULL) 2059 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 2060 2061 if (hws->funcs.setup_vupdate_interrupt) 2062 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 2063 } 2064 2065 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 2066 pipe_ctx->plane_res.hubp, 2067 &pipe_ctx->dlg_regs, 2068 &pipe_ctx->ttu_regs, 2069 &pipe_ctx->rq_regs, 2070 &pipe_ctx->pipe_dlg_param); 2071 } 2072 2073 return true; 2074 } 2075 2076 void dcn20_enable_writeback( 2077 struct dc *dc, 2078 struct dc_writeback_info *wb_info, 2079 struct dc_state *context) 2080 { 2081 struct dwbc *dwb; 2082 struct mcif_wb *mcif_wb; 2083 struct timing_generator *optc; 2084 2085 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2086 ASSERT(wb_info->wb_enabled); 2087 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2088 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2089 2090 /* set the OPTC source mux */ 2091 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 2092 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2093 /* set MCIF_WB buffer and arbitration configuration */ 2094 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2095 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2096 /* Enable MCIF_WB */ 2097 mcif_wb->funcs->enable_mcif(mcif_wb); 2098 /* Enable DWB */ 2099 dwb->funcs->enable(dwb, &wb_info->dwb_params); 2100 /* TODO: add sequence to enable/disable warmup */ 2101 } 2102 2103 void dcn20_disable_writeback( 2104 struct dc *dc, 2105 unsigned int dwb_pipe_inst) 2106 { 2107 struct dwbc *dwb; 2108 struct mcif_wb *mcif_wb; 2109 2110 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2111 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2112 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2113 2114 dwb->funcs->disable(dwb); 2115 mcif_wb->funcs->disable_mcif(mcif_wb); 2116 } 2117 2118 bool dcn20_wait_for_blank_complete( 2119 struct output_pixel_processor *opp) 2120 { 2121 int counter; 2122 2123 for (counter = 0; counter < 1000; counter++) { 2124 if (opp->funcs->dpg_is_blanked(opp)) 2125 break; 2126 2127 udelay(100); 2128 } 2129 2130 if (counter == 1000) { 2131 dm_error("DC: failed to blank crtc!\n"); 2132 return false; 2133 } 2134 2135 return true; 2136 } 2137 2138 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2139 { 2140 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2141 2142 if (!hubp) 2143 return false; 2144 return hubp->funcs->dmdata_status_done(hubp); 2145 } 2146 2147 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2148 { 2149 struct dce_hwseq *hws = dc->hwseq; 2150 2151 if (pipe_ctx->stream_res.dsc) { 2152 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2153 2154 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2155 while (odm_pipe) { 2156 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2157 odm_pipe = odm_pipe->next_odm_pipe; 2158 } 2159 } 2160 } 2161 2162 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2163 { 2164 struct dce_hwseq *hws = dc->hwseq; 2165 2166 if (pipe_ctx->stream_res.dsc) { 2167 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2168 2169 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2170 while (odm_pipe) { 2171 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2172 odm_pipe = odm_pipe->next_odm_pipe; 2173 } 2174 } 2175 } 2176 2177 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2178 { 2179 struct dc_dmdata_attributes attr = { 0 }; 2180 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2181 2182 attr.dmdata_mode = DMDATA_HW_MODE; 2183 attr.dmdata_size = 2184 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2185 attr.address.quad_part = 2186 pipe_ctx->stream->dmdata_address.quad_part; 2187 attr.dmdata_dl_delta = 0; 2188 attr.dmdata_qos_mode = 0; 2189 attr.dmdata_qos_level = 0; 2190 attr.dmdata_repeat = 1; /* always repeat */ 2191 attr.dmdata_updated = 1; 2192 attr.dmdata_sw_data = NULL; 2193 2194 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2195 } 2196 2197 void dcn20_init_vm_ctx( 2198 struct dce_hwseq *hws, 2199 struct dc *dc, 2200 struct dc_virtual_addr_space_config *va_config, 2201 int vmid) 2202 { 2203 struct dcn_hubbub_virt_addr_config config; 2204 2205 if (vmid == 0) { 2206 ASSERT(0); /* VMID cannot be 0 for vm context */ 2207 return; 2208 } 2209 2210 config.page_table_start_addr = va_config->page_table_start_addr; 2211 config.page_table_end_addr = va_config->page_table_end_addr; 2212 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2213 config.page_table_depth = va_config->page_table_depth; 2214 config.page_table_base_addr = va_config->page_table_base_addr; 2215 2216 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2217 } 2218 2219 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2220 { 2221 struct dcn_hubbub_phys_addr_config config; 2222 2223 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2224 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2225 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2226 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2227 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2228 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2229 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2230 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2231 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2232 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2233 2234 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2235 } 2236 2237 static bool patch_address_for_sbs_tb_stereo( 2238 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2239 { 2240 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2241 bool sec_split = pipe_ctx->top_pipe && 2242 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2243 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2244 (pipe_ctx->stream->timing.timing_3d_format == 2245 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2246 pipe_ctx->stream->timing.timing_3d_format == 2247 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2248 *addr = plane_state->address.grph_stereo.left_addr; 2249 plane_state->address.grph_stereo.left_addr = 2250 plane_state->address.grph_stereo.right_addr; 2251 return true; 2252 } 2253 2254 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2255 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2256 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2257 plane_state->address.grph_stereo.right_addr = 2258 plane_state->address.grph_stereo.left_addr; 2259 plane_state->address.grph_stereo.right_meta_addr = 2260 plane_state->address.grph_stereo.left_meta_addr; 2261 } 2262 return false; 2263 } 2264 2265 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2266 { 2267 bool addr_patched = false; 2268 PHYSICAL_ADDRESS_LOC addr; 2269 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2270 2271 if (plane_state == NULL) 2272 return; 2273 2274 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2275 2276 // Call Helper to track VMID use 2277 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2278 2279 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2280 pipe_ctx->plane_res.hubp, 2281 &plane_state->address, 2282 plane_state->flip_immediate); 2283 2284 plane_state->status.requested_address = plane_state->address; 2285 2286 if (plane_state->flip_immediate) 2287 plane_state->status.current_address = plane_state->address; 2288 2289 if (addr_patched) 2290 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2291 } 2292 2293 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2294 struct dc_link_settings *link_settings) 2295 { 2296 struct encoder_unblank_param params = {0}; 2297 struct dc_stream_state *stream = pipe_ctx->stream; 2298 struct dc_link *link = stream->link; 2299 struct dce_hwseq *hws = link->dc->hwseq; 2300 struct pipe_ctx *odm_pipe; 2301 2302 params.opp_cnt = 1; 2303 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2304 params.opp_cnt++; 2305 } 2306 /* only 3 items below are used by unblank */ 2307 params.timing = pipe_ctx->stream->timing; 2308 2309 params.link_settings.link_rate = link_settings->link_rate; 2310 2311 if (is_dp_128b_132b_signal(pipe_ctx)) { 2312 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2313 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2314 pipe_ctx->stream_res.hpo_dp_stream_enc, 2315 pipe_ctx->stream_res.tg->inst); 2316 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2317 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2318 params.timing.pix_clk_100hz /= 2; 2319 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2320 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2321 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2322 } 2323 2324 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2325 hws->funcs.edp_backlight_control(link, true); 2326 } 2327 } 2328 2329 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2330 { 2331 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2332 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2333 2334 if (start_line < 0) 2335 start_line = 0; 2336 2337 if (tg->funcs->setup_vertical_interrupt2) 2338 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2339 } 2340 2341 static void dcn20_reset_back_end_for_pipe( 2342 struct dc *dc, 2343 struct pipe_ctx *pipe_ctx, 2344 struct dc_state *context) 2345 { 2346 int i; 2347 struct dc_link *link = pipe_ctx->stream->link; 2348 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2349 2350 DC_LOGGER_INIT(dc->ctx->logger); 2351 if (pipe_ctx->stream_res.stream_enc == NULL) { 2352 pipe_ctx->stream = NULL; 2353 return; 2354 } 2355 2356 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2357 /* DPMS may already disable or */ 2358 /* dpms_off status is incorrect due to fastboot 2359 * feature. When system resume from S4 with second 2360 * screen only, the dpms_off would be true but 2361 * VBIOS lit up eDP, so check link status too. 2362 */ 2363 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2364 core_link_disable_stream(pipe_ctx); 2365 else if (pipe_ctx->stream_res.audio) 2366 dc->hwss.disable_audio_stream(pipe_ctx); 2367 2368 /* free acquired resources */ 2369 if (pipe_ctx->stream_res.audio) { 2370 /*disable az_endpoint*/ 2371 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2372 2373 /*free audio*/ 2374 if (dc->caps.dynamic_audio == true) { 2375 /*we have to dynamic arbitrate the audio endpoints*/ 2376 /*we free the resource, need reset is_audio_acquired*/ 2377 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2378 pipe_ctx->stream_res.audio, false); 2379 pipe_ctx->stream_res.audio = NULL; 2380 } 2381 } 2382 } 2383 else if (pipe_ctx->stream_res.dsc) { 2384 dp_set_dsc_enable(pipe_ctx, false); 2385 } 2386 2387 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2388 * back end share by all pipes and will be disable only when disable 2389 * parent pipe. 2390 */ 2391 if (pipe_ctx->top_pipe == NULL) { 2392 2393 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2394 2395 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2396 2397 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2398 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2399 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2400 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2401 2402 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2403 pipe_ctx->stream_res.tg->funcs->set_drr( 2404 pipe_ctx->stream_res.tg, NULL); 2405 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 2406 * the case where the same symclk is shared across multiple otg 2407 * instances 2408 */ 2409 link->phy_state.symclk_ref_cnts.otg = 0; 2410 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { 2411 link_hwss->disable_link_output(link, 2412 &pipe_ctx->link_res, pipe_ctx->stream->signal); 2413 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 2414 } 2415 } 2416 2417 for (i = 0; i < dc->res_pool->pipe_count; i++) 2418 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2419 break; 2420 2421 if (i == dc->res_pool->pipe_count) 2422 return; 2423 2424 pipe_ctx->stream = NULL; 2425 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2426 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2427 } 2428 2429 void dcn20_reset_hw_ctx_wrap( 2430 struct dc *dc, 2431 struct dc_state *context) 2432 { 2433 int i; 2434 struct dce_hwseq *hws = dc->hwseq; 2435 2436 /* Reset Back End*/ 2437 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2438 struct pipe_ctx *pipe_ctx_old = 2439 &dc->current_state->res_ctx.pipe_ctx[i]; 2440 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2441 2442 if (!pipe_ctx_old->stream) 2443 continue; 2444 2445 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2446 continue; 2447 2448 if (!pipe_ctx->stream || 2449 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2450 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2451 2452 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2453 if (hws->funcs.enable_stream_gating) 2454 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2455 if (old_clk) 2456 old_clk->funcs->cs_power_down(old_clk); 2457 } 2458 } 2459 } 2460 2461 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2462 { 2463 struct mpc *mpc = dc->res_pool->mpc; 2464 2465 // input to MPCC is always RGB, by default leave black_color at 0 2466 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2467 get_hdr_visual_confirm_color(pipe_ctx, color); 2468 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2469 get_surface_visual_confirm_color(pipe_ctx, color); 2470 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2471 get_mpctree_visual_confirm_color(pipe_ctx, color); 2472 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2473 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2474 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP) 2475 get_subvp_visual_confirm_color(dc, pipe_ctx, color); 2476 2477 if (mpc->funcs->set_bg_color) { 2478 memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color)); 2479 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2480 } 2481 } 2482 2483 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2484 { 2485 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2486 struct mpcc_blnd_cfg blnd_cfg = {0}; 2487 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2488 int mpcc_id; 2489 struct mpcc *new_mpcc; 2490 struct mpc *mpc = dc->res_pool->mpc; 2491 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2492 2493 blnd_cfg.overlap_only = false; 2494 blnd_cfg.global_gain = 0xff; 2495 2496 if (per_pixel_alpha) { 2497 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2498 if (pipe_ctx->plane_state->global_alpha) { 2499 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2500 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2501 } else { 2502 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2503 } 2504 } else { 2505 blnd_cfg.pre_multiplied_alpha = false; 2506 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2507 } 2508 2509 if (pipe_ctx->plane_state->global_alpha) 2510 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2511 else 2512 blnd_cfg.global_alpha = 0xff; 2513 2514 blnd_cfg.background_color_bpc = 4; 2515 blnd_cfg.bottom_gain_mode = 0; 2516 blnd_cfg.top_gain = 0x1f000; 2517 blnd_cfg.bottom_inside_gain = 0x1f000; 2518 blnd_cfg.bottom_outside_gain = 0x1f000; 2519 2520 if (pipe_ctx->plane_state->format 2521 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2522 blnd_cfg.pre_multiplied_alpha = false; 2523 2524 /* 2525 * TODO: remove hack 2526 * Note: currently there is a bug in init_hw such that 2527 * on resume from hibernate, BIOS sets up MPCC0, and 2528 * we do mpcc_remove but the mpcc cannot go to idle 2529 * after remove. This cause us to pick mpcc1 here, 2530 * which causes a pstate hang for yet unknown reason. 2531 */ 2532 mpcc_id = hubp->inst; 2533 2534 /* If there is no full update, don't need to touch MPC tree*/ 2535 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2536 !pipe_ctx->update_flags.bits.mpcc) { 2537 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2538 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2539 return; 2540 } 2541 2542 /* check if this MPCC is already being used */ 2543 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2544 /* remove MPCC if being used */ 2545 if (new_mpcc != NULL) 2546 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2547 else 2548 if (dc->debug.sanity_checks) 2549 mpc->funcs->assert_mpcc_idle_before_connect( 2550 dc->res_pool->mpc, mpcc_id); 2551 2552 /* Call MPC to insert new plane */ 2553 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2554 mpc_tree_params, 2555 &blnd_cfg, 2556 NULL, 2557 NULL, 2558 hubp->inst, 2559 mpcc_id); 2560 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2561 2562 ASSERT(new_mpcc != NULL); 2563 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2564 hubp->mpcc_id = mpcc_id; 2565 } 2566 2567 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2568 { 2569 enum dc_lane_count lane_count = 2570 pipe_ctx->stream->link->cur_link_settings.lane_count; 2571 2572 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2573 struct dc_link *link = pipe_ctx->stream->link; 2574 2575 uint32_t active_total_with_borders; 2576 uint32_t early_control = 0; 2577 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2578 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2579 struct dc *dc = pipe_ctx->stream->ctx->dc; 2580 2581 if (is_dp_128b_132b_signal(pipe_ctx)) { 2582 if (dc->hwseq->funcs.setup_hpo_hw_control) 2583 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2584 } 2585 2586 link_hwss->setup_stream_encoder(pipe_ctx); 2587 2588 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2589 if (dc->hwss.program_dmdata_engine) 2590 dc->hwss.program_dmdata_engine(pipe_ctx); 2591 } 2592 2593 dc->hwss.update_info_frame(pipe_ctx); 2594 2595 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2596 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2597 2598 /* enable early control to avoid corruption on DP monitor*/ 2599 active_total_with_borders = 2600 timing->h_addressable 2601 + timing->h_border_left 2602 + timing->h_border_right; 2603 2604 if (lane_count != 0) 2605 early_control = active_total_with_borders % lane_count; 2606 2607 if (early_control == 0) 2608 early_control = lane_count; 2609 2610 tg->funcs->set_early_control(tg, early_control); 2611 2612 if (dc->hwseq->funcs.set_pixels_per_cycle) 2613 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); 2614 2615 /* enable audio only within mode set */ 2616 if (pipe_ctx->stream_res.audio != NULL) { 2617 if (is_dp_128b_132b_signal(pipe_ctx)) 2618 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc); 2619 else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2620 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2621 } 2622 } 2623 2624 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2625 { 2626 struct dc_stream_state *stream = pipe_ctx->stream; 2627 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2628 bool enable = false; 2629 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2630 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2631 ? dmdata_dp 2632 : dmdata_hdmi; 2633 2634 /* if using dynamic meta, don't set up generic infopackets */ 2635 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2636 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2637 enable = true; 2638 } 2639 2640 if (!hubp) 2641 return; 2642 2643 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2644 return; 2645 2646 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2647 hubp->inst, mode); 2648 } 2649 2650 void dcn20_fpga_init_hw(struct dc *dc) 2651 { 2652 int i, j; 2653 struct dce_hwseq *hws = dc->hwseq; 2654 struct resource_pool *res_pool = dc->res_pool; 2655 struct dc_state *context = dc->current_state; 2656 2657 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2658 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2659 2660 // Initialize the dccg 2661 if (res_pool->dccg->funcs->dccg_init) 2662 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2663 2664 //Enable ability to power gate / don't force power on permanently 2665 hws->funcs.enable_power_gating_plane(hws, true); 2666 2667 // Specific to FPGA dccg and registers 2668 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2669 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2670 2671 hws->funcs.dccg_init(hws); 2672 2673 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2674 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2675 if (REG(REFCLK_CNTL)) 2676 REG_WRITE(REFCLK_CNTL, 0); 2677 // 2678 2679 2680 /* Blank pixel data with OPP DPG */ 2681 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2682 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2683 2684 if (tg->funcs->is_tg_enabled(tg)) 2685 dcn20_init_blank(dc, tg); 2686 } 2687 2688 for (i = 0; i < res_pool->timing_generator_count; i++) { 2689 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2690 2691 if (tg->funcs->is_tg_enabled(tg)) 2692 tg->funcs->lock(tg); 2693 } 2694 2695 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2696 struct dpp *dpp = res_pool->dpps[i]; 2697 2698 dpp->funcs->dpp_reset(dpp); 2699 } 2700 2701 /* Reset all MPCC muxes */ 2702 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2703 2704 /* initialize OPP mpc_tree parameter */ 2705 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2706 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2707 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2708 for (j = 0; j < MAX_PIPES; j++) 2709 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2710 } 2711 2712 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2713 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2714 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2715 struct hubp *hubp = dc->res_pool->hubps[i]; 2716 struct dpp *dpp = dc->res_pool->dpps[i]; 2717 2718 pipe_ctx->stream_res.tg = tg; 2719 pipe_ctx->pipe_idx = i; 2720 2721 pipe_ctx->plane_res.hubp = hubp; 2722 pipe_ctx->plane_res.dpp = dpp; 2723 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2724 hubp->mpcc_id = dpp->inst; 2725 hubp->opp_id = OPP_ID_INVALID; 2726 hubp->power_gated = false; 2727 pipe_ctx->stream_res.opp = NULL; 2728 2729 hubp->funcs->hubp_init(hubp); 2730 2731 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2732 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2733 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2734 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2735 /*to do*/ 2736 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2737 } 2738 2739 /* initialize DWB pointer to MCIF_WB */ 2740 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2741 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2742 2743 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2744 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2745 2746 if (tg->funcs->is_tg_enabled(tg)) 2747 tg->funcs->unlock(tg); 2748 } 2749 2750 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2751 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2752 2753 dc->hwss.disable_plane(dc, pipe_ctx); 2754 2755 pipe_ctx->stream_res.tg = NULL; 2756 pipe_ctx->plane_res.hubp = NULL; 2757 } 2758 2759 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2760 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2761 2762 tg->funcs->tg_init(tg); 2763 } 2764 2765 if (dc->res_pool->hubbub->funcs->init_crb) 2766 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2767 } 2768 #ifndef TRIM_FSFT 2769 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2770 struct dc_crtc_timing *timing, 2771 unsigned int max_input_rate_in_khz) 2772 { 2773 unsigned int old_v_front_porch; 2774 unsigned int old_v_total; 2775 unsigned int max_input_rate_in_100hz; 2776 unsigned long long new_v_total; 2777 2778 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2779 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2780 return false; 2781 2782 old_v_total = timing->v_total; 2783 old_v_front_porch = timing->v_front_porch; 2784 2785 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2786 timing->pix_clk_100hz = max_input_rate_in_100hz; 2787 2788 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2789 2790 timing->v_total = new_v_total; 2791 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2792 return true; 2793 } 2794 #endif 2795 2796 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2797 struct pipe_ctx *pipe_ctx, 2798 enum controller_dp_test_pattern test_pattern, 2799 enum controller_dp_color_space color_space, 2800 enum dc_color_depth color_depth, 2801 const struct tg_color *solid_color, 2802 int width, int height, int offset) 2803 { 2804 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2805 color_space, color_depth, solid_color, width, height, offset); 2806 } 2807