1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "vm_helper.h" 50 #include "dccg.h" 51 #include "dc_dmub_srv.h" 52 #include "dce/dmub_hw_lock_mgr.h" 53 #include "hw_sequencer.h" 54 #include "dpcd_defs.h" 55 #include "inc/link_enc_cfg.h" 56 #include "link_hwss.h" 57 #include "link.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 #define CTX \ 62 hws->ctx 63 #define REG(reg)\ 64 hws->regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 static int find_free_gsl_group(const struct dc *dc) 71 { 72 if (dc->res_pool->gsl_groups.gsl_0 == 0) 73 return 1; 74 if (dc->res_pool->gsl_groups.gsl_1 == 0) 75 return 2; 76 if (dc->res_pool->gsl_groups.gsl_2 == 0) 77 return 3; 78 79 return 0; 80 } 81 82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 83 * This is only used to lock pipes in pipe splitting case with immediate flip 84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 85 * so we get tearing with freesync since we cannot flip multiple pipes 86 * atomically. 87 * We use GSL for this: 88 * - immediate flip: find first available GSL group if not already assigned 89 * program gsl with that group, set current OTG as master 90 * and always us 0x4 = AND of flip_ready from all pipes 91 * - vsync flip: disable GSL if used 92 * 93 * Groups in stream_res are stored as +1 from HW registers, i.e. 94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 95 * Using a magic value like -1 would require tracking all inits/resets 96 */ 97 static void dcn20_setup_gsl_group_as_lock( 98 const struct dc *dc, 99 struct pipe_ctx *pipe_ctx, 100 bool enable) 101 { 102 struct gsl_params gsl; 103 int group_idx; 104 105 memset(&gsl, 0, sizeof(struct gsl_params)); 106 107 if (enable) { 108 /* return if group already assigned since GSL was set up 109 * for vsync flip, we would unassign so it can't be "left over" 110 */ 111 if (pipe_ctx->stream_res.gsl_group > 0) 112 return; 113 114 group_idx = find_free_gsl_group(dc); 115 ASSERT(group_idx != 0); 116 pipe_ctx->stream_res.gsl_group = group_idx; 117 118 /* set gsl group reg field and mark resource used */ 119 switch (group_idx) { 120 case 1: 121 gsl.gsl0_en = 1; 122 dc->res_pool->gsl_groups.gsl_0 = 1; 123 break; 124 case 2: 125 gsl.gsl1_en = 1; 126 dc->res_pool->gsl_groups.gsl_1 = 1; 127 break; 128 case 3: 129 gsl.gsl2_en = 1; 130 dc->res_pool->gsl_groups.gsl_2 = 1; 131 break; 132 default: 133 BREAK_TO_DEBUGGER(); 134 return; // invalid case 135 } 136 gsl.gsl_master_en = 1; 137 } else { 138 group_idx = pipe_ctx->stream_res.gsl_group; 139 if (group_idx == 0) 140 return; // if not in use, just return 141 142 pipe_ctx->stream_res.gsl_group = 0; 143 144 /* unset gsl group reg field and mark resource free */ 145 switch (group_idx) { 146 case 1: 147 gsl.gsl0_en = 0; 148 dc->res_pool->gsl_groups.gsl_0 = 0; 149 break; 150 case 2: 151 gsl.gsl1_en = 0; 152 dc->res_pool->gsl_groups.gsl_1 = 0; 153 break; 154 case 3: 155 gsl.gsl2_en = 0; 156 dc->res_pool->gsl_groups.gsl_2 = 0; 157 break; 158 default: 159 BREAK_TO_DEBUGGER(); 160 return; 161 } 162 gsl.gsl_master_en = 0; 163 } 164 165 /* at this point we want to program whether it's to enable or disable */ 166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 168 pipe_ctx->stream_res.tg->funcs->set_gsl( 169 pipe_ctx->stream_res.tg, 170 &gsl); 171 172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 174 } else 175 BREAK_TO_DEBUGGER(); 176 } 177 178 void dcn20_set_flip_control_gsl( 179 struct pipe_ctx *pipe_ctx, 180 bool flip_immediate) 181 { 182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 184 pipe_ctx->plane_res.hubp, flip_immediate); 185 186 } 187 188 void dcn20_enable_power_gating_plane( 189 struct dce_hwseq *hws, 190 bool enable) 191 { 192 bool force_on = true; /* disable power gating */ 193 194 if (enable) 195 force_on = false; 196 197 /* DCHUBP0/1/2/3/4/5 */ 198 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 199 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 200 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 201 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 202 if (REG(DOMAIN8_PG_CONFIG)) 203 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 204 if (REG(DOMAIN10_PG_CONFIG)) 205 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 206 207 /* DPP0/1/2/3/4/5 */ 208 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 209 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 210 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 211 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 212 if (REG(DOMAIN9_PG_CONFIG)) 213 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 214 if (REG(DOMAIN11_PG_CONFIG)) 215 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 216 217 /* DCS0/1/2/3/4/5 */ 218 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 219 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 220 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 221 if (REG(DOMAIN19_PG_CONFIG)) 222 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 223 if (REG(DOMAIN20_PG_CONFIG)) 224 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 225 if (REG(DOMAIN21_PG_CONFIG)) 226 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 227 } 228 229 void dcn20_dccg_init(struct dce_hwseq *hws) 230 { 231 /* 232 * set MICROSECOND_TIME_BASE_DIV 233 * 100Mhz refclk -> 0x120264 234 * 27Mhz refclk -> 0x12021b 235 * 48Mhz refclk -> 0x120230 236 * 237 */ 238 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 239 240 /* 241 * set MILLISECOND_TIME_BASE_DIV 242 * 100Mhz refclk -> 0x1186a0 243 * 27Mhz refclk -> 0x106978 244 * 48Mhz refclk -> 0x10bb80 245 * 246 */ 247 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 248 249 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 250 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 251 } 252 253 void dcn20_disable_vga( 254 struct dce_hwseq *hws) 255 { 256 REG_WRITE(D1VGA_CONTROL, 0); 257 REG_WRITE(D2VGA_CONTROL, 0); 258 REG_WRITE(D3VGA_CONTROL, 0); 259 REG_WRITE(D4VGA_CONTROL, 0); 260 REG_WRITE(D5VGA_CONTROL, 0); 261 REG_WRITE(D6VGA_CONTROL, 0); 262 } 263 264 void dcn20_program_triple_buffer( 265 const struct dc *dc, 266 struct pipe_ctx *pipe_ctx, 267 bool enable_triple_buffer) 268 { 269 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 270 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 271 pipe_ctx->plane_res.hubp, 272 enable_triple_buffer); 273 } 274 } 275 276 /* Blank pixel data during initialization */ 277 void dcn20_init_blank( 278 struct dc *dc, 279 struct timing_generator *tg) 280 { 281 struct dce_hwseq *hws = dc->hwseq; 282 enum dc_color_space color_space; 283 struct tg_color black_color = {0}; 284 struct output_pixel_processor *opp = NULL; 285 struct output_pixel_processor *bottom_opp = NULL; 286 uint32_t num_opps, opp_id_src0, opp_id_src1; 287 uint32_t otg_active_width, otg_active_height; 288 289 /* program opp dpg blank color */ 290 color_space = COLOR_SPACE_SRGB; 291 color_space_to_black_color(dc, color_space, &black_color); 292 293 /* get the OTG active size */ 294 tg->funcs->get_otg_active_size(tg, 295 &otg_active_width, 296 &otg_active_height); 297 298 /* get the OPTC source */ 299 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 300 301 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 302 ASSERT(false); 303 return; 304 } 305 opp = dc->res_pool->opps[opp_id_src0]; 306 307 if (num_opps == 2) { 308 otg_active_width = otg_active_width / 2; 309 310 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 311 ASSERT(false); 312 return; 313 } 314 bottom_opp = dc->res_pool->opps[opp_id_src1]; 315 } 316 317 opp->funcs->opp_set_disp_pattern_generator( 318 opp, 319 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 320 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 321 COLOR_DEPTH_UNDEFINED, 322 &black_color, 323 otg_active_width, 324 otg_active_height, 325 0); 326 327 if (num_opps == 2) { 328 bottom_opp->funcs->opp_set_disp_pattern_generator( 329 bottom_opp, 330 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 331 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 332 COLOR_DEPTH_UNDEFINED, 333 &black_color, 334 otg_active_width, 335 otg_active_height, 336 0); 337 } 338 339 hws->funcs.wait_for_blank_complete(opp); 340 } 341 342 void dcn20_dsc_pg_control( 343 struct dce_hwseq *hws, 344 unsigned int dsc_inst, 345 bool power_on) 346 { 347 uint32_t power_gate = power_on ? 0 : 1; 348 uint32_t pwr_status = power_on ? 0 : 2; 349 uint32_t org_ip_request_cntl = 0; 350 351 if (hws->ctx->dc->debug.disable_dsc_power_gate) 352 return; 353 354 if (REG(DOMAIN16_PG_CONFIG) == 0) 355 return; 356 357 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 358 if (org_ip_request_cntl == 0) 359 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 360 361 switch (dsc_inst) { 362 case 0: /* DSC0 */ 363 REG_UPDATE(DOMAIN16_PG_CONFIG, 364 DOMAIN16_POWER_GATE, power_gate); 365 366 REG_WAIT(DOMAIN16_PG_STATUS, 367 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 368 1, 1000); 369 break; 370 case 1: /* DSC1 */ 371 REG_UPDATE(DOMAIN17_PG_CONFIG, 372 DOMAIN17_POWER_GATE, power_gate); 373 374 REG_WAIT(DOMAIN17_PG_STATUS, 375 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 376 1, 1000); 377 break; 378 case 2: /* DSC2 */ 379 REG_UPDATE(DOMAIN18_PG_CONFIG, 380 DOMAIN18_POWER_GATE, power_gate); 381 382 REG_WAIT(DOMAIN18_PG_STATUS, 383 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 384 1, 1000); 385 break; 386 case 3: /* DSC3 */ 387 REG_UPDATE(DOMAIN19_PG_CONFIG, 388 DOMAIN19_POWER_GATE, power_gate); 389 390 REG_WAIT(DOMAIN19_PG_STATUS, 391 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 392 1, 1000); 393 break; 394 case 4: /* DSC4 */ 395 REG_UPDATE(DOMAIN20_PG_CONFIG, 396 DOMAIN20_POWER_GATE, power_gate); 397 398 REG_WAIT(DOMAIN20_PG_STATUS, 399 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 400 1, 1000); 401 break; 402 case 5: /* DSC5 */ 403 REG_UPDATE(DOMAIN21_PG_CONFIG, 404 DOMAIN21_POWER_GATE, power_gate); 405 406 REG_WAIT(DOMAIN21_PG_STATUS, 407 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 408 1, 1000); 409 break; 410 default: 411 BREAK_TO_DEBUGGER(); 412 break; 413 } 414 415 if (org_ip_request_cntl == 0) 416 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 417 } 418 419 void dcn20_dpp_pg_control( 420 struct dce_hwseq *hws, 421 unsigned int dpp_inst, 422 bool power_on) 423 { 424 uint32_t power_gate = power_on ? 0 : 1; 425 uint32_t pwr_status = power_on ? 0 : 2; 426 427 if (hws->ctx->dc->debug.disable_dpp_power_gate) 428 return; 429 if (REG(DOMAIN1_PG_CONFIG) == 0) 430 return; 431 432 switch (dpp_inst) { 433 case 0: /* DPP0 */ 434 REG_UPDATE(DOMAIN1_PG_CONFIG, 435 DOMAIN1_POWER_GATE, power_gate); 436 437 REG_WAIT(DOMAIN1_PG_STATUS, 438 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 439 1, 1000); 440 break; 441 case 1: /* DPP1 */ 442 REG_UPDATE(DOMAIN3_PG_CONFIG, 443 DOMAIN3_POWER_GATE, power_gate); 444 445 REG_WAIT(DOMAIN3_PG_STATUS, 446 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 447 1, 1000); 448 break; 449 case 2: /* DPP2 */ 450 REG_UPDATE(DOMAIN5_PG_CONFIG, 451 DOMAIN5_POWER_GATE, power_gate); 452 453 REG_WAIT(DOMAIN5_PG_STATUS, 454 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 455 1, 1000); 456 break; 457 case 3: /* DPP3 */ 458 REG_UPDATE(DOMAIN7_PG_CONFIG, 459 DOMAIN7_POWER_GATE, power_gate); 460 461 REG_WAIT(DOMAIN7_PG_STATUS, 462 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 463 1, 1000); 464 break; 465 case 4: /* DPP4 */ 466 REG_UPDATE(DOMAIN9_PG_CONFIG, 467 DOMAIN9_POWER_GATE, power_gate); 468 469 REG_WAIT(DOMAIN9_PG_STATUS, 470 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 471 1, 1000); 472 break; 473 case 5: /* DPP5 */ 474 /* 475 * Do not power gate DPP5, should be left at HW default, power on permanently. 476 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 477 * reset. 478 * REG_UPDATE(DOMAIN11_PG_CONFIG, 479 * DOMAIN11_POWER_GATE, power_gate); 480 * 481 * REG_WAIT(DOMAIN11_PG_STATUS, 482 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 483 * 1, 1000); 484 */ 485 break; 486 default: 487 BREAK_TO_DEBUGGER(); 488 break; 489 } 490 } 491 492 493 void dcn20_hubp_pg_control( 494 struct dce_hwseq *hws, 495 unsigned int hubp_inst, 496 bool power_on) 497 { 498 uint32_t power_gate = power_on ? 0 : 1; 499 uint32_t pwr_status = power_on ? 0 : 2; 500 501 if (hws->ctx->dc->debug.disable_hubp_power_gate) 502 return; 503 if (REG(DOMAIN0_PG_CONFIG) == 0) 504 return; 505 506 switch (hubp_inst) { 507 case 0: /* DCHUBP0 */ 508 REG_UPDATE(DOMAIN0_PG_CONFIG, 509 DOMAIN0_POWER_GATE, power_gate); 510 511 REG_WAIT(DOMAIN0_PG_STATUS, 512 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 513 1, 1000); 514 break; 515 case 1: /* DCHUBP1 */ 516 REG_UPDATE(DOMAIN2_PG_CONFIG, 517 DOMAIN2_POWER_GATE, power_gate); 518 519 REG_WAIT(DOMAIN2_PG_STATUS, 520 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 521 1, 1000); 522 break; 523 case 2: /* DCHUBP2 */ 524 REG_UPDATE(DOMAIN4_PG_CONFIG, 525 DOMAIN4_POWER_GATE, power_gate); 526 527 REG_WAIT(DOMAIN4_PG_STATUS, 528 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 529 1, 1000); 530 break; 531 case 3: /* DCHUBP3 */ 532 REG_UPDATE(DOMAIN6_PG_CONFIG, 533 DOMAIN6_POWER_GATE, power_gate); 534 535 REG_WAIT(DOMAIN6_PG_STATUS, 536 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 537 1, 1000); 538 break; 539 case 4: /* DCHUBP4 */ 540 REG_UPDATE(DOMAIN8_PG_CONFIG, 541 DOMAIN8_POWER_GATE, power_gate); 542 543 REG_WAIT(DOMAIN8_PG_STATUS, 544 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 545 1, 1000); 546 break; 547 case 5: /* DCHUBP5 */ 548 /* 549 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 550 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 551 * reset. 552 * REG_UPDATE(DOMAIN10_PG_CONFIG, 553 * DOMAIN10_POWER_GATE, power_gate); 554 * 555 * REG_WAIT(DOMAIN10_PG_STATUS, 556 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 557 * 1, 1000); 558 */ 559 break; 560 default: 561 BREAK_TO_DEBUGGER(); 562 break; 563 } 564 } 565 566 567 /* disable HW used by plane. 568 * note: cannot disable until disconnect is complete 569 */ 570 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 571 { 572 struct dce_hwseq *hws = dc->hwseq; 573 struct hubp *hubp = pipe_ctx->plane_res.hubp; 574 struct dpp *dpp = pipe_ctx->plane_res.dpp; 575 576 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 577 578 /* In flip immediate with pipe splitting case GSL is used for 579 * synchronization so we must disable it when the plane is disabled. 580 */ 581 if (pipe_ctx->stream_res.gsl_group != 0) 582 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 583 584 if (hubp->funcs->hubp_update_mall_sel) 585 hubp->funcs->hubp_update_mall_sel(hubp, 0, false); 586 587 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 588 589 hubp->funcs->hubp_clk_cntl(hubp, false); 590 591 dpp->funcs->dpp_dppclk_control(dpp, false, false); 592 593 hubp->power_gated = true; 594 595 hws->funcs.plane_atomic_power_down(dc, 596 pipe_ctx->plane_res.dpp, 597 pipe_ctx->plane_res.hubp); 598 599 pipe_ctx->stream = NULL; 600 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 601 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 602 pipe_ctx->top_pipe = NULL; 603 pipe_ctx->bottom_pipe = NULL; 604 pipe_ctx->plane_state = NULL; 605 } 606 607 608 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 609 { 610 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom; 611 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; 612 613 DC_LOGGER_INIT(dc->ctx->logger); 614 615 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 616 return; 617 618 dcn20_plane_atomic_disable(dc, pipe_ctx); 619 620 /* Turn back off the phantom OTG after the phantom plane is fully disabled 621 */ 622 if (is_phantom) 623 if (tg && tg->funcs->disable_phantom_crtc) 624 tg->funcs->disable_phantom_crtc(tg); 625 626 DC_LOG_DC("Power down front end %d\n", 627 pipe_ctx->pipe_idx); 628 } 629 630 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 631 { 632 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 633 } 634 635 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 636 int opp_cnt) 637 { 638 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 639 int flow_ctrl_cnt; 640 641 if (opp_cnt >= 2) 642 hblank_halved = true; 643 644 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 645 stream->timing.h_border_left - 646 stream->timing.h_border_right; 647 648 if (hblank_halved) 649 flow_ctrl_cnt /= 2; 650 651 /* ODM combine 4:1 case */ 652 if (opp_cnt == 4) 653 flow_ctrl_cnt /= 2; 654 655 return flow_ctrl_cnt; 656 } 657 658 enum dc_status dcn20_enable_stream_timing( 659 struct pipe_ctx *pipe_ctx, 660 struct dc_state *context, 661 struct dc *dc) 662 { 663 struct dce_hwseq *hws = dc->hwseq; 664 struct dc_stream_state *stream = pipe_ctx->stream; 665 struct drr_params params = {0}; 666 unsigned int event_triggers = 0; 667 struct pipe_ctx *odm_pipe; 668 int opp_cnt = 1; 669 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 670 bool interlace = stream->timing.flags.INTERLACE; 671 int i; 672 struct mpc_dwb_flow_control flow_control; 673 struct mpc *mpc = dc->res_pool->mpc; 674 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 675 unsigned int k1_div = PIXEL_RATE_DIV_NA; 676 unsigned int k2_div = PIXEL_RATE_DIV_NA; 677 678 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 679 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 680 681 dc->res_pool->dccg->funcs->set_pixel_rate_div( 682 dc->res_pool->dccg, 683 pipe_ctx->stream_res.tg->inst, 684 k1_div, k2_div); 685 } 686 /* by upper caller loop, pipe0 is parent pipe and be called first. 687 * back end is set up by for pipe0. Other children pipe share back end 688 * with pipe 0. No program is needed. 689 */ 690 if (pipe_ctx->top_pipe != NULL) 691 return DC_OK; 692 693 /* TODO check if timing_changed, disable stream if timing changed */ 694 695 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 696 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 697 opp_cnt++; 698 } 699 700 if (opp_cnt > 1) 701 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 702 pipe_ctx->stream_res.tg, 703 opp_inst, opp_cnt, 704 &pipe_ctx->stream->timing); 705 706 /* HW program guide assume display already disable 707 * by unplug sequence. OTG assume stop. 708 */ 709 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 710 711 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 712 pipe_ctx->clock_source, 713 &pipe_ctx->stream_res.pix_clk_params, 714 link_dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 715 &pipe_ctx->pll_settings)) { 716 BREAK_TO_DEBUGGER(); 717 return DC_ERROR_UNEXPECTED; 718 } 719 720 if (dc_is_hdmi_tmds_signal(stream->signal)) { 721 stream->link->phy_state.symclk_ref_cnts.otg = 1; 722 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 723 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 724 else 725 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 726 } 727 728 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 729 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 730 731 pipe_ctx->stream_res.tg->funcs->program_timing( 732 pipe_ctx->stream_res.tg, 733 &stream->timing, 734 pipe_ctx->pipe_dlg_param.vready_offset, 735 pipe_ctx->pipe_dlg_param.vstartup_start, 736 pipe_ctx->pipe_dlg_param.vupdate_offset, 737 pipe_ctx->pipe_dlg_param.vupdate_width, 738 pipe_ctx->stream->signal, 739 true); 740 741 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 742 flow_control.flow_ctrl_mode = 0; 743 flow_control.flow_ctrl_cnt0 = 0x80; 744 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 745 if (mpc->funcs->set_out_rate_control) { 746 for (i = 0; i < opp_cnt; ++i) { 747 mpc->funcs->set_out_rate_control( 748 mpc, opp_inst[i], 749 true, 750 rate_control_2x_pclk, 751 &flow_control); 752 } 753 } 754 755 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 756 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 757 odm_pipe->stream_res.opp, 758 true); 759 760 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 761 pipe_ctx->stream_res.opp, 762 true); 763 764 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 765 766 /* VTG is within DCHUB command block. DCFCLK is always on */ 767 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 768 BREAK_TO_DEBUGGER(); 769 return DC_ERROR_UNEXPECTED; 770 } 771 772 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 773 774 params.vertical_total_min = stream->adjust.v_total_min; 775 params.vertical_total_max = stream->adjust.v_total_max; 776 params.vertical_total_mid = stream->adjust.v_total_mid; 777 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 778 if (pipe_ctx->stream_res.tg->funcs->set_drr) 779 pipe_ctx->stream_res.tg->funcs->set_drr( 780 pipe_ctx->stream_res.tg, ¶ms); 781 782 // DRR should set trigger event to monitor surface update event 783 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 784 event_triggers = 0x80; 785 /* Event triggers and num frames initialized for DRR, but can be 786 * later updated for PSR use. Note DRR trigger events are generated 787 * regardless of whether num frames met. 788 */ 789 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 790 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 791 pipe_ctx->stream_res.tg, event_triggers, 2); 792 793 /* TODO program crtc source select for non-virtual signal*/ 794 /* TODO program FMT */ 795 /* TODO setup link_enc */ 796 /* TODO set stream attributes */ 797 /* TODO program audio */ 798 /* TODO enable stream if timing changed */ 799 /* TODO unblank stream if DP */ 800 801 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 802 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 803 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 804 } 805 return DC_OK; 806 } 807 808 void dcn20_program_output_csc(struct dc *dc, 809 struct pipe_ctx *pipe_ctx, 810 enum dc_color_space colorspace, 811 uint16_t *matrix, 812 int opp_id) 813 { 814 struct mpc *mpc = dc->res_pool->mpc; 815 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 816 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 817 818 if (mpc->funcs->power_on_mpc_mem_pwr) 819 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 820 821 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 822 if (mpc->funcs->set_output_csc != NULL) 823 mpc->funcs->set_output_csc(mpc, 824 opp_id, 825 matrix, 826 ocsc_mode); 827 } else { 828 if (mpc->funcs->set_ocsc_default != NULL) 829 mpc->funcs->set_ocsc_default(mpc, 830 opp_id, 831 colorspace, 832 ocsc_mode); 833 } 834 } 835 836 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 837 const struct dc_stream_state *stream) 838 { 839 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 840 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 841 struct pwl_params *params = NULL; 842 /* 843 * program OGAM only for the top pipe 844 * if there is a pipe split then fix diagnostic is required: 845 * how to pass OGAM parameter for stream. 846 * if programming for all pipes is required then remove condition 847 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 848 */ 849 if (mpc->funcs->power_on_mpc_mem_pwr) 850 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 851 if (pipe_ctx->top_pipe == NULL 852 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 853 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 854 params = &stream->out_transfer_func->pwl; 855 else if (pipe_ctx->stream->out_transfer_func->type == 856 TF_TYPE_DISTRIBUTED_POINTS && 857 cm_helper_translate_curve_to_hw_format( 858 stream->out_transfer_func, 859 &mpc->blender_params, false)) 860 params = &mpc->blender_params; 861 /* 862 * there is no ROM 863 */ 864 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 865 BREAK_TO_DEBUGGER(); 866 } 867 /* 868 * if above if is not executed then 'params' equal to 0 and set in bypass 869 */ 870 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 871 872 return true; 873 } 874 875 bool dcn20_set_blend_lut( 876 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 877 { 878 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 879 bool result = true; 880 struct pwl_params *blend_lut = NULL; 881 882 if (plane_state->blend_tf) { 883 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 884 blend_lut = &plane_state->blend_tf->pwl; 885 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 886 cm_helper_translate_curve_to_hw_format( 887 plane_state->blend_tf, 888 &dpp_base->regamma_params, false); 889 blend_lut = &dpp_base->regamma_params; 890 } 891 } 892 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 893 894 return result; 895 } 896 897 bool dcn20_set_shaper_3dlut( 898 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 899 { 900 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 901 bool result = true; 902 struct pwl_params *shaper_lut = NULL; 903 904 if (plane_state->in_shaper_func) { 905 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 906 shaper_lut = &plane_state->in_shaper_func->pwl; 907 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 908 cm_helper_translate_curve_to_hw_format( 909 plane_state->in_shaper_func, 910 &dpp_base->shaper_params, true); 911 shaper_lut = &dpp_base->shaper_params; 912 } 913 } 914 915 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 916 if (plane_state->lut3d_func && 917 plane_state->lut3d_func->state.bits.initialized == 1) 918 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 919 &plane_state->lut3d_func->lut_3d); 920 else 921 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 922 923 return result; 924 } 925 926 bool dcn20_set_input_transfer_func(struct dc *dc, 927 struct pipe_ctx *pipe_ctx, 928 const struct dc_plane_state *plane_state) 929 { 930 struct dce_hwseq *hws = dc->hwseq; 931 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 932 const struct dc_transfer_func *tf = NULL; 933 bool result = true; 934 bool use_degamma_ram = false; 935 936 if (dpp_base == NULL || plane_state == NULL) 937 return false; 938 939 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 940 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 941 942 if (plane_state->in_transfer_func) 943 tf = plane_state->in_transfer_func; 944 945 946 if (tf == NULL) { 947 dpp_base->funcs->dpp_set_degamma(dpp_base, 948 IPP_DEGAMMA_MODE_BYPASS); 949 return true; 950 } 951 952 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 953 use_degamma_ram = true; 954 955 if (use_degamma_ram == true) { 956 if (tf->type == TF_TYPE_HWPWL) 957 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 958 &tf->pwl); 959 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 960 cm_helper_translate_curve_to_degamma_hw_format(tf, 961 &dpp_base->degamma_params); 962 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 963 &dpp_base->degamma_params); 964 } 965 return true; 966 } 967 /* handle here the optimized cases when de-gamma ROM could be used. 968 * 969 */ 970 if (tf->type == TF_TYPE_PREDEFINED) { 971 switch (tf->tf) { 972 case TRANSFER_FUNCTION_SRGB: 973 dpp_base->funcs->dpp_set_degamma(dpp_base, 974 IPP_DEGAMMA_MODE_HW_sRGB); 975 break; 976 case TRANSFER_FUNCTION_BT709: 977 dpp_base->funcs->dpp_set_degamma(dpp_base, 978 IPP_DEGAMMA_MODE_HW_xvYCC); 979 break; 980 case TRANSFER_FUNCTION_LINEAR: 981 dpp_base->funcs->dpp_set_degamma(dpp_base, 982 IPP_DEGAMMA_MODE_BYPASS); 983 break; 984 case TRANSFER_FUNCTION_PQ: 985 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 986 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 987 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 988 result = true; 989 break; 990 default: 991 result = false; 992 break; 993 } 994 } else if (tf->type == TF_TYPE_BYPASS) 995 dpp_base->funcs->dpp_set_degamma(dpp_base, 996 IPP_DEGAMMA_MODE_BYPASS); 997 else { 998 /* 999 * if we are here, we did not handle correctly. 1000 * fix is required for this use case 1001 */ 1002 BREAK_TO_DEBUGGER(); 1003 dpp_base->funcs->dpp_set_degamma(dpp_base, 1004 IPP_DEGAMMA_MODE_BYPASS); 1005 } 1006 1007 return result; 1008 } 1009 1010 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1011 { 1012 struct pipe_ctx *odm_pipe; 1013 int opp_cnt = 1; 1014 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 1015 1016 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1017 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 1018 opp_cnt++; 1019 } 1020 1021 if (opp_cnt > 1) 1022 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1023 pipe_ctx->stream_res.tg, 1024 opp_inst, opp_cnt, 1025 &pipe_ctx->stream->timing); 1026 else 1027 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1028 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1029 } 1030 1031 void dcn20_blank_pixel_data( 1032 struct dc *dc, 1033 struct pipe_ctx *pipe_ctx, 1034 bool blank) 1035 { 1036 struct tg_color black_color = {0}; 1037 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1038 struct dc_stream_state *stream = pipe_ctx->stream; 1039 enum dc_color_space color_space = stream->output_color_space; 1040 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1041 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1042 struct pipe_ctx *odm_pipe; 1043 int odm_cnt = 1; 1044 1045 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1046 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1047 1048 if (stream->link->test_pattern_enabled) 1049 return; 1050 1051 /* get opp dpg blank color */ 1052 color_space_to_black_color(dc, color_space, &black_color); 1053 1054 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1055 odm_cnt++; 1056 1057 width = width / odm_cnt; 1058 1059 if (blank) { 1060 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1061 1062 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1063 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1064 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1065 } 1066 } else { 1067 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1068 } 1069 1070 dc->hwss.set_disp_pattern_generator(dc, 1071 pipe_ctx, 1072 test_pattern, 1073 test_pattern_color_space, 1074 stream->timing.display_color_depth, 1075 &black_color, 1076 width, 1077 height, 1078 0); 1079 1080 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1081 dc->hwss.set_disp_pattern_generator(dc, 1082 odm_pipe, 1083 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1084 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1085 test_pattern_color_space, 1086 stream->timing.display_color_depth, 1087 &black_color, 1088 width, 1089 height, 1090 0); 1091 } 1092 1093 if (!blank && dc->debug.enable_single_display_2to1_odm_policy) { 1094 /* when exiting dynamic ODM need to reinit DPG state for unused pipes */ 1095 struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe; 1096 1097 odm_pipe = pipe_ctx->next_odm_pipe; 1098 1099 while (old_odm_pipe) { 1100 if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx) 1101 dc->hwss.set_disp_pattern_generator(dc, 1102 old_odm_pipe, 1103 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 1104 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 1105 COLOR_DEPTH_888, 1106 NULL, 1107 0, 1108 0, 1109 0); 1110 old_odm_pipe = old_odm_pipe->next_odm_pipe; 1111 if (odm_pipe) 1112 odm_pipe = odm_pipe->next_odm_pipe; 1113 } 1114 } 1115 1116 if (!blank) 1117 if (stream_res->abm) { 1118 dc->hwss.set_pipe(pipe_ctx); 1119 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1120 } 1121 } 1122 1123 1124 static void dcn20_power_on_plane( 1125 struct dce_hwseq *hws, 1126 struct pipe_ctx *pipe_ctx) 1127 { 1128 DC_LOGGER_INIT(hws->ctx->logger); 1129 if (REG(DC_IP_REQUEST_CNTL)) { 1130 REG_SET(DC_IP_REQUEST_CNTL, 0, 1131 IP_REQUEST_EN, 1); 1132 1133 if (hws->funcs.dpp_pg_control) 1134 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1135 1136 if (hws->funcs.hubp_pg_control) 1137 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1138 1139 REG_SET(DC_IP_REQUEST_CNTL, 0, 1140 IP_REQUEST_EN, 0); 1141 DC_LOG_DEBUG( 1142 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1143 } 1144 } 1145 1146 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1147 struct dc_state *context) 1148 { 1149 //if (dc->debug.sanity_checks) { 1150 // dcn10_verify_allow_pstate_change_high(dc); 1151 //} 1152 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1153 1154 /* enable DCFCLK current DCHUB */ 1155 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1156 1157 /* initialize HUBP on power up */ 1158 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1159 1160 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1161 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1162 pipe_ctx->stream_res.opp, 1163 true); 1164 1165 /* TODO: enable/disable in dm as per update type. 1166 if (plane_state) { 1167 DC_LOG_DC(dc->ctx->logger, 1168 "Pipe:%d 0x%x: addr hi:0x%x, " 1169 "addr low:0x%x, " 1170 "src: %d, %d, %d," 1171 " %d; dst: %d, %d, %d, %d;\n", 1172 pipe_ctx->pipe_idx, 1173 plane_state, 1174 plane_state->address.grph.addr.high_part, 1175 plane_state->address.grph.addr.low_part, 1176 plane_state->src_rect.x, 1177 plane_state->src_rect.y, 1178 plane_state->src_rect.width, 1179 plane_state->src_rect.height, 1180 plane_state->dst_rect.x, 1181 plane_state->dst_rect.y, 1182 plane_state->dst_rect.width, 1183 plane_state->dst_rect.height); 1184 1185 DC_LOG_DC(dc->ctx->logger, 1186 "Pipe %d: width, height, x, y format:%d\n" 1187 "viewport:%d, %d, %d, %d\n" 1188 "recout: %d, %d, %d, %d\n", 1189 pipe_ctx->pipe_idx, 1190 plane_state->format, 1191 pipe_ctx->plane_res.scl_data.viewport.width, 1192 pipe_ctx->plane_res.scl_data.viewport.height, 1193 pipe_ctx->plane_res.scl_data.viewport.x, 1194 pipe_ctx->plane_res.scl_data.viewport.y, 1195 pipe_ctx->plane_res.scl_data.recout.width, 1196 pipe_ctx->plane_res.scl_data.recout.height, 1197 pipe_ctx->plane_res.scl_data.recout.x, 1198 pipe_ctx->plane_res.scl_data.recout.y); 1199 print_rq_dlg_ttu(dc, pipe_ctx); 1200 } 1201 */ 1202 if (dc->vm_pa_config.valid) { 1203 struct vm_system_aperture_param apt; 1204 1205 apt.sys_default.quad_part = 0; 1206 1207 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1208 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1209 1210 // Program system aperture settings 1211 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1212 } 1213 1214 if (!pipe_ctx->top_pipe 1215 && pipe_ctx->plane_state 1216 && pipe_ctx->plane_state->flip_int_enabled 1217 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1218 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1219 1220 // if (dc->debug.sanity_checks) { 1221 // dcn10_verify_allow_pstate_change_high(dc); 1222 // } 1223 } 1224 1225 void dcn20_pipe_control_lock( 1226 struct dc *dc, 1227 struct pipe_ctx *pipe, 1228 bool lock) 1229 { 1230 struct pipe_ctx *temp_pipe; 1231 bool flip_immediate = false; 1232 1233 /* use TG master update lock to lock everything on the TG 1234 * therefore only top pipe need to lock 1235 */ 1236 if (!pipe || pipe->top_pipe) 1237 return; 1238 1239 if (pipe->plane_state != NULL) 1240 flip_immediate = pipe->plane_state->flip_immediate; 1241 1242 if (pipe->stream_res.gsl_group > 0) { 1243 temp_pipe = pipe->bottom_pipe; 1244 while (!flip_immediate && temp_pipe) { 1245 if (temp_pipe->plane_state != NULL) 1246 flip_immediate = temp_pipe->plane_state->flip_immediate; 1247 temp_pipe = temp_pipe->bottom_pipe; 1248 } 1249 } 1250 1251 if (flip_immediate && lock) { 1252 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1253 int i; 1254 1255 temp_pipe = pipe; 1256 while (temp_pipe) { 1257 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1258 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1259 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1260 break; 1261 udelay(1); 1262 } 1263 1264 /* no reason it should take this long for immediate flips */ 1265 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1266 } 1267 temp_pipe = temp_pipe->bottom_pipe; 1268 } 1269 } 1270 1271 /* In flip immediate and pipe splitting case, we need to use GSL 1272 * for synchronization. Only do setup on locking and on flip type change. 1273 */ 1274 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1275 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1276 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1277 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1278 1279 if (pipe->plane_state != NULL) 1280 flip_immediate = pipe->plane_state->flip_immediate; 1281 1282 temp_pipe = pipe->bottom_pipe; 1283 while (flip_immediate && temp_pipe) { 1284 if (temp_pipe->plane_state != NULL) 1285 flip_immediate = temp_pipe->plane_state->flip_immediate; 1286 temp_pipe = temp_pipe->bottom_pipe; 1287 } 1288 1289 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1290 !flip_immediate) 1291 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1292 1293 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1294 union dmub_hw_lock_flags hw_locks = { 0 }; 1295 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1296 1297 hw_locks.bits.lock_pipe = 1; 1298 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1299 1300 if (pipe->plane_state != NULL) 1301 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1302 1303 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1304 lock, 1305 &hw_locks, 1306 &inst_flags); 1307 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1308 if (lock) 1309 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1310 else 1311 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1312 } else { 1313 if (lock) 1314 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1315 else 1316 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1317 } 1318 } 1319 1320 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1321 { 1322 new_pipe->update_flags.raw = 0; 1323 1324 /* If non-phantom pipe is being transitioned to a phantom pipe, 1325 * set disable and return immediately. This is because the pipe 1326 * that was previously in use must be fully disabled before we 1327 * can "enable" it as a phantom pipe (since the OTG will certainly 1328 * be different). The post_unlock sequence will set the correct 1329 * update flags to enable the phantom pipe. 1330 */ 1331 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom && 1332 new_pipe->plane_state && new_pipe->plane_state->is_phantom) { 1333 new_pipe->update_flags.bits.disable = 1; 1334 return; 1335 } 1336 1337 /* Exit on unchanged, unused pipe */ 1338 if (!old_pipe->plane_state && !new_pipe->plane_state) 1339 return; 1340 /* Detect pipe enable/disable */ 1341 if (!old_pipe->plane_state && new_pipe->plane_state) { 1342 new_pipe->update_flags.bits.enable = 1; 1343 new_pipe->update_flags.bits.mpcc = 1; 1344 new_pipe->update_flags.bits.dppclk = 1; 1345 new_pipe->update_flags.bits.hubp_interdependent = 1; 1346 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1347 new_pipe->update_flags.bits.gamut_remap = 1; 1348 new_pipe->update_flags.bits.scaler = 1; 1349 new_pipe->update_flags.bits.viewport = 1; 1350 new_pipe->update_flags.bits.det_size = 1; 1351 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1352 new_pipe->update_flags.bits.odm = 1; 1353 new_pipe->update_flags.bits.global_sync = 1; 1354 } 1355 return; 1356 } 1357 1358 /* For SubVP we need to unconditionally enable because any phantom pipes are 1359 * always removed then newly added for every full updates whenever SubVP is in use. 1360 * The remove-add sequence of the phantom pipe always results in the pipe 1361 * being blanked in enable_stream_timing (DPG). 1362 */ 1363 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 1364 new_pipe->update_flags.bits.enable = 1; 1365 1366 /* Phantom pipes are effectively disabled, if the pipe was previously phantom 1367 * we have to enable 1368 */ 1369 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom && 1370 new_pipe->plane_state && !new_pipe->plane_state->is_phantom) 1371 new_pipe->update_flags.bits.enable = 1; 1372 1373 if (old_pipe->plane_state && !new_pipe->plane_state) { 1374 new_pipe->update_flags.bits.disable = 1; 1375 return; 1376 } 1377 1378 /* Detect plane change */ 1379 if (old_pipe->plane_state != new_pipe->plane_state) { 1380 new_pipe->update_flags.bits.plane_changed = true; 1381 } 1382 1383 /* Detect top pipe only changes */ 1384 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1385 /* Detect odm changes */ 1386 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1387 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1388 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1389 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1390 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1391 new_pipe->update_flags.bits.odm = 1; 1392 1393 /* Detect global sync changes */ 1394 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1395 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1396 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1397 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1398 new_pipe->update_flags.bits.global_sync = 1; 1399 } 1400 1401 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1402 new_pipe->update_flags.bits.det_size = 1; 1403 1404 /* 1405 * Detect opp / tg change, only set on change, not on enable 1406 * Assume mpcc inst = pipe index, if not this code needs to be updated 1407 * since mpcc is what is affected by these. In fact all of our sequence 1408 * makes this assumption at the moment with how hubp reset is matched to 1409 * same index mpcc reset. 1410 */ 1411 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1412 new_pipe->update_flags.bits.opp_changed = 1; 1413 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1414 new_pipe->update_flags.bits.tg_changed = 1; 1415 1416 /* 1417 * Detect mpcc blending changes, only dpp inst and opp matter here, 1418 * mpccs getting removed/inserted update connected ones during their own 1419 * programming 1420 */ 1421 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1422 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1423 new_pipe->update_flags.bits.mpcc = 1; 1424 1425 /* Detect dppclk change */ 1426 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1427 new_pipe->update_flags.bits.dppclk = 1; 1428 1429 /* Check for scl update */ 1430 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1431 new_pipe->update_flags.bits.scaler = 1; 1432 /* Check for vp update */ 1433 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1434 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1435 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1436 new_pipe->update_flags.bits.viewport = 1; 1437 1438 /* Detect dlg/ttu/rq updates */ 1439 { 1440 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1441 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1442 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1443 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1444 1445 /* Detect pipe interdependent updates */ 1446 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1447 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1448 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1449 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1450 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1451 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1452 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1453 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1454 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1455 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1456 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1457 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1458 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1459 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1460 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1461 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1462 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1463 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1464 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1465 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1466 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1467 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1468 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1469 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1470 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1471 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1472 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1473 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1474 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1475 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1476 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1477 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1478 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1479 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1480 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1481 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1482 new_pipe->update_flags.bits.hubp_interdependent = 1; 1483 } 1484 /* Detect any other updates to ttu/rq/dlg */ 1485 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1486 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1487 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1488 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1489 } 1490 } 1491 1492 static void dcn20_update_dchubp_dpp( 1493 struct dc *dc, 1494 struct pipe_ctx *pipe_ctx, 1495 struct dc_state *context) 1496 { 1497 struct dce_hwseq *hws = dc->hwseq; 1498 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1499 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1500 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1501 struct dccg *dccg = dc->res_pool->dccg; 1502 bool viewport_changed = false; 1503 1504 if (pipe_ctx->update_flags.bits.dppclk) 1505 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1506 1507 if (pipe_ctx->update_flags.bits.enable) 1508 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 1509 1510 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1511 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1512 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1513 */ 1514 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1515 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1516 1517 hubp->funcs->hubp_setup( 1518 hubp, 1519 &pipe_ctx->dlg_regs, 1520 &pipe_ctx->ttu_regs, 1521 &pipe_ctx->rq_regs, 1522 &pipe_ctx->pipe_dlg_param); 1523 1524 if (hubp->funcs->set_unbounded_requesting) 1525 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1526 } 1527 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1528 hubp->funcs->hubp_setup_interdependent( 1529 hubp, 1530 &pipe_ctx->dlg_regs, 1531 &pipe_ctx->ttu_regs); 1532 1533 if (pipe_ctx->update_flags.bits.enable || 1534 pipe_ctx->update_flags.bits.plane_changed || 1535 plane_state->update_flags.bits.bpp_change || 1536 plane_state->update_flags.bits.input_csc_change || 1537 plane_state->update_flags.bits.color_space_change || 1538 plane_state->update_flags.bits.coeff_reduction_change) { 1539 struct dc_bias_and_scale bns_params = {0}; 1540 1541 // program the input csc 1542 dpp->funcs->dpp_setup(dpp, 1543 plane_state->format, 1544 EXPANSION_MODE_ZERO, 1545 plane_state->input_csc_color_matrix, 1546 plane_state->color_space, 1547 NULL); 1548 1549 if (dpp->funcs->dpp_program_bias_and_scale) { 1550 //TODO :for CNVC set scale and bias registers if necessary 1551 build_prescale_params(&bns_params, plane_state); 1552 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1553 } 1554 } 1555 1556 if (pipe_ctx->update_flags.bits.mpcc 1557 || pipe_ctx->update_flags.bits.plane_changed 1558 || plane_state->update_flags.bits.global_alpha_change 1559 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1560 // MPCC inst is equal to pipe index in practice 1561 int mpcc_inst = hubp->inst; 1562 int opp_inst; 1563 int opp_count = dc->res_pool->pipe_count; 1564 1565 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1566 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1567 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1568 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1569 break; 1570 } 1571 } 1572 hws->funcs.update_mpcc(dc, pipe_ctx); 1573 } 1574 1575 if (pipe_ctx->update_flags.bits.scaler || 1576 plane_state->update_flags.bits.scaling_change || 1577 plane_state->update_flags.bits.position_change || 1578 plane_state->update_flags.bits.per_pixel_alpha_change || 1579 pipe_ctx->stream->update_flags.bits.scaling) { 1580 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1581 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1582 /* scaler configuration */ 1583 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1584 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1585 } 1586 1587 if (pipe_ctx->update_flags.bits.viewport || 1588 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1589 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1590 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1591 1592 hubp->funcs->mem_program_viewport( 1593 hubp, 1594 &pipe_ctx->plane_res.scl_data.viewport, 1595 &pipe_ctx->plane_res.scl_data.viewport_c); 1596 viewport_changed = true; 1597 } 1598 1599 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1600 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1601 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1602 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1603 dc->hwss.set_cursor_position(pipe_ctx); 1604 dc->hwss.set_cursor_attribute(pipe_ctx); 1605 1606 if (dc->hwss.set_cursor_sdr_white_level) 1607 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1608 } 1609 1610 /* Any updates are handled in dc interface, just need 1611 * to apply existing for plane enable / opp change */ 1612 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1613 || pipe_ctx->update_flags.bits.plane_changed 1614 || pipe_ctx->stream->update_flags.bits.gamut_remap 1615 || pipe_ctx->stream->update_flags.bits.out_csc) { 1616 /* dpp/cm gamut remap*/ 1617 dc->hwss.program_gamut_remap(pipe_ctx); 1618 1619 /*call the dcn2 method which uses mpc csc*/ 1620 dc->hwss.program_output_csc(dc, 1621 pipe_ctx, 1622 pipe_ctx->stream->output_color_space, 1623 pipe_ctx->stream->csc_color_matrix.matrix, 1624 hubp->opp_id); 1625 } 1626 1627 if (pipe_ctx->update_flags.bits.enable || 1628 pipe_ctx->update_flags.bits.plane_changed || 1629 pipe_ctx->update_flags.bits.opp_changed || 1630 plane_state->update_flags.bits.pixel_format_change || 1631 plane_state->update_flags.bits.horizontal_mirror_change || 1632 plane_state->update_flags.bits.rotation_change || 1633 plane_state->update_flags.bits.swizzle_change || 1634 plane_state->update_flags.bits.dcc_change || 1635 plane_state->update_flags.bits.bpp_change || 1636 plane_state->update_flags.bits.scaling_change || 1637 plane_state->update_flags.bits.plane_size_change) { 1638 struct plane_size size = plane_state->plane_size; 1639 1640 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1641 hubp->funcs->hubp_program_surface_config( 1642 hubp, 1643 plane_state->format, 1644 &plane_state->tiling_info, 1645 &size, 1646 plane_state->rotation, 1647 &plane_state->dcc, 1648 plane_state->horizontal_mirror, 1649 0); 1650 hubp->power_gated = false; 1651 } 1652 1653 if (pipe_ctx->update_flags.bits.enable || 1654 pipe_ctx->update_flags.bits.plane_changed || 1655 plane_state->update_flags.bits.addr_update) 1656 hws->funcs.update_plane_addr(dc, pipe_ctx); 1657 1658 if (pipe_ctx->update_flags.bits.enable) 1659 hubp->funcs->set_blank(hubp, false); 1660 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1661 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1662 && hubp->funcs->phantom_hubp_post_enable) 1663 hubp->funcs->phantom_hubp_post_enable(hubp); 1664 } 1665 1666 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) 1667 { 1668 struct pipe_ctx *other_pipe; 1669 int vready_offset = pipe->pipe_dlg_param.vready_offset; 1670 1671 /* Always use the largest vready_offset of all connected pipes */ 1672 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { 1673 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1674 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1675 } 1676 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { 1677 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1678 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1679 } 1680 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) { 1681 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1682 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1683 } 1684 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) { 1685 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1686 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1687 } 1688 1689 return vready_offset; 1690 } 1691 1692 static void dcn20_program_pipe( 1693 struct dc *dc, 1694 struct pipe_ctx *pipe_ctx, 1695 struct dc_state *context) 1696 { 1697 struct dce_hwseq *hws = dc->hwseq; 1698 /* Only need to unblank on top pipe */ 1699 1700 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1701 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1702 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1703 1704 /* Only update TG on top pipe */ 1705 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1706 && !pipe_ctx->prev_odm_pipe) { 1707 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1708 pipe_ctx->stream_res.tg, 1709 calculate_vready_offset_for_group(pipe_ctx), 1710 pipe_ctx->pipe_dlg_param.vstartup_start, 1711 pipe_ctx->pipe_dlg_param.vupdate_offset, 1712 pipe_ctx->pipe_dlg_param.vupdate_width); 1713 1714 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1715 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1716 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1717 } 1718 1719 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1720 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1721 1722 if (hws->funcs.setup_vupdate_interrupt) 1723 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1724 } 1725 1726 if (pipe_ctx->update_flags.bits.odm) 1727 hws->funcs.update_odm(dc, context, pipe_ctx); 1728 1729 if (pipe_ctx->update_flags.bits.enable) { 1730 dcn20_enable_plane(dc, pipe_ctx, context); 1731 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1732 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1733 } 1734 1735 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1736 dc->res_pool->hubbub->funcs->program_det_size( 1737 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1738 1739 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1740 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1741 1742 if (pipe_ctx->update_flags.bits.enable 1743 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1744 hws->funcs.set_hdr_multiplier(pipe_ctx); 1745 1746 if (pipe_ctx->update_flags.bits.enable || 1747 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1748 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1749 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1750 1751 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1752 * only do gamma programming for powering on, internal memcmp to avoid 1753 * updating on slave planes 1754 */ 1755 if (pipe_ctx->update_flags.bits.enable || 1756 pipe_ctx->update_flags.bits.plane_changed || 1757 pipe_ctx->stream->update_flags.bits.out_tf || 1758 pipe_ctx->plane_state->update_flags.bits.output_tf_change) 1759 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1760 1761 /* If the pipe has been enabled or has a different opp, we 1762 * should reprogram the fmt. This deals with cases where 1763 * interation between mpc and odm combine on different streams 1764 * causes a different pipe to be chosen to odm combine with. 1765 */ 1766 if (pipe_ctx->update_flags.bits.enable 1767 || pipe_ctx->update_flags.bits.opp_changed) { 1768 1769 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1770 pipe_ctx->stream_res.opp, 1771 COLOR_SPACE_YCBCR601, 1772 pipe_ctx->stream->timing.display_color_depth, 1773 pipe_ctx->stream->signal); 1774 1775 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1776 pipe_ctx->stream_res.opp, 1777 &pipe_ctx->stream->bit_depth_params, 1778 &pipe_ctx->stream->clamping); 1779 } 1780 1781 /* Set ABM pipe after other pipe configurations done */ 1782 if (pipe_ctx->plane_state->visible) { 1783 if (pipe_ctx->stream_res.abm) { 1784 dc->hwss.set_pipe(pipe_ctx); 1785 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm, 1786 pipe_ctx->stream->abm_level); 1787 } 1788 } 1789 } 1790 1791 void dcn20_program_front_end_for_ctx( 1792 struct dc *dc, 1793 struct dc_state *context) 1794 { 1795 int i; 1796 struct dce_hwseq *hws = dc->hwseq; 1797 DC_LOGGER_INIT(dc->ctx->logger); 1798 1799 /* Carry over GSL groups in case the context is changing. */ 1800 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1801 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1802 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1803 1804 if (pipe_ctx->stream == old_pipe_ctx->stream) 1805 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group; 1806 } 1807 1808 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1809 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1810 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1811 1812 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1813 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1814 /*turn off triple buffer for full update*/ 1815 dc->hwss.program_triplebuffer( 1816 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1817 } 1818 } 1819 } 1820 1821 /* Set pipe update flags and lock pipes */ 1822 for (i = 0; i < dc->res_pool->pipe_count; i++) 1823 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1824 &context->res_ctx.pipe_ctx[i]); 1825 1826 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double 1827 * buffer updates properly) 1828 */ 1829 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1830 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; 1831 1832 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream && 1833 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1834 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; 1835 1836 if (tg->funcs->enable_crtc) 1837 tg->funcs->enable_crtc(tg); 1838 } 1839 } 1840 /* OTG blank before disabling all front ends */ 1841 for (i = 0; i < dc->res_pool->pipe_count; i++) 1842 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1843 && !context->res_ctx.pipe_ctx[i].top_pipe 1844 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1845 && context->res_ctx.pipe_ctx[i].stream) 1846 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1847 1848 1849 /* Disconnect mpcc */ 1850 for (i = 0; i < dc->res_pool->pipe_count; i++) 1851 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1852 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1853 struct hubbub *hubbub = dc->res_pool->hubbub; 1854 1855 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom 1856 * then we want to do the programming here (effectively it's being disabled). If we do 1857 * the programming later the DET won't be updated until the OTG for the phantom pipe is 1858 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with 1859 * DET allocation. 1860 */ 1861 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || 1862 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom))) 1863 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1864 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1865 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1866 } 1867 1868 /* 1869 * Program all updated pipes, order matters for mpcc setup. Start with 1870 * top pipe and program all pipes that follow in order 1871 */ 1872 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1873 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1874 1875 if (pipe->plane_state && !pipe->top_pipe) { 1876 while (pipe) { 1877 if (hws->funcs.program_pipe) 1878 hws->funcs.program_pipe(dc, pipe, context); 1879 else { 1880 /* Don't program phantom pipes in the regular front end programming sequence. 1881 * There is an MPO transition case where a pipe being used by a video plane is 1882 * transitioned directly to be a phantom pipe when closing the MPO video. However 1883 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away), 1884 * but the MPO still exists until the double buffered update of the main pipe so we 1885 * will get a frame of underflow if the phantom pipe is programmed here. 1886 */ 1887 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) 1888 dcn20_program_pipe(dc, pipe, context); 1889 } 1890 1891 pipe = pipe->bottom_pipe; 1892 } 1893 } 1894 /* Program secondary blending tree and writeback pipes */ 1895 pipe = &context->res_ctx.pipe_ctx[i]; 1896 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1897 && pipe->stream && pipe->stream->num_wb_info > 0 1898 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1899 || pipe->stream->update_flags.raw) 1900 && hws->funcs.program_all_writeback_pipes_in_tree) 1901 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1902 1903 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1904 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1905 !pipe->top_pipe && 1906 pipe->stream && 1907 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1908 dc->current_state->stream_status[0].plane_count == 1 && 1909 context->stream_status[0].plane_count > 1) { 1910 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1911 } 1912 1913 /* when dynamic ODM is active, pipes must be reconfigured when all planes are 1914 * disabled, as some transitions will leave software and hardware state 1915 * mismatched. 1916 */ 1917 if (dc->debug.enable_single_display_2to1_odm_policy && 1918 pipe->stream && 1919 pipe->update_flags.bits.disable && 1920 !pipe->prev_odm_pipe && 1921 hws->funcs.update_odm) 1922 hws->funcs.update_odm(dc, context, pipe); 1923 } 1924 } 1925 1926 void dcn20_post_unlock_program_front_end( 1927 struct dc *dc, 1928 struct dc_state *context) 1929 { 1930 int i; 1931 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1932 struct dce_hwseq *hwseq = dc->hwseq; 1933 1934 DC_LOGGER_INIT(dc->ctx->logger); 1935 1936 for (i = 0; i < dc->res_pool->pipe_count; i++) 1937 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1938 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1939 1940 /* 1941 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1942 * part of the enable operation otherwise, DM may request an immediate flip which 1943 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1944 * is unsupported on DCN. 1945 */ 1946 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1947 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1948 // Don't check flip pending on phantom pipes 1949 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && 1950 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1951 struct hubp *hubp = pipe->plane_res.hubp; 1952 int j = 0; 1953 1954 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1955 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1956 udelay(1); 1957 } 1958 } 1959 1960 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1961 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1962 1963 if (pipe->plane_state && !pipe->top_pipe) { 1964 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition 1965 * case (if a pipe being used for a video plane transitions to a phantom pipe, it 1966 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end 1967 * programming sequence). 1968 */ 1969 while (pipe) { 1970 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1971 /* When turning on the phantom pipe we want to run through the 1972 * entire enable sequence, so apply all the "enable" flags. 1973 */ 1974 if (dc->hwss.apply_update_flags_for_phantom) 1975 dc->hwss.apply_update_flags_for_phantom(pipe); 1976 if (dc->hwss.update_phantom_vp_position) 1977 dc->hwss.update_phantom_vp_position(dc, context, pipe); 1978 dcn20_program_pipe(dc, pipe, context); 1979 } 1980 pipe = pipe->bottom_pipe; 1981 } 1982 } 1983 } 1984 1985 /* Only program the MALL registers after all the main and phantom pipes 1986 * are done programming. 1987 */ 1988 if (hwseq->funcs.program_mall_pipe_config) 1989 hwseq->funcs.program_mall_pipe_config(dc, context); 1990 1991 /* WA to apply WM setting*/ 1992 if (hwseq->wa.DEGVIDCN21) 1993 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1994 1995 1996 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1997 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1998 1999 if (dc->current_state->stream_status[0].plane_count == 1 && 2000 context->stream_status[0].plane_count > 1) { 2001 2002 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2003 2004 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 2005 2006 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 2007 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 2008 } 2009 } 2010 } 2011 2012 void dcn20_prepare_bandwidth( 2013 struct dc *dc, 2014 struct dc_state *context) 2015 { 2016 struct hubbub *hubbub = dc->res_pool->hubbub; 2017 unsigned int compbuf_size_kb = 0; 2018 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; 2019 unsigned int i; 2020 2021 dc->clk_mgr->funcs->update_clocks( 2022 dc->clk_mgr, 2023 context, 2024 false); 2025 2026 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2027 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2028 2029 // At optimize don't restore the original watermark value 2030 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2031 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2032 break; 2033 } 2034 } 2035 2036 /* program dchubbub watermarks: 2037 * For assigning wm_optimized_required, use |= operator since we don't want 2038 * to clear the value if the optimize has not happened yet 2039 */ 2040 dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub, 2041 &context->bw_ctx.bw.dcn.watermarks, 2042 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2043 false); 2044 2045 // Restore the real watermark so we can commit the value to DMCUB 2046 // DMCUB uses the "original" watermark value in SubVP MCLK switch 2047 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; 2048 2049 /* decrease compbuf size */ 2050 if (hubbub->funcs->program_compbuf_size) { 2051 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { 2052 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 2053 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes); 2054 } else { 2055 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 2056 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); 2057 } 2058 2059 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 2060 } 2061 } 2062 2063 void dcn20_optimize_bandwidth( 2064 struct dc *dc, 2065 struct dc_state *context) 2066 { 2067 struct hubbub *hubbub = dc->res_pool->hubbub; 2068 int i; 2069 2070 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2071 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2072 2073 // At optimize don't need to restore the original watermark value 2074 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2075 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2076 break; 2077 } 2078 } 2079 2080 /* program dchubbub watermarks */ 2081 hubbub->funcs->program_watermarks(hubbub, 2082 &context->bw_ctx.bw.dcn.watermarks, 2083 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2084 true); 2085 2086 if (dc->clk_mgr->dc_mode_softmax_enabled) 2087 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 2088 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 2089 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 2090 2091 /* increase compbuf size */ 2092 if (hubbub->funcs->program_compbuf_size) 2093 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 2094 2095 dc->clk_mgr->funcs->update_clocks( 2096 dc->clk_mgr, 2097 context, 2098 true); 2099 if (dc_extended_blank_supported(dc) && context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 2100 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 2101 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2102 2103 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 2104 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 2105 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 2106 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 2107 pipe_ctx->dlg_regs.optimized_min_dst_y_next_start); 2108 } 2109 } 2110 } 2111 2112 bool dcn20_update_bandwidth( 2113 struct dc *dc, 2114 struct dc_state *context) 2115 { 2116 int i; 2117 struct dce_hwseq *hws = dc->hwseq; 2118 2119 /* recalculate DML parameters */ 2120 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 2121 return false; 2122 2123 /* apply updated bandwidth parameters */ 2124 dc->hwss.prepare_bandwidth(dc, context); 2125 2126 /* update hubp configs for all pipes */ 2127 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2128 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2129 2130 if (pipe_ctx->plane_state == NULL) 2131 continue; 2132 2133 if (pipe_ctx->top_pipe == NULL) { 2134 bool blank = !is_pipe_tree_visible(pipe_ctx); 2135 2136 pipe_ctx->stream_res.tg->funcs->program_global_sync( 2137 pipe_ctx->stream_res.tg, 2138 calculate_vready_offset_for_group(pipe_ctx), 2139 pipe_ctx->pipe_dlg_param.vstartup_start, 2140 pipe_ctx->pipe_dlg_param.vupdate_offset, 2141 pipe_ctx->pipe_dlg_param.vupdate_width); 2142 2143 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 2144 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 2145 2146 if (pipe_ctx->prev_odm_pipe == NULL) 2147 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 2148 2149 if (hws->funcs.setup_vupdate_interrupt) 2150 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 2151 } 2152 2153 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 2154 pipe_ctx->plane_res.hubp, 2155 &pipe_ctx->dlg_regs, 2156 &pipe_ctx->ttu_regs, 2157 &pipe_ctx->rq_regs, 2158 &pipe_ctx->pipe_dlg_param); 2159 } 2160 2161 return true; 2162 } 2163 2164 void dcn20_enable_writeback( 2165 struct dc *dc, 2166 struct dc_writeback_info *wb_info, 2167 struct dc_state *context) 2168 { 2169 struct dwbc *dwb; 2170 struct mcif_wb *mcif_wb; 2171 struct timing_generator *optc; 2172 2173 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2174 ASSERT(wb_info->wb_enabled); 2175 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2176 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2177 2178 /* set the OPTC source mux */ 2179 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 2180 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2181 /* set MCIF_WB buffer and arbitration configuration */ 2182 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2183 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2184 /* Enable MCIF_WB */ 2185 mcif_wb->funcs->enable_mcif(mcif_wb); 2186 /* Enable DWB */ 2187 dwb->funcs->enable(dwb, &wb_info->dwb_params); 2188 /* TODO: add sequence to enable/disable warmup */ 2189 } 2190 2191 void dcn20_disable_writeback( 2192 struct dc *dc, 2193 unsigned int dwb_pipe_inst) 2194 { 2195 struct dwbc *dwb; 2196 struct mcif_wb *mcif_wb; 2197 2198 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2199 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2200 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2201 2202 dwb->funcs->disable(dwb); 2203 mcif_wb->funcs->disable_mcif(mcif_wb); 2204 } 2205 2206 bool dcn20_wait_for_blank_complete( 2207 struct output_pixel_processor *opp) 2208 { 2209 int counter; 2210 2211 for (counter = 0; counter < 1000; counter++) { 2212 if (opp->funcs->dpg_is_blanked(opp)) 2213 break; 2214 2215 udelay(100); 2216 } 2217 2218 if (counter == 1000) { 2219 dm_error("DC: failed to blank crtc!\n"); 2220 return false; 2221 } 2222 2223 return true; 2224 } 2225 2226 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2227 { 2228 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2229 2230 if (!hubp) 2231 return false; 2232 return hubp->funcs->dmdata_status_done(hubp); 2233 } 2234 2235 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2236 { 2237 struct dce_hwseq *hws = dc->hwseq; 2238 2239 if (pipe_ctx->stream_res.dsc) { 2240 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2241 2242 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2243 while (odm_pipe) { 2244 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2245 odm_pipe = odm_pipe->next_odm_pipe; 2246 } 2247 } 2248 } 2249 2250 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2251 { 2252 struct dce_hwseq *hws = dc->hwseq; 2253 2254 if (pipe_ctx->stream_res.dsc) { 2255 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2256 2257 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2258 while (odm_pipe) { 2259 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2260 odm_pipe = odm_pipe->next_odm_pipe; 2261 } 2262 } 2263 } 2264 2265 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2266 { 2267 struct dc_dmdata_attributes attr = { 0 }; 2268 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2269 2270 attr.dmdata_mode = DMDATA_HW_MODE; 2271 attr.dmdata_size = 2272 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2273 attr.address.quad_part = 2274 pipe_ctx->stream->dmdata_address.quad_part; 2275 attr.dmdata_dl_delta = 0; 2276 attr.dmdata_qos_mode = 0; 2277 attr.dmdata_qos_level = 0; 2278 attr.dmdata_repeat = 1; /* always repeat */ 2279 attr.dmdata_updated = 1; 2280 attr.dmdata_sw_data = NULL; 2281 2282 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2283 } 2284 2285 void dcn20_init_vm_ctx( 2286 struct dce_hwseq *hws, 2287 struct dc *dc, 2288 struct dc_virtual_addr_space_config *va_config, 2289 int vmid) 2290 { 2291 struct dcn_hubbub_virt_addr_config config; 2292 2293 if (vmid == 0) { 2294 ASSERT(0); /* VMID cannot be 0 for vm context */ 2295 return; 2296 } 2297 2298 config.page_table_start_addr = va_config->page_table_start_addr; 2299 config.page_table_end_addr = va_config->page_table_end_addr; 2300 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2301 config.page_table_depth = va_config->page_table_depth; 2302 config.page_table_base_addr = va_config->page_table_base_addr; 2303 2304 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2305 } 2306 2307 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2308 { 2309 struct dcn_hubbub_phys_addr_config config; 2310 2311 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2312 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2313 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2314 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2315 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2316 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2317 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2318 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2319 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2320 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2321 2322 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2323 } 2324 2325 static bool patch_address_for_sbs_tb_stereo( 2326 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2327 { 2328 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2329 bool sec_split = pipe_ctx->top_pipe && 2330 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2331 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2332 (pipe_ctx->stream->timing.timing_3d_format == 2333 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2334 pipe_ctx->stream->timing.timing_3d_format == 2335 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2336 *addr = plane_state->address.grph_stereo.left_addr; 2337 plane_state->address.grph_stereo.left_addr = 2338 plane_state->address.grph_stereo.right_addr; 2339 return true; 2340 } 2341 2342 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2343 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2344 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2345 plane_state->address.grph_stereo.right_addr = 2346 plane_state->address.grph_stereo.left_addr; 2347 plane_state->address.grph_stereo.right_meta_addr = 2348 plane_state->address.grph_stereo.left_meta_addr; 2349 } 2350 return false; 2351 } 2352 2353 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2354 { 2355 bool addr_patched = false; 2356 PHYSICAL_ADDRESS_LOC addr; 2357 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2358 2359 if (plane_state == NULL) 2360 return; 2361 2362 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2363 2364 // Call Helper to track VMID use 2365 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2366 2367 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2368 pipe_ctx->plane_res.hubp, 2369 &plane_state->address, 2370 plane_state->flip_immediate); 2371 2372 plane_state->status.requested_address = plane_state->address; 2373 2374 if (plane_state->flip_immediate) 2375 plane_state->status.current_address = plane_state->address; 2376 2377 if (addr_patched) 2378 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2379 } 2380 2381 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2382 struct dc_link_settings *link_settings) 2383 { 2384 struct encoder_unblank_param params = {0}; 2385 struct dc_stream_state *stream = pipe_ctx->stream; 2386 struct dc_link *link = stream->link; 2387 struct dce_hwseq *hws = link->dc->hwseq; 2388 struct pipe_ctx *odm_pipe; 2389 2390 params.opp_cnt = 1; 2391 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2392 params.opp_cnt++; 2393 } 2394 /* only 3 items below are used by unblank */ 2395 params.timing = pipe_ctx->stream->timing; 2396 2397 params.link_settings.link_rate = link_settings->link_rate; 2398 2399 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 2400 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2401 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2402 pipe_ctx->stream_res.hpo_dp_stream_enc, 2403 pipe_ctx->stream_res.tg->inst); 2404 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2405 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2406 params.timing.pix_clk_100hz /= 2; 2407 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2408 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2409 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2410 } 2411 2412 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2413 hws->funcs.edp_backlight_control(link, true); 2414 } 2415 } 2416 2417 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2418 { 2419 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2420 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2421 2422 if (start_line < 0) 2423 start_line = 0; 2424 2425 if (tg->funcs->setup_vertical_interrupt2) 2426 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2427 } 2428 2429 static void dcn20_reset_back_end_for_pipe( 2430 struct dc *dc, 2431 struct pipe_ctx *pipe_ctx, 2432 struct dc_state *context) 2433 { 2434 int i; 2435 struct dc_link *link = pipe_ctx->stream->link; 2436 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2437 2438 DC_LOGGER_INIT(dc->ctx->logger); 2439 if (pipe_ctx->stream_res.stream_enc == NULL) { 2440 pipe_ctx->stream = NULL; 2441 return; 2442 } 2443 2444 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2445 /* DPMS may already disable or */ 2446 /* dpms_off status is incorrect due to fastboot 2447 * feature. When system resume from S4 with second 2448 * screen only, the dpms_off would be true but 2449 * VBIOS lit up eDP, so check link status too. 2450 */ 2451 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2452 link_set_dpms_off(pipe_ctx); 2453 else if (pipe_ctx->stream_res.audio) 2454 dc->hwss.disable_audio_stream(pipe_ctx); 2455 2456 /* free acquired resources */ 2457 if (pipe_ctx->stream_res.audio) { 2458 /*disable az_endpoint*/ 2459 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2460 2461 /*free audio*/ 2462 if (dc->caps.dynamic_audio == true) { 2463 /*we have to dynamic arbitrate the audio endpoints*/ 2464 /*we free the resource, need reset is_audio_acquired*/ 2465 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2466 pipe_ctx->stream_res.audio, false); 2467 pipe_ctx->stream_res.audio = NULL; 2468 } 2469 } 2470 } 2471 else if (pipe_ctx->stream_res.dsc) { 2472 link_set_dsc_enable(pipe_ctx, false); 2473 } 2474 2475 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2476 * back end share by all pipes and will be disable only when disable 2477 * parent pipe. 2478 */ 2479 if (pipe_ctx->top_pipe == NULL) { 2480 2481 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2482 2483 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2484 2485 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2486 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2487 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2488 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2489 2490 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2491 pipe_ctx->stream_res.tg->funcs->set_drr( 2492 pipe_ctx->stream_res.tg, NULL); 2493 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 2494 * the case where the same symclk is shared across multiple otg 2495 * instances 2496 */ 2497 link->phy_state.symclk_ref_cnts.otg = 0; 2498 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { 2499 link_hwss->disable_link_output(link, 2500 &pipe_ctx->link_res, pipe_ctx->stream->signal); 2501 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 2502 } 2503 } 2504 2505 for (i = 0; i < dc->res_pool->pipe_count; i++) 2506 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2507 break; 2508 2509 if (i == dc->res_pool->pipe_count) 2510 return; 2511 2512 pipe_ctx->stream = NULL; 2513 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2514 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2515 } 2516 2517 void dcn20_reset_hw_ctx_wrap( 2518 struct dc *dc, 2519 struct dc_state *context) 2520 { 2521 int i; 2522 struct dce_hwseq *hws = dc->hwseq; 2523 2524 /* Reset Back End*/ 2525 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2526 struct pipe_ctx *pipe_ctx_old = 2527 &dc->current_state->res_ctx.pipe_ctx[i]; 2528 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2529 2530 if (!pipe_ctx_old->stream) 2531 continue; 2532 2533 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2534 continue; 2535 2536 if (!pipe_ctx->stream || 2537 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2538 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2539 2540 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2541 if (hws->funcs.enable_stream_gating) 2542 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2543 if (old_clk) 2544 old_clk->funcs->cs_power_down(old_clk); 2545 } 2546 } 2547 } 2548 2549 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2550 { 2551 struct mpc *mpc = dc->res_pool->mpc; 2552 2553 // input to MPCC is always RGB, by default leave black_color at 0 2554 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2555 get_hdr_visual_confirm_color(pipe_ctx, color); 2556 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2557 get_surface_visual_confirm_color(pipe_ctx, color); 2558 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2559 get_mpctree_visual_confirm_color(pipe_ctx, color); 2560 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2561 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2562 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP) 2563 get_subvp_visual_confirm_color(dc, pipe_ctx, color); 2564 2565 if (mpc->funcs->set_bg_color) { 2566 memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color)); 2567 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2568 } 2569 } 2570 2571 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2572 { 2573 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2574 struct mpcc_blnd_cfg blnd_cfg = {0}; 2575 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2576 int mpcc_id; 2577 struct mpcc *new_mpcc; 2578 struct mpc *mpc = dc->res_pool->mpc; 2579 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2580 2581 blnd_cfg.overlap_only = false; 2582 blnd_cfg.global_gain = 0xff; 2583 2584 if (per_pixel_alpha) { 2585 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2586 if (pipe_ctx->plane_state->global_alpha) { 2587 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2588 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2589 } else { 2590 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2591 } 2592 } else { 2593 blnd_cfg.pre_multiplied_alpha = false; 2594 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2595 } 2596 2597 if (pipe_ctx->plane_state->global_alpha) 2598 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2599 else 2600 blnd_cfg.global_alpha = 0xff; 2601 2602 blnd_cfg.background_color_bpc = 4; 2603 blnd_cfg.bottom_gain_mode = 0; 2604 blnd_cfg.top_gain = 0x1f000; 2605 blnd_cfg.bottom_inside_gain = 0x1f000; 2606 blnd_cfg.bottom_outside_gain = 0x1f000; 2607 2608 if (pipe_ctx->plane_state->format 2609 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2610 blnd_cfg.pre_multiplied_alpha = false; 2611 2612 /* 2613 * TODO: remove hack 2614 * Note: currently there is a bug in init_hw such that 2615 * on resume from hibernate, BIOS sets up MPCC0, and 2616 * we do mpcc_remove but the mpcc cannot go to idle 2617 * after remove. This cause us to pick mpcc1 here, 2618 * which causes a pstate hang for yet unknown reason. 2619 */ 2620 mpcc_id = hubp->inst; 2621 2622 /* If there is no full update, don't need to touch MPC tree*/ 2623 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2624 !pipe_ctx->update_flags.bits.mpcc) { 2625 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2626 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2627 return; 2628 } 2629 2630 /* check if this MPCC is already being used */ 2631 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2632 /* remove MPCC if being used */ 2633 if (new_mpcc != NULL) 2634 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2635 else 2636 if (dc->debug.sanity_checks) 2637 mpc->funcs->assert_mpcc_idle_before_connect( 2638 dc->res_pool->mpc, mpcc_id); 2639 2640 /* Call MPC to insert new plane */ 2641 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2642 mpc_tree_params, 2643 &blnd_cfg, 2644 NULL, 2645 NULL, 2646 hubp->inst, 2647 mpcc_id); 2648 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2649 2650 ASSERT(new_mpcc != NULL); 2651 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2652 hubp->mpcc_id = mpcc_id; 2653 } 2654 2655 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 2656 { 2657 switch (link->link_enc->transmitter) { 2658 case TRANSMITTER_UNIPHY_A: 2659 return PHYD32CLKA; 2660 case TRANSMITTER_UNIPHY_B: 2661 return PHYD32CLKB; 2662 case TRANSMITTER_UNIPHY_C: 2663 return PHYD32CLKC; 2664 case TRANSMITTER_UNIPHY_D: 2665 return PHYD32CLKD; 2666 case TRANSMITTER_UNIPHY_E: 2667 return PHYD32CLKE; 2668 default: 2669 return PHYD32CLKA; 2670 } 2671 } 2672 2673 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx) 2674 { 2675 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2676 int count = 1; 2677 2678 while (odm_pipe != NULL) { 2679 count++; 2680 odm_pipe = odm_pipe->next_odm_pipe; 2681 } 2682 2683 return count; 2684 } 2685 2686 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2687 { 2688 enum dc_lane_count lane_count = 2689 pipe_ctx->stream->link->cur_link_settings.lane_count; 2690 2691 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2692 struct dc_link *link = pipe_ctx->stream->link; 2693 2694 uint32_t active_total_with_borders; 2695 uint32_t early_control = 0; 2696 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2697 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2698 struct dc *dc = pipe_ctx->stream->ctx->dc; 2699 struct dtbclk_dto_params dto_params = {0}; 2700 struct dccg *dccg = dc->res_pool->dccg; 2701 enum phyd32clk_clock_source phyd32clk; 2702 int dp_hpo_inst; 2703 struct dce_hwseq *hws = dc->hwseq; 2704 unsigned int k1_div = PIXEL_RATE_DIV_NA; 2705 unsigned int k2_div = PIXEL_RATE_DIV_NA; 2706 2707 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 2708 if (dc->hwseq->funcs.setup_hpo_hw_control) 2709 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2710 } 2711 2712 if (link_is_dp_128b_132b_signal(pipe_ctx)) { 2713 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 2714 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 2715 2716 phyd32clk = get_phyd32clk_src(link); 2717 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 2718 2719 dto_params.otg_inst = tg->inst; 2720 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; 2721 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); 2722 dto_params.timing = &pipe_ctx->stream->timing; 2723 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2724 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 2725 } 2726 2727 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 2728 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 2729 2730 dc->res_pool->dccg->funcs->set_pixel_rate_div( 2731 dc->res_pool->dccg, 2732 pipe_ctx->stream_res.tg->inst, 2733 k1_div, k2_div); 2734 } 2735 2736 link_hwss->setup_stream_encoder(pipe_ctx); 2737 2738 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2739 if (dc->hwss.program_dmdata_engine) 2740 dc->hwss.program_dmdata_engine(pipe_ctx); 2741 } 2742 2743 dc->hwss.update_info_frame(pipe_ctx); 2744 2745 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2746 link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2747 2748 /* enable early control to avoid corruption on DP monitor*/ 2749 active_total_with_borders = 2750 timing->h_addressable 2751 + timing->h_border_left 2752 + timing->h_border_right; 2753 2754 if (lane_count != 0) 2755 early_control = active_total_with_borders % lane_count; 2756 2757 if (early_control == 0) 2758 early_control = lane_count; 2759 2760 tg->funcs->set_early_control(tg, early_control); 2761 2762 if (dc->hwseq->funcs.set_pixels_per_cycle) 2763 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); 2764 } 2765 2766 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2767 { 2768 struct dc_stream_state *stream = pipe_ctx->stream; 2769 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2770 bool enable = false; 2771 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2772 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2773 ? dmdata_dp 2774 : dmdata_hdmi; 2775 2776 /* if using dynamic meta, don't set up generic infopackets */ 2777 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2778 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2779 enable = true; 2780 } 2781 2782 if (!hubp) 2783 return; 2784 2785 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2786 return; 2787 2788 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2789 hubp->inst, mode); 2790 } 2791 2792 void dcn20_fpga_init_hw(struct dc *dc) 2793 { 2794 int i, j; 2795 struct dce_hwseq *hws = dc->hwseq; 2796 struct resource_pool *res_pool = dc->res_pool; 2797 struct dc_state *context = dc->current_state; 2798 2799 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2800 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2801 2802 // Initialize the dccg 2803 if (res_pool->dccg->funcs->dccg_init) 2804 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2805 2806 //Enable ability to power gate / don't force power on permanently 2807 hws->funcs.enable_power_gating_plane(hws, true); 2808 2809 // Specific to FPGA dccg and registers 2810 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2811 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2812 2813 hws->funcs.dccg_init(hws); 2814 2815 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2816 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2817 if (REG(REFCLK_CNTL)) 2818 REG_WRITE(REFCLK_CNTL, 0); 2819 // 2820 2821 2822 /* Blank pixel data with OPP DPG */ 2823 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2824 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2825 2826 if (tg->funcs->is_tg_enabled(tg)) 2827 dcn20_init_blank(dc, tg); 2828 } 2829 2830 for (i = 0; i < res_pool->timing_generator_count; i++) { 2831 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2832 2833 if (tg->funcs->is_tg_enabled(tg)) 2834 tg->funcs->lock(tg); 2835 } 2836 2837 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2838 struct dpp *dpp = res_pool->dpps[i]; 2839 2840 dpp->funcs->dpp_reset(dpp); 2841 } 2842 2843 /* Reset all MPCC muxes */ 2844 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2845 2846 /* initialize OPP mpc_tree parameter */ 2847 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2848 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2849 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2850 for (j = 0; j < MAX_PIPES; j++) 2851 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2852 } 2853 2854 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2855 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2856 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2857 struct hubp *hubp = dc->res_pool->hubps[i]; 2858 struct dpp *dpp = dc->res_pool->dpps[i]; 2859 2860 pipe_ctx->stream_res.tg = tg; 2861 pipe_ctx->pipe_idx = i; 2862 2863 pipe_ctx->plane_res.hubp = hubp; 2864 pipe_ctx->plane_res.dpp = dpp; 2865 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2866 hubp->mpcc_id = dpp->inst; 2867 hubp->opp_id = OPP_ID_INVALID; 2868 hubp->power_gated = false; 2869 pipe_ctx->stream_res.opp = NULL; 2870 2871 hubp->funcs->hubp_init(hubp); 2872 2873 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2874 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2875 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2876 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2877 /*to do*/ 2878 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2879 } 2880 2881 /* initialize DWB pointer to MCIF_WB */ 2882 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2883 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2884 2885 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2886 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2887 2888 if (tg->funcs->is_tg_enabled(tg)) 2889 tg->funcs->unlock(tg); 2890 } 2891 2892 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2893 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2894 2895 dc->hwss.disable_plane(dc, pipe_ctx); 2896 2897 pipe_ctx->stream_res.tg = NULL; 2898 pipe_ctx->plane_res.hubp = NULL; 2899 } 2900 2901 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2902 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2903 2904 tg->funcs->tg_init(tg); 2905 } 2906 2907 if (dc->res_pool->hubbub->funcs->init_crb) 2908 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2909 } 2910 #ifndef TRIM_FSFT 2911 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2912 struct dc_crtc_timing *timing, 2913 unsigned int max_input_rate_in_khz) 2914 { 2915 unsigned int old_v_front_porch; 2916 unsigned int old_v_total; 2917 unsigned int max_input_rate_in_100hz; 2918 unsigned long long new_v_total; 2919 2920 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2921 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2922 return false; 2923 2924 old_v_total = timing->v_total; 2925 old_v_front_porch = timing->v_front_porch; 2926 2927 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2928 timing->pix_clk_100hz = max_input_rate_in_100hz; 2929 2930 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2931 2932 timing->v_total = new_v_total; 2933 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2934 return true; 2935 } 2936 #endif 2937 2938 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2939 struct pipe_ctx *pipe_ctx, 2940 enum controller_dp_test_pattern test_pattern, 2941 enum controller_dp_color_space color_space, 2942 enum dc_color_depth color_depth, 2943 const struct tg_color *solid_color, 2944 int width, int height, int offset) 2945 { 2946 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2947 color_space, color_depth, solid_color, width, height, offset); 2948 } 2949