1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "vm_helper.h" 50 #include "dccg.h" 51 #include "dc_dmub_srv.h" 52 #include "dce/dmub_hw_lock_mgr.h" 53 #include "hw_sequencer.h" 54 #include "dpcd_defs.h" 55 #include "inc/link_enc_cfg.h" 56 #include "link_hwss.h" 57 #include "link.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 #define CTX \ 62 hws->ctx 63 #define REG(reg)\ 64 hws->regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 static int find_free_gsl_group(const struct dc *dc) 71 { 72 if (dc->res_pool->gsl_groups.gsl_0 == 0) 73 return 1; 74 if (dc->res_pool->gsl_groups.gsl_1 == 0) 75 return 2; 76 if (dc->res_pool->gsl_groups.gsl_2 == 0) 77 return 3; 78 79 return 0; 80 } 81 82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 83 * This is only used to lock pipes in pipe splitting case with immediate flip 84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 85 * so we get tearing with freesync since we cannot flip multiple pipes 86 * atomically. 87 * We use GSL for this: 88 * - immediate flip: find first available GSL group if not already assigned 89 * program gsl with that group, set current OTG as master 90 * and always us 0x4 = AND of flip_ready from all pipes 91 * - vsync flip: disable GSL if used 92 * 93 * Groups in stream_res are stored as +1 from HW registers, i.e. 94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 95 * Using a magic value like -1 would require tracking all inits/resets 96 */ 97 static void dcn20_setup_gsl_group_as_lock( 98 const struct dc *dc, 99 struct pipe_ctx *pipe_ctx, 100 bool enable) 101 { 102 struct gsl_params gsl; 103 int group_idx; 104 105 memset(&gsl, 0, sizeof(struct gsl_params)); 106 107 if (enable) { 108 /* return if group already assigned since GSL was set up 109 * for vsync flip, we would unassign so it can't be "left over" 110 */ 111 if (pipe_ctx->stream_res.gsl_group > 0) 112 return; 113 114 group_idx = find_free_gsl_group(dc); 115 ASSERT(group_idx != 0); 116 pipe_ctx->stream_res.gsl_group = group_idx; 117 118 /* set gsl group reg field and mark resource used */ 119 switch (group_idx) { 120 case 1: 121 gsl.gsl0_en = 1; 122 dc->res_pool->gsl_groups.gsl_0 = 1; 123 break; 124 case 2: 125 gsl.gsl1_en = 1; 126 dc->res_pool->gsl_groups.gsl_1 = 1; 127 break; 128 case 3: 129 gsl.gsl2_en = 1; 130 dc->res_pool->gsl_groups.gsl_2 = 1; 131 break; 132 default: 133 BREAK_TO_DEBUGGER(); 134 return; // invalid case 135 } 136 gsl.gsl_master_en = 1; 137 } else { 138 group_idx = pipe_ctx->stream_res.gsl_group; 139 if (group_idx == 0) 140 return; // if not in use, just return 141 142 pipe_ctx->stream_res.gsl_group = 0; 143 144 /* unset gsl group reg field and mark resource free */ 145 switch (group_idx) { 146 case 1: 147 gsl.gsl0_en = 0; 148 dc->res_pool->gsl_groups.gsl_0 = 0; 149 break; 150 case 2: 151 gsl.gsl1_en = 0; 152 dc->res_pool->gsl_groups.gsl_1 = 0; 153 break; 154 case 3: 155 gsl.gsl2_en = 0; 156 dc->res_pool->gsl_groups.gsl_2 = 0; 157 break; 158 default: 159 BREAK_TO_DEBUGGER(); 160 return; 161 } 162 gsl.gsl_master_en = 0; 163 } 164 165 /* at this point we want to program whether it's to enable or disable */ 166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 168 pipe_ctx->stream_res.tg->funcs->set_gsl( 169 pipe_ctx->stream_res.tg, 170 &gsl); 171 172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 174 } else 175 BREAK_TO_DEBUGGER(); 176 } 177 178 void dcn20_set_flip_control_gsl( 179 struct pipe_ctx *pipe_ctx, 180 bool flip_immediate) 181 { 182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 184 pipe_ctx->plane_res.hubp, flip_immediate); 185 186 } 187 188 void dcn20_enable_power_gating_plane( 189 struct dce_hwseq *hws, 190 bool enable) 191 { 192 bool force_on = true; /* disable power gating */ 193 uint32_t org_ip_request_cntl = 0; 194 195 if (enable) 196 force_on = false; 197 198 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 199 if (org_ip_request_cntl == 0) 200 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 201 202 /* DCHUBP0/1/2/3/4/5 */ 203 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 204 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 205 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 206 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 207 if (REG(DOMAIN8_PG_CONFIG)) 208 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 209 if (REG(DOMAIN10_PG_CONFIG)) 210 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 211 212 /* DPP0/1/2/3/4/5 */ 213 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 214 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 215 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 216 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 217 if (REG(DOMAIN9_PG_CONFIG)) 218 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 219 if (REG(DOMAIN11_PG_CONFIG)) 220 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 221 222 /* DCS0/1/2/3/4/5 */ 223 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 224 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 225 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 226 if (REG(DOMAIN19_PG_CONFIG)) 227 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 228 if (REG(DOMAIN20_PG_CONFIG)) 229 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 230 if (REG(DOMAIN21_PG_CONFIG)) 231 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 232 233 if (org_ip_request_cntl == 0) 234 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 235 236 } 237 238 void dcn20_dccg_init(struct dce_hwseq *hws) 239 { 240 /* 241 * set MICROSECOND_TIME_BASE_DIV 242 * 100Mhz refclk -> 0x120264 243 * 27Mhz refclk -> 0x12021b 244 * 48Mhz refclk -> 0x120230 245 * 246 */ 247 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 248 249 /* 250 * set MILLISECOND_TIME_BASE_DIV 251 * 100Mhz refclk -> 0x1186a0 252 * 27Mhz refclk -> 0x106978 253 * 48Mhz refclk -> 0x10bb80 254 * 255 */ 256 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 257 258 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 259 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 260 } 261 262 void dcn20_disable_vga( 263 struct dce_hwseq *hws) 264 { 265 REG_WRITE(D1VGA_CONTROL, 0); 266 REG_WRITE(D2VGA_CONTROL, 0); 267 REG_WRITE(D3VGA_CONTROL, 0); 268 REG_WRITE(D4VGA_CONTROL, 0); 269 REG_WRITE(D5VGA_CONTROL, 0); 270 REG_WRITE(D6VGA_CONTROL, 0); 271 } 272 273 void dcn20_program_triple_buffer( 274 const struct dc *dc, 275 struct pipe_ctx *pipe_ctx, 276 bool enable_triple_buffer) 277 { 278 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 279 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 280 pipe_ctx->plane_res.hubp, 281 enable_triple_buffer); 282 } 283 } 284 285 /* Blank pixel data during initialization */ 286 void dcn20_init_blank( 287 struct dc *dc, 288 struct timing_generator *tg) 289 { 290 struct dce_hwseq *hws = dc->hwseq; 291 enum dc_color_space color_space; 292 struct tg_color black_color = {0}; 293 struct output_pixel_processor *opp = NULL; 294 struct output_pixel_processor *bottom_opp = NULL; 295 uint32_t num_opps, opp_id_src0, opp_id_src1; 296 uint32_t otg_active_width, otg_active_height; 297 298 /* program opp dpg blank color */ 299 color_space = COLOR_SPACE_SRGB; 300 color_space_to_black_color(dc, color_space, &black_color); 301 302 /* get the OTG active size */ 303 tg->funcs->get_otg_active_size(tg, 304 &otg_active_width, 305 &otg_active_height); 306 307 /* get the OPTC source */ 308 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 309 310 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 311 ASSERT(false); 312 return; 313 } 314 opp = dc->res_pool->opps[opp_id_src0]; 315 316 /* don't override the blank pattern if already enabled with the correct one. */ 317 if (opp->funcs->dpg_is_blanked && opp->funcs->dpg_is_blanked(opp)) 318 return; 319 320 if (num_opps == 2) { 321 otg_active_width = otg_active_width / 2; 322 323 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 324 ASSERT(false); 325 return; 326 } 327 bottom_opp = dc->res_pool->opps[opp_id_src1]; 328 } 329 330 opp->funcs->opp_set_disp_pattern_generator( 331 opp, 332 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 333 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 334 COLOR_DEPTH_UNDEFINED, 335 &black_color, 336 otg_active_width, 337 otg_active_height, 338 0); 339 340 if (num_opps == 2) { 341 bottom_opp->funcs->opp_set_disp_pattern_generator( 342 bottom_opp, 343 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 344 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 345 COLOR_DEPTH_UNDEFINED, 346 &black_color, 347 otg_active_width, 348 otg_active_height, 349 0); 350 } 351 352 hws->funcs.wait_for_blank_complete(opp); 353 } 354 355 void dcn20_dsc_pg_control( 356 struct dce_hwseq *hws, 357 unsigned int dsc_inst, 358 bool power_on) 359 { 360 uint32_t power_gate = power_on ? 0 : 1; 361 uint32_t pwr_status = power_on ? 0 : 2; 362 uint32_t org_ip_request_cntl = 0; 363 364 if (hws->ctx->dc->debug.disable_dsc_power_gate) 365 return; 366 367 if (REG(DOMAIN16_PG_CONFIG) == 0) 368 return; 369 370 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 371 if (org_ip_request_cntl == 0) 372 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 373 374 switch (dsc_inst) { 375 case 0: /* DSC0 */ 376 REG_UPDATE(DOMAIN16_PG_CONFIG, 377 DOMAIN16_POWER_GATE, power_gate); 378 379 REG_WAIT(DOMAIN16_PG_STATUS, 380 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 381 1, 1000); 382 break; 383 case 1: /* DSC1 */ 384 REG_UPDATE(DOMAIN17_PG_CONFIG, 385 DOMAIN17_POWER_GATE, power_gate); 386 387 REG_WAIT(DOMAIN17_PG_STATUS, 388 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 389 1, 1000); 390 break; 391 case 2: /* DSC2 */ 392 REG_UPDATE(DOMAIN18_PG_CONFIG, 393 DOMAIN18_POWER_GATE, power_gate); 394 395 REG_WAIT(DOMAIN18_PG_STATUS, 396 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 397 1, 1000); 398 break; 399 case 3: /* DSC3 */ 400 REG_UPDATE(DOMAIN19_PG_CONFIG, 401 DOMAIN19_POWER_GATE, power_gate); 402 403 REG_WAIT(DOMAIN19_PG_STATUS, 404 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 405 1, 1000); 406 break; 407 case 4: /* DSC4 */ 408 REG_UPDATE(DOMAIN20_PG_CONFIG, 409 DOMAIN20_POWER_GATE, power_gate); 410 411 REG_WAIT(DOMAIN20_PG_STATUS, 412 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 413 1, 1000); 414 break; 415 case 5: /* DSC5 */ 416 REG_UPDATE(DOMAIN21_PG_CONFIG, 417 DOMAIN21_POWER_GATE, power_gate); 418 419 REG_WAIT(DOMAIN21_PG_STATUS, 420 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 421 1, 1000); 422 break; 423 default: 424 BREAK_TO_DEBUGGER(); 425 break; 426 } 427 428 if (org_ip_request_cntl == 0) 429 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 430 } 431 432 void dcn20_dpp_pg_control( 433 struct dce_hwseq *hws, 434 unsigned int dpp_inst, 435 bool power_on) 436 { 437 uint32_t power_gate = power_on ? 0 : 1; 438 uint32_t pwr_status = power_on ? 0 : 2; 439 440 if (hws->ctx->dc->debug.disable_dpp_power_gate) 441 return; 442 if (REG(DOMAIN1_PG_CONFIG) == 0) 443 return; 444 445 switch (dpp_inst) { 446 case 0: /* DPP0 */ 447 REG_UPDATE(DOMAIN1_PG_CONFIG, 448 DOMAIN1_POWER_GATE, power_gate); 449 450 REG_WAIT(DOMAIN1_PG_STATUS, 451 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 452 1, 1000); 453 break; 454 case 1: /* DPP1 */ 455 REG_UPDATE(DOMAIN3_PG_CONFIG, 456 DOMAIN3_POWER_GATE, power_gate); 457 458 REG_WAIT(DOMAIN3_PG_STATUS, 459 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 460 1, 1000); 461 break; 462 case 2: /* DPP2 */ 463 REG_UPDATE(DOMAIN5_PG_CONFIG, 464 DOMAIN5_POWER_GATE, power_gate); 465 466 REG_WAIT(DOMAIN5_PG_STATUS, 467 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 468 1, 1000); 469 break; 470 case 3: /* DPP3 */ 471 REG_UPDATE(DOMAIN7_PG_CONFIG, 472 DOMAIN7_POWER_GATE, power_gate); 473 474 REG_WAIT(DOMAIN7_PG_STATUS, 475 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 476 1, 1000); 477 break; 478 case 4: /* DPP4 */ 479 REG_UPDATE(DOMAIN9_PG_CONFIG, 480 DOMAIN9_POWER_GATE, power_gate); 481 482 REG_WAIT(DOMAIN9_PG_STATUS, 483 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 484 1, 1000); 485 break; 486 case 5: /* DPP5 */ 487 /* 488 * Do not power gate DPP5, should be left at HW default, power on permanently. 489 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 490 * reset. 491 * REG_UPDATE(DOMAIN11_PG_CONFIG, 492 * DOMAIN11_POWER_GATE, power_gate); 493 * 494 * REG_WAIT(DOMAIN11_PG_STATUS, 495 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 496 * 1, 1000); 497 */ 498 break; 499 default: 500 BREAK_TO_DEBUGGER(); 501 break; 502 } 503 } 504 505 506 void dcn20_hubp_pg_control( 507 struct dce_hwseq *hws, 508 unsigned int hubp_inst, 509 bool power_on) 510 { 511 uint32_t power_gate = power_on ? 0 : 1; 512 uint32_t pwr_status = power_on ? 0 : 2; 513 514 if (hws->ctx->dc->debug.disable_hubp_power_gate) 515 return; 516 if (REG(DOMAIN0_PG_CONFIG) == 0) 517 return; 518 519 switch (hubp_inst) { 520 case 0: /* DCHUBP0 */ 521 REG_UPDATE(DOMAIN0_PG_CONFIG, 522 DOMAIN0_POWER_GATE, power_gate); 523 524 REG_WAIT(DOMAIN0_PG_STATUS, 525 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 526 1, 1000); 527 break; 528 case 1: /* DCHUBP1 */ 529 REG_UPDATE(DOMAIN2_PG_CONFIG, 530 DOMAIN2_POWER_GATE, power_gate); 531 532 REG_WAIT(DOMAIN2_PG_STATUS, 533 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 534 1, 1000); 535 break; 536 case 2: /* DCHUBP2 */ 537 REG_UPDATE(DOMAIN4_PG_CONFIG, 538 DOMAIN4_POWER_GATE, power_gate); 539 540 REG_WAIT(DOMAIN4_PG_STATUS, 541 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 542 1, 1000); 543 break; 544 case 3: /* DCHUBP3 */ 545 REG_UPDATE(DOMAIN6_PG_CONFIG, 546 DOMAIN6_POWER_GATE, power_gate); 547 548 REG_WAIT(DOMAIN6_PG_STATUS, 549 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 550 1, 1000); 551 break; 552 case 4: /* DCHUBP4 */ 553 REG_UPDATE(DOMAIN8_PG_CONFIG, 554 DOMAIN8_POWER_GATE, power_gate); 555 556 REG_WAIT(DOMAIN8_PG_STATUS, 557 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 558 1, 1000); 559 break; 560 case 5: /* DCHUBP5 */ 561 /* 562 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 563 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 564 * reset. 565 * REG_UPDATE(DOMAIN10_PG_CONFIG, 566 * DOMAIN10_POWER_GATE, power_gate); 567 * 568 * REG_WAIT(DOMAIN10_PG_STATUS, 569 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 570 * 1, 1000); 571 */ 572 break; 573 default: 574 BREAK_TO_DEBUGGER(); 575 break; 576 } 577 } 578 579 580 /* disable HW used by plane. 581 * note: cannot disable until disconnect is complete 582 */ 583 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 584 { 585 struct dce_hwseq *hws = dc->hwseq; 586 struct hubp *hubp = pipe_ctx->plane_res.hubp; 587 struct dpp *dpp = pipe_ctx->plane_res.dpp; 588 589 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 590 591 /* In flip immediate with pipe splitting case GSL is used for 592 * synchronization so we must disable it when the plane is disabled. 593 */ 594 if (pipe_ctx->stream_res.gsl_group != 0) 595 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 596 597 if (hubp->funcs->hubp_update_mall_sel) 598 hubp->funcs->hubp_update_mall_sel(hubp, 0, false); 599 600 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 601 602 hubp->funcs->hubp_clk_cntl(hubp, false); 603 604 dpp->funcs->dpp_dppclk_control(dpp, false, false); 605 606 hubp->power_gated = true; 607 608 hws->funcs.plane_atomic_power_down(dc, 609 pipe_ctx->plane_res.dpp, 610 pipe_ctx->plane_res.hubp); 611 612 pipe_ctx->stream = NULL; 613 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 614 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 615 pipe_ctx->top_pipe = NULL; 616 pipe_ctx->bottom_pipe = NULL; 617 pipe_ctx->plane_state = NULL; 618 } 619 620 621 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 622 { 623 bool is_phantom = pipe_ctx->plane_state && pipe_ctx->plane_state->is_phantom; 624 struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; 625 626 DC_LOGGER_INIT(dc->ctx->logger); 627 628 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 629 return; 630 631 dcn20_plane_atomic_disable(dc, pipe_ctx); 632 633 /* Turn back off the phantom OTG after the phantom plane is fully disabled 634 */ 635 if (is_phantom) 636 if (tg && tg->funcs->disable_phantom_crtc) 637 tg->funcs->disable_phantom_crtc(tg); 638 639 DC_LOG_DC("Power down front end %d\n", 640 pipe_ctx->pipe_idx); 641 } 642 643 void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) 644 { 645 dcn20_blank_pixel_data(dc, pipe_ctx, blank); 646 } 647 648 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 649 int opp_cnt) 650 { 651 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 652 int flow_ctrl_cnt; 653 654 if (opp_cnt >= 2) 655 hblank_halved = true; 656 657 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 658 stream->timing.h_border_left - 659 stream->timing.h_border_right; 660 661 if (hblank_halved) 662 flow_ctrl_cnt /= 2; 663 664 /* ODM combine 4:1 case */ 665 if (opp_cnt == 4) 666 flow_ctrl_cnt /= 2; 667 668 return flow_ctrl_cnt; 669 } 670 671 enum dc_status dcn20_enable_stream_timing( 672 struct pipe_ctx *pipe_ctx, 673 struct dc_state *context, 674 struct dc *dc) 675 { 676 struct dce_hwseq *hws = dc->hwseq; 677 struct dc_stream_state *stream = pipe_ctx->stream; 678 struct drr_params params = {0}; 679 unsigned int event_triggers = 0; 680 struct pipe_ctx *odm_pipe; 681 int opp_cnt = 1; 682 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 683 bool interlace = stream->timing.flags.INTERLACE; 684 int i; 685 struct mpc_dwb_flow_control flow_control; 686 struct mpc *mpc = dc->res_pool->mpc; 687 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 688 unsigned int k1_div = PIXEL_RATE_DIV_NA; 689 unsigned int k2_div = PIXEL_RATE_DIV_NA; 690 691 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 692 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 693 694 dc->res_pool->dccg->funcs->set_pixel_rate_div( 695 dc->res_pool->dccg, 696 pipe_ctx->stream_res.tg->inst, 697 k1_div, k2_div); 698 } 699 /* by upper caller loop, pipe0 is parent pipe and be called first. 700 * back end is set up by for pipe0. Other children pipe share back end 701 * with pipe 0. No program is needed. 702 */ 703 if (pipe_ctx->top_pipe != NULL) 704 return DC_OK; 705 706 /* TODO check if timing_changed, disable stream if timing changed */ 707 708 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 709 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 710 opp_cnt++; 711 } 712 713 if (opp_cnt > 1) 714 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 715 pipe_ctx->stream_res.tg, 716 opp_inst, opp_cnt, 717 &pipe_ctx->stream->timing); 718 719 /* HW program guide assume display already disable 720 * by unplug sequence. OTG assume stop. 721 */ 722 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 723 724 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 725 pipe_ctx->clock_source, 726 &pipe_ctx->stream_res.pix_clk_params, 727 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 728 &pipe_ctx->pll_settings)) { 729 BREAK_TO_DEBUGGER(); 730 return DC_ERROR_UNEXPECTED; 731 } 732 733 if (dc_is_hdmi_tmds_signal(stream->signal)) { 734 stream->link->phy_state.symclk_ref_cnts.otg = 1; 735 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 736 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 737 else 738 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 739 } 740 741 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 742 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 743 744 pipe_ctx->stream_res.tg->funcs->program_timing( 745 pipe_ctx->stream_res.tg, 746 &stream->timing, 747 pipe_ctx->pipe_dlg_param.vready_offset, 748 pipe_ctx->pipe_dlg_param.vstartup_start, 749 pipe_ctx->pipe_dlg_param.vupdate_offset, 750 pipe_ctx->pipe_dlg_param.vupdate_width, 751 pipe_ctx->stream->signal, 752 true); 753 754 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 755 flow_control.flow_ctrl_mode = 0; 756 flow_control.flow_ctrl_cnt0 = 0x80; 757 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 758 if (mpc->funcs->set_out_rate_control) { 759 for (i = 0; i < opp_cnt; ++i) { 760 mpc->funcs->set_out_rate_control( 761 mpc, opp_inst[i], 762 true, 763 rate_control_2x_pclk, 764 &flow_control); 765 } 766 } 767 768 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 769 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 770 odm_pipe->stream_res.opp, 771 true); 772 773 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 774 pipe_ctx->stream_res.opp, 775 true); 776 777 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 778 779 /* VTG is within DCHUB command block. DCFCLK is always on */ 780 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 781 BREAK_TO_DEBUGGER(); 782 return DC_ERROR_UNEXPECTED; 783 } 784 785 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 786 787 params.vertical_total_min = stream->adjust.v_total_min; 788 params.vertical_total_max = stream->adjust.v_total_max; 789 params.vertical_total_mid = stream->adjust.v_total_mid; 790 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 791 if (pipe_ctx->stream_res.tg->funcs->set_drr) 792 pipe_ctx->stream_res.tg->funcs->set_drr( 793 pipe_ctx->stream_res.tg, ¶ms); 794 795 // DRR should set trigger event to monitor surface update event 796 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 797 event_triggers = 0x80; 798 /* Event triggers and num frames initialized for DRR, but can be 799 * later updated for PSR use. Note DRR trigger events are generated 800 * regardless of whether num frames met. 801 */ 802 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 803 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 804 pipe_ctx->stream_res.tg, event_triggers, 2); 805 806 /* TODO program crtc source select for non-virtual signal*/ 807 /* TODO program FMT */ 808 /* TODO setup link_enc */ 809 /* TODO set stream attributes */ 810 /* TODO program audio */ 811 /* TODO enable stream if timing changed */ 812 /* TODO unblank stream if DP */ 813 814 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { 815 if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) 816 pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); 817 } 818 return DC_OK; 819 } 820 821 void dcn20_program_output_csc(struct dc *dc, 822 struct pipe_ctx *pipe_ctx, 823 enum dc_color_space colorspace, 824 uint16_t *matrix, 825 int opp_id) 826 { 827 struct mpc *mpc = dc->res_pool->mpc; 828 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 829 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 830 831 if (mpc->funcs->power_on_mpc_mem_pwr) 832 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 833 834 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 835 if (mpc->funcs->set_output_csc != NULL) 836 mpc->funcs->set_output_csc(mpc, 837 opp_id, 838 matrix, 839 ocsc_mode); 840 } else { 841 if (mpc->funcs->set_ocsc_default != NULL) 842 mpc->funcs->set_ocsc_default(mpc, 843 opp_id, 844 colorspace, 845 ocsc_mode); 846 } 847 } 848 849 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 850 const struct dc_stream_state *stream) 851 { 852 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 853 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 854 struct pwl_params *params = NULL; 855 /* 856 * program OGAM only for the top pipe 857 * if there is a pipe split then fix diagnostic is required: 858 * how to pass OGAM parameter for stream. 859 * if programming for all pipes is required then remove condition 860 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 861 */ 862 if (mpc->funcs->power_on_mpc_mem_pwr) 863 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 864 if (pipe_ctx->top_pipe == NULL 865 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 866 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 867 params = &stream->out_transfer_func->pwl; 868 else if (pipe_ctx->stream->out_transfer_func->type == 869 TF_TYPE_DISTRIBUTED_POINTS && 870 cm_helper_translate_curve_to_hw_format(dc->ctx, 871 stream->out_transfer_func, 872 &mpc->blender_params, false)) 873 params = &mpc->blender_params; 874 /* 875 * there is no ROM 876 */ 877 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 878 BREAK_TO_DEBUGGER(); 879 } 880 /* 881 * if above if is not executed then 'params' equal to 0 and set in bypass 882 */ 883 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 884 885 return true; 886 } 887 888 bool dcn20_set_blend_lut( 889 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 890 { 891 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 892 bool result = true; 893 struct pwl_params *blend_lut = NULL; 894 895 if (plane_state->blend_tf) { 896 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 897 blend_lut = &plane_state->blend_tf->pwl; 898 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 899 cm_helper_translate_curve_to_hw_format(plane_state->ctx, 900 plane_state->blend_tf, 901 &dpp_base->regamma_params, false); 902 blend_lut = &dpp_base->regamma_params; 903 } 904 } 905 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 906 907 return result; 908 } 909 910 bool dcn20_set_shaper_3dlut( 911 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 912 { 913 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 914 bool result = true; 915 struct pwl_params *shaper_lut = NULL; 916 917 if (plane_state->in_shaper_func) { 918 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 919 shaper_lut = &plane_state->in_shaper_func->pwl; 920 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 921 cm_helper_translate_curve_to_hw_format(plane_state->ctx, 922 plane_state->in_shaper_func, 923 &dpp_base->shaper_params, true); 924 shaper_lut = &dpp_base->shaper_params; 925 } 926 } 927 928 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 929 if (plane_state->lut3d_func && 930 plane_state->lut3d_func->state.bits.initialized == 1) 931 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 932 &plane_state->lut3d_func->lut_3d); 933 else 934 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 935 936 return result; 937 } 938 939 bool dcn20_set_input_transfer_func(struct dc *dc, 940 struct pipe_ctx *pipe_ctx, 941 const struct dc_plane_state *plane_state) 942 { 943 struct dce_hwseq *hws = dc->hwseq; 944 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 945 const struct dc_transfer_func *tf = NULL; 946 bool result = true; 947 bool use_degamma_ram = false; 948 949 if (dpp_base == NULL || plane_state == NULL) 950 return false; 951 952 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 953 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 954 955 if (plane_state->in_transfer_func) 956 tf = plane_state->in_transfer_func; 957 958 959 if (tf == NULL) { 960 dpp_base->funcs->dpp_set_degamma(dpp_base, 961 IPP_DEGAMMA_MODE_BYPASS); 962 return true; 963 } 964 965 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 966 use_degamma_ram = true; 967 968 if (use_degamma_ram == true) { 969 if (tf->type == TF_TYPE_HWPWL) 970 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 971 &tf->pwl); 972 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 973 cm_helper_translate_curve_to_degamma_hw_format(tf, 974 &dpp_base->degamma_params); 975 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 976 &dpp_base->degamma_params); 977 } 978 return true; 979 } 980 /* handle here the optimized cases when de-gamma ROM could be used. 981 * 982 */ 983 if (tf->type == TF_TYPE_PREDEFINED) { 984 switch (tf->tf) { 985 case TRANSFER_FUNCTION_SRGB: 986 dpp_base->funcs->dpp_set_degamma(dpp_base, 987 IPP_DEGAMMA_MODE_HW_sRGB); 988 break; 989 case TRANSFER_FUNCTION_BT709: 990 dpp_base->funcs->dpp_set_degamma(dpp_base, 991 IPP_DEGAMMA_MODE_HW_xvYCC); 992 break; 993 case TRANSFER_FUNCTION_LINEAR: 994 dpp_base->funcs->dpp_set_degamma(dpp_base, 995 IPP_DEGAMMA_MODE_BYPASS); 996 break; 997 case TRANSFER_FUNCTION_PQ: 998 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 999 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 1000 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 1001 result = true; 1002 break; 1003 default: 1004 result = false; 1005 break; 1006 } 1007 } else if (tf->type == TF_TYPE_BYPASS) 1008 dpp_base->funcs->dpp_set_degamma(dpp_base, 1009 IPP_DEGAMMA_MODE_BYPASS); 1010 else { 1011 /* 1012 * if we are here, we did not handle correctly. 1013 * fix is required for this use case 1014 */ 1015 BREAK_TO_DEBUGGER(); 1016 dpp_base->funcs->dpp_set_degamma(dpp_base, 1017 IPP_DEGAMMA_MODE_BYPASS); 1018 } 1019 1020 return result; 1021 } 1022 1023 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 1024 { 1025 struct pipe_ctx *odm_pipe; 1026 int opp_cnt = 1; 1027 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 1028 1029 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1030 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 1031 opp_cnt++; 1032 } 1033 1034 if (opp_cnt > 1) 1035 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 1036 pipe_ctx->stream_res.tg, 1037 opp_inst, opp_cnt, 1038 &pipe_ctx->stream->timing); 1039 else 1040 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 1041 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1042 } 1043 1044 void dcn20_blank_pixel_data( 1045 struct dc *dc, 1046 struct pipe_ctx *pipe_ctx, 1047 bool blank) 1048 { 1049 struct tg_color black_color = {0}; 1050 struct stream_resource *stream_res = &pipe_ctx->stream_res; 1051 struct dc_stream_state *stream = pipe_ctx->stream; 1052 enum dc_color_space color_space = stream->output_color_space; 1053 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1054 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1055 struct pipe_ctx *odm_pipe; 1056 int odm_cnt = 1; 1057 int h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1058 int v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1059 int odm_slice_width, last_odm_slice_width, offset = 0; 1060 1061 if (stream->link->test_pattern_enabled) 1062 return; 1063 1064 /* get opp dpg blank color */ 1065 color_space_to_black_color(dc, color_space, &black_color); 1066 1067 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1068 odm_cnt++; 1069 odm_slice_width = h_active / odm_cnt; 1070 last_odm_slice_width = h_active - odm_slice_width * (odm_cnt - 1); 1071 1072 if (blank) { 1073 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1074 1075 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1076 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1077 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1078 } 1079 } else { 1080 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1081 } 1082 1083 odm_pipe = pipe_ctx; 1084 1085 while (odm_pipe->next_odm_pipe) { 1086 dc->hwss.set_disp_pattern_generator(dc, 1087 odm_pipe, 1088 test_pattern, 1089 test_pattern_color_space, 1090 stream->timing.display_color_depth, 1091 &black_color, 1092 odm_slice_width, 1093 v_active, 1094 offset); 1095 offset += odm_slice_width; 1096 odm_pipe = odm_pipe->next_odm_pipe; 1097 } 1098 1099 dc->hwss.set_disp_pattern_generator(dc, 1100 odm_pipe, 1101 test_pattern, 1102 test_pattern_color_space, 1103 stream->timing.display_color_depth, 1104 &black_color, 1105 last_odm_slice_width, 1106 v_active, 1107 offset); 1108 1109 if (!blank) 1110 if (stream_res->abm) { 1111 dc->hwss.set_pipe(pipe_ctx); 1112 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1113 } 1114 } 1115 1116 1117 static void dcn20_power_on_plane_resources( 1118 struct dce_hwseq *hws, 1119 struct pipe_ctx *pipe_ctx) 1120 { 1121 DC_LOGGER_INIT(hws->ctx->logger); 1122 1123 if (hws->funcs.dpp_root_clock_control) 1124 hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1125 1126 if (REG(DC_IP_REQUEST_CNTL)) { 1127 REG_SET(DC_IP_REQUEST_CNTL, 0, 1128 IP_REQUEST_EN, 1); 1129 1130 if (hws->funcs.dpp_pg_control) 1131 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1132 1133 if (hws->funcs.hubp_pg_control) 1134 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1135 1136 REG_SET(DC_IP_REQUEST_CNTL, 0, 1137 IP_REQUEST_EN, 0); 1138 DC_LOG_DEBUG( 1139 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1140 } 1141 } 1142 1143 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1144 struct dc_state *context) 1145 { 1146 //if (dc->debug.sanity_checks) { 1147 // dcn10_verify_allow_pstate_change_high(dc); 1148 //} 1149 dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx); 1150 1151 /* enable DCFCLK current DCHUB */ 1152 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1153 1154 /* initialize HUBP on power up */ 1155 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1156 1157 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1158 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1159 pipe_ctx->stream_res.opp, 1160 true); 1161 1162 /* TODO: enable/disable in dm as per update type. 1163 if (plane_state) { 1164 DC_LOG_DC(dc->ctx->logger, 1165 "Pipe:%d 0x%x: addr hi:0x%x, " 1166 "addr low:0x%x, " 1167 "src: %d, %d, %d," 1168 " %d; dst: %d, %d, %d, %d;\n", 1169 pipe_ctx->pipe_idx, 1170 plane_state, 1171 plane_state->address.grph.addr.high_part, 1172 plane_state->address.grph.addr.low_part, 1173 plane_state->src_rect.x, 1174 plane_state->src_rect.y, 1175 plane_state->src_rect.width, 1176 plane_state->src_rect.height, 1177 plane_state->dst_rect.x, 1178 plane_state->dst_rect.y, 1179 plane_state->dst_rect.width, 1180 plane_state->dst_rect.height); 1181 1182 DC_LOG_DC(dc->ctx->logger, 1183 "Pipe %d: width, height, x, y format:%d\n" 1184 "viewport:%d, %d, %d, %d\n" 1185 "recout: %d, %d, %d, %d\n", 1186 pipe_ctx->pipe_idx, 1187 plane_state->format, 1188 pipe_ctx->plane_res.scl_data.viewport.width, 1189 pipe_ctx->plane_res.scl_data.viewport.height, 1190 pipe_ctx->plane_res.scl_data.viewport.x, 1191 pipe_ctx->plane_res.scl_data.viewport.y, 1192 pipe_ctx->plane_res.scl_data.recout.width, 1193 pipe_ctx->plane_res.scl_data.recout.height, 1194 pipe_ctx->plane_res.scl_data.recout.x, 1195 pipe_ctx->plane_res.scl_data.recout.y); 1196 print_rq_dlg_ttu(dc, pipe_ctx); 1197 } 1198 */ 1199 if (dc->vm_pa_config.valid) { 1200 struct vm_system_aperture_param apt; 1201 1202 apt.sys_default.quad_part = 0; 1203 1204 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1205 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1206 1207 // Program system aperture settings 1208 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1209 } 1210 1211 if (!pipe_ctx->top_pipe 1212 && pipe_ctx->plane_state 1213 && pipe_ctx->plane_state->flip_int_enabled 1214 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1215 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1216 1217 // if (dc->debug.sanity_checks) { 1218 // dcn10_verify_allow_pstate_change_high(dc); 1219 // } 1220 } 1221 1222 void dcn20_pipe_control_lock( 1223 struct dc *dc, 1224 struct pipe_ctx *pipe, 1225 bool lock) 1226 { 1227 struct pipe_ctx *temp_pipe; 1228 bool flip_immediate = false; 1229 1230 /* use TG master update lock to lock everything on the TG 1231 * therefore only top pipe need to lock 1232 */ 1233 if (!pipe || pipe->top_pipe) 1234 return; 1235 1236 if (pipe->plane_state != NULL) 1237 flip_immediate = pipe->plane_state->flip_immediate; 1238 1239 if (pipe->stream_res.gsl_group > 0) { 1240 temp_pipe = pipe->bottom_pipe; 1241 while (!flip_immediate && temp_pipe) { 1242 if (temp_pipe->plane_state != NULL) 1243 flip_immediate = temp_pipe->plane_state->flip_immediate; 1244 temp_pipe = temp_pipe->bottom_pipe; 1245 } 1246 } 1247 1248 if (flip_immediate && lock) { 1249 const int TIMEOUT_FOR_FLIP_PENDING_US = 100000; 1250 unsigned int polling_interval_us = 1; 1251 int i; 1252 1253 temp_pipe = pipe; 1254 while (temp_pipe) { 1255 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1256 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING_US / polling_interval_us; ++i) { 1257 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1258 break; 1259 udelay(polling_interval_us); 1260 } 1261 1262 /* no reason it should take this long for immediate flips */ 1263 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING_US); 1264 } 1265 temp_pipe = temp_pipe->bottom_pipe; 1266 } 1267 } 1268 1269 /* In flip immediate and pipe splitting case, we need to use GSL 1270 * for synchronization. Only do setup on locking and on flip type change. 1271 */ 1272 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1273 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1274 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1275 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1276 1277 if (pipe->plane_state != NULL) 1278 flip_immediate = pipe->plane_state->flip_immediate; 1279 1280 temp_pipe = pipe->bottom_pipe; 1281 while (flip_immediate && temp_pipe) { 1282 if (temp_pipe->plane_state != NULL) 1283 flip_immediate = temp_pipe->plane_state->flip_immediate; 1284 temp_pipe = temp_pipe->bottom_pipe; 1285 } 1286 1287 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1288 !flip_immediate) 1289 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1290 1291 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1292 union dmub_hw_lock_flags hw_locks = { 0 }; 1293 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1294 1295 hw_locks.bits.lock_pipe = 1; 1296 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1297 1298 if (pipe->plane_state != NULL) 1299 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1300 1301 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1302 lock, 1303 &hw_locks, 1304 &inst_flags); 1305 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1306 if (lock) 1307 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1308 else 1309 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1310 } else { 1311 if (lock) 1312 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1313 else 1314 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1315 } 1316 } 1317 1318 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1319 { 1320 new_pipe->update_flags.raw = 0; 1321 1322 /* If non-phantom pipe is being transitioned to a phantom pipe, 1323 * set disable and return immediately. This is because the pipe 1324 * that was previously in use must be fully disabled before we 1325 * can "enable" it as a phantom pipe (since the OTG will certainly 1326 * be different). The post_unlock sequence will set the correct 1327 * update flags to enable the phantom pipe. 1328 */ 1329 if (old_pipe->plane_state && !old_pipe->plane_state->is_phantom && 1330 new_pipe->plane_state && new_pipe->plane_state->is_phantom) { 1331 new_pipe->update_flags.bits.disable = 1; 1332 return; 1333 } 1334 1335 /* Exit on unchanged, unused pipe */ 1336 if (!old_pipe->plane_state && !new_pipe->plane_state) 1337 return; 1338 /* Detect pipe enable/disable */ 1339 if (!old_pipe->plane_state && new_pipe->plane_state) { 1340 new_pipe->update_flags.bits.enable = 1; 1341 new_pipe->update_flags.bits.mpcc = 1; 1342 new_pipe->update_flags.bits.dppclk = 1; 1343 new_pipe->update_flags.bits.hubp_interdependent = 1; 1344 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1345 new_pipe->update_flags.bits.unbounded_req = 1; 1346 new_pipe->update_flags.bits.gamut_remap = 1; 1347 new_pipe->update_flags.bits.scaler = 1; 1348 new_pipe->update_flags.bits.viewport = 1; 1349 new_pipe->update_flags.bits.det_size = 1; 1350 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1351 new_pipe->update_flags.bits.odm = 1; 1352 new_pipe->update_flags.bits.global_sync = 1; 1353 } 1354 return; 1355 } 1356 1357 /* For SubVP we need to unconditionally enable because any phantom pipes are 1358 * always removed then newly added for every full updates whenever SubVP is in use. 1359 * The remove-add sequence of the phantom pipe always results in the pipe 1360 * being blanked in enable_stream_timing (DPG). 1361 */ 1362 if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) 1363 new_pipe->update_flags.bits.enable = 1; 1364 1365 /* Phantom pipes are effectively disabled, if the pipe was previously phantom 1366 * we have to enable 1367 */ 1368 if (old_pipe->plane_state && old_pipe->plane_state->is_phantom && 1369 new_pipe->plane_state && !new_pipe->plane_state->is_phantom) 1370 new_pipe->update_flags.bits.enable = 1; 1371 1372 if (old_pipe->plane_state && !new_pipe->plane_state) { 1373 new_pipe->update_flags.bits.disable = 1; 1374 return; 1375 } 1376 1377 /* Detect plane change */ 1378 if (old_pipe->plane_state != new_pipe->plane_state) { 1379 new_pipe->update_flags.bits.plane_changed = true; 1380 } 1381 1382 /* Detect top pipe only changes */ 1383 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1384 /* Detect odm changes */ 1385 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1386 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1387 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1388 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1389 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1390 new_pipe->update_flags.bits.odm = 1; 1391 1392 /* Detect global sync changes */ 1393 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1394 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1395 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1396 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1397 new_pipe->update_flags.bits.global_sync = 1; 1398 } 1399 1400 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1401 new_pipe->update_flags.bits.det_size = 1; 1402 1403 /* 1404 * Detect opp / tg change, only set on change, not on enable 1405 * Assume mpcc inst = pipe index, if not this code needs to be updated 1406 * since mpcc is what is affected by these. In fact all of our sequence 1407 * makes this assumption at the moment with how hubp reset is matched to 1408 * same index mpcc reset. 1409 */ 1410 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1411 new_pipe->update_flags.bits.opp_changed = 1; 1412 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1413 new_pipe->update_flags.bits.tg_changed = 1; 1414 1415 /* 1416 * Detect mpcc blending changes, only dpp inst and opp matter here, 1417 * mpccs getting removed/inserted update connected ones during their own 1418 * programming 1419 */ 1420 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1421 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1422 new_pipe->update_flags.bits.mpcc = 1; 1423 1424 /* Detect dppclk change */ 1425 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1426 new_pipe->update_flags.bits.dppclk = 1; 1427 1428 /* Check for scl update */ 1429 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1430 new_pipe->update_flags.bits.scaler = 1; 1431 /* Check for vp update */ 1432 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1433 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1434 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1435 new_pipe->update_flags.bits.viewport = 1; 1436 1437 /* Detect dlg/ttu/rq updates */ 1438 { 1439 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1440 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1441 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1442 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1443 1444 /* Detect pipe interdependent updates */ 1445 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1446 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1447 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1448 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1449 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1450 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1451 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1452 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1453 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1454 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1455 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1456 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1457 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1458 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1459 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1460 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1461 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1462 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1463 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1464 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1465 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1466 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1467 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1468 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1469 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1470 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1471 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1472 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1473 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1474 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1475 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1476 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1477 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1478 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1479 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1480 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1481 new_pipe->update_flags.bits.hubp_interdependent = 1; 1482 } 1483 /* Detect any other updates to ttu/rq/dlg */ 1484 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1485 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1486 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1487 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1488 } 1489 1490 if (old_pipe->unbounded_req != new_pipe->unbounded_req) 1491 new_pipe->update_flags.bits.unbounded_req = 1; 1492 } 1493 1494 static void dcn20_update_dchubp_dpp( 1495 struct dc *dc, 1496 struct pipe_ctx *pipe_ctx, 1497 struct dc_state *context) 1498 { 1499 struct dce_hwseq *hws = dc->hwseq; 1500 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1501 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1502 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1503 struct dccg *dccg = dc->res_pool->dccg; 1504 bool viewport_changed = false; 1505 1506 if (pipe_ctx->update_flags.bits.dppclk) 1507 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1508 1509 if (pipe_ctx->update_flags.bits.enable) 1510 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); 1511 1512 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1513 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1514 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1515 */ 1516 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1517 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1518 1519 hubp->funcs->hubp_setup( 1520 hubp, 1521 &pipe_ctx->dlg_regs, 1522 &pipe_ctx->ttu_regs, 1523 &pipe_ctx->rq_regs, 1524 &pipe_ctx->pipe_dlg_param); 1525 } 1526 1527 if (pipe_ctx->update_flags.bits.unbounded_req && hubp->funcs->set_unbounded_requesting) 1528 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1529 1530 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1531 hubp->funcs->hubp_setup_interdependent( 1532 hubp, 1533 &pipe_ctx->dlg_regs, 1534 &pipe_ctx->ttu_regs); 1535 1536 if (pipe_ctx->update_flags.bits.enable || 1537 pipe_ctx->update_flags.bits.plane_changed || 1538 plane_state->update_flags.bits.bpp_change || 1539 plane_state->update_flags.bits.input_csc_change || 1540 plane_state->update_flags.bits.color_space_change || 1541 plane_state->update_flags.bits.coeff_reduction_change) { 1542 struct dc_bias_and_scale bns_params = {0}; 1543 1544 // program the input csc 1545 dpp->funcs->dpp_setup(dpp, 1546 plane_state->format, 1547 EXPANSION_MODE_ZERO, 1548 plane_state->input_csc_color_matrix, 1549 plane_state->color_space, 1550 NULL); 1551 1552 if (dpp->funcs->dpp_program_bias_and_scale) { 1553 //TODO :for CNVC set scale and bias registers if necessary 1554 build_prescale_params(&bns_params, plane_state); 1555 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1556 } 1557 } 1558 1559 if (pipe_ctx->update_flags.bits.mpcc 1560 || pipe_ctx->update_flags.bits.plane_changed 1561 || plane_state->update_flags.bits.global_alpha_change 1562 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1563 // MPCC inst is equal to pipe index in practice 1564 hws->funcs.update_mpcc(dc, pipe_ctx); 1565 } 1566 1567 if (pipe_ctx->update_flags.bits.scaler || 1568 plane_state->update_flags.bits.scaling_change || 1569 plane_state->update_flags.bits.position_change || 1570 plane_state->update_flags.bits.per_pixel_alpha_change || 1571 pipe_ctx->stream->update_flags.bits.scaling) { 1572 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1573 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1574 /* scaler configuration */ 1575 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1576 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1577 } 1578 1579 if (pipe_ctx->update_flags.bits.viewport || 1580 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1581 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1582 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1583 1584 hubp->funcs->mem_program_viewport( 1585 hubp, 1586 &pipe_ctx->plane_res.scl_data.viewport, 1587 &pipe_ctx->plane_res.scl_data.viewport_c); 1588 viewport_changed = true; 1589 } 1590 1591 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1592 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1593 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1594 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1595 dc->hwss.set_cursor_position(pipe_ctx); 1596 dc->hwss.set_cursor_attribute(pipe_ctx); 1597 1598 if (dc->hwss.set_cursor_sdr_white_level) 1599 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1600 } 1601 1602 /* Any updates are handled in dc interface, just need 1603 * to apply existing for plane enable / opp change */ 1604 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1605 || pipe_ctx->update_flags.bits.plane_changed 1606 || pipe_ctx->stream->update_flags.bits.gamut_remap 1607 || plane_state->update_flags.bits.gamut_remap_change 1608 || pipe_ctx->stream->update_flags.bits.out_csc) { 1609 /* dpp/cm gamut remap*/ 1610 dc->hwss.program_gamut_remap(pipe_ctx); 1611 1612 /*call the dcn2 method which uses mpc csc*/ 1613 dc->hwss.program_output_csc(dc, 1614 pipe_ctx, 1615 pipe_ctx->stream->output_color_space, 1616 pipe_ctx->stream->csc_color_matrix.matrix, 1617 hubp->opp_id); 1618 } 1619 1620 if (pipe_ctx->update_flags.bits.enable || 1621 pipe_ctx->update_flags.bits.plane_changed || 1622 pipe_ctx->update_flags.bits.opp_changed || 1623 plane_state->update_flags.bits.pixel_format_change || 1624 plane_state->update_flags.bits.horizontal_mirror_change || 1625 plane_state->update_flags.bits.rotation_change || 1626 plane_state->update_flags.bits.swizzle_change || 1627 plane_state->update_flags.bits.dcc_change || 1628 plane_state->update_flags.bits.bpp_change || 1629 plane_state->update_flags.bits.scaling_change || 1630 plane_state->update_flags.bits.plane_size_change) { 1631 struct plane_size size = plane_state->plane_size; 1632 1633 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1634 hubp->funcs->hubp_program_surface_config( 1635 hubp, 1636 plane_state->format, 1637 &plane_state->tiling_info, 1638 &size, 1639 plane_state->rotation, 1640 &plane_state->dcc, 1641 plane_state->horizontal_mirror, 1642 0); 1643 hubp->power_gated = false; 1644 } 1645 1646 if (pipe_ctx->update_flags.bits.enable || 1647 pipe_ctx->update_flags.bits.plane_changed || 1648 plane_state->update_flags.bits.addr_update) 1649 hws->funcs.update_plane_addr(dc, pipe_ctx); 1650 1651 if (pipe_ctx->update_flags.bits.enable) 1652 hubp->funcs->set_blank(hubp, false); 1653 /* If the stream paired with this plane is phantom, the plane is also phantom */ 1654 if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM 1655 && hubp->funcs->phantom_hubp_post_enable) 1656 hubp->funcs->phantom_hubp_post_enable(hubp); 1657 } 1658 1659 static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) 1660 { 1661 struct pipe_ctx *other_pipe; 1662 int vready_offset = pipe->pipe_dlg_param.vready_offset; 1663 1664 /* Always use the largest vready_offset of all connected pipes */ 1665 for (other_pipe = pipe->bottom_pipe; other_pipe != NULL; other_pipe = other_pipe->bottom_pipe) { 1666 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1667 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1668 } 1669 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { 1670 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1671 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1672 } 1673 for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe) { 1674 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1675 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1676 } 1677 for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->prev_odm_pipe) { 1678 if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) 1679 vready_offset = other_pipe->pipe_dlg_param.vready_offset; 1680 } 1681 1682 return vready_offset; 1683 } 1684 1685 static void dcn20_program_pipe( 1686 struct dc *dc, 1687 struct pipe_ctx *pipe_ctx, 1688 struct dc_state *context) 1689 { 1690 struct dce_hwseq *hws = dc->hwseq; 1691 1692 /* Only need to unblank on top pipe */ 1693 if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) { 1694 if (pipe_ctx->update_flags.bits.enable || 1695 pipe_ctx->update_flags.bits.odm || 1696 pipe_ctx->stream->update_flags.bits.abm_level) 1697 hws->funcs.blank_pixel_data(dc, pipe_ctx, 1698 !pipe_ctx->plane_state || 1699 !pipe_ctx->plane_state->visible); 1700 } 1701 1702 /* Only update TG on top pipe */ 1703 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1704 && !pipe_ctx->prev_odm_pipe) { 1705 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1706 pipe_ctx->stream_res.tg, 1707 calculate_vready_offset_for_group(pipe_ctx), 1708 pipe_ctx->pipe_dlg_param.vstartup_start, 1709 pipe_ctx->pipe_dlg_param.vupdate_offset, 1710 pipe_ctx->pipe_dlg_param.vupdate_width); 1711 1712 if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) 1713 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1714 1715 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1716 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1717 1718 if (hws->funcs.setup_vupdate_interrupt) 1719 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1720 } 1721 1722 if (pipe_ctx->update_flags.bits.odm) 1723 hws->funcs.update_odm(dc, context, pipe_ctx); 1724 1725 if (pipe_ctx->update_flags.bits.enable) { 1726 dcn20_enable_plane(dc, pipe_ctx, context); 1727 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1728 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1729 } 1730 1731 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1732 dc->res_pool->hubbub->funcs->program_det_size( 1733 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1734 1735 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1736 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1737 1738 if (pipe_ctx->update_flags.bits.enable 1739 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1740 hws->funcs.set_hdr_multiplier(pipe_ctx); 1741 1742 if (pipe_ctx->update_flags.bits.enable || 1743 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1744 pipe_ctx->plane_state->update_flags.bits.gamma_change || 1745 pipe_ctx->plane_state->update_flags.bits.lut_3d) 1746 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1747 1748 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1749 * only do gamma programming for powering on, internal memcmp to avoid 1750 * updating on slave planes 1751 */ 1752 if (pipe_ctx->update_flags.bits.enable || 1753 pipe_ctx->update_flags.bits.plane_changed || 1754 pipe_ctx->stream->update_flags.bits.out_tf || 1755 pipe_ctx->plane_state->update_flags.bits.output_tf_change) 1756 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1757 1758 /* If the pipe has been enabled or has a different opp, we 1759 * should reprogram the fmt. This deals with cases where 1760 * interation between mpc and odm combine on different streams 1761 * causes a different pipe to be chosen to odm combine with. 1762 */ 1763 if (pipe_ctx->update_flags.bits.enable 1764 || pipe_ctx->update_flags.bits.opp_changed) { 1765 1766 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1767 pipe_ctx->stream_res.opp, 1768 COLOR_SPACE_YCBCR601, 1769 pipe_ctx->stream->timing.display_color_depth, 1770 pipe_ctx->stream->signal); 1771 1772 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1773 pipe_ctx->stream_res.opp, 1774 &pipe_ctx->stream->bit_depth_params, 1775 &pipe_ctx->stream->clamping); 1776 } 1777 1778 /* Set ABM pipe after other pipe configurations done */ 1779 if (pipe_ctx->plane_state->visible) { 1780 if (pipe_ctx->stream_res.abm) { 1781 dc->hwss.set_pipe(pipe_ctx); 1782 pipe_ctx->stream_res.abm->funcs->set_abm_level(pipe_ctx->stream_res.abm, 1783 pipe_ctx->stream->abm_level); 1784 } 1785 } 1786 } 1787 1788 void dcn20_program_front_end_for_ctx( 1789 struct dc *dc, 1790 struct dc_state *context) 1791 { 1792 int i; 1793 struct dce_hwseq *hws = dc->hwseq; 1794 DC_LOGGER_INIT(dc->ctx->logger); 1795 1796 /* Carry over GSL groups in case the context is changing. */ 1797 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1798 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1799 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 1800 1801 if (pipe_ctx->stream == old_pipe_ctx->stream) 1802 pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group; 1803 } 1804 1805 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1806 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1807 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1808 1809 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1810 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1811 /*turn off triple buffer for full update*/ 1812 dc->hwss.program_triplebuffer( 1813 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1814 } 1815 } 1816 } 1817 1818 /* Set pipe update flags and lock pipes */ 1819 for (i = 0; i < dc->res_pool->pipe_count; i++) 1820 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1821 &context->res_ctx.pipe_ctx[i]); 1822 1823 /* When disabling phantom pipes, turn on phantom OTG first (so we can get double 1824 * buffer updates properly) 1825 */ 1826 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1827 struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; 1828 1829 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream && 1830 dc->current_state->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { 1831 struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; 1832 1833 if (tg->funcs->enable_crtc) 1834 tg->funcs->enable_crtc(tg); 1835 } 1836 } 1837 /* OTG blank before disabling all front ends */ 1838 for (i = 0; i < dc->res_pool->pipe_count; i++) 1839 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1840 && !context->res_ctx.pipe_ctx[i].top_pipe 1841 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1842 && context->res_ctx.pipe_ctx[i].stream) 1843 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1844 1845 1846 /* Disconnect mpcc */ 1847 for (i = 0; i < dc->res_pool->pipe_count; i++) 1848 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1849 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1850 struct hubbub *hubbub = dc->res_pool->hubbub; 1851 1852 /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom 1853 * then we want to do the programming here (effectively it's being disabled). If we do 1854 * the programming later the DET won't be updated until the OTG for the phantom pipe is 1855 * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with 1856 * DET allocation. 1857 */ 1858 if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || 1859 (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom))) 1860 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1861 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1862 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1863 } 1864 1865 /* 1866 * Program all updated pipes, order matters for mpcc setup. Start with 1867 * top pipe and program all pipes that follow in order 1868 */ 1869 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1870 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1871 1872 if (pipe->plane_state && !pipe->top_pipe) { 1873 while (pipe) { 1874 if (hws->funcs.program_pipe) 1875 hws->funcs.program_pipe(dc, pipe, context); 1876 else { 1877 /* Don't program phantom pipes in the regular front end programming sequence. 1878 * There is an MPO transition case where a pipe being used by a video plane is 1879 * transitioned directly to be a phantom pipe when closing the MPO video. However 1880 * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away), 1881 * but the MPO still exists until the double buffered update of the main pipe so we 1882 * will get a frame of underflow if the phantom pipe is programmed here. 1883 */ 1884 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) 1885 dcn20_program_pipe(dc, pipe, context); 1886 } 1887 1888 pipe = pipe->bottom_pipe; 1889 } 1890 } 1891 /* Program secondary blending tree and writeback pipes */ 1892 pipe = &context->res_ctx.pipe_ctx[i]; 1893 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1894 && pipe->stream && pipe->stream->num_wb_info > 0 1895 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1896 || pipe->stream->update_flags.raw) 1897 && hws->funcs.program_all_writeback_pipes_in_tree) 1898 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1899 1900 /* Avoid underflow by check of pipe line read when adding 2nd plane. */ 1901 if (hws->wa.wait_hubpret_read_start_during_mpo_transition && 1902 !pipe->top_pipe && 1903 pipe->stream && 1904 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && 1905 dc->current_state->stream_status[0].plane_count == 1 && 1906 context->stream_status[0].plane_count > 1) { 1907 pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); 1908 } 1909 1910 /* when dynamic ODM is active, pipes must be reconfigured when all planes are 1911 * disabled, as some transitions will leave software and hardware state 1912 * mismatched. 1913 */ 1914 if (dc->debug.enable_single_display_2to1_odm_policy && 1915 pipe->stream && 1916 pipe->update_flags.bits.disable && 1917 !pipe->prev_odm_pipe && 1918 hws->funcs.update_odm) 1919 hws->funcs.update_odm(dc, context, pipe); 1920 } 1921 } 1922 1923 void dcn20_post_unlock_program_front_end( 1924 struct dc *dc, 1925 struct dc_state *context) 1926 { 1927 int i; 1928 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_US = 100000; 1929 unsigned int polling_interval_us = 1; 1930 struct dce_hwseq *hwseq = dc->hwseq; 1931 1932 DC_LOGGER_INIT(dc->ctx->logger); 1933 1934 for (i = 0; i < dc->res_pool->pipe_count; i++) 1935 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1936 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1937 1938 /* 1939 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1940 * part of the enable operation otherwise, DM may request an immediate flip which 1941 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1942 * is unsupported on DCN. 1943 */ 1944 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1945 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1946 // Don't check flip pending on phantom pipes 1947 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && 1948 pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { 1949 struct hubp *hubp = pipe->plane_res.hubp; 1950 int j = 0; 1951 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us 1952 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1953 udelay(polling_interval_us); 1954 } 1955 } 1956 1957 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1958 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1959 1960 if (pipe->plane_state && !pipe->top_pipe) { 1961 /* Program phantom pipe here to prevent a frame of underflow in the MPO transition 1962 * case (if a pipe being used for a video plane transitions to a phantom pipe, it 1963 * can underflow due to HUBP_VTG_SEL programming if done in the regular front end 1964 * programming sequence). 1965 */ 1966 while (pipe) { 1967 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 1968 /* When turning on the phantom pipe we want to run through the 1969 * entire enable sequence, so apply all the "enable" flags. 1970 */ 1971 if (dc->hwss.apply_update_flags_for_phantom) 1972 dc->hwss.apply_update_flags_for_phantom(pipe); 1973 if (dc->hwss.update_phantom_vp_position) 1974 dc->hwss.update_phantom_vp_position(dc, context, pipe); 1975 dcn20_program_pipe(dc, pipe, context); 1976 } 1977 pipe = pipe->bottom_pipe; 1978 } 1979 } 1980 } 1981 1982 /* P-State support transitions: 1983 * Natural -> FPO: P-State disabled in prepare, force disallow anytime is safe 1984 * FPO -> Natural: Unforce anytime after FW disable is safe (P-State will assert naturally) 1985 * Unsupported -> FPO: P-State enabled in optimize, force disallow anytime is safe 1986 * FPO -> Unsupported: P-State disabled in prepare, unforce disallow anytime is safe 1987 * FPO <-> SubVP: Force disallow is maintained on the FPO / SubVP pipes 1988 */ 1989 if (hwseq && hwseq->funcs.update_force_pstate) 1990 dc->hwseq->funcs.update_force_pstate(dc, context); 1991 1992 /* Only program the MALL registers after all the main and phantom pipes 1993 * are done programming. 1994 */ 1995 if (hwseq->funcs.program_mall_pipe_config) 1996 hwseq->funcs.program_mall_pipe_config(dc, context); 1997 1998 /* WA to apply WM setting*/ 1999 if (hwseq->wa.DEGVIDCN21) 2000 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 2001 2002 2003 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 2004 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 2005 2006 if (dc->current_state->stream_status[0].plane_count == 1 && 2007 context->stream_status[0].plane_count > 1) { 2008 2009 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 2010 2011 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 2012 2013 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 2014 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 2015 } 2016 } 2017 } 2018 2019 void dcn20_prepare_bandwidth( 2020 struct dc *dc, 2021 struct dc_state *context) 2022 { 2023 struct hubbub *hubbub = dc->res_pool->hubbub; 2024 unsigned int compbuf_size_kb = 0; 2025 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; 2026 unsigned int i; 2027 2028 dc->clk_mgr->funcs->update_clocks( 2029 dc->clk_mgr, 2030 context, 2031 false); 2032 2033 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2034 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2035 2036 // At optimize don't restore the original watermark value 2037 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2038 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2039 break; 2040 } 2041 } 2042 2043 /* program dchubbub watermarks: 2044 * For assigning wm_optimized_required, use |= operator since we don't want 2045 * to clear the value if the optimize has not happened yet 2046 */ 2047 dc->wm_optimized_required |= hubbub->funcs->program_watermarks(hubbub, 2048 &context->bw_ctx.bw.dcn.watermarks, 2049 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2050 false); 2051 2052 // Restore the real watermark so we can commit the value to DMCUB 2053 // DMCUB uses the "original" watermark value in SubVP MCLK switch 2054 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; 2055 2056 /* decrease compbuf size */ 2057 if (hubbub->funcs->program_compbuf_size) { 2058 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) { 2059 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; 2060 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.dml.ip.min_comp_buffer_size_kbytes); 2061 } else { 2062 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; 2063 dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); 2064 } 2065 2066 hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false); 2067 } 2068 } 2069 2070 void dcn20_optimize_bandwidth( 2071 struct dc *dc, 2072 struct dc_state *context) 2073 { 2074 struct hubbub *hubbub = dc->res_pool->hubbub; 2075 int i; 2076 2077 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2078 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2079 2080 // At optimize don't need to restore the original watermark value 2081 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { 2082 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2083 break; 2084 } 2085 } 2086 2087 /* program dchubbub watermarks */ 2088 hubbub->funcs->program_watermarks(hubbub, 2089 &context->bw_ctx.bw.dcn.watermarks, 2090 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 2091 true); 2092 2093 if (dc->clk_mgr->dc_mode_softmax_enabled) 2094 if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 2095 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 2096 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); 2097 2098 /* increase compbuf size */ 2099 if (hubbub->funcs->program_compbuf_size) 2100 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 2101 2102 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { 2103 dc_dmub_srv_p_state_delegate(dc, 2104 true, context); 2105 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; 2106 dc->clk_mgr->clks.fw_based_mclk_switching = true; 2107 } else { 2108 dc->clk_mgr->clks.fw_based_mclk_switching = false; 2109 } 2110 2111 dc->clk_mgr->funcs->update_clocks( 2112 dc->clk_mgr, 2113 context, 2114 true); 2115 if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { 2116 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 2117 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2118 2119 if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank 2120 && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max 2121 && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) 2122 pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, 2123 pipe_ctx->dlg_regs.min_dst_y_next_start); 2124 } 2125 } 2126 } 2127 2128 bool dcn20_update_bandwidth( 2129 struct dc *dc, 2130 struct dc_state *context) 2131 { 2132 int i; 2133 struct dce_hwseq *hws = dc->hwseq; 2134 2135 /* recalculate DML parameters */ 2136 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 2137 return false; 2138 2139 /* apply updated bandwidth parameters */ 2140 dc->hwss.prepare_bandwidth(dc, context); 2141 2142 /* update hubp configs for all pipes */ 2143 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2144 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2145 2146 if (pipe_ctx->plane_state == NULL) 2147 continue; 2148 2149 if (pipe_ctx->top_pipe == NULL) { 2150 bool blank = !is_pipe_tree_visible(pipe_ctx); 2151 2152 pipe_ctx->stream_res.tg->funcs->program_global_sync( 2153 pipe_ctx->stream_res.tg, 2154 calculate_vready_offset_for_group(pipe_ctx), 2155 pipe_ctx->pipe_dlg_param.vstartup_start, 2156 pipe_ctx->pipe_dlg_param.vupdate_offset, 2157 pipe_ctx->pipe_dlg_param.vupdate_width); 2158 2159 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 2160 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 2161 2162 if (pipe_ctx->prev_odm_pipe == NULL) 2163 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 2164 2165 if (hws->funcs.setup_vupdate_interrupt) 2166 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 2167 } 2168 2169 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 2170 pipe_ctx->plane_res.hubp, 2171 &pipe_ctx->dlg_regs, 2172 &pipe_ctx->ttu_regs, 2173 &pipe_ctx->rq_regs, 2174 &pipe_ctx->pipe_dlg_param); 2175 } 2176 2177 return true; 2178 } 2179 2180 void dcn20_enable_writeback( 2181 struct dc *dc, 2182 struct dc_writeback_info *wb_info, 2183 struct dc_state *context) 2184 { 2185 struct dwbc *dwb; 2186 struct mcif_wb *mcif_wb; 2187 struct timing_generator *optc; 2188 2189 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2190 ASSERT(wb_info->wb_enabled); 2191 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2192 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2193 2194 /* set the OPTC source mux */ 2195 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 2196 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2197 /* set MCIF_WB buffer and arbitration configuration */ 2198 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2199 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2200 /* Enable MCIF_WB */ 2201 mcif_wb->funcs->enable_mcif(mcif_wb); 2202 /* Enable DWB */ 2203 dwb->funcs->enable(dwb, &wb_info->dwb_params); 2204 /* TODO: add sequence to enable/disable warmup */ 2205 } 2206 2207 void dcn20_disable_writeback( 2208 struct dc *dc, 2209 unsigned int dwb_pipe_inst) 2210 { 2211 struct dwbc *dwb; 2212 struct mcif_wb *mcif_wb; 2213 2214 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 2215 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 2216 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 2217 2218 dwb->funcs->disable(dwb); 2219 mcif_wb->funcs->disable_mcif(mcif_wb); 2220 } 2221 2222 bool dcn20_wait_for_blank_complete( 2223 struct output_pixel_processor *opp) 2224 { 2225 int counter; 2226 2227 for (counter = 0; counter < 1000; counter++) { 2228 if (opp->funcs->dpg_is_blanked(opp)) 2229 break; 2230 2231 udelay(100); 2232 } 2233 2234 if (counter == 1000) { 2235 dm_error("DC: failed to blank crtc!\n"); 2236 return false; 2237 } 2238 2239 return true; 2240 } 2241 2242 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 2243 { 2244 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2245 2246 if (!hubp) 2247 return false; 2248 return hubp->funcs->dmdata_status_done(hubp); 2249 } 2250 2251 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2252 { 2253 struct dce_hwseq *hws = dc->hwseq; 2254 2255 if (pipe_ctx->stream_res.dsc) { 2256 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2257 2258 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 2259 while (odm_pipe) { 2260 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 2261 odm_pipe = odm_pipe->next_odm_pipe; 2262 } 2263 } 2264 } 2265 2266 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 2267 { 2268 struct dce_hwseq *hws = dc->hwseq; 2269 2270 if (pipe_ctx->stream_res.dsc) { 2271 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2272 2273 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 2274 while (odm_pipe) { 2275 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2276 odm_pipe = odm_pipe->next_odm_pipe; 2277 } 2278 } 2279 } 2280 2281 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2282 { 2283 struct dc_dmdata_attributes attr = { 0 }; 2284 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2285 2286 attr.dmdata_mode = DMDATA_HW_MODE; 2287 attr.dmdata_size = 2288 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2289 attr.address.quad_part = 2290 pipe_ctx->stream->dmdata_address.quad_part; 2291 attr.dmdata_dl_delta = 0; 2292 attr.dmdata_qos_mode = 0; 2293 attr.dmdata_qos_level = 0; 2294 attr.dmdata_repeat = 1; /* always repeat */ 2295 attr.dmdata_updated = 1; 2296 attr.dmdata_sw_data = NULL; 2297 2298 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2299 } 2300 2301 void dcn20_init_vm_ctx( 2302 struct dce_hwseq *hws, 2303 struct dc *dc, 2304 struct dc_virtual_addr_space_config *va_config, 2305 int vmid) 2306 { 2307 struct dcn_hubbub_virt_addr_config config; 2308 2309 if (vmid == 0) { 2310 ASSERT(0); /* VMID cannot be 0 for vm context */ 2311 return; 2312 } 2313 2314 config.page_table_start_addr = va_config->page_table_start_addr; 2315 config.page_table_end_addr = va_config->page_table_end_addr; 2316 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2317 config.page_table_depth = va_config->page_table_depth; 2318 config.page_table_base_addr = va_config->page_table_base_addr; 2319 2320 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2321 } 2322 2323 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2324 { 2325 struct dcn_hubbub_phys_addr_config config; 2326 2327 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2328 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2329 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2330 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2331 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2332 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2333 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2334 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2335 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2336 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2337 2338 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2339 } 2340 2341 static bool patch_address_for_sbs_tb_stereo( 2342 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2343 { 2344 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2345 bool sec_split = pipe_ctx->top_pipe && 2346 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2347 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2348 (pipe_ctx->stream->timing.timing_3d_format == 2349 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2350 pipe_ctx->stream->timing.timing_3d_format == 2351 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2352 *addr = plane_state->address.grph_stereo.left_addr; 2353 plane_state->address.grph_stereo.left_addr = 2354 plane_state->address.grph_stereo.right_addr; 2355 return true; 2356 } 2357 2358 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2359 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2360 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2361 plane_state->address.grph_stereo.right_addr = 2362 plane_state->address.grph_stereo.left_addr; 2363 plane_state->address.grph_stereo.right_meta_addr = 2364 plane_state->address.grph_stereo.left_meta_addr; 2365 } 2366 return false; 2367 } 2368 2369 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2370 { 2371 bool addr_patched = false; 2372 PHYSICAL_ADDRESS_LOC addr; 2373 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2374 2375 if (plane_state == NULL) 2376 return; 2377 2378 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2379 2380 // Call Helper to track VMID use 2381 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2382 2383 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2384 pipe_ctx->plane_res.hubp, 2385 &plane_state->address, 2386 plane_state->flip_immediate); 2387 2388 plane_state->status.requested_address = plane_state->address; 2389 2390 if (plane_state->flip_immediate) 2391 plane_state->status.current_address = plane_state->address; 2392 2393 if (addr_patched) 2394 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2395 } 2396 2397 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2398 struct dc_link_settings *link_settings) 2399 { 2400 struct encoder_unblank_param params = {0}; 2401 struct dc_stream_state *stream = pipe_ctx->stream; 2402 struct dc_link *link = stream->link; 2403 struct dce_hwseq *hws = link->dc->hwseq; 2404 struct pipe_ctx *odm_pipe; 2405 2406 params.opp_cnt = 1; 2407 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2408 params.opp_cnt++; 2409 } 2410 /* only 3 items below are used by unblank */ 2411 params.timing = pipe_ctx->stream->timing; 2412 2413 params.link_settings.link_rate = link_settings->link_rate; 2414 2415 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2416 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2417 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2418 pipe_ctx->stream_res.hpo_dp_stream_enc, 2419 pipe_ctx->stream_res.tg->inst); 2420 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2421 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2422 params.timing.pix_clk_100hz /= 2; 2423 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2424 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2425 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2426 } 2427 2428 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2429 hws->funcs.edp_backlight_control(link, true); 2430 } 2431 } 2432 2433 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2434 { 2435 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2436 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2437 2438 if (start_line < 0) 2439 start_line = 0; 2440 2441 if (tg->funcs->setup_vertical_interrupt2) 2442 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2443 } 2444 2445 static void dcn20_reset_back_end_for_pipe( 2446 struct dc *dc, 2447 struct pipe_ctx *pipe_ctx, 2448 struct dc_state *context) 2449 { 2450 int i; 2451 struct dc_link *link = pipe_ctx->stream->link; 2452 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2453 2454 DC_LOGGER_INIT(dc->ctx->logger); 2455 if (pipe_ctx->stream_res.stream_enc == NULL) { 2456 pipe_ctx->stream = NULL; 2457 return; 2458 } 2459 2460 /* DPMS may already disable or */ 2461 /* dpms_off status is incorrect due to fastboot 2462 * feature. When system resume from S4 with second 2463 * screen only, the dpms_off would be true but 2464 * VBIOS lit up eDP, so check link status too. 2465 */ 2466 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2467 dc->link_srv->set_dpms_off(pipe_ctx); 2468 else if (pipe_ctx->stream_res.audio) 2469 dc->hwss.disable_audio_stream(pipe_ctx); 2470 2471 /* free acquired resources */ 2472 if (pipe_ctx->stream_res.audio) { 2473 /*disable az_endpoint*/ 2474 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2475 2476 /*free audio*/ 2477 if (dc->caps.dynamic_audio == true) { 2478 /*we have to dynamic arbitrate the audio endpoints*/ 2479 /*we free the resource, need reset is_audio_acquired*/ 2480 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2481 pipe_ctx->stream_res.audio, false); 2482 pipe_ctx->stream_res.audio = NULL; 2483 } 2484 } 2485 2486 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2487 * back end share by all pipes and will be disable only when disable 2488 * parent pipe. 2489 */ 2490 if (pipe_ctx->top_pipe == NULL) { 2491 2492 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2493 2494 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2495 2496 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2497 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2498 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2499 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2500 2501 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2502 pipe_ctx->stream_res.tg->funcs->set_drr( 2503 pipe_ctx->stream_res.tg, NULL); 2504 /* TODO - convert symclk_ref_cnts for otg to a bit map to solve 2505 * the case where the same symclk is shared across multiple otg 2506 * instances 2507 */ 2508 link->phy_state.symclk_ref_cnts.otg = 0; 2509 if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { 2510 link_hwss->disable_link_output(link, 2511 &pipe_ctx->link_res, pipe_ctx->stream->signal); 2512 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 2513 } 2514 } 2515 2516 for (i = 0; i < dc->res_pool->pipe_count; i++) 2517 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2518 break; 2519 2520 if (i == dc->res_pool->pipe_count) 2521 return; 2522 2523 pipe_ctx->stream = NULL; 2524 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2525 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2526 } 2527 2528 void dcn20_reset_hw_ctx_wrap( 2529 struct dc *dc, 2530 struct dc_state *context) 2531 { 2532 int i; 2533 struct dce_hwseq *hws = dc->hwseq; 2534 2535 /* Reset Back End*/ 2536 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2537 struct pipe_ctx *pipe_ctx_old = 2538 &dc->current_state->res_ctx.pipe_ctx[i]; 2539 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2540 2541 if (!pipe_ctx_old->stream) 2542 continue; 2543 2544 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2545 continue; 2546 2547 if (!pipe_ctx->stream || 2548 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2549 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2550 2551 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2552 if (hws->funcs.enable_stream_gating) 2553 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2554 if (old_clk) 2555 old_clk->funcs->cs_power_down(old_clk); 2556 } 2557 } 2558 } 2559 2560 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2561 { 2562 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2563 struct mpcc_blnd_cfg blnd_cfg = {0}; 2564 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2565 int mpcc_id; 2566 struct mpcc *new_mpcc; 2567 struct mpc *mpc = dc->res_pool->mpc; 2568 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2569 2570 blnd_cfg.overlap_only = false; 2571 blnd_cfg.global_gain = 0xff; 2572 2573 if (per_pixel_alpha) { 2574 blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; 2575 if (pipe_ctx->plane_state->global_alpha) { 2576 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; 2577 blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; 2578 } else { 2579 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2580 } 2581 } else { 2582 blnd_cfg.pre_multiplied_alpha = false; 2583 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2584 } 2585 2586 if (pipe_ctx->plane_state->global_alpha) 2587 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2588 else 2589 blnd_cfg.global_alpha = 0xff; 2590 2591 blnd_cfg.background_color_bpc = 4; 2592 blnd_cfg.bottom_gain_mode = 0; 2593 blnd_cfg.top_gain = 0x1f000; 2594 blnd_cfg.bottom_inside_gain = 0x1f000; 2595 blnd_cfg.bottom_outside_gain = 0x1f000; 2596 2597 if (pipe_ctx->plane_state->format 2598 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2599 blnd_cfg.pre_multiplied_alpha = false; 2600 2601 /* 2602 * TODO: remove hack 2603 * Note: currently there is a bug in init_hw such that 2604 * on resume from hibernate, BIOS sets up MPCC0, and 2605 * we do mpcc_remove but the mpcc cannot go to idle 2606 * after remove. This cause us to pick mpcc1 here, 2607 * which causes a pstate hang for yet unknown reason. 2608 */ 2609 mpcc_id = hubp->inst; 2610 2611 /* If there is no full update, don't need to touch MPC tree*/ 2612 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2613 !pipe_ctx->update_flags.bits.mpcc) { 2614 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2615 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); 2616 return; 2617 } 2618 2619 /* check if this MPCC is already being used */ 2620 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2621 /* remove MPCC if being used */ 2622 if (new_mpcc != NULL) 2623 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2624 else 2625 if (dc->debug.sanity_checks) 2626 mpc->funcs->assert_mpcc_idle_before_connect( 2627 dc->res_pool->mpc, mpcc_id); 2628 2629 /* Call MPC to insert new plane */ 2630 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2631 mpc_tree_params, 2632 &blnd_cfg, 2633 NULL, 2634 NULL, 2635 hubp->inst, 2636 mpcc_id); 2637 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); 2638 2639 ASSERT(new_mpcc != NULL); 2640 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2641 hubp->mpcc_id = mpcc_id; 2642 } 2643 2644 static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link) 2645 { 2646 switch (link->link_enc->transmitter) { 2647 case TRANSMITTER_UNIPHY_A: 2648 return PHYD32CLKA; 2649 case TRANSMITTER_UNIPHY_B: 2650 return PHYD32CLKB; 2651 case TRANSMITTER_UNIPHY_C: 2652 return PHYD32CLKC; 2653 case TRANSMITTER_UNIPHY_D: 2654 return PHYD32CLKD; 2655 case TRANSMITTER_UNIPHY_E: 2656 return PHYD32CLKE; 2657 default: 2658 return PHYD32CLKA; 2659 } 2660 } 2661 2662 static int get_odm_segment_count(struct pipe_ctx *pipe_ctx) 2663 { 2664 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 2665 int count = 1; 2666 2667 while (odm_pipe != NULL) { 2668 count++; 2669 odm_pipe = odm_pipe->next_odm_pipe; 2670 } 2671 2672 return count; 2673 } 2674 2675 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2676 { 2677 enum dc_lane_count lane_count = 2678 pipe_ctx->stream->link->cur_link_settings.lane_count; 2679 2680 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2681 struct dc_link *link = pipe_ctx->stream->link; 2682 2683 uint32_t active_total_with_borders; 2684 uint32_t early_control = 0; 2685 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2686 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2687 struct dc *dc = pipe_ctx->stream->ctx->dc; 2688 struct dtbclk_dto_params dto_params = {0}; 2689 struct dccg *dccg = dc->res_pool->dccg; 2690 enum phyd32clk_clock_source phyd32clk; 2691 int dp_hpo_inst; 2692 struct dce_hwseq *hws = dc->hwseq; 2693 unsigned int k1_div = PIXEL_RATE_DIV_NA; 2694 unsigned int k2_div = PIXEL_RATE_DIV_NA; 2695 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 2696 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2697 2698 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2699 if (dc->hwseq->funcs.setup_hpo_hw_control) 2700 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true); 2701 } 2702 2703 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2704 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 2705 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 2706 2707 phyd32clk = get_phyd32clk_src(link); 2708 dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 2709 2710 dto_params.otg_inst = tg->inst; 2711 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; 2712 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); 2713 dto_params.timing = &pipe_ctx->stream->timing; 2714 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2715 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 2716 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->enable_symclk_se) 2717 dccg->funcs->enable_symclk_se(dccg, 2718 stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); 2719 2720 if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { 2721 hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); 2722 2723 dc->res_pool->dccg->funcs->set_pixel_rate_div( 2724 dc->res_pool->dccg, 2725 pipe_ctx->stream_res.tg->inst, 2726 k1_div, k2_div); 2727 } 2728 2729 link_hwss->setup_stream_encoder(pipe_ctx); 2730 2731 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2732 if (dc->hwss.program_dmdata_engine) 2733 dc->hwss.program_dmdata_engine(pipe_ctx); 2734 } 2735 2736 dc->hwss.update_info_frame(pipe_ctx); 2737 2738 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2739 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2740 2741 /* enable early control to avoid corruption on DP monitor*/ 2742 active_total_with_borders = 2743 timing->h_addressable 2744 + timing->h_border_left 2745 + timing->h_border_right; 2746 2747 if (lane_count != 0) 2748 early_control = active_total_with_borders % lane_count; 2749 2750 if (early_control == 0) 2751 early_control = lane_count; 2752 2753 tg->funcs->set_early_control(tg, early_control); 2754 2755 if (dc->hwseq->funcs.set_pixels_per_cycle) 2756 dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); 2757 } 2758 2759 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2760 { 2761 struct dc_stream_state *stream = pipe_ctx->stream; 2762 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2763 bool enable = false; 2764 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2765 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2766 ? dmdata_dp 2767 : dmdata_hdmi; 2768 2769 /* if using dynamic meta, don't set up generic infopackets */ 2770 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2771 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2772 enable = true; 2773 } 2774 2775 if (!hubp) 2776 return; 2777 2778 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2779 return; 2780 2781 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2782 hubp->inst, mode); 2783 } 2784 2785 void dcn20_fpga_init_hw(struct dc *dc) 2786 { 2787 int i, j; 2788 struct dce_hwseq *hws = dc->hwseq; 2789 struct resource_pool *res_pool = dc->res_pool; 2790 struct dc_state *context = dc->current_state; 2791 2792 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2793 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2794 2795 // Initialize the dccg 2796 if (res_pool->dccg->funcs->dccg_init) 2797 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2798 2799 //Enable ability to power gate / don't force power on permanently 2800 hws->funcs.enable_power_gating_plane(hws, true); 2801 2802 // Specific to FPGA dccg and registers 2803 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2804 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2805 2806 hws->funcs.dccg_init(hws); 2807 2808 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2809 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2810 if (REG(REFCLK_CNTL)) 2811 REG_WRITE(REFCLK_CNTL, 0); 2812 // 2813 2814 2815 /* Blank pixel data with OPP DPG */ 2816 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2817 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2818 2819 if (tg->funcs->is_tg_enabled(tg)) 2820 dcn20_init_blank(dc, tg); 2821 } 2822 2823 for (i = 0; i < res_pool->timing_generator_count; i++) { 2824 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2825 2826 if (tg->funcs->is_tg_enabled(tg)) 2827 tg->funcs->lock(tg); 2828 } 2829 2830 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2831 struct dpp *dpp = res_pool->dpps[i]; 2832 2833 dpp->funcs->dpp_reset(dpp); 2834 } 2835 2836 /* Reset all MPCC muxes */ 2837 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2838 2839 /* initialize OPP mpc_tree parameter */ 2840 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2841 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2842 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2843 for (j = 0; j < MAX_PIPES; j++) 2844 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2845 } 2846 2847 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2848 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2849 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2850 struct hubp *hubp = dc->res_pool->hubps[i]; 2851 struct dpp *dpp = dc->res_pool->dpps[i]; 2852 2853 pipe_ctx->stream_res.tg = tg; 2854 pipe_ctx->pipe_idx = i; 2855 2856 pipe_ctx->plane_res.hubp = hubp; 2857 pipe_ctx->plane_res.dpp = dpp; 2858 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2859 hubp->mpcc_id = dpp->inst; 2860 hubp->opp_id = OPP_ID_INVALID; 2861 hubp->power_gated = false; 2862 pipe_ctx->stream_res.opp = NULL; 2863 2864 hubp->funcs->hubp_init(hubp); 2865 2866 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2867 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2868 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2869 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2870 /*to do*/ 2871 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2872 } 2873 2874 /* initialize DWB pointer to MCIF_WB */ 2875 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2876 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2877 2878 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2879 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2880 2881 if (tg->funcs->is_tg_enabled(tg)) 2882 tg->funcs->unlock(tg); 2883 } 2884 2885 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2886 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2887 2888 dc->hwss.disable_plane(dc, pipe_ctx); 2889 2890 pipe_ctx->stream_res.tg = NULL; 2891 pipe_ctx->plane_res.hubp = NULL; 2892 } 2893 2894 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2895 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2896 2897 tg->funcs->tg_init(tg); 2898 } 2899 2900 if (dc->res_pool->hubbub->funcs->init_crb) 2901 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2902 } 2903 #ifndef TRIM_FSFT 2904 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2905 struct dc_crtc_timing *timing, 2906 unsigned int max_input_rate_in_khz) 2907 { 2908 unsigned int old_v_front_porch; 2909 unsigned int old_v_total; 2910 unsigned int max_input_rate_in_100hz; 2911 unsigned long long new_v_total; 2912 2913 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2914 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2915 return false; 2916 2917 old_v_total = timing->v_total; 2918 old_v_front_porch = timing->v_front_porch; 2919 2920 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2921 timing->pix_clk_100hz = max_input_rate_in_100hz; 2922 2923 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2924 2925 timing->v_total = new_v_total; 2926 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2927 return true; 2928 } 2929 #endif 2930 2931 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2932 struct pipe_ctx *pipe_ctx, 2933 enum controller_dp_test_pattern test_pattern, 2934 enum controller_dp_color_space color_space, 2935 enum dc_color_depth color_depth, 2936 const struct tg_color *solid_color, 2937 int width, int height, int offset) 2938 { 2939 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2940 color_space, color_depth, solid_color, width, height, offset); 2941 } 2942