1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 #include "dc_dmub_srv.h" 53 #include "dce/dmub_hw_lock_mgr.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 62 #undef FN 63 #define FN(reg_name, field_name) \ 64 hws->shifts->field_name, hws->masks->field_name 65 66 static int find_free_gsl_group(const struct dc *dc) 67 { 68 if (dc->res_pool->gsl_groups.gsl_0 == 0) 69 return 1; 70 if (dc->res_pool->gsl_groups.gsl_1 == 0) 71 return 2; 72 if (dc->res_pool->gsl_groups.gsl_2 == 0) 73 return 3; 74 75 return 0; 76 } 77 78 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 79 * This is only used to lock pipes in pipe splitting case with immediate flip 80 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 81 * so we get tearing with freesync since we cannot flip multiple pipes 82 * atomically. 83 * We use GSL for this: 84 * - immediate flip: find first available GSL group if not already assigned 85 * program gsl with that group, set current OTG as master 86 * and always us 0x4 = AND of flip_ready from all pipes 87 * - vsync flip: disable GSL if used 88 * 89 * Groups in stream_res are stored as +1 from HW registers, i.e. 90 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 91 * Using a magic value like -1 would require tracking all inits/resets 92 */ 93 static void dcn20_setup_gsl_group_as_lock( 94 const struct dc *dc, 95 struct pipe_ctx *pipe_ctx, 96 bool enable) 97 { 98 struct gsl_params gsl; 99 int group_idx; 100 101 memset(&gsl, 0, sizeof(struct gsl_params)); 102 103 if (enable) { 104 /* return if group already assigned since GSL was set up 105 * for vsync flip, we would unassign so it can't be "left over" 106 */ 107 if (pipe_ctx->stream_res.gsl_group > 0) 108 return; 109 110 group_idx = find_free_gsl_group(dc); 111 ASSERT(group_idx != 0); 112 pipe_ctx->stream_res.gsl_group = group_idx; 113 114 /* set gsl group reg field and mark resource used */ 115 switch (group_idx) { 116 case 1: 117 gsl.gsl0_en = 1; 118 dc->res_pool->gsl_groups.gsl_0 = 1; 119 break; 120 case 2: 121 gsl.gsl1_en = 1; 122 dc->res_pool->gsl_groups.gsl_1 = 1; 123 break; 124 case 3: 125 gsl.gsl2_en = 1; 126 dc->res_pool->gsl_groups.gsl_2 = 1; 127 break; 128 default: 129 BREAK_TO_DEBUGGER(); 130 return; // invalid case 131 } 132 gsl.gsl_master_en = 1; 133 } else { 134 group_idx = pipe_ctx->stream_res.gsl_group; 135 if (group_idx == 0) 136 return; // if not in use, just return 137 138 pipe_ctx->stream_res.gsl_group = 0; 139 140 /* unset gsl group reg field and mark resource free */ 141 switch (group_idx) { 142 case 1: 143 gsl.gsl0_en = 0; 144 dc->res_pool->gsl_groups.gsl_0 = 0; 145 break; 146 case 2: 147 gsl.gsl1_en = 0; 148 dc->res_pool->gsl_groups.gsl_1 = 0; 149 break; 150 case 3: 151 gsl.gsl2_en = 0; 152 dc->res_pool->gsl_groups.gsl_2 = 0; 153 break; 154 default: 155 BREAK_TO_DEBUGGER(); 156 return; 157 } 158 gsl.gsl_master_en = 0; 159 } 160 161 /* at this point we want to program whether it's to enable or disable */ 162 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 163 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 164 pipe_ctx->stream_res.tg->funcs->set_gsl( 165 pipe_ctx->stream_res.tg, 166 &gsl); 167 168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 169 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 170 } else 171 BREAK_TO_DEBUGGER(); 172 } 173 174 void dcn20_set_flip_control_gsl( 175 struct pipe_ctx *pipe_ctx, 176 bool flip_immediate) 177 { 178 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 179 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 180 pipe_ctx->plane_res.hubp, flip_immediate); 181 182 } 183 184 void dcn20_enable_power_gating_plane( 185 struct dce_hwseq *hws, 186 bool enable) 187 { 188 bool force_on = true; /* disable power gating */ 189 190 if (enable) 191 force_on = false; 192 193 /* DCHUBP0/1/2/3/4/5 */ 194 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 195 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 196 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 197 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 198 if (REG(DOMAIN8_PG_CONFIG)) 199 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 200 if (REG(DOMAIN10_PG_CONFIG)) 201 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 202 203 /* DPP0/1/2/3/4/5 */ 204 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 205 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 206 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 207 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 208 if (REG(DOMAIN9_PG_CONFIG)) 209 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 210 if (REG(DOMAIN11_PG_CONFIG)) 211 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 212 213 /* DCS0/1/2/3/4/5 */ 214 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 215 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 216 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 217 if (REG(DOMAIN19_PG_CONFIG)) 218 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 219 if (REG(DOMAIN20_PG_CONFIG)) 220 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 221 if (REG(DOMAIN21_PG_CONFIG)) 222 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 223 } 224 225 void dcn20_dccg_init(struct dce_hwseq *hws) 226 { 227 /* 228 * set MICROSECOND_TIME_BASE_DIV 229 * 100Mhz refclk -> 0x120264 230 * 27Mhz refclk -> 0x12021b 231 * 48Mhz refclk -> 0x120230 232 * 233 */ 234 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 235 236 /* 237 * set MILLISECOND_TIME_BASE_DIV 238 * 100Mhz refclk -> 0x1186a0 239 * 27Mhz refclk -> 0x106978 240 * 48Mhz refclk -> 0x10bb80 241 * 242 */ 243 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 244 245 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 246 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); 247 } 248 249 void dcn20_disable_vga( 250 struct dce_hwseq *hws) 251 { 252 REG_WRITE(D1VGA_CONTROL, 0); 253 REG_WRITE(D2VGA_CONTROL, 0); 254 REG_WRITE(D3VGA_CONTROL, 0); 255 REG_WRITE(D4VGA_CONTROL, 0); 256 REG_WRITE(D5VGA_CONTROL, 0); 257 REG_WRITE(D6VGA_CONTROL, 0); 258 } 259 260 void dcn20_program_triple_buffer( 261 const struct dc *dc, 262 struct pipe_ctx *pipe_ctx, 263 bool enable_triple_buffer) 264 { 265 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 266 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 267 pipe_ctx->plane_res.hubp, 268 enable_triple_buffer); 269 } 270 } 271 272 /* Blank pixel data during initialization */ 273 void dcn20_init_blank( 274 struct dc *dc, 275 struct timing_generator *tg) 276 { 277 struct dce_hwseq *hws = dc->hwseq; 278 enum dc_color_space color_space; 279 struct tg_color black_color = {0}; 280 struct output_pixel_processor *opp = NULL; 281 struct output_pixel_processor *bottom_opp = NULL; 282 uint32_t num_opps, opp_id_src0, opp_id_src1; 283 uint32_t otg_active_width, otg_active_height; 284 285 /* program opp dpg blank color */ 286 color_space = COLOR_SPACE_SRGB; 287 color_space_to_black_color(dc, color_space, &black_color); 288 289 /* get the OTG active size */ 290 tg->funcs->get_otg_active_size(tg, 291 &otg_active_width, 292 &otg_active_height); 293 294 /* get the OPTC source */ 295 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 296 297 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 298 ASSERT(false); 299 return; 300 } 301 opp = dc->res_pool->opps[opp_id_src0]; 302 303 if (num_opps == 2) { 304 otg_active_width = otg_active_width / 2; 305 306 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 307 ASSERT(false); 308 return; 309 } 310 bottom_opp = dc->res_pool->opps[opp_id_src1]; 311 } 312 313 opp->funcs->opp_set_disp_pattern_generator( 314 opp, 315 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 316 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 317 COLOR_DEPTH_UNDEFINED, 318 &black_color, 319 otg_active_width, 320 otg_active_height, 321 0); 322 323 if (num_opps == 2) { 324 bottom_opp->funcs->opp_set_disp_pattern_generator( 325 bottom_opp, 326 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 327 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 328 COLOR_DEPTH_UNDEFINED, 329 &black_color, 330 otg_active_width, 331 otg_active_height, 332 0); 333 } 334 335 hws->funcs.wait_for_blank_complete(opp); 336 } 337 338 void dcn20_dsc_pg_control( 339 struct dce_hwseq *hws, 340 unsigned int dsc_inst, 341 bool power_on) 342 { 343 uint32_t power_gate = power_on ? 0 : 1; 344 uint32_t pwr_status = power_on ? 0 : 2; 345 uint32_t org_ip_request_cntl = 0; 346 347 if (hws->ctx->dc->debug.disable_dsc_power_gate) 348 return; 349 350 if (REG(DOMAIN16_PG_CONFIG) == 0) 351 return; 352 353 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 354 if (org_ip_request_cntl == 0) 355 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 356 357 switch (dsc_inst) { 358 case 0: /* DSC0 */ 359 REG_UPDATE(DOMAIN16_PG_CONFIG, 360 DOMAIN16_POWER_GATE, power_gate); 361 362 REG_WAIT(DOMAIN16_PG_STATUS, 363 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 364 1, 1000); 365 break; 366 case 1: /* DSC1 */ 367 REG_UPDATE(DOMAIN17_PG_CONFIG, 368 DOMAIN17_POWER_GATE, power_gate); 369 370 REG_WAIT(DOMAIN17_PG_STATUS, 371 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 372 1, 1000); 373 break; 374 case 2: /* DSC2 */ 375 REG_UPDATE(DOMAIN18_PG_CONFIG, 376 DOMAIN18_POWER_GATE, power_gate); 377 378 REG_WAIT(DOMAIN18_PG_STATUS, 379 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 380 1, 1000); 381 break; 382 case 3: /* DSC3 */ 383 REG_UPDATE(DOMAIN19_PG_CONFIG, 384 DOMAIN19_POWER_GATE, power_gate); 385 386 REG_WAIT(DOMAIN19_PG_STATUS, 387 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 388 1, 1000); 389 break; 390 case 4: /* DSC4 */ 391 REG_UPDATE(DOMAIN20_PG_CONFIG, 392 DOMAIN20_POWER_GATE, power_gate); 393 394 REG_WAIT(DOMAIN20_PG_STATUS, 395 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 396 1, 1000); 397 break; 398 case 5: /* DSC5 */ 399 REG_UPDATE(DOMAIN21_PG_CONFIG, 400 DOMAIN21_POWER_GATE, power_gate); 401 402 REG_WAIT(DOMAIN21_PG_STATUS, 403 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 404 1, 1000); 405 break; 406 default: 407 BREAK_TO_DEBUGGER(); 408 break; 409 } 410 411 if (org_ip_request_cntl == 0) 412 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 413 } 414 415 void dcn20_dpp_pg_control( 416 struct dce_hwseq *hws, 417 unsigned int dpp_inst, 418 bool power_on) 419 { 420 uint32_t power_gate = power_on ? 0 : 1; 421 uint32_t pwr_status = power_on ? 0 : 2; 422 423 if (hws->ctx->dc->debug.disable_dpp_power_gate) 424 return; 425 if (REG(DOMAIN1_PG_CONFIG) == 0) 426 return; 427 428 switch (dpp_inst) { 429 case 0: /* DPP0 */ 430 REG_UPDATE(DOMAIN1_PG_CONFIG, 431 DOMAIN1_POWER_GATE, power_gate); 432 433 REG_WAIT(DOMAIN1_PG_STATUS, 434 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 435 1, 1000); 436 break; 437 case 1: /* DPP1 */ 438 REG_UPDATE(DOMAIN3_PG_CONFIG, 439 DOMAIN3_POWER_GATE, power_gate); 440 441 REG_WAIT(DOMAIN3_PG_STATUS, 442 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 443 1, 1000); 444 break; 445 case 2: /* DPP2 */ 446 REG_UPDATE(DOMAIN5_PG_CONFIG, 447 DOMAIN5_POWER_GATE, power_gate); 448 449 REG_WAIT(DOMAIN5_PG_STATUS, 450 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 451 1, 1000); 452 break; 453 case 3: /* DPP3 */ 454 REG_UPDATE(DOMAIN7_PG_CONFIG, 455 DOMAIN7_POWER_GATE, power_gate); 456 457 REG_WAIT(DOMAIN7_PG_STATUS, 458 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 459 1, 1000); 460 break; 461 case 4: /* DPP4 */ 462 REG_UPDATE(DOMAIN9_PG_CONFIG, 463 DOMAIN9_POWER_GATE, power_gate); 464 465 REG_WAIT(DOMAIN9_PG_STATUS, 466 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 467 1, 1000); 468 break; 469 case 5: /* DPP5 */ 470 /* 471 * Do not power gate DPP5, should be left at HW default, power on permanently. 472 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 473 * reset. 474 * REG_UPDATE(DOMAIN11_PG_CONFIG, 475 * DOMAIN11_POWER_GATE, power_gate); 476 * 477 * REG_WAIT(DOMAIN11_PG_STATUS, 478 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 479 * 1, 1000); 480 */ 481 break; 482 default: 483 BREAK_TO_DEBUGGER(); 484 break; 485 } 486 } 487 488 489 void dcn20_hubp_pg_control( 490 struct dce_hwseq *hws, 491 unsigned int hubp_inst, 492 bool power_on) 493 { 494 uint32_t power_gate = power_on ? 0 : 1; 495 uint32_t pwr_status = power_on ? 0 : 2; 496 497 if (hws->ctx->dc->debug.disable_hubp_power_gate) 498 return; 499 if (REG(DOMAIN0_PG_CONFIG) == 0) 500 return; 501 502 switch (hubp_inst) { 503 case 0: /* DCHUBP0 */ 504 REG_UPDATE(DOMAIN0_PG_CONFIG, 505 DOMAIN0_POWER_GATE, power_gate); 506 507 REG_WAIT(DOMAIN0_PG_STATUS, 508 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 509 1, 1000); 510 break; 511 case 1: /* DCHUBP1 */ 512 REG_UPDATE(DOMAIN2_PG_CONFIG, 513 DOMAIN2_POWER_GATE, power_gate); 514 515 REG_WAIT(DOMAIN2_PG_STATUS, 516 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 517 1, 1000); 518 break; 519 case 2: /* DCHUBP2 */ 520 REG_UPDATE(DOMAIN4_PG_CONFIG, 521 DOMAIN4_POWER_GATE, power_gate); 522 523 REG_WAIT(DOMAIN4_PG_STATUS, 524 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 525 1, 1000); 526 break; 527 case 3: /* DCHUBP3 */ 528 REG_UPDATE(DOMAIN6_PG_CONFIG, 529 DOMAIN6_POWER_GATE, power_gate); 530 531 REG_WAIT(DOMAIN6_PG_STATUS, 532 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 533 1, 1000); 534 break; 535 case 4: /* DCHUBP4 */ 536 REG_UPDATE(DOMAIN8_PG_CONFIG, 537 DOMAIN8_POWER_GATE, power_gate); 538 539 REG_WAIT(DOMAIN8_PG_STATUS, 540 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 541 1, 1000); 542 break; 543 case 5: /* DCHUBP5 */ 544 /* 545 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 546 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 547 * reset. 548 * REG_UPDATE(DOMAIN10_PG_CONFIG, 549 * DOMAIN10_POWER_GATE, power_gate); 550 * 551 * REG_WAIT(DOMAIN10_PG_STATUS, 552 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 553 * 1, 1000); 554 */ 555 break; 556 default: 557 BREAK_TO_DEBUGGER(); 558 break; 559 } 560 } 561 562 563 /* disable HW used by plane. 564 * note: cannot disable until disconnect is complete 565 */ 566 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 567 { 568 struct dce_hwseq *hws = dc->hwseq; 569 struct hubp *hubp = pipe_ctx->plane_res.hubp; 570 struct dpp *dpp = pipe_ctx->plane_res.dpp; 571 572 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 573 574 /* In flip immediate with pipe splitting case GSL is used for 575 * synchronization so we must disable it when the plane is disabled. 576 */ 577 if (pipe_ctx->stream_res.gsl_group != 0) 578 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 579 580 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 581 582 hubp->funcs->hubp_clk_cntl(hubp, false); 583 584 dpp->funcs->dpp_dppclk_control(dpp, false, false); 585 586 hubp->power_gated = true; 587 588 hws->funcs.plane_atomic_power_down(dc, 589 pipe_ctx->plane_res.dpp, 590 pipe_ctx->plane_res.hubp); 591 592 pipe_ctx->stream = NULL; 593 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 594 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 595 pipe_ctx->top_pipe = NULL; 596 pipe_ctx->bottom_pipe = NULL; 597 pipe_ctx->plane_state = NULL; 598 } 599 600 601 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 602 { 603 DC_LOGGER_INIT(dc->ctx->logger); 604 605 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 606 return; 607 608 dcn20_plane_atomic_disable(dc, pipe_ctx); 609 610 DC_LOG_DC("Power down front end %d\n", 611 pipe_ctx->pipe_idx); 612 } 613 614 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 615 int opp_cnt) 616 { 617 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 618 int flow_ctrl_cnt; 619 620 if (opp_cnt >= 2) 621 hblank_halved = true; 622 623 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 624 stream->timing.h_border_left - 625 stream->timing.h_border_right; 626 627 if (hblank_halved) 628 flow_ctrl_cnt /= 2; 629 630 /* ODM combine 4:1 case */ 631 if (opp_cnt == 4) 632 flow_ctrl_cnt /= 2; 633 634 return flow_ctrl_cnt; 635 } 636 637 enum dc_status dcn20_enable_stream_timing( 638 struct pipe_ctx *pipe_ctx, 639 struct dc_state *context, 640 struct dc *dc) 641 { 642 struct dce_hwseq *hws = dc->hwseq; 643 struct dc_stream_state *stream = pipe_ctx->stream; 644 struct drr_params params = {0}; 645 unsigned int event_triggers = 0; 646 struct pipe_ctx *odm_pipe; 647 int opp_cnt = 1; 648 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 649 bool interlace = stream->timing.flags.INTERLACE; 650 int i; 651 struct mpc_dwb_flow_control flow_control; 652 struct mpc *mpc = dc->res_pool->mpc; 653 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 654 655 /* by upper caller loop, pipe0 is parent pipe and be called first. 656 * back end is set up by for pipe0. Other children pipe share back end 657 * with pipe 0. No program is needed. 658 */ 659 if (pipe_ctx->top_pipe != NULL) 660 return DC_OK; 661 662 /* TODO check if timing_changed, disable stream if timing changed */ 663 664 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 665 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 666 opp_cnt++; 667 } 668 669 if (opp_cnt > 1) 670 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 671 pipe_ctx->stream_res.tg, 672 opp_inst, opp_cnt, 673 &pipe_ctx->stream->timing); 674 675 /* HW program guide assume display already disable 676 * by unplug sequence. OTG assume stop. 677 */ 678 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 679 680 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 681 pipe_ctx->clock_source, 682 &pipe_ctx->stream_res.pix_clk_params, 683 &pipe_ctx->pll_settings)) { 684 BREAK_TO_DEBUGGER(); 685 return DC_ERROR_UNEXPECTED; 686 } 687 688 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 689 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 690 691 pipe_ctx->stream_res.tg->funcs->program_timing( 692 pipe_ctx->stream_res.tg, 693 &stream->timing, 694 pipe_ctx->pipe_dlg_param.vready_offset, 695 pipe_ctx->pipe_dlg_param.vstartup_start, 696 pipe_ctx->pipe_dlg_param.vupdate_offset, 697 pipe_ctx->pipe_dlg_param.vupdate_width, 698 pipe_ctx->stream->signal, 699 true); 700 701 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 702 flow_control.flow_ctrl_mode = 0; 703 flow_control.flow_ctrl_cnt0 = 0x80; 704 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 705 if (mpc->funcs->set_out_rate_control) { 706 for (i = 0; i < opp_cnt; ++i) { 707 mpc->funcs->set_out_rate_control( 708 mpc, opp_inst[i], 709 true, 710 rate_control_2x_pclk, 711 &flow_control); 712 } 713 } 714 715 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 716 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 717 odm_pipe->stream_res.opp, 718 true); 719 720 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 721 pipe_ctx->stream_res.opp, 722 true); 723 724 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 725 726 /* VTG is within DCHUB command block. DCFCLK is always on */ 727 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 728 BREAK_TO_DEBUGGER(); 729 return DC_ERROR_UNEXPECTED; 730 } 731 732 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 733 734 params.vertical_total_min = stream->adjust.v_total_min; 735 params.vertical_total_max = stream->adjust.v_total_max; 736 params.vertical_total_mid = stream->adjust.v_total_mid; 737 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 738 if (pipe_ctx->stream_res.tg->funcs->set_drr) 739 pipe_ctx->stream_res.tg->funcs->set_drr( 740 pipe_ctx->stream_res.tg, ¶ms); 741 742 // DRR should set trigger event to monitor surface update event 743 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 744 event_triggers = 0x80; 745 /* Event triggers and num frames initialized for DRR, but can be 746 * later updated for PSR use. Note DRR trigger events are generated 747 * regardless of whether num frames met. 748 */ 749 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 750 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 751 pipe_ctx->stream_res.tg, event_triggers, 2); 752 753 /* TODO program crtc source select for non-virtual signal*/ 754 /* TODO program FMT */ 755 /* TODO setup link_enc */ 756 /* TODO set stream attributes */ 757 /* TODO program audio */ 758 /* TODO enable stream if timing changed */ 759 /* TODO unblank stream if DP */ 760 761 return DC_OK; 762 } 763 764 void dcn20_program_output_csc(struct dc *dc, 765 struct pipe_ctx *pipe_ctx, 766 enum dc_color_space colorspace, 767 uint16_t *matrix, 768 int opp_id) 769 { 770 struct mpc *mpc = dc->res_pool->mpc; 771 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 772 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 773 774 if (mpc->funcs->power_on_mpc_mem_pwr) 775 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 776 777 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 778 if (mpc->funcs->set_output_csc != NULL) 779 mpc->funcs->set_output_csc(mpc, 780 opp_id, 781 matrix, 782 ocsc_mode); 783 } else { 784 if (mpc->funcs->set_ocsc_default != NULL) 785 mpc->funcs->set_ocsc_default(mpc, 786 opp_id, 787 colorspace, 788 ocsc_mode); 789 } 790 } 791 792 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 793 const struct dc_stream_state *stream) 794 { 795 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 796 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 797 struct pwl_params *params = NULL; 798 /* 799 * program OGAM only for the top pipe 800 * if there is a pipe split then fix diagnostic is required: 801 * how to pass OGAM parameter for stream. 802 * if programming for all pipes is required then remove condition 803 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 804 */ 805 if (mpc->funcs->power_on_mpc_mem_pwr) 806 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 807 if (pipe_ctx->top_pipe == NULL 808 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 809 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 810 params = &stream->out_transfer_func->pwl; 811 else if (pipe_ctx->stream->out_transfer_func->type == 812 TF_TYPE_DISTRIBUTED_POINTS && 813 cm_helper_translate_curve_to_hw_format( 814 stream->out_transfer_func, 815 &mpc->blender_params, false)) 816 params = &mpc->blender_params; 817 /* 818 * there is no ROM 819 */ 820 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 821 BREAK_TO_DEBUGGER(); 822 } 823 /* 824 * if above if is not executed then 'params' equal to 0 and set in bypass 825 */ 826 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 827 828 return true; 829 } 830 831 bool dcn20_set_blend_lut( 832 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 833 { 834 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 835 bool result = true; 836 struct pwl_params *blend_lut = NULL; 837 838 if (plane_state->blend_tf) { 839 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 840 blend_lut = &plane_state->blend_tf->pwl; 841 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 842 cm_helper_translate_curve_to_hw_format( 843 plane_state->blend_tf, 844 &dpp_base->regamma_params, false); 845 blend_lut = &dpp_base->regamma_params; 846 } 847 } 848 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 849 850 return result; 851 } 852 853 bool dcn20_set_shaper_3dlut( 854 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 855 { 856 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 857 bool result = true; 858 struct pwl_params *shaper_lut = NULL; 859 860 if (plane_state->in_shaper_func) { 861 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 862 shaper_lut = &plane_state->in_shaper_func->pwl; 863 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 864 cm_helper_translate_curve_to_hw_format( 865 plane_state->in_shaper_func, 866 &dpp_base->shaper_params, true); 867 shaper_lut = &dpp_base->shaper_params; 868 } 869 } 870 871 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 872 if (plane_state->lut3d_func && 873 plane_state->lut3d_func->state.bits.initialized == 1) 874 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 875 &plane_state->lut3d_func->lut_3d); 876 else 877 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 878 879 return result; 880 } 881 882 bool dcn20_set_input_transfer_func(struct dc *dc, 883 struct pipe_ctx *pipe_ctx, 884 const struct dc_plane_state *plane_state) 885 { 886 struct dce_hwseq *hws = dc->hwseq; 887 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 888 const struct dc_transfer_func *tf = NULL; 889 bool result = true; 890 bool use_degamma_ram = false; 891 892 if (dpp_base == NULL || plane_state == NULL) 893 return false; 894 895 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 896 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 897 898 if (plane_state->in_transfer_func) 899 tf = plane_state->in_transfer_func; 900 901 902 if (tf == NULL) { 903 dpp_base->funcs->dpp_set_degamma(dpp_base, 904 IPP_DEGAMMA_MODE_BYPASS); 905 return true; 906 } 907 908 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 909 use_degamma_ram = true; 910 911 if (use_degamma_ram == true) { 912 if (tf->type == TF_TYPE_HWPWL) 913 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 914 &tf->pwl); 915 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 916 cm_helper_translate_curve_to_degamma_hw_format(tf, 917 &dpp_base->degamma_params); 918 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 919 &dpp_base->degamma_params); 920 } 921 return true; 922 } 923 /* handle here the optimized cases when de-gamma ROM could be used. 924 * 925 */ 926 if (tf->type == TF_TYPE_PREDEFINED) { 927 switch (tf->tf) { 928 case TRANSFER_FUNCTION_SRGB: 929 dpp_base->funcs->dpp_set_degamma(dpp_base, 930 IPP_DEGAMMA_MODE_HW_sRGB); 931 break; 932 case TRANSFER_FUNCTION_BT709: 933 dpp_base->funcs->dpp_set_degamma(dpp_base, 934 IPP_DEGAMMA_MODE_HW_xvYCC); 935 break; 936 case TRANSFER_FUNCTION_LINEAR: 937 dpp_base->funcs->dpp_set_degamma(dpp_base, 938 IPP_DEGAMMA_MODE_BYPASS); 939 break; 940 case TRANSFER_FUNCTION_PQ: 941 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 942 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 943 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 944 result = true; 945 break; 946 default: 947 result = false; 948 break; 949 } 950 } else if (tf->type == TF_TYPE_BYPASS) 951 dpp_base->funcs->dpp_set_degamma(dpp_base, 952 IPP_DEGAMMA_MODE_BYPASS); 953 else { 954 /* 955 * if we are here, we did not handle correctly. 956 * fix is required for this use case 957 */ 958 BREAK_TO_DEBUGGER(); 959 dpp_base->funcs->dpp_set_degamma(dpp_base, 960 IPP_DEGAMMA_MODE_BYPASS); 961 } 962 963 return result; 964 } 965 966 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 967 { 968 struct pipe_ctx *odm_pipe; 969 int opp_cnt = 1; 970 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 971 972 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 973 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 974 opp_cnt++; 975 } 976 977 if (opp_cnt > 1) 978 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 979 pipe_ctx->stream_res.tg, 980 opp_inst, opp_cnt, 981 &pipe_ctx->stream->timing); 982 else 983 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 984 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 985 } 986 987 void dcn20_blank_pixel_data( 988 struct dc *dc, 989 struct pipe_ctx *pipe_ctx, 990 bool blank) 991 { 992 struct tg_color black_color = {0}; 993 struct stream_resource *stream_res = &pipe_ctx->stream_res; 994 struct dc_stream_state *stream = pipe_ctx->stream; 995 enum dc_color_space color_space = stream->output_color_space; 996 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 997 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 998 struct pipe_ctx *odm_pipe; 999 int odm_cnt = 1; 1000 1001 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1002 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1003 1004 if (stream->link->test_pattern_enabled) 1005 return; 1006 1007 /* get opp dpg blank color */ 1008 color_space_to_black_color(dc, color_space, &black_color); 1009 1010 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1011 odm_cnt++; 1012 1013 width = width / odm_cnt; 1014 1015 if (blank) { 1016 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1017 1018 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1019 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1020 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1021 } 1022 } else { 1023 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1024 } 1025 1026 dc->hwss.set_disp_pattern_generator(dc, 1027 pipe_ctx, 1028 test_pattern, 1029 test_pattern_color_space, 1030 stream->timing.display_color_depth, 1031 &black_color, 1032 width, 1033 height, 1034 0); 1035 1036 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1037 dc->hwss.set_disp_pattern_generator(dc, 1038 odm_pipe, 1039 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1040 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1041 test_pattern_color_space, 1042 stream->timing.display_color_depth, 1043 &black_color, 1044 width, 1045 height, 1046 0); 1047 } 1048 1049 if (!blank) 1050 if (stream_res->abm) { 1051 dc->hwss.set_pipe(pipe_ctx); 1052 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1053 } 1054 } 1055 1056 1057 static void dcn20_power_on_plane( 1058 struct dce_hwseq *hws, 1059 struct pipe_ctx *pipe_ctx) 1060 { 1061 DC_LOGGER_INIT(hws->ctx->logger); 1062 if (REG(DC_IP_REQUEST_CNTL)) { 1063 REG_SET(DC_IP_REQUEST_CNTL, 0, 1064 IP_REQUEST_EN, 1); 1065 1066 if (hws->funcs.dpp_pg_control) 1067 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1068 1069 if (hws->funcs.hubp_pg_control) 1070 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1071 1072 REG_SET(DC_IP_REQUEST_CNTL, 0, 1073 IP_REQUEST_EN, 0); 1074 DC_LOG_DEBUG( 1075 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1076 } 1077 } 1078 1079 void dcn20_enable_plane( 1080 struct dc *dc, 1081 struct pipe_ctx *pipe_ctx, 1082 struct dc_state *context) 1083 { 1084 //if (dc->debug.sanity_checks) { 1085 // dcn10_verify_allow_pstate_change_high(dc); 1086 //} 1087 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1088 1089 /* enable DCFCLK current DCHUB */ 1090 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1091 1092 /* initialize HUBP on power up */ 1093 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1094 1095 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1096 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1097 pipe_ctx->stream_res.opp, 1098 true); 1099 1100 /* TODO: enable/disable in dm as per update type. 1101 if (plane_state) { 1102 DC_LOG_DC(dc->ctx->logger, 1103 "Pipe:%d 0x%x: addr hi:0x%x, " 1104 "addr low:0x%x, " 1105 "src: %d, %d, %d," 1106 " %d; dst: %d, %d, %d, %d;\n", 1107 pipe_ctx->pipe_idx, 1108 plane_state, 1109 plane_state->address.grph.addr.high_part, 1110 plane_state->address.grph.addr.low_part, 1111 plane_state->src_rect.x, 1112 plane_state->src_rect.y, 1113 plane_state->src_rect.width, 1114 plane_state->src_rect.height, 1115 plane_state->dst_rect.x, 1116 plane_state->dst_rect.y, 1117 plane_state->dst_rect.width, 1118 plane_state->dst_rect.height); 1119 1120 DC_LOG_DC(dc->ctx->logger, 1121 "Pipe %d: width, height, x, y format:%d\n" 1122 "viewport:%d, %d, %d, %d\n" 1123 "recout: %d, %d, %d, %d\n", 1124 pipe_ctx->pipe_idx, 1125 plane_state->format, 1126 pipe_ctx->plane_res.scl_data.viewport.width, 1127 pipe_ctx->plane_res.scl_data.viewport.height, 1128 pipe_ctx->plane_res.scl_data.viewport.x, 1129 pipe_ctx->plane_res.scl_data.viewport.y, 1130 pipe_ctx->plane_res.scl_data.recout.width, 1131 pipe_ctx->plane_res.scl_data.recout.height, 1132 pipe_ctx->plane_res.scl_data.recout.x, 1133 pipe_ctx->plane_res.scl_data.recout.y); 1134 print_rq_dlg_ttu(dc, pipe_ctx); 1135 } 1136 */ 1137 if (dc->vm_pa_config.valid) { 1138 struct vm_system_aperture_param apt; 1139 1140 apt.sys_default.quad_part = 0; 1141 1142 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1143 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1144 1145 // Program system aperture settings 1146 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1147 } 1148 1149 // if (dc->debug.sanity_checks) { 1150 // dcn10_verify_allow_pstate_change_high(dc); 1151 // } 1152 } 1153 1154 void dcn20_pipe_control_lock( 1155 struct dc *dc, 1156 struct pipe_ctx *pipe, 1157 bool lock) 1158 { 1159 struct pipe_ctx *temp_pipe; 1160 bool flip_immediate = false; 1161 1162 /* use TG master update lock to lock everything on the TG 1163 * therefore only top pipe need to lock 1164 */ 1165 if (!pipe || pipe->top_pipe) 1166 return; 1167 1168 if (pipe->plane_state != NULL) 1169 flip_immediate = pipe->plane_state->flip_immediate; 1170 1171 if (pipe->stream_res.gsl_group > 0) { 1172 temp_pipe = pipe->bottom_pipe; 1173 while (!flip_immediate && temp_pipe) { 1174 if (temp_pipe->plane_state != NULL) 1175 flip_immediate = temp_pipe->plane_state->flip_immediate; 1176 temp_pipe = temp_pipe->bottom_pipe; 1177 } 1178 } 1179 1180 if (flip_immediate && lock) { 1181 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1182 int i; 1183 1184 temp_pipe = pipe; 1185 while (temp_pipe) { 1186 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1187 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1188 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1189 break; 1190 udelay(1); 1191 } 1192 1193 /* no reason it should take this long for immediate flips */ 1194 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1195 } 1196 temp_pipe = temp_pipe->bottom_pipe; 1197 } 1198 } 1199 1200 /* In flip immediate and pipe splitting case, we need to use GSL 1201 * for synchronization. Only do setup on locking and on flip type change. 1202 */ 1203 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1204 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1205 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1206 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1207 1208 if (pipe->plane_state != NULL) 1209 flip_immediate = pipe->plane_state->flip_immediate; 1210 1211 temp_pipe = pipe->bottom_pipe; 1212 while (flip_immediate && temp_pipe) { 1213 if (temp_pipe->plane_state != NULL) 1214 flip_immediate = temp_pipe->plane_state->flip_immediate; 1215 temp_pipe = temp_pipe->bottom_pipe; 1216 } 1217 1218 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1219 !flip_immediate) 1220 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1221 1222 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1223 union dmub_hw_lock_flags hw_locks = { 0 }; 1224 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1225 1226 hw_locks.bits.lock_pipe = 1; 1227 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1228 1229 if (pipe->plane_state != NULL) 1230 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1231 1232 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1233 lock, 1234 &hw_locks, 1235 &inst_flags); 1236 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1237 if (lock) 1238 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1239 else 1240 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1241 } else { 1242 if (lock) 1243 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1244 else 1245 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1246 } 1247 } 1248 1249 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1250 { 1251 new_pipe->update_flags.raw = 0; 1252 1253 /* Exit on unchanged, unused pipe */ 1254 if (!old_pipe->plane_state && !new_pipe->plane_state) 1255 return; 1256 /* Detect pipe enable/disable */ 1257 if (!old_pipe->plane_state && new_pipe->plane_state) { 1258 new_pipe->update_flags.bits.enable = 1; 1259 new_pipe->update_flags.bits.mpcc = 1; 1260 new_pipe->update_flags.bits.dppclk = 1; 1261 new_pipe->update_flags.bits.hubp_interdependent = 1; 1262 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1263 new_pipe->update_flags.bits.gamut_remap = 1; 1264 new_pipe->update_flags.bits.scaler = 1; 1265 new_pipe->update_flags.bits.viewport = 1; 1266 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1267 new_pipe->update_flags.bits.odm = 1; 1268 new_pipe->update_flags.bits.global_sync = 1; 1269 } 1270 return; 1271 } 1272 if (old_pipe->plane_state && !new_pipe->plane_state) { 1273 new_pipe->update_flags.bits.disable = 1; 1274 return; 1275 } 1276 1277 /* Detect plane change */ 1278 if (old_pipe->plane_state != new_pipe->plane_state) { 1279 new_pipe->update_flags.bits.plane_changed = true; 1280 } 1281 1282 /* Detect top pipe only changes */ 1283 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1284 /* Detect odm changes */ 1285 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1286 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1287 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1288 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1289 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1290 new_pipe->update_flags.bits.odm = 1; 1291 1292 /* Detect global sync changes */ 1293 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1294 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1295 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1296 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1297 new_pipe->update_flags.bits.global_sync = 1; 1298 } 1299 1300 /* 1301 * Detect opp / tg change, only set on change, not on enable 1302 * Assume mpcc inst = pipe index, if not this code needs to be updated 1303 * since mpcc is what is affected by these. In fact all of our sequence 1304 * makes this assumption at the moment with how hubp reset is matched to 1305 * same index mpcc reset. 1306 */ 1307 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1308 new_pipe->update_flags.bits.opp_changed = 1; 1309 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1310 new_pipe->update_flags.bits.tg_changed = 1; 1311 1312 /* 1313 * Detect mpcc blending changes, only dpp inst and opp matter here, 1314 * mpccs getting removed/inserted update connected ones during their own 1315 * programming 1316 */ 1317 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1318 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1319 new_pipe->update_flags.bits.mpcc = 1; 1320 1321 /* Detect dppclk change */ 1322 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1323 new_pipe->update_flags.bits.dppclk = 1; 1324 1325 /* Check for scl update */ 1326 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1327 new_pipe->update_flags.bits.scaler = 1; 1328 /* Check for vp update */ 1329 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1330 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1331 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1332 new_pipe->update_flags.bits.viewport = 1; 1333 1334 /* Detect dlg/ttu/rq updates */ 1335 { 1336 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1337 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1338 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1339 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1340 1341 /* Detect pipe interdependent updates */ 1342 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1343 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1344 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1345 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1346 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1347 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1348 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1349 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1350 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1351 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1352 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1353 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1354 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1355 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1356 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1357 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1358 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1359 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1360 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1361 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1362 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1363 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1364 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1365 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1366 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1367 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1368 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1369 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1370 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1371 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1372 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1373 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1374 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1375 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1376 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1377 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1378 new_pipe->update_flags.bits.hubp_interdependent = 1; 1379 } 1380 /* Detect any other updates to ttu/rq/dlg */ 1381 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1382 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1383 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1384 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1385 } 1386 } 1387 1388 static void dcn20_update_dchubp_dpp( 1389 struct dc *dc, 1390 struct pipe_ctx *pipe_ctx, 1391 struct dc_state *context) 1392 { 1393 struct dce_hwseq *hws = dc->hwseq; 1394 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1395 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1396 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1397 bool viewport_changed = false; 1398 1399 if (pipe_ctx->update_flags.bits.dppclk) 1400 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1401 1402 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1403 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1404 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1405 */ 1406 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1407 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1408 1409 hubp->funcs->hubp_setup( 1410 hubp, 1411 &pipe_ctx->dlg_regs, 1412 &pipe_ctx->ttu_regs, 1413 &pipe_ctx->rq_regs, 1414 &pipe_ctx->pipe_dlg_param); 1415 } 1416 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1417 hubp->funcs->hubp_setup_interdependent( 1418 hubp, 1419 &pipe_ctx->dlg_regs, 1420 &pipe_ctx->ttu_regs); 1421 1422 if (pipe_ctx->update_flags.bits.enable || 1423 pipe_ctx->update_flags.bits.plane_changed || 1424 plane_state->update_flags.bits.bpp_change || 1425 plane_state->update_flags.bits.input_csc_change || 1426 plane_state->update_flags.bits.color_space_change || 1427 plane_state->update_flags.bits.coeff_reduction_change) { 1428 struct dc_bias_and_scale bns_params = {0}; 1429 1430 // program the input csc 1431 dpp->funcs->dpp_setup(dpp, 1432 plane_state->format, 1433 EXPANSION_MODE_ZERO, 1434 plane_state->input_csc_color_matrix, 1435 plane_state->color_space, 1436 NULL); 1437 1438 if (dpp->funcs->dpp_program_bias_and_scale) { 1439 //TODO :for CNVC set scale and bias registers if necessary 1440 build_prescale_params(&bns_params, plane_state); 1441 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1442 } 1443 } 1444 1445 if (pipe_ctx->update_flags.bits.mpcc 1446 || pipe_ctx->update_flags.bits.plane_changed 1447 || plane_state->update_flags.bits.global_alpha_change 1448 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1449 // MPCC inst is equal to pipe index in practice 1450 int mpcc_inst = hubp->inst; 1451 int opp_inst; 1452 int opp_count = dc->res_pool->pipe_count; 1453 1454 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1455 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1456 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1457 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1458 break; 1459 } 1460 } 1461 hws->funcs.update_mpcc(dc, pipe_ctx); 1462 } 1463 1464 if (pipe_ctx->update_flags.bits.scaler || 1465 plane_state->update_flags.bits.scaling_change || 1466 plane_state->update_flags.bits.position_change || 1467 plane_state->update_flags.bits.per_pixel_alpha_change || 1468 pipe_ctx->stream->update_flags.bits.scaling) { 1469 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1470 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP); 1471 /* scaler configuration */ 1472 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1473 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1474 } 1475 1476 if (pipe_ctx->update_flags.bits.viewport || 1477 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1478 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1479 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1480 1481 hubp->funcs->mem_program_viewport( 1482 hubp, 1483 &pipe_ctx->plane_res.scl_data.viewport, 1484 &pipe_ctx->plane_res.scl_data.viewport_c); 1485 viewport_changed = true; 1486 } 1487 1488 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1489 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1490 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1491 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1492 dc->hwss.set_cursor_position(pipe_ctx); 1493 dc->hwss.set_cursor_attribute(pipe_ctx); 1494 1495 if (dc->hwss.set_cursor_sdr_white_level) 1496 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1497 } 1498 1499 /* Any updates are handled in dc interface, just need 1500 * to apply existing for plane enable / opp change */ 1501 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1502 || pipe_ctx->stream->update_flags.bits.gamut_remap 1503 || pipe_ctx->stream->update_flags.bits.out_csc) { 1504 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 1505 1506 if (mpc->funcs->set_gamut_remap) { 1507 int i; 1508 int mpcc_id = hubp->inst; 1509 struct mpc_grph_gamut_adjustment adjust; 1510 bool enable_remap_dpp = false; 1511 1512 memset(&adjust, 0, sizeof(adjust)); 1513 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 1514 1515 /* save the enablement of gamut remap for dpp */ 1516 enable_remap_dpp = pipe_ctx->stream->gamut_remap_matrix.enable_remap; 1517 1518 /* force bypass gamut remap for dpp/cm */ 1519 pipe_ctx->stream->gamut_remap_matrix.enable_remap = false; 1520 dc->hwss.program_gamut_remap(pipe_ctx); 1521 1522 /* restore gamut remap flag and use this remap into mpc */ 1523 pipe_ctx->stream->gamut_remap_matrix.enable_remap = enable_remap_dpp; 1524 1525 /* build remap matrix for top plane if enabled */ 1526 if (enable_remap_dpp && pipe_ctx->top_pipe == NULL) { 1527 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 1528 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 1529 adjust.temperature_matrix[i] = 1530 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 1531 } 1532 mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust); 1533 } else 1534 /* dpp/cm gamut remap*/ 1535 dc->hwss.program_gamut_remap(pipe_ctx); 1536 1537 /*call the dcn2 method which uses mpc csc*/ 1538 dc->hwss.program_output_csc(dc, 1539 pipe_ctx, 1540 pipe_ctx->stream->output_color_space, 1541 pipe_ctx->stream->csc_color_matrix.matrix, 1542 hubp->opp_id); 1543 } 1544 1545 if (pipe_ctx->update_flags.bits.enable || 1546 pipe_ctx->update_flags.bits.plane_changed || 1547 pipe_ctx->update_flags.bits.opp_changed || 1548 plane_state->update_flags.bits.pixel_format_change || 1549 plane_state->update_flags.bits.horizontal_mirror_change || 1550 plane_state->update_flags.bits.rotation_change || 1551 plane_state->update_flags.bits.swizzle_change || 1552 plane_state->update_flags.bits.dcc_change || 1553 plane_state->update_flags.bits.bpp_change || 1554 plane_state->update_flags.bits.scaling_change || 1555 plane_state->update_flags.bits.plane_size_change) { 1556 struct plane_size size = plane_state->plane_size; 1557 1558 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1559 hubp->funcs->hubp_program_surface_config( 1560 hubp, 1561 plane_state->format, 1562 &plane_state->tiling_info, 1563 &size, 1564 plane_state->rotation, 1565 &plane_state->dcc, 1566 plane_state->horizontal_mirror, 1567 0); 1568 hubp->power_gated = false; 1569 } 1570 1571 if (pipe_ctx->update_flags.bits.enable || 1572 pipe_ctx->update_flags.bits.plane_changed || 1573 plane_state->update_flags.bits.addr_update) 1574 hws->funcs.update_plane_addr(dc, pipe_ctx); 1575 1576 1577 1578 if (is_pipe_tree_visible(pipe_ctx)) 1579 dc->hwss.set_hubp_blank(dc, pipe_ctx, false); 1580 } 1581 1582 1583 static void dcn20_program_pipe( 1584 struct dc *dc, 1585 struct pipe_ctx *pipe_ctx, 1586 struct dc_state *context) 1587 { 1588 struct dce_hwseq *hws = dc->hwseq; 1589 /* Only need to unblank on top pipe */ 1590 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1591 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1592 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1593 1594 /* Only update TG on top pipe */ 1595 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1596 && !pipe_ctx->prev_odm_pipe) { 1597 1598 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1599 pipe_ctx->stream_res.tg, 1600 pipe_ctx->pipe_dlg_param.vready_offset, 1601 pipe_ctx->pipe_dlg_param.vstartup_start, 1602 pipe_ctx->pipe_dlg_param.vupdate_offset, 1603 pipe_ctx->pipe_dlg_param.vupdate_width); 1604 1605 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1606 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1607 1608 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1609 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1610 1611 if (hws->funcs.setup_vupdate_interrupt) 1612 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1613 } 1614 1615 if (pipe_ctx->update_flags.bits.odm) 1616 hws->funcs.update_odm(dc, context, pipe_ctx); 1617 1618 if (pipe_ctx->update_flags.bits.enable) { 1619 dcn20_enable_plane(dc, pipe_ctx, context); 1620 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1621 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1622 } 1623 1624 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1625 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1626 1627 if (pipe_ctx->update_flags.bits.enable 1628 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1629 hws->funcs.set_hdr_multiplier(pipe_ctx); 1630 1631 if (pipe_ctx->update_flags.bits.enable || 1632 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1633 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1634 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1635 1636 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1637 * only do gamma programming for powering on, internal memcmp to avoid 1638 * updating on slave planes 1639 */ 1640 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1641 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1642 1643 /* If the pipe has been enabled or has a different opp, we 1644 * should reprogram the fmt. This deals with cases where 1645 * interation between mpc and odm combine on different streams 1646 * causes a different pipe to be chosen to odm combine with. 1647 */ 1648 if (pipe_ctx->update_flags.bits.enable 1649 || pipe_ctx->update_flags.bits.opp_changed) { 1650 1651 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1652 pipe_ctx->stream_res.opp, 1653 COLOR_SPACE_YCBCR601, 1654 pipe_ctx->stream->timing.display_color_depth, 1655 pipe_ctx->stream->signal); 1656 1657 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1658 pipe_ctx->stream_res.opp, 1659 &pipe_ctx->stream->bit_depth_params, 1660 &pipe_ctx->stream->clamping); 1661 } 1662 } 1663 1664 void dcn20_program_front_end_for_ctx( 1665 struct dc *dc, 1666 struct dc_state *context) 1667 { 1668 int i; 1669 struct dce_hwseq *hws = dc->hwseq; 1670 DC_LOGGER_INIT(dc->ctx->logger); 1671 1672 /* Carry over GSL groups in case the context is changing. */ 1673 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1674 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1675 struct pipe_ctx *old_pipe_ctx = 1676 &dc->current_state->res_ctx.pipe_ctx[i]; 1677 1678 if (pipe_ctx->stream == old_pipe_ctx->stream) 1679 pipe_ctx->stream_res.gsl_group = 1680 old_pipe_ctx->stream_res.gsl_group; 1681 } 1682 1683 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1684 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1685 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1686 1687 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1688 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1689 /*turn off triple buffer for full update*/ 1690 dc->hwss.program_triplebuffer( 1691 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1692 } 1693 } 1694 } 1695 1696 /* Set pipe update flags and lock pipes */ 1697 for (i = 0; i < dc->res_pool->pipe_count; i++) 1698 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1699 &context->res_ctx.pipe_ctx[i]); 1700 1701 /* OTG blank before disabling all front ends */ 1702 for (i = 0; i < dc->res_pool->pipe_count; i++) 1703 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1704 && !context->res_ctx.pipe_ctx[i].top_pipe 1705 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1706 && context->res_ctx.pipe_ctx[i].stream) 1707 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1708 1709 1710 /* Disconnect mpcc */ 1711 for (i = 0; i < dc->res_pool->pipe_count; i++) 1712 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1713 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1714 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1715 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1716 } 1717 1718 /* 1719 * Program all updated pipes, order matters for mpcc setup. Start with 1720 * top pipe and program all pipes that follow in order 1721 */ 1722 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1723 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1724 1725 if (pipe->plane_state && !pipe->top_pipe) { 1726 while (pipe) { 1727 dcn20_program_pipe(dc, pipe, context); 1728 pipe = pipe->bottom_pipe; 1729 } 1730 /* Program secondary blending tree and writeback pipes */ 1731 pipe = &context->res_ctx.pipe_ctx[i]; 1732 if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0 1733 && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw) 1734 && hws->funcs.program_all_writeback_pipes_in_tree) 1735 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1736 } 1737 } 1738 } 1739 1740 void dcn20_post_unlock_program_front_end( 1741 struct dc *dc, 1742 struct dc_state *context) 1743 { 1744 int i; 1745 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1746 struct dce_hwseq *hwseq = dc->hwseq; 1747 1748 DC_LOGGER_INIT(dc->ctx->logger); 1749 1750 for (i = 0; i < dc->res_pool->pipe_count; i++) 1751 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1752 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1753 1754 /* 1755 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1756 * part of the enable operation otherwise, DM may request an immediate flip which 1757 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1758 * is unsupported on DCN. 1759 */ 1760 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1761 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1762 1763 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1764 struct hubp *hubp = pipe->plane_res.hubp; 1765 int j = 0; 1766 1767 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1768 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1769 mdelay(1); 1770 } 1771 } 1772 1773 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1774 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1775 1776 if (pipe->vtp_locked) { 1777 dc->hwss.set_hubp_blank(dc, pipe, true); 1778 pipe->vtp_locked = false; 1779 } 1780 } 1781 /* WA to apply WM setting*/ 1782 if (hwseq->wa.DEGVIDCN21) 1783 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1784 1785 1786 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1787 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1788 1789 if (dc->current_state->stream_status[0].plane_count == 1 && 1790 context->stream_status[0].plane_count > 1) { 1791 1792 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1793 1794 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1795 1796 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1797 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1798 } 1799 } 1800 } 1801 1802 void dcn20_prepare_bandwidth( 1803 struct dc *dc, 1804 struct dc_state *context) 1805 { 1806 struct hubbub *hubbub = dc->res_pool->hubbub; 1807 1808 dc->clk_mgr->funcs->update_clocks( 1809 dc->clk_mgr, 1810 context, 1811 false); 1812 1813 /* program dchubbub watermarks */ 1814 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 1815 &context->bw_ctx.bw.dcn.watermarks, 1816 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1817 false); 1818 } 1819 1820 void dcn20_optimize_bandwidth( 1821 struct dc *dc, 1822 struct dc_state *context) 1823 { 1824 struct hubbub *hubbub = dc->res_pool->hubbub; 1825 1826 /* program dchubbub watermarks */ 1827 hubbub->funcs->program_watermarks(hubbub, 1828 &context->bw_ctx.bw.dcn.watermarks, 1829 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1830 true); 1831 1832 dc->clk_mgr->funcs->update_clocks( 1833 dc->clk_mgr, 1834 context, 1835 true); 1836 } 1837 1838 bool dcn20_update_bandwidth( 1839 struct dc *dc, 1840 struct dc_state *context) 1841 { 1842 int i; 1843 struct dce_hwseq *hws = dc->hwseq; 1844 1845 /* recalculate DML parameters */ 1846 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1847 return false; 1848 1849 /* apply updated bandwidth parameters */ 1850 dc->hwss.prepare_bandwidth(dc, context); 1851 1852 /* update hubp configs for all pipes */ 1853 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1854 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1855 1856 if (pipe_ctx->plane_state == NULL) 1857 continue; 1858 1859 if (pipe_ctx->top_pipe == NULL) { 1860 bool blank = !is_pipe_tree_visible(pipe_ctx); 1861 1862 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1863 pipe_ctx->stream_res.tg, 1864 pipe_ctx->pipe_dlg_param.vready_offset, 1865 pipe_ctx->pipe_dlg_param.vstartup_start, 1866 pipe_ctx->pipe_dlg_param.vupdate_offset, 1867 pipe_ctx->pipe_dlg_param.vupdate_width); 1868 1869 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1870 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 1871 1872 if (pipe_ctx->prev_odm_pipe == NULL) 1873 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 1874 1875 if (hws->funcs.setup_vupdate_interrupt) 1876 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1877 } 1878 1879 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1880 pipe_ctx->plane_res.hubp, 1881 &pipe_ctx->dlg_regs, 1882 &pipe_ctx->ttu_regs, 1883 &pipe_ctx->rq_regs, 1884 &pipe_ctx->pipe_dlg_param); 1885 } 1886 1887 return true; 1888 } 1889 1890 void dcn20_enable_writeback( 1891 struct dc *dc, 1892 struct dc_writeback_info *wb_info, 1893 struct dc_state *context) 1894 { 1895 struct dwbc *dwb; 1896 struct mcif_wb *mcif_wb; 1897 struct timing_generator *optc; 1898 1899 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1900 ASSERT(wb_info->wb_enabled); 1901 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1902 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1903 1904 /* set the OPTC source mux */ 1905 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 1906 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1907 /* set MCIF_WB buffer and arbitration configuration */ 1908 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1909 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1910 /* Enable MCIF_WB */ 1911 mcif_wb->funcs->enable_mcif(mcif_wb); 1912 /* Enable DWB */ 1913 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1914 /* TODO: add sequence to enable/disable warmup */ 1915 } 1916 1917 void dcn20_disable_writeback( 1918 struct dc *dc, 1919 unsigned int dwb_pipe_inst) 1920 { 1921 struct dwbc *dwb; 1922 struct mcif_wb *mcif_wb; 1923 1924 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1925 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1926 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1927 1928 dwb->funcs->disable(dwb); 1929 mcif_wb->funcs->disable_mcif(mcif_wb); 1930 } 1931 1932 bool dcn20_wait_for_blank_complete( 1933 struct output_pixel_processor *opp) 1934 { 1935 int counter; 1936 1937 for (counter = 0; counter < 1000; counter++) { 1938 if (opp->funcs->dpg_is_blanked(opp)) 1939 break; 1940 1941 udelay(100); 1942 } 1943 1944 if (counter == 1000) { 1945 dm_error("DC: failed to blank crtc!\n"); 1946 return false; 1947 } 1948 1949 return true; 1950 } 1951 1952 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1953 { 1954 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1955 1956 if (!hubp) 1957 return false; 1958 return hubp->funcs->dmdata_status_done(hubp); 1959 } 1960 1961 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1962 { 1963 struct dce_hwseq *hws = dc->hwseq; 1964 1965 if (pipe_ctx->stream_res.dsc) { 1966 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1967 1968 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1969 while (odm_pipe) { 1970 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 1971 odm_pipe = odm_pipe->next_odm_pipe; 1972 } 1973 } 1974 } 1975 1976 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1977 { 1978 struct dce_hwseq *hws = dc->hwseq; 1979 1980 if (pipe_ctx->stream_res.dsc) { 1981 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1982 1983 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 1984 while (odm_pipe) { 1985 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 1986 odm_pipe = odm_pipe->next_odm_pipe; 1987 } 1988 } 1989 } 1990 1991 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 1992 { 1993 struct dc_dmdata_attributes attr = { 0 }; 1994 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1995 1996 attr.dmdata_mode = DMDATA_HW_MODE; 1997 attr.dmdata_size = 1998 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 1999 attr.address.quad_part = 2000 pipe_ctx->stream->dmdata_address.quad_part; 2001 attr.dmdata_dl_delta = 0; 2002 attr.dmdata_qos_mode = 0; 2003 attr.dmdata_qos_level = 0; 2004 attr.dmdata_repeat = 1; /* always repeat */ 2005 attr.dmdata_updated = 1; 2006 attr.dmdata_sw_data = NULL; 2007 2008 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2009 } 2010 2011 void dcn20_init_vm_ctx( 2012 struct dce_hwseq *hws, 2013 struct dc *dc, 2014 struct dc_virtual_addr_space_config *va_config, 2015 int vmid) 2016 { 2017 struct dcn_hubbub_virt_addr_config config; 2018 2019 if (vmid == 0) { 2020 ASSERT(0); /* VMID cannot be 0 for vm context */ 2021 return; 2022 } 2023 2024 config.page_table_start_addr = va_config->page_table_start_addr; 2025 config.page_table_end_addr = va_config->page_table_end_addr; 2026 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2027 config.page_table_depth = va_config->page_table_depth; 2028 config.page_table_base_addr = va_config->page_table_base_addr; 2029 2030 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2031 } 2032 2033 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2034 { 2035 struct dcn_hubbub_phys_addr_config config; 2036 2037 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2038 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2039 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2040 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2041 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2042 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2043 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2044 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2045 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2046 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2047 2048 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2049 } 2050 2051 static bool patch_address_for_sbs_tb_stereo( 2052 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2053 { 2054 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2055 bool sec_split = pipe_ctx->top_pipe && 2056 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2057 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2058 (pipe_ctx->stream->timing.timing_3d_format == 2059 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2060 pipe_ctx->stream->timing.timing_3d_format == 2061 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2062 *addr = plane_state->address.grph_stereo.left_addr; 2063 plane_state->address.grph_stereo.left_addr = 2064 plane_state->address.grph_stereo.right_addr; 2065 return true; 2066 } 2067 2068 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2069 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2070 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2071 plane_state->address.grph_stereo.right_addr = 2072 plane_state->address.grph_stereo.left_addr; 2073 plane_state->address.grph_stereo.right_meta_addr = 2074 plane_state->address.grph_stereo.left_meta_addr; 2075 } 2076 return false; 2077 } 2078 2079 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2080 { 2081 bool addr_patched = false; 2082 PHYSICAL_ADDRESS_LOC addr; 2083 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2084 2085 if (plane_state == NULL) 2086 return; 2087 2088 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2089 2090 // Call Helper to track VMID use 2091 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2092 2093 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2094 pipe_ctx->plane_res.hubp, 2095 &plane_state->address, 2096 plane_state->flip_immediate); 2097 2098 plane_state->status.requested_address = plane_state->address; 2099 2100 if (plane_state->flip_immediate) 2101 plane_state->status.current_address = plane_state->address; 2102 2103 if (addr_patched) 2104 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2105 } 2106 2107 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2108 struct dc_link_settings *link_settings) 2109 { 2110 struct encoder_unblank_param params = { { 0 } }; 2111 struct dc_stream_state *stream = pipe_ctx->stream; 2112 struct dc_link *link = stream->link; 2113 struct dce_hwseq *hws = link->dc->hwseq; 2114 struct pipe_ctx *odm_pipe; 2115 2116 params.opp_cnt = 1; 2117 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2118 params.opp_cnt++; 2119 } 2120 /* only 3 items below are used by unblank */ 2121 params.timing = pipe_ctx->stream->timing; 2122 2123 params.link_settings.link_rate = link_settings->link_rate; 2124 2125 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2126 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2127 params.timing.pix_clk_100hz /= 2; 2128 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2129 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2130 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 2131 } 2132 2133 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2134 hws->funcs.edp_backlight_control(link, true); 2135 } 2136 } 2137 2138 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2139 { 2140 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2141 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2142 2143 if (start_line < 0) 2144 start_line = 0; 2145 2146 if (tg->funcs->setup_vertical_interrupt2) 2147 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2148 } 2149 2150 static void dcn20_reset_back_end_for_pipe( 2151 struct dc *dc, 2152 struct pipe_ctx *pipe_ctx, 2153 struct dc_state *context) 2154 { 2155 int i; 2156 struct dc_link *link; 2157 DC_LOGGER_INIT(dc->ctx->logger); 2158 if (pipe_ctx->stream_res.stream_enc == NULL) { 2159 pipe_ctx->stream = NULL; 2160 return; 2161 } 2162 2163 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2164 link = pipe_ctx->stream->link; 2165 /* DPMS may already disable or */ 2166 /* dpms_off status is incorrect due to fastboot 2167 * feature. When system resume from S4 with second 2168 * screen only, the dpms_off would be true but 2169 * VBIOS lit up eDP, so check link status too. 2170 */ 2171 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2172 core_link_disable_stream(pipe_ctx); 2173 else if (pipe_ctx->stream_res.audio) 2174 dc->hwss.disable_audio_stream(pipe_ctx); 2175 2176 /* free acquired resources */ 2177 if (pipe_ctx->stream_res.audio) { 2178 /*disable az_endpoint*/ 2179 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2180 2181 /*free audio*/ 2182 if (dc->caps.dynamic_audio == true) { 2183 /*we have to dynamic arbitrate the audio endpoints*/ 2184 /*we free the resource, need reset is_audio_acquired*/ 2185 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2186 pipe_ctx->stream_res.audio, false); 2187 pipe_ctx->stream_res.audio = NULL; 2188 } 2189 } 2190 } 2191 else if (pipe_ctx->stream_res.dsc) { 2192 dp_set_dsc_enable(pipe_ctx, false); 2193 } 2194 2195 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2196 * back end share by all pipes and will be disable only when disable 2197 * parent pipe. 2198 */ 2199 if (pipe_ctx->top_pipe == NULL) { 2200 2201 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2202 2203 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2204 2205 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2206 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2207 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2208 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2209 2210 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2211 pipe_ctx->stream_res.tg->funcs->set_drr( 2212 pipe_ctx->stream_res.tg, NULL); 2213 } 2214 2215 for (i = 0; i < dc->res_pool->pipe_count; i++) 2216 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2217 break; 2218 2219 if (i == dc->res_pool->pipe_count) 2220 return; 2221 2222 pipe_ctx->stream = NULL; 2223 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2224 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2225 } 2226 2227 void dcn20_reset_hw_ctx_wrap( 2228 struct dc *dc, 2229 struct dc_state *context) 2230 { 2231 int i; 2232 struct dce_hwseq *hws = dc->hwseq; 2233 2234 /* Reset Back End*/ 2235 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2236 struct pipe_ctx *pipe_ctx_old = 2237 &dc->current_state->res_ctx.pipe_ctx[i]; 2238 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2239 2240 if (!pipe_ctx_old->stream) 2241 continue; 2242 2243 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2244 continue; 2245 2246 if (!pipe_ctx->stream || 2247 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2248 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2249 2250 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2251 if (hws->funcs.enable_stream_gating) 2252 hws->funcs.enable_stream_gating(dc, pipe_ctx); 2253 if (old_clk) 2254 old_clk->funcs->cs_power_down(old_clk); 2255 } 2256 } 2257 } 2258 2259 void dcn20_get_mpctree_visual_confirm_color( 2260 struct pipe_ctx *pipe_ctx, 2261 struct tg_color *color) 2262 { 2263 const struct tg_color pipe_colors[6] = { 2264 {MAX_TG_COLOR_VALUE, 0, 0}, // red 2265 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, // orange 2266 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, // yellow 2267 {0, MAX_TG_COLOR_VALUE, 0}, // green 2268 {0, 0, MAX_TG_COLOR_VALUE}, // blue 2269 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple 2270 }; 2271 2272 struct pipe_ctx *top_pipe = pipe_ctx; 2273 2274 while (top_pipe->top_pipe) { 2275 top_pipe = top_pipe->top_pipe; 2276 } 2277 2278 *color = pipe_colors[top_pipe->pipe_idx]; 2279 } 2280 2281 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2282 { 2283 struct dce_hwseq *hws = dc->hwseq; 2284 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2285 struct mpcc_blnd_cfg blnd_cfg = { {0} }; 2286 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2287 int mpcc_id; 2288 struct mpcc *new_mpcc; 2289 struct mpc *mpc = dc->res_pool->mpc; 2290 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2291 2292 // input to MPCC is always RGB, by default leave black_color at 0 2293 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { 2294 hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color); 2295 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { 2296 hws->funcs.get_surface_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color); 2297 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) { 2298 dcn20_get_mpctree_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color); 2299 } 2300 2301 if (per_pixel_alpha) 2302 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2303 else 2304 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2305 2306 blnd_cfg.overlap_only = false; 2307 blnd_cfg.global_gain = 0xff; 2308 2309 if (pipe_ctx->plane_state->global_alpha) 2310 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2311 else 2312 blnd_cfg.global_alpha = 0xff; 2313 2314 blnd_cfg.background_color_bpc = 4; 2315 blnd_cfg.bottom_gain_mode = 0; 2316 blnd_cfg.top_gain = 0x1f000; 2317 blnd_cfg.bottom_inside_gain = 0x1f000; 2318 blnd_cfg.bottom_outside_gain = 0x1f000; 2319 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 2320 if (pipe_ctx->plane_state->format 2321 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2322 blnd_cfg.pre_multiplied_alpha = false; 2323 2324 /* 2325 * TODO: remove hack 2326 * Note: currently there is a bug in init_hw such that 2327 * on resume from hibernate, BIOS sets up MPCC0, and 2328 * we do mpcc_remove but the mpcc cannot go to idle 2329 * after remove. This cause us to pick mpcc1 here, 2330 * which causes a pstate hang for yet unknown reason. 2331 */ 2332 mpcc_id = hubp->inst; 2333 2334 /* If there is no full update, don't need to touch MPC tree*/ 2335 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2336 !pipe_ctx->update_flags.bits.mpcc) { 2337 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2338 return; 2339 } 2340 2341 /* check if this MPCC is already being used */ 2342 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2343 /* remove MPCC if being used */ 2344 if (new_mpcc != NULL) 2345 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2346 else 2347 if (dc->debug.sanity_checks) 2348 mpc->funcs->assert_mpcc_idle_before_connect( 2349 dc->res_pool->mpc, mpcc_id); 2350 2351 /* Call MPC to insert new plane */ 2352 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2353 mpc_tree_params, 2354 &blnd_cfg, 2355 NULL, 2356 NULL, 2357 hubp->inst, 2358 mpcc_id); 2359 2360 ASSERT(new_mpcc != NULL); 2361 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2362 hubp->mpcc_id = mpcc_id; 2363 } 2364 2365 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2366 { 2367 enum dc_lane_count lane_count = 2368 pipe_ctx->stream->link->cur_link_settings.lane_count; 2369 2370 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2371 struct dc_link *link = pipe_ctx->stream->link; 2372 2373 uint32_t active_total_with_borders; 2374 uint32_t early_control = 0; 2375 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2376 2377 /* For MST, there are multiply stream go to only one link. 2378 * connect DIG back_end to front_end while enable_stream and 2379 * disconnect them during disable_stream 2380 * BY this, it is logic clean to separate stream and link 2381 */ 2382 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 2383 pipe_ctx->stream_res.stream_enc->id, true); 2384 2385 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2386 if (link->dc->hwss.program_dmdata_engine) 2387 link->dc->hwss.program_dmdata_engine(pipe_ctx); 2388 } 2389 2390 link->dc->hwss.update_info_frame(pipe_ctx); 2391 2392 /* enable early control to avoid corruption on DP monitor*/ 2393 active_total_with_borders = 2394 timing->h_addressable 2395 + timing->h_border_left 2396 + timing->h_border_right; 2397 2398 if (lane_count != 0) 2399 early_control = active_total_with_borders % lane_count; 2400 2401 if (early_control == 0) 2402 early_control = lane_count; 2403 2404 tg->funcs->set_early_control(tg, early_control); 2405 2406 /* enable audio only within mode set */ 2407 if (pipe_ctx->stream_res.audio != NULL) { 2408 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2409 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2410 } 2411 } 2412 2413 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2414 { 2415 struct dc_stream_state *stream = pipe_ctx->stream; 2416 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2417 bool enable = false; 2418 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2419 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2420 ? dmdata_dp 2421 : dmdata_hdmi; 2422 2423 /* if using dynamic meta, don't set up generic infopackets */ 2424 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2425 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2426 enable = true; 2427 } 2428 2429 if (!hubp) 2430 return; 2431 2432 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2433 return; 2434 2435 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2436 hubp->inst, mode); 2437 } 2438 2439 void dcn20_fpga_init_hw(struct dc *dc) 2440 { 2441 int i, j; 2442 struct dce_hwseq *hws = dc->hwseq; 2443 struct resource_pool *res_pool = dc->res_pool; 2444 struct dc_state *context = dc->current_state; 2445 2446 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2447 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2448 2449 // Initialize the dccg 2450 if (res_pool->dccg->funcs->dccg_init) 2451 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2452 2453 //Enable ability to power gate / don't force power on permanently 2454 hws->funcs.enable_power_gating_plane(hws, true); 2455 2456 // Specific to FPGA dccg and registers 2457 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2458 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2459 2460 hws->funcs.dccg_init(hws); 2461 2462 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2463 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2464 if (REG(REFCLK_CNTL)) 2465 REG_WRITE(REFCLK_CNTL, 0); 2466 // 2467 2468 2469 /* Blank pixel data with OPP DPG */ 2470 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2471 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2472 2473 if (tg->funcs->is_tg_enabled(tg)) 2474 dcn20_init_blank(dc, tg); 2475 } 2476 2477 for (i = 0; i < res_pool->timing_generator_count; i++) { 2478 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2479 2480 if (tg->funcs->is_tg_enabled(tg)) 2481 tg->funcs->lock(tg); 2482 } 2483 2484 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2485 struct dpp *dpp = res_pool->dpps[i]; 2486 2487 dpp->funcs->dpp_reset(dpp); 2488 } 2489 2490 /* Reset all MPCC muxes */ 2491 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2492 2493 /* initialize OPP mpc_tree parameter */ 2494 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2495 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2496 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2497 for (j = 0; j < MAX_PIPES; j++) 2498 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2499 } 2500 2501 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2502 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2503 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2504 struct hubp *hubp = dc->res_pool->hubps[i]; 2505 struct dpp *dpp = dc->res_pool->dpps[i]; 2506 2507 pipe_ctx->stream_res.tg = tg; 2508 pipe_ctx->pipe_idx = i; 2509 2510 pipe_ctx->plane_res.hubp = hubp; 2511 pipe_ctx->plane_res.dpp = dpp; 2512 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2513 hubp->mpcc_id = dpp->inst; 2514 hubp->opp_id = OPP_ID_INVALID; 2515 hubp->power_gated = false; 2516 pipe_ctx->stream_res.opp = NULL; 2517 2518 hubp->funcs->hubp_init(hubp); 2519 2520 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2521 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2522 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2523 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2524 /*to do*/ 2525 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2526 } 2527 2528 /* initialize DWB pointer to MCIF_WB */ 2529 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2530 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2531 2532 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2533 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2534 2535 if (tg->funcs->is_tg_enabled(tg)) 2536 tg->funcs->unlock(tg); 2537 } 2538 2539 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2540 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2541 2542 dc->hwss.disable_plane(dc, pipe_ctx); 2543 2544 pipe_ctx->stream_res.tg = NULL; 2545 pipe_ctx->plane_res.hubp = NULL; 2546 } 2547 2548 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2549 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2550 2551 tg->funcs->tg_init(tg); 2552 } 2553 } 2554 #ifndef TRIM_FSFT 2555 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2556 struct dc_crtc_timing *timing, 2557 unsigned int max_input_rate_in_khz) 2558 { 2559 unsigned int old_v_front_porch; 2560 unsigned int old_v_total; 2561 unsigned int max_input_rate_in_100hz; 2562 unsigned long long new_v_total; 2563 2564 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2565 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2566 return false; 2567 2568 old_v_total = timing->v_total; 2569 old_v_front_porch = timing->v_front_porch; 2570 2571 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2572 timing->pix_clk_100hz = max_input_rate_in_100hz; 2573 2574 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2575 2576 timing->v_total = new_v_total; 2577 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2578 return true; 2579 } 2580 #endif 2581 2582 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2583 struct pipe_ctx *pipe_ctx, 2584 enum controller_dp_test_pattern test_pattern, 2585 enum controller_dp_color_space color_space, 2586 enum dc_color_depth color_depth, 2587 const struct tg_color *solid_color, 2588 int width, int height, int offset) 2589 { 2590 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2591 color_space, color_depth, solid_color, width, height, offset); 2592 } 2593