1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 #include "dc_dmub_srv.h" 53 #include "dce/dmub_hw_lock_mgr.h" 54 #include "hw_sequencer.h" 55 #include "inc/link_dpcd.h" 56 #include "dpcd_defs.h" 57 #include "inc/link_enc_cfg.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 #define CTX \ 62 hws->ctx 63 #define REG(reg)\ 64 hws->regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 hws->shifts->field_name, hws->masks->field_name 69 70 static int find_free_gsl_group(const struct dc *dc) 71 { 72 if (dc->res_pool->gsl_groups.gsl_0 == 0) 73 return 1; 74 if (dc->res_pool->gsl_groups.gsl_1 == 0) 75 return 2; 76 if (dc->res_pool->gsl_groups.gsl_2 == 0) 77 return 3; 78 79 return 0; 80 } 81 82 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 83 * This is only used to lock pipes in pipe splitting case with immediate flip 84 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 85 * so we get tearing with freesync since we cannot flip multiple pipes 86 * atomically. 87 * We use GSL for this: 88 * - immediate flip: find first available GSL group if not already assigned 89 * program gsl with that group, set current OTG as master 90 * and always us 0x4 = AND of flip_ready from all pipes 91 * - vsync flip: disable GSL if used 92 * 93 * Groups in stream_res are stored as +1 from HW registers, i.e. 94 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 95 * Using a magic value like -1 would require tracking all inits/resets 96 */ 97 static void dcn20_setup_gsl_group_as_lock( 98 const struct dc *dc, 99 struct pipe_ctx *pipe_ctx, 100 bool enable) 101 { 102 struct gsl_params gsl; 103 int group_idx; 104 105 memset(&gsl, 0, sizeof(struct gsl_params)); 106 107 if (enable) { 108 /* return if group already assigned since GSL was set up 109 * for vsync flip, we would unassign so it can't be "left over" 110 */ 111 if (pipe_ctx->stream_res.gsl_group > 0) 112 return; 113 114 group_idx = find_free_gsl_group(dc); 115 ASSERT(group_idx != 0); 116 pipe_ctx->stream_res.gsl_group = group_idx; 117 118 /* set gsl group reg field and mark resource used */ 119 switch (group_idx) { 120 case 1: 121 gsl.gsl0_en = 1; 122 dc->res_pool->gsl_groups.gsl_0 = 1; 123 break; 124 case 2: 125 gsl.gsl1_en = 1; 126 dc->res_pool->gsl_groups.gsl_1 = 1; 127 break; 128 case 3: 129 gsl.gsl2_en = 1; 130 dc->res_pool->gsl_groups.gsl_2 = 1; 131 break; 132 default: 133 BREAK_TO_DEBUGGER(); 134 return; // invalid case 135 } 136 gsl.gsl_master_en = 1; 137 } else { 138 group_idx = pipe_ctx->stream_res.gsl_group; 139 if (group_idx == 0) 140 return; // if not in use, just return 141 142 pipe_ctx->stream_res.gsl_group = 0; 143 144 /* unset gsl group reg field and mark resource free */ 145 switch (group_idx) { 146 case 1: 147 gsl.gsl0_en = 0; 148 dc->res_pool->gsl_groups.gsl_0 = 0; 149 break; 150 case 2: 151 gsl.gsl1_en = 0; 152 dc->res_pool->gsl_groups.gsl_1 = 0; 153 break; 154 case 3: 155 gsl.gsl2_en = 0; 156 dc->res_pool->gsl_groups.gsl_2 = 0; 157 break; 158 default: 159 BREAK_TO_DEBUGGER(); 160 return; 161 } 162 gsl.gsl_master_en = 0; 163 } 164 165 /* at this point we want to program whether it's to enable or disable */ 166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 168 pipe_ctx->stream_res.tg->funcs->set_gsl( 169 pipe_ctx->stream_res.tg, 170 &gsl); 171 172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 174 } else 175 BREAK_TO_DEBUGGER(); 176 } 177 178 void dcn20_set_flip_control_gsl( 179 struct pipe_ctx *pipe_ctx, 180 bool flip_immediate) 181 { 182 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 183 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 184 pipe_ctx->plane_res.hubp, flip_immediate); 185 186 } 187 188 void dcn20_enable_power_gating_plane( 189 struct dce_hwseq *hws, 190 bool enable) 191 { 192 bool force_on = true; /* disable power gating */ 193 194 if (enable) 195 force_on = false; 196 197 /* DCHUBP0/1/2/3/4/5 */ 198 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 199 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 200 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 201 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 202 if (REG(DOMAIN8_PG_CONFIG)) 203 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 204 if (REG(DOMAIN10_PG_CONFIG)) 205 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 206 207 /* DPP0/1/2/3/4/5 */ 208 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 209 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 210 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 211 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 212 if (REG(DOMAIN9_PG_CONFIG)) 213 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 214 if (REG(DOMAIN11_PG_CONFIG)) 215 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 216 217 /* DCS0/1/2/3/4/5 */ 218 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 219 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 220 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 221 if (REG(DOMAIN19_PG_CONFIG)) 222 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 223 if (REG(DOMAIN20_PG_CONFIG)) 224 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 225 if (REG(DOMAIN21_PG_CONFIG)) 226 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 227 } 228 229 void dcn20_dccg_init(struct dce_hwseq *hws) 230 { 231 /* 232 * set MICROSECOND_TIME_BASE_DIV 233 * 100Mhz refclk -> 0x120264 234 * 27Mhz refclk -> 0x12021b 235 * 48Mhz refclk -> 0x120230 236 * 237 */ 238 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 239 240 /* 241 * set MILLISECOND_TIME_BASE_DIV 242 * 100Mhz refclk -> 0x1186a0 243 * 27Mhz refclk -> 0x106978 244 * 48Mhz refclk -> 0x10bb80 245 * 246 */ 247 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 248 249 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 250 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); 251 } 252 253 void dcn20_disable_vga( 254 struct dce_hwseq *hws) 255 { 256 REG_WRITE(D1VGA_CONTROL, 0); 257 REG_WRITE(D2VGA_CONTROL, 0); 258 REG_WRITE(D3VGA_CONTROL, 0); 259 REG_WRITE(D4VGA_CONTROL, 0); 260 REG_WRITE(D5VGA_CONTROL, 0); 261 REG_WRITE(D6VGA_CONTROL, 0); 262 } 263 264 void dcn20_program_triple_buffer( 265 const struct dc *dc, 266 struct pipe_ctx *pipe_ctx, 267 bool enable_triple_buffer) 268 { 269 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 270 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 271 pipe_ctx->plane_res.hubp, 272 enable_triple_buffer); 273 } 274 } 275 276 /* Blank pixel data during initialization */ 277 void dcn20_init_blank( 278 struct dc *dc, 279 struct timing_generator *tg) 280 { 281 struct dce_hwseq *hws = dc->hwseq; 282 enum dc_color_space color_space; 283 struct tg_color black_color = {0}; 284 struct output_pixel_processor *opp = NULL; 285 struct output_pixel_processor *bottom_opp = NULL; 286 uint32_t num_opps, opp_id_src0, opp_id_src1; 287 uint32_t otg_active_width, otg_active_height; 288 289 /* program opp dpg blank color */ 290 color_space = COLOR_SPACE_SRGB; 291 color_space_to_black_color(dc, color_space, &black_color); 292 293 /* get the OTG active size */ 294 tg->funcs->get_otg_active_size(tg, 295 &otg_active_width, 296 &otg_active_height); 297 298 /* get the OPTC source */ 299 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 300 301 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 302 ASSERT(false); 303 return; 304 } 305 opp = dc->res_pool->opps[opp_id_src0]; 306 307 if (num_opps == 2) { 308 otg_active_width = otg_active_width / 2; 309 310 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 311 ASSERT(false); 312 return; 313 } 314 bottom_opp = dc->res_pool->opps[opp_id_src1]; 315 } 316 317 opp->funcs->opp_set_disp_pattern_generator( 318 opp, 319 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 320 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 321 COLOR_DEPTH_UNDEFINED, 322 &black_color, 323 otg_active_width, 324 otg_active_height, 325 0); 326 327 if (num_opps == 2) { 328 bottom_opp->funcs->opp_set_disp_pattern_generator( 329 bottom_opp, 330 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 331 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 332 COLOR_DEPTH_UNDEFINED, 333 &black_color, 334 otg_active_width, 335 otg_active_height, 336 0); 337 } 338 339 hws->funcs.wait_for_blank_complete(opp); 340 } 341 342 void dcn20_dsc_pg_control( 343 struct dce_hwseq *hws, 344 unsigned int dsc_inst, 345 bool power_on) 346 { 347 uint32_t power_gate = power_on ? 0 : 1; 348 uint32_t pwr_status = power_on ? 0 : 2; 349 uint32_t org_ip_request_cntl = 0; 350 351 if (hws->ctx->dc->debug.disable_dsc_power_gate) 352 return; 353 354 if (REG(DOMAIN16_PG_CONFIG) == 0) 355 return; 356 357 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 358 if (org_ip_request_cntl == 0) 359 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 360 361 switch (dsc_inst) { 362 case 0: /* DSC0 */ 363 REG_UPDATE(DOMAIN16_PG_CONFIG, 364 DOMAIN16_POWER_GATE, power_gate); 365 366 REG_WAIT(DOMAIN16_PG_STATUS, 367 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 368 1, 1000); 369 break; 370 case 1: /* DSC1 */ 371 REG_UPDATE(DOMAIN17_PG_CONFIG, 372 DOMAIN17_POWER_GATE, power_gate); 373 374 REG_WAIT(DOMAIN17_PG_STATUS, 375 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 376 1, 1000); 377 break; 378 case 2: /* DSC2 */ 379 REG_UPDATE(DOMAIN18_PG_CONFIG, 380 DOMAIN18_POWER_GATE, power_gate); 381 382 REG_WAIT(DOMAIN18_PG_STATUS, 383 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 384 1, 1000); 385 break; 386 case 3: /* DSC3 */ 387 REG_UPDATE(DOMAIN19_PG_CONFIG, 388 DOMAIN19_POWER_GATE, power_gate); 389 390 REG_WAIT(DOMAIN19_PG_STATUS, 391 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 392 1, 1000); 393 break; 394 case 4: /* DSC4 */ 395 REG_UPDATE(DOMAIN20_PG_CONFIG, 396 DOMAIN20_POWER_GATE, power_gate); 397 398 REG_WAIT(DOMAIN20_PG_STATUS, 399 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 400 1, 1000); 401 break; 402 case 5: /* DSC5 */ 403 REG_UPDATE(DOMAIN21_PG_CONFIG, 404 DOMAIN21_POWER_GATE, power_gate); 405 406 REG_WAIT(DOMAIN21_PG_STATUS, 407 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 408 1, 1000); 409 break; 410 default: 411 BREAK_TO_DEBUGGER(); 412 break; 413 } 414 415 if (org_ip_request_cntl == 0) 416 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 417 } 418 419 void dcn20_dpp_pg_control( 420 struct dce_hwseq *hws, 421 unsigned int dpp_inst, 422 bool power_on) 423 { 424 uint32_t power_gate = power_on ? 0 : 1; 425 uint32_t pwr_status = power_on ? 0 : 2; 426 427 if (hws->ctx->dc->debug.disable_dpp_power_gate) 428 return; 429 if (REG(DOMAIN1_PG_CONFIG) == 0) 430 return; 431 432 switch (dpp_inst) { 433 case 0: /* DPP0 */ 434 REG_UPDATE(DOMAIN1_PG_CONFIG, 435 DOMAIN1_POWER_GATE, power_gate); 436 437 REG_WAIT(DOMAIN1_PG_STATUS, 438 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 439 1, 1000); 440 break; 441 case 1: /* DPP1 */ 442 REG_UPDATE(DOMAIN3_PG_CONFIG, 443 DOMAIN3_POWER_GATE, power_gate); 444 445 REG_WAIT(DOMAIN3_PG_STATUS, 446 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 447 1, 1000); 448 break; 449 case 2: /* DPP2 */ 450 REG_UPDATE(DOMAIN5_PG_CONFIG, 451 DOMAIN5_POWER_GATE, power_gate); 452 453 REG_WAIT(DOMAIN5_PG_STATUS, 454 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 455 1, 1000); 456 break; 457 case 3: /* DPP3 */ 458 REG_UPDATE(DOMAIN7_PG_CONFIG, 459 DOMAIN7_POWER_GATE, power_gate); 460 461 REG_WAIT(DOMAIN7_PG_STATUS, 462 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 463 1, 1000); 464 break; 465 case 4: /* DPP4 */ 466 REG_UPDATE(DOMAIN9_PG_CONFIG, 467 DOMAIN9_POWER_GATE, power_gate); 468 469 REG_WAIT(DOMAIN9_PG_STATUS, 470 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 471 1, 1000); 472 break; 473 case 5: /* DPP5 */ 474 /* 475 * Do not power gate DPP5, should be left at HW default, power on permanently. 476 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 477 * reset. 478 * REG_UPDATE(DOMAIN11_PG_CONFIG, 479 * DOMAIN11_POWER_GATE, power_gate); 480 * 481 * REG_WAIT(DOMAIN11_PG_STATUS, 482 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 483 * 1, 1000); 484 */ 485 break; 486 default: 487 BREAK_TO_DEBUGGER(); 488 break; 489 } 490 } 491 492 493 void dcn20_hubp_pg_control( 494 struct dce_hwseq *hws, 495 unsigned int hubp_inst, 496 bool power_on) 497 { 498 uint32_t power_gate = power_on ? 0 : 1; 499 uint32_t pwr_status = power_on ? 0 : 2; 500 501 if (hws->ctx->dc->debug.disable_hubp_power_gate) 502 return; 503 if (REG(DOMAIN0_PG_CONFIG) == 0) 504 return; 505 506 switch (hubp_inst) { 507 case 0: /* DCHUBP0 */ 508 REG_UPDATE(DOMAIN0_PG_CONFIG, 509 DOMAIN0_POWER_GATE, power_gate); 510 511 REG_WAIT(DOMAIN0_PG_STATUS, 512 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 513 1, 1000); 514 break; 515 case 1: /* DCHUBP1 */ 516 REG_UPDATE(DOMAIN2_PG_CONFIG, 517 DOMAIN2_POWER_GATE, power_gate); 518 519 REG_WAIT(DOMAIN2_PG_STATUS, 520 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 521 1, 1000); 522 break; 523 case 2: /* DCHUBP2 */ 524 REG_UPDATE(DOMAIN4_PG_CONFIG, 525 DOMAIN4_POWER_GATE, power_gate); 526 527 REG_WAIT(DOMAIN4_PG_STATUS, 528 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 529 1, 1000); 530 break; 531 case 3: /* DCHUBP3 */ 532 REG_UPDATE(DOMAIN6_PG_CONFIG, 533 DOMAIN6_POWER_GATE, power_gate); 534 535 REG_WAIT(DOMAIN6_PG_STATUS, 536 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 537 1, 1000); 538 break; 539 case 4: /* DCHUBP4 */ 540 REG_UPDATE(DOMAIN8_PG_CONFIG, 541 DOMAIN8_POWER_GATE, power_gate); 542 543 REG_WAIT(DOMAIN8_PG_STATUS, 544 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 545 1, 1000); 546 break; 547 case 5: /* DCHUBP5 */ 548 /* 549 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 550 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 551 * reset. 552 * REG_UPDATE(DOMAIN10_PG_CONFIG, 553 * DOMAIN10_POWER_GATE, power_gate); 554 * 555 * REG_WAIT(DOMAIN10_PG_STATUS, 556 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 557 * 1, 1000); 558 */ 559 break; 560 default: 561 BREAK_TO_DEBUGGER(); 562 break; 563 } 564 } 565 566 567 /* disable HW used by plane. 568 * note: cannot disable until disconnect is complete 569 */ 570 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 571 { 572 struct dce_hwseq *hws = dc->hwseq; 573 struct hubp *hubp = pipe_ctx->plane_res.hubp; 574 struct dpp *dpp = pipe_ctx->plane_res.dpp; 575 576 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 577 578 /* In flip immediate with pipe splitting case GSL is used for 579 * synchronization so we must disable it when the plane is disabled. 580 */ 581 if (pipe_ctx->stream_res.gsl_group != 0) 582 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 583 584 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 585 586 hubp->funcs->hubp_clk_cntl(hubp, false); 587 588 dpp->funcs->dpp_dppclk_control(dpp, false, false); 589 590 hubp->power_gated = true; 591 592 hws->funcs.plane_atomic_power_down(dc, 593 pipe_ctx->plane_res.dpp, 594 pipe_ctx->plane_res.hubp); 595 596 pipe_ctx->stream = NULL; 597 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 598 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 599 pipe_ctx->top_pipe = NULL; 600 pipe_ctx->bottom_pipe = NULL; 601 pipe_ctx->plane_state = NULL; 602 } 603 604 605 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 606 { 607 DC_LOGGER_INIT(dc->ctx->logger); 608 609 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 610 return; 611 612 dcn20_plane_atomic_disable(dc, pipe_ctx); 613 614 DC_LOG_DC("Power down front end %d\n", 615 pipe_ctx->pipe_idx); 616 } 617 618 static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, 619 int opp_cnt) 620 { 621 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); 622 int flow_ctrl_cnt; 623 624 if (opp_cnt >= 2) 625 hblank_halved = true; 626 627 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - 628 stream->timing.h_border_left - 629 stream->timing.h_border_right; 630 631 if (hblank_halved) 632 flow_ctrl_cnt /= 2; 633 634 /* ODM combine 4:1 case */ 635 if (opp_cnt == 4) 636 flow_ctrl_cnt /= 2; 637 638 return flow_ctrl_cnt; 639 } 640 641 enum dc_status dcn20_enable_stream_timing( 642 struct pipe_ctx *pipe_ctx, 643 struct dc_state *context, 644 struct dc *dc) 645 { 646 struct dce_hwseq *hws = dc->hwseq; 647 struct dc_stream_state *stream = pipe_ctx->stream; 648 struct drr_params params = {0}; 649 unsigned int event_triggers = 0; 650 struct pipe_ctx *odm_pipe; 651 int opp_cnt = 1; 652 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 653 bool interlace = stream->timing.flags.INTERLACE; 654 int i; 655 struct mpc_dwb_flow_control flow_control; 656 struct mpc *mpc = dc->res_pool->mpc; 657 bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); 658 659 /* by upper caller loop, pipe0 is parent pipe and be called first. 660 * back end is set up by for pipe0. Other children pipe share back end 661 * with pipe 0. No program is needed. 662 */ 663 if (pipe_ctx->top_pipe != NULL) 664 return DC_OK; 665 666 /* TODO check if timing_changed, disable stream if timing changed */ 667 668 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 669 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 670 opp_cnt++; 671 } 672 673 if (opp_cnt > 1) 674 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 675 pipe_ctx->stream_res.tg, 676 opp_inst, opp_cnt, 677 &pipe_ctx->stream->timing); 678 679 /* HW program guide assume display already disable 680 * by unplug sequence. OTG assume stop. 681 */ 682 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 683 684 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 685 pipe_ctx->clock_source, 686 &pipe_ctx->stream_res.pix_clk_params, 687 &pipe_ctx->pll_settings)) { 688 BREAK_TO_DEBUGGER(); 689 return DC_ERROR_UNEXPECTED; 690 } 691 692 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 693 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 694 695 pipe_ctx->stream_res.tg->funcs->program_timing( 696 pipe_ctx->stream_res.tg, 697 &stream->timing, 698 pipe_ctx->pipe_dlg_param.vready_offset, 699 pipe_ctx->pipe_dlg_param.vstartup_start, 700 pipe_ctx->pipe_dlg_param.vupdate_offset, 701 pipe_ctx->pipe_dlg_param.vupdate_width, 702 pipe_ctx->stream->signal, 703 true); 704 705 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; 706 flow_control.flow_ctrl_mode = 0; 707 flow_control.flow_ctrl_cnt0 = 0x80; 708 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); 709 if (mpc->funcs->set_out_rate_control) { 710 for (i = 0; i < opp_cnt; ++i) { 711 mpc->funcs->set_out_rate_control( 712 mpc, opp_inst[i], 713 true, 714 rate_control_2x_pclk, 715 &flow_control); 716 } 717 } 718 719 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 720 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 721 odm_pipe->stream_res.opp, 722 true); 723 724 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 725 pipe_ctx->stream_res.opp, 726 true); 727 728 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 729 730 /* VTG is within DCHUB command block. DCFCLK is always on */ 731 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 732 BREAK_TO_DEBUGGER(); 733 return DC_ERROR_UNEXPECTED; 734 } 735 736 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 737 738 params.vertical_total_min = stream->adjust.v_total_min; 739 params.vertical_total_max = stream->adjust.v_total_max; 740 params.vertical_total_mid = stream->adjust.v_total_mid; 741 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 742 if (pipe_ctx->stream_res.tg->funcs->set_drr) 743 pipe_ctx->stream_res.tg->funcs->set_drr( 744 pipe_ctx->stream_res.tg, ¶ms); 745 746 // DRR should set trigger event to monitor surface update event 747 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 748 event_triggers = 0x80; 749 /* Event triggers and num frames initialized for DRR, but can be 750 * later updated for PSR use. Note DRR trigger events are generated 751 * regardless of whether num frames met. 752 */ 753 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 754 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 755 pipe_ctx->stream_res.tg, event_triggers, 2); 756 757 /* TODO program crtc source select for non-virtual signal*/ 758 /* TODO program FMT */ 759 /* TODO setup link_enc */ 760 /* TODO set stream attributes */ 761 /* TODO program audio */ 762 /* TODO enable stream if timing changed */ 763 /* TODO unblank stream if DP */ 764 765 return DC_OK; 766 } 767 768 void dcn20_program_output_csc(struct dc *dc, 769 struct pipe_ctx *pipe_ctx, 770 enum dc_color_space colorspace, 771 uint16_t *matrix, 772 int opp_id) 773 { 774 struct mpc *mpc = dc->res_pool->mpc; 775 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 776 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 777 778 if (mpc->funcs->power_on_mpc_mem_pwr) 779 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 780 781 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 782 if (mpc->funcs->set_output_csc != NULL) 783 mpc->funcs->set_output_csc(mpc, 784 opp_id, 785 matrix, 786 ocsc_mode); 787 } else { 788 if (mpc->funcs->set_ocsc_default != NULL) 789 mpc->funcs->set_ocsc_default(mpc, 790 opp_id, 791 colorspace, 792 ocsc_mode); 793 } 794 } 795 796 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 797 const struct dc_stream_state *stream) 798 { 799 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 800 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 801 struct pwl_params *params = NULL; 802 /* 803 * program OGAM only for the top pipe 804 * if there is a pipe split then fix diagnostic is required: 805 * how to pass OGAM parameter for stream. 806 * if programming for all pipes is required then remove condition 807 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 808 */ 809 if (mpc->funcs->power_on_mpc_mem_pwr) 810 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 811 if (pipe_ctx->top_pipe == NULL 812 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 813 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 814 params = &stream->out_transfer_func->pwl; 815 else if (pipe_ctx->stream->out_transfer_func->type == 816 TF_TYPE_DISTRIBUTED_POINTS && 817 cm_helper_translate_curve_to_hw_format( 818 stream->out_transfer_func, 819 &mpc->blender_params, false)) 820 params = &mpc->blender_params; 821 /* 822 * there is no ROM 823 */ 824 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 825 BREAK_TO_DEBUGGER(); 826 } 827 /* 828 * if above if is not executed then 'params' equal to 0 and set in bypass 829 */ 830 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 831 832 return true; 833 } 834 835 bool dcn20_set_blend_lut( 836 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 837 { 838 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 839 bool result = true; 840 struct pwl_params *blend_lut = NULL; 841 842 if (plane_state->blend_tf) { 843 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 844 blend_lut = &plane_state->blend_tf->pwl; 845 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 846 cm_helper_translate_curve_to_hw_format( 847 plane_state->blend_tf, 848 &dpp_base->regamma_params, false); 849 blend_lut = &dpp_base->regamma_params; 850 } 851 } 852 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 853 854 return result; 855 } 856 857 bool dcn20_set_shaper_3dlut( 858 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 859 { 860 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 861 bool result = true; 862 struct pwl_params *shaper_lut = NULL; 863 864 if (plane_state->in_shaper_func) { 865 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 866 shaper_lut = &plane_state->in_shaper_func->pwl; 867 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 868 cm_helper_translate_curve_to_hw_format( 869 plane_state->in_shaper_func, 870 &dpp_base->shaper_params, true); 871 shaper_lut = &dpp_base->shaper_params; 872 } 873 } 874 875 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 876 if (plane_state->lut3d_func && 877 plane_state->lut3d_func->state.bits.initialized == 1) 878 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 879 &plane_state->lut3d_func->lut_3d); 880 else 881 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 882 883 return result; 884 } 885 886 bool dcn20_set_input_transfer_func(struct dc *dc, 887 struct pipe_ctx *pipe_ctx, 888 const struct dc_plane_state *plane_state) 889 { 890 struct dce_hwseq *hws = dc->hwseq; 891 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 892 const struct dc_transfer_func *tf = NULL; 893 bool result = true; 894 bool use_degamma_ram = false; 895 896 if (dpp_base == NULL || plane_state == NULL) 897 return false; 898 899 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 900 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 901 902 if (plane_state->in_transfer_func) 903 tf = plane_state->in_transfer_func; 904 905 906 if (tf == NULL) { 907 dpp_base->funcs->dpp_set_degamma(dpp_base, 908 IPP_DEGAMMA_MODE_BYPASS); 909 return true; 910 } 911 912 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 913 use_degamma_ram = true; 914 915 if (use_degamma_ram == true) { 916 if (tf->type == TF_TYPE_HWPWL) 917 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 918 &tf->pwl); 919 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 920 cm_helper_translate_curve_to_degamma_hw_format(tf, 921 &dpp_base->degamma_params); 922 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 923 &dpp_base->degamma_params); 924 } 925 return true; 926 } 927 /* handle here the optimized cases when de-gamma ROM could be used. 928 * 929 */ 930 if (tf->type == TF_TYPE_PREDEFINED) { 931 switch (tf->tf) { 932 case TRANSFER_FUNCTION_SRGB: 933 dpp_base->funcs->dpp_set_degamma(dpp_base, 934 IPP_DEGAMMA_MODE_HW_sRGB); 935 break; 936 case TRANSFER_FUNCTION_BT709: 937 dpp_base->funcs->dpp_set_degamma(dpp_base, 938 IPP_DEGAMMA_MODE_HW_xvYCC); 939 break; 940 case TRANSFER_FUNCTION_LINEAR: 941 dpp_base->funcs->dpp_set_degamma(dpp_base, 942 IPP_DEGAMMA_MODE_BYPASS); 943 break; 944 case TRANSFER_FUNCTION_PQ: 945 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 946 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 947 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 948 result = true; 949 break; 950 default: 951 result = false; 952 break; 953 } 954 } else if (tf->type == TF_TYPE_BYPASS) 955 dpp_base->funcs->dpp_set_degamma(dpp_base, 956 IPP_DEGAMMA_MODE_BYPASS); 957 else { 958 /* 959 * if we are here, we did not handle correctly. 960 * fix is required for this use case 961 */ 962 BREAK_TO_DEBUGGER(); 963 dpp_base->funcs->dpp_set_degamma(dpp_base, 964 IPP_DEGAMMA_MODE_BYPASS); 965 } 966 967 return result; 968 } 969 970 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 971 { 972 struct pipe_ctx *odm_pipe; 973 int opp_cnt = 1; 974 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 975 976 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 977 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 978 opp_cnt++; 979 } 980 981 if (opp_cnt > 1) 982 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 983 pipe_ctx->stream_res.tg, 984 opp_inst, opp_cnt, 985 &pipe_ctx->stream->timing); 986 else 987 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 988 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 989 } 990 991 void dcn20_blank_pixel_data( 992 struct dc *dc, 993 struct pipe_ctx *pipe_ctx, 994 bool blank) 995 { 996 struct tg_color black_color = {0}; 997 struct stream_resource *stream_res = &pipe_ctx->stream_res; 998 struct dc_stream_state *stream = pipe_ctx->stream; 999 enum dc_color_space color_space = stream->output_color_space; 1000 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 1001 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 1002 struct pipe_ctx *odm_pipe; 1003 int odm_cnt = 1; 1004 1005 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 1006 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 1007 1008 if (stream->link->test_pattern_enabled) 1009 return; 1010 1011 /* get opp dpg blank color */ 1012 color_space_to_black_color(dc, color_space, &black_color); 1013 1014 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1015 odm_cnt++; 1016 1017 width = width / odm_cnt; 1018 1019 if (blank) { 1020 dc->hwss.set_abm_immediate_disable(pipe_ctx); 1021 1022 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 1023 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 1024 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 1025 } 1026 } else { 1027 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 1028 } 1029 1030 dc->hwss.set_disp_pattern_generator(dc, 1031 pipe_ctx, 1032 test_pattern, 1033 test_pattern_color_space, 1034 stream->timing.display_color_depth, 1035 &black_color, 1036 width, 1037 height, 1038 0); 1039 1040 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1041 dc->hwss.set_disp_pattern_generator(dc, 1042 odm_pipe, 1043 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 1044 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 1045 test_pattern_color_space, 1046 stream->timing.display_color_depth, 1047 &black_color, 1048 width, 1049 height, 1050 0); 1051 } 1052 1053 if (!blank) 1054 if (stream_res->abm) { 1055 dc->hwss.set_pipe(pipe_ctx); 1056 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1057 } 1058 } 1059 1060 1061 static void dcn20_power_on_plane( 1062 struct dce_hwseq *hws, 1063 struct pipe_ctx *pipe_ctx) 1064 { 1065 DC_LOGGER_INIT(hws->ctx->logger); 1066 if (REG(DC_IP_REQUEST_CNTL)) { 1067 REG_SET(DC_IP_REQUEST_CNTL, 0, 1068 IP_REQUEST_EN, 1); 1069 1070 if (hws->funcs.dpp_pg_control) 1071 hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1072 1073 if (hws->funcs.hubp_pg_control) 1074 hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1075 1076 REG_SET(DC_IP_REQUEST_CNTL, 0, 1077 IP_REQUEST_EN, 0); 1078 DC_LOG_DEBUG( 1079 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1080 } 1081 } 1082 1083 static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, 1084 struct dc_state *context) 1085 { 1086 //if (dc->debug.sanity_checks) { 1087 // dcn10_verify_allow_pstate_change_high(dc); 1088 //} 1089 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1090 1091 /* enable DCFCLK current DCHUB */ 1092 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1093 1094 /* initialize HUBP on power up */ 1095 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1096 1097 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1098 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1099 pipe_ctx->stream_res.opp, 1100 true); 1101 1102 /* TODO: enable/disable in dm as per update type. 1103 if (plane_state) { 1104 DC_LOG_DC(dc->ctx->logger, 1105 "Pipe:%d 0x%x: addr hi:0x%x, " 1106 "addr low:0x%x, " 1107 "src: %d, %d, %d," 1108 " %d; dst: %d, %d, %d, %d;\n", 1109 pipe_ctx->pipe_idx, 1110 plane_state, 1111 plane_state->address.grph.addr.high_part, 1112 plane_state->address.grph.addr.low_part, 1113 plane_state->src_rect.x, 1114 plane_state->src_rect.y, 1115 plane_state->src_rect.width, 1116 plane_state->src_rect.height, 1117 plane_state->dst_rect.x, 1118 plane_state->dst_rect.y, 1119 plane_state->dst_rect.width, 1120 plane_state->dst_rect.height); 1121 1122 DC_LOG_DC(dc->ctx->logger, 1123 "Pipe %d: width, height, x, y format:%d\n" 1124 "viewport:%d, %d, %d, %d\n" 1125 "recout: %d, %d, %d, %d\n", 1126 pipe_ctx->pipe_idx, 1127 plane_state->format, 1128 pipe_ctx->plane_res.scl_data.viewport.width, 1129 pipe_ctx->plane_res.scl_data.viewport.height, 1130 pipe_ctx->plane_res.scl_data.viewport.x, 1131 pipe_ctx->plane_res.scl_data.viewport.y, 1132 pipe_ctx->plane_res.scl_data.recout.width, 1133 pipe_ctx->plane_res.scl_data.recout.height, 1134 pipe_ctx->plane_res.scl_data.recout.x, 1135 pipe_ctx->plane_res.scl_data.recout.y); 1136 print_rq_dlg_ttu(dc, pipe_ctx); 1137 } 1138 */ 1139 if (dc->vm_pa_config.valid) { 1140 struct vm_system_aperture_param apt; 1141 1142 apt.sys_default.quad_part = 0; 1143 1144 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1145 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1146 1147 // Program system aperture settings 1148 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1149 } 1150 1151 if (!pipe_ctx->top_pipe 1152 && pipe_ctx->plane_state 1153 && pipe_ctx->plane_state->flip_int_enabled 1154 && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) 1155 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); 1156 1157 // if (dc->debug.sanity_checks) { 1158 // dcn10_verify_allow_pstate_change_high(dc); 1159 // } 1160 } 1161 1162 void dcn20_pipe_control_lock( 1163 struct dc *dc, 1164 struct pipe_ctx *pipe, 1165 bool lock) 1166 { 1167 struct pipe_ctx *temp_pipe; 1168 bool flip_immediate = false; 1169 1170 /* use TG master update lock to lock everything on the TG 1171 * therefore only top pipe need to lock 1172 */ 1173 if (!pipe || pipe->top_pipe) 1174 return; 1175 1176 if (pipe->plane_state != NULL) 1177 flip_immediate = pipe->plane_state->flip_immediate; 1178 1179 if (pipe->stream_res.gsl_group > 0) { 1180 temp_pipe = pipe->bottom_pipe; 1181 while (!flip_immediate && temp_pipe) { 1182 if (temp_pipe->plane_state != NULL) 1183 flip_immediate = temp_pipe->plane_state->flip_immediate; 1184 temp_pipe = temp_pipe->bottom_pipe; 1185 } 1186 } 1187 1188 if (flip_immediate && lock) { 1189 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1190 int i; 1191 1192 temp_pipe = pipe; 1193 while (temp_pipe) { 1194 if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { 1195 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1196 if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) 1197 break; 1198 udelay(1); 1199 } 1200 1201 /* no reason it should take this long for immediate flips */ 1202 ASSERT(i != TIMEOUT_FOR_FLIP_PENDING); 1203 } 1204 temp_pipe = temp_pipe->bottom_pipe; 1205 } 1206 } 1207 1208 /* In flip immediate and pipe splitting case, we need to use GSL 1209 * for synchronization. Only do setup on locking and on flip type change. 1210 */ 1211 if (lock && (pipe->bottom_pipe != NULL || !flip_immediate)) 1212 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1213 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1214 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1215 1216 if (pipe->plane_state != NULL) 1217 flip_immediate = pipe->plane_state->flip_immediate; 1218 1219 temp_pipe = pipe->bottom_pipe; 1220 while (flip_immediate && temp_pipe) { 1221 if (temp_pipe->plane_state != NULL) 1222 flip_immediate = temp_pipe->plane_state->flip_immediate; 1223 temp_pipe = temp_pipe->bottom_pipe; 1224 } 1225 1226 if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && 1227 !flip_immediate) 1228 dcn20_setup_gsl_group_as_lock(dc, pipe, false); 1229 1230 if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { 1231 union dmub_hw_lock_flags hw_locks = { 0 }; 1232 struct dmub_hw_lock_inst_flags inst_flags = { 0 }; 1233 1234 hw_locks.bits.lock_pipe = 1; 1235 inst_flags.otg_inst = pipe->stream_res.tg->inst; 1236 1237 if (pipe->plane_state != NULL) 1238 hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; 1239 1240 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, 1241 lock, 1242 &hw_locks, 1243 &inst_flags); 1244 } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1245 if (lock) 1246 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1247 else 1248 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1249 } else { 1250 if (lock) 1251 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1252 else 1253 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1254 } 1255 } 1256 1257 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1258 { 1259 new_pipe->update_flags.raw = 0; 1260 1261 /* Exit on unchanged, unused pipe */ 1262 if (!old_pipe->plane_state && !new_pipe->plane_state) 1263 return; 1264 /* Detect pipe enable/disable */ 1265 if (!old_pipe->plane_state && new_pipe->plane_state) { 1266 new_pipe->update_flags.bits.enable = 1; 1267 new_pipe->update_flags.bits.mpcc = 1; 1268 new_pipe->update_flags.bits.dppclk = 1; 1269 new_pipe->update_flags.bits.hubp_interdependent = 1; 1270 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1271 new_pipe->update_flags.bits.gamut_remap = 1; 1272 new_pipe->update_flags.bits.scaler = 1; 1273 new_pipe->update_flags.bits.viewport = 1; 1274 new_pipe->update_flags.bits.det_size = 1; 1275 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1276 new_pipe->update_flags.bits.odm = 1; 1277 new_pipe->update_flags.bits.global_sync = 1; 1278 } 1279 return; 1280 } 1281 if (old_pipe->plane_state && !new_pipe->plane_state) { 1282 new_pipe->update_flags.bits.disable = 1; 1283 return; 1284 } 1285 1286 /* Detect plane change */ 1287 if (old_pipe->plane_state != new_pipe->plane_state) { 1288 new_pipe->update_flags.bits.plane_changed = true; 1289 } 1290 1291 /* Detect top pipe only changes */ 1292 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1293 /* Detect odm changes */ 1294 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1295 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1296 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1297 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1298 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1299 new_pipe->update_flags.bits.odm = 1; 1300 1301 /* Detect global sync changes */ 1302 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1303 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1304 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1305 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1306 new_pipe->update_flags.bits.global_sync = 1; 1307 } 1308 1309 if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) 1310 new_pipe->update_flags.bits.det_size = 1; 1311 1312 /* 1313 * Detect opp / tg change, only set on change, not on enable 1314 * Assume mpcc inst = pipe index, if not this code needs to be updated 1315 * since mpcc is what is affected by these. In fact all of our sequence 1316 * makes this assumption at the moment with how hubp reset is matched to 1317 * same index mpcc reset. 1318 */ 1319 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1320 new_pipe->update_flags.bits.opp_changed = 1; 1321 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1322 new_pipe->update_flags.bits.tg_changed = 1; 1323 1324 /* 1325 * Detect mpcc blending changes, only dpp inst and opp matter here, 1326 * mpccs getting removed/inserted update connected ones during their own 1327 * programming 1328 */ 1329 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1330 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1331 new_pipe->update_flags.bits.mpcc = 1; 1332 1333 /* Detect dppclk change */ 1334 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1335 new_pipe->update_flags.bits.dppclk = 1; 1336 1337 /* Check for scl update */ 1338 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1339 new_pipe->update_flags.bits.scaler = 1; 1340 /* Check for vp update */ 1341 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1342 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1343 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1344 new_pipe->update_flags.bits.viewport = 1; 1345 1346 /* Detect dlg/ttu/rq updates */ 1347 { 1348 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1349 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1350 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1351 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1352 1353 /* Detect pipe interdependent updates */ 1354 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1355 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1356 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1357 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1358 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1359 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1360 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1361 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1362 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1363 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1364 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1365 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1366 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1367 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1368 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1369 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1370 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1371 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1372 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1373 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1374 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1375 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1376 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1377 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1378 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1379 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1380 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1381 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1382 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1383 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1384 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1385 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1386 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1387 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1388 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1389 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1390 new_pipe->update_flags.bits.hubp_interdependent = 1; 1391 } 1392 /* Detect any other updates to ttu/rq/dlg */ 1393 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1394 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1395 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1396 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1397 } 1398 } 1399 1400 static void dcn20_update_dchubp_dpp( 1401 struct dc *dc, 1402 struct pipe_ctx *pipe_ctx, 1403 struct dc_state *context) 1404 { 1405 struct dce_hwseq *hws = dc->hwseq; 1406 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1407 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1408 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1409 bool viewport_changed = false; 1410 1411 if (pipe_ctx->update_flags.bits.dppclk) 1412 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1413 1414 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1415 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1416 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1417 */ 1418 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1419 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1420 1421 hubp->funcs->hubp_setup( 1422 hubp, 1423 &pipe_ctx->dlg_regs, 1424 &pipe_ctx->ttu_regs, 1425 &pipe_ctx->rq_regs, 1426 &pipe_ctx->pipe_dlg_param); 1427 1428 if (hubp->funcs->set_unbounded_requesting) 1429 hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); 1430 } 1431 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1432 hubp->funcs->hubp_setup_interdependent( 1433 hubp, 1434 &pipe_ctx->dlg_regs, 1435 &pipe_ctx->ttu_regs); 1436 1437 if (pipe_ctx->update_flags.bits.enable || 1438 pipe_ctx->update_flags.bits.plane_changed || 1439 plane_state->update_flags.bits.bpp_change || 1440 plane_state->update_flags.bits.input_csc_change || 1441 plane_state->update_flags.bits.color_space_change || 1442 plane_state->update_flags.bits.coeff_reduction_change) { 1443 struct dc_bias_and_scale bns_params = {0}; 1444 1445 // program the input csc 1446 dpp->funcs->dpp_setup(dpp, 1447 plane_state->format, 1448 EXPANSION_MODE_ZERO, 1449 plane_state->input_csc_color_matrix, 1450 plane_state->color_space, 1451 NULL); 1452 1453 if (dpp->funcs->dpp_program_bias_and_scale) { 1454 //TODO :for CNVC set scale and bias registers if necessary 1455 build_prescale_params(&bns_params, plane_state); 1456 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1457 } 1458 } 1459 1460 if (pipe_ctx->update_flags.bits.mpcc 1461 || pipe_ctx->update_flags.bits.plane_changed 1462 || plane_state->update_flags.bits.global_alpha_change 1463 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1464 // MPCC inst is equal to pipe index in practice 1465 int mpcc_inst = hubp->inst; 1466 int opp_inst; 1467 int opp_count = dc->res_pool->pipe_count; 1468 1469 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1470 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1471 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1472 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1473 break; 1474 } 1475 } 1476 hws->funcs.update_mpcc(dc, pipe_ctx); 1477 } 1478 1479 if (pipe_ctx->update_flags.bits.scaler || 1480 plane_state->update_flags.bits.scaling_change || 1481 plane_state->update_flags.bits.position_change || 1482 plane_state->update_flags.bits.per_pixel_alpha_change || 1483 pipe_ctx->stream->update_flags.bits.scaling) { 1484 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1485 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP); 1486 /* scaler configuration */ 1487 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1488 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1489 } 1490 1491 if (pipe_ctx->update_flags.bits.viewport || 1492 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1493 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1494 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1495 1496 hubp->funcs->mem_program_viewport( 1497 hubp, 1498 &pipe_ctx->plane_res.scl_data.viewport, 1499 &pipe_ctx->plane_res.scl_data.viewport_c); 1500 viewport_changed = true; 1501 } 1502 1503 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1504 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1505 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) && 1506 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1507 dc->hwss.set_cursor_position(pipe_ctx); 1508 dc->hwss.set_cursor_attribute(pipe_ctx); 1509 1510 if (dc->hwss.set_cursor_sdr_white_level) 1511 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1512 } 1513 1514 /* Any updates are handled in dc interface, just need 1515 * to apply existing for plane enable / opp change */ 1516 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1517 || pipe_ctx->stream->update_flags.bits.gamut_remap 1518 || pipe_ctx->stream->update_flags.bits.out_csc) { 1519 /* dpp/cm gamut remap*/ 1520 dc->hwss.program_gamut_remap(pipe_ctx); 1521 1522 /*call the dcn2 method which uses mpc csc*/ 1523 dc->hwss.program_output_csc(dc, 1524 pipe_ctx, 1525 pipe_ctx->stream->output_color_space, 1526 pipe_ctx->stream->csc_color_matrix.matrix, 1527 hubp->opp_id); 1528 } 1529 1530 if (pipe_ctx->update_flags.bits.enable || 1531 pipe_ctx->update_flags.bits.plane_changed || 1532 pipe_ctx->update_flags.bits.opp_changed || 1533 plane_state->update_flags.bits.pixel_format_change || 1534 plane_state->update_flags.bits.horizontal_mirror_change || 1535 plane_state->update_flags.bits.rotation_change || 1536 plane_state->update_flags.bits.swizzle_change || 1537 plane_state->update_flags.bits.dcc_change || 1538 plane_state->update_flags.bits.bpp_change || 1539 plane_state->update_flags.bits.scaling_change || 1540 plane_state->update_flags.bits.plane_size_change) { 1541 struct plane_size size = plane_state->plane_size; 1542 1543 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1544 hubp->funcs->hubp_program_surface_config( 1545 hubp, 1546 plane_state->format, 1547 &plane_state->tiling_info, 1548 &size, 1549 plane_state->rotation, 1550 &plane_state->dcc, 1551 plane_state->horizontal_mirror, 1552 0); 1553 hubp->power_gated = false; 1554 } 1555 1556 if (pipe_ctx->update_flags.bits.enable || 1557 pipe_ctx->update_flags.bits.plane_changed || 1558 plane_state->update_flags.bits.addr_update) 1559 hws->funcs.update_plane_addr(dc, pipe_ctx); 1560 1561 1562 1563 if (pipe_ctx->update_flags.bits.enable) 1564 hubp->funcs->set_blank(hubp, false); 1565 } 1566 1567 1568 static void dcn20_program_pipe( 1569 struct dc *dc, 1570 struct pipe_ctx *pipe_ctx, 1571 struct dc_state *context) 1572 { 1573 struct dce_hwseq *hws = dc->hwseq; 1574 /* Only need to unblank on top pipe */ 1575 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1576 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1577 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1578 1579 /* Only update TG on top pipe */ 1580 if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe 1581 && !pipe_ctx->prev_odm_pipe) { 1582 1583 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1584 pipe_ctx->stream_res.tg, 1585 pipe_ctx->pipe_dlg_param.vready_offset, 1586 pipe_ctx->pipe_dlg_param.vstartup_start, 1587 pipe_ctx->pipe_dlg_param.vupdate_offset, 1588 pipe_ctx->pipe_dlg_param.vupdate_width); 1589 1590 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 1591 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 1592 1593 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1594 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true); 1595 1596 if (hws->funcs.setup_vupdate_interrupt) 1597 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1598 } 1599 1600 if (pipe_ctx->update_flags.bits.odm) 1601 hws->funcs.update_odm(dc, context, pipe_ctx); 1602 1603 if (pipe_ctx->update_flags.bits.enable) { 1604 dcn20_enable_plane(dc, pipe_ctx, context); 1605 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1606 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1607 } 1608 1609 if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) 1610 dc->res_pool->hubbub->funcs->program_det_size( 1611 dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); 1612 1613 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1614 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1615 1616 if (pipe_ctx->update_flags.bits.enable 1617 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1618 hws->funcs.set_hdr_multiplier(pipe_ctx); 1619 1620 if (pipe_ctx->update_flags.bits.enable || 1621 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1622 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1623 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1624 1625 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1626 * only do gamma programming for powering on, internal memcmp to avoid 1627 * updating on slave planes 1628 */ 1629 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1630 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1631 1632 /* If the pipe has been enabled or has a different opp, we 1633 * should reprogram the fmt. This deals with cases where 1634 * interation between mpc and odm combine on different streams 1635 * causes a different pipe to be chosen to odm combine with. 1636 */ 1637 if (pipe_ctx->update_flags.bits.enable 1638 || pipe_ctx->update_flags.bits.opp_changed) { 1639 1640 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1641 pipe_ctx->stream_res.opp, 1642 COLOR_SPACE_YCBCR601, 1643 pipe_ctx->stream->timing.display_color_depth, 1644 pipe_ctx->stream->signal); 1645 1646 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1647 pipe_ctx->stream_res.opp, 1648 &pipe_ctx->stream->bit_depth_params, 1649 &pipe_ctx->stream->clamping); 1650 } 1651 } 1652 1653 void dcn20_program_front_end_for_ctx( 1654 struct dc *dc, 1655 struct dc_state *context) 1656 { 1657 int i; 1658 struct dce_hwseq *hws = dc->hwseq; 1659 DC_LOGGER_INIT(dc->ctx->logger); 1660 1661 /* Carry over GSL groups in case the context is changing. */ 1662 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1663 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1664 struct pipe_ctx *old_pipe_ctx = 1665 &dc->current_state->res_ctx.pipe_ctx[i]; 1666 1667 if (pipe_ctx->stream == old_pipe_ctx->stream) 1668 pipe_ctx->stream_res.gsl_group = 1669 old_pipe_ctx->stream_res.gsl_group; 1670 } 1671 1672 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { 1673 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1674 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1675 1676 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1677 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1678 /*turn off triple buffer for full update*/ 1679 dc->hwss.program_triplebuffer( 1680 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1681 } 1682 } 1683 } 1684 1685 /* Set pipe update flags and lock pipes */ 1686 for (i = 0; i < dc->res_pool->pipe_count; i++) 1687 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1688 &context->res_ctx.pipe_ctx[i]); 1689 1690 /* OTG blank before disabling all front ends */ 1691 for (i = 0; i < dc->res_pool->pipe_count; i++) 1692 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1693 && !context->res_ctx.pipe_ctx[i].top_pipe 1694 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1695 && context->res_ctx.pipe_ctx[i].stream) 1696 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1697 1698 1699 /* Disconnect mpcc */ 1700 for (i = 0; i < dc->res_pool->pipe_count; i++) 1701 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1702 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1703 struct hubbub *hubbub = dc->res_pool->hubbub; 1704 1705 if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1706 hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); 1707 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1708 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1709 } 1710 1711 /* 1712 * Program all updated pipes, order matters for mpcc setup. Start with 1713 * top pipe and program all pipes that follow in order 1714 */ 1715 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1716 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1717 1718 if (pipe->plane_state && !pipe->top_pipe) { 1719 while (pipe) { 1720 if (hws->funcs.program_pipe) 1721 hws->funcs.program_pipe(dc, pipe, context); 1722 else 1723 dcn20_program_pipe(dc, pipe, context); 1724 1725 pipe = pipe->bottom_pipe; 1726 } 1727 } 1728 /* Program secondary blending tree and writeback pipes */ 1729 pipe = &context->res_ctx.pipe_ctx[i]; 1730 if (!pipe->top_pipe && !pipe->prev_odm_pipe 1731 && pipe->stream && pipe->stream->num_wb_info > 0 1732 && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) 1733 || pipe->stream->update_flags.raw) 1734 && hws->funcs.program_all_writeback_pipes_in_tree) 1735 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1736 } 1737 } 1738 1739 void dcn20_post_unlock_program_front_end( 1740 struct dc *dc, 1741 struct dc_state *context) 1742 { 1743 int i; 1744 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1745 struct dce_hwseq *hwseq = dc->hwseq; 1746 1747 DC_LOGGER_INIT(dc->ctx->logger); 1748 1749 for (i = 0; i < dc->res_pool->pipe_count; i++) 1750 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1751 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1752 1753 /* 1754 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1755 * part of the enable operation otherwise, DM may request an immediate flip which 1756 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1757 * is unsupported on DCN. 1758 */ 1759 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1760 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1761 1762 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1763 struct hubp *hubp = pipe->plane_res.hubp; 1764 int j = 0; 1765 1766 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1767 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1768 mdelay(1); 1769 } 1770 } 1771 1772 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1773 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1774 struct pipe_ctx *mpcc_pipe; 1775 1776 if (pipe->vtp_locked) { 1777 dc->hwseq->funcs.wait_for_blank_complete(pipe->stream_res.opp); 1778 pipe->plane_res.hubp->funcs->set_blank(pipe->plane_res.hubp, true); 1779 pipe->vtp_locked = false; 1780 1781 for (mpcc_pipe = pipe->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) 1782 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); 1783 1784 for (i = 0; i < dc->res_pool->pipe_count; i++) 1785 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1786 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1787 } 1788 } 1789 /* WA to apply WM setting*/ 1790 if (hwseq->wa.DEGVIDCN21) 1791 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1792 1793 1794 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1795 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1796 1797 if (dc->current_state->stream_status[0].plane_count == 1 && 1798 context->stream_status[0].plane_count > 1) { 1799 1800 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1801 1802 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1803 1804 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1805 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1806 } 1807 } 1808 } 1809 1810 void dcn20_prepare_bandwidth( 1811 struct dc *dc, 1812 struct dc_state *context) 1813 { 1814 struct hubbub *hubbub = dc->res_pool->hubbub; 1815 1816 dc->clk_mgr->funcs->update_clocks( 1817 dc->clk_mgr, 1818 context, 1819 false); 1820 1821 /* program dchubbub watermarks */ 1822 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 1823 &context->bw_ctx.bw.dcn.watermarks, 1824 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1825 false); 1826 /* decrease compbuf size */ 1827 if (hubbub->funcs->program_compbuf_size) 1828 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false); 1829 } 1830 1831 void dcn20_optimize_bandwidth( 1832 struct dc *dc, 1833 struct dc_state *context) 1834 { 1835 struct hubbub *hubbub = dc->res_pool->hubbub; 1836 1837 /* program dchubbub watermarks */ 1838 hubbub->funcs->program_watermarks(hubbub, 1839 &context->bw_ctx.bw.dcn.watermarks, 1840 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1841 true); 1842 1843 dc->clk_mgr->funcs->update_clocks( 1844 dc->clk_mgr, 1845 context, 1846 true); 1847 /* increase compbuf size */ 1848 if (hubbub->funcs->program_compbuf_size) 1849 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); 1850 } 1851 1852 bool dcn20_update_bandwidth( 1853 struct dc *dc, 1854 struct dc_state *context) 1855 { 1856 int i; 1857 struct dce_hwseq *hws = dc->hwseq; 1858 1859 /* recalculate DML parameters */ 1860 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1861 return false; 1862 1863 /* apply updated bandwidth parameters */ 1864 dc->hwss.prepare_bandwidth(dc, context); 1865 1866 /* update hubp configs for all pipes */ 1867 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1868 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1869 1870 if (pipe_ctx->plane_state == NULL) 1871 continue; 1872 1873 if (pipe_ctx->top_pipe == NULL) { 1874 bool blank = !is_pipe_tree_visible(pipe_ctx); 1875 1876 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1877 pipe_ctx->stream_res.tg, 1878 pipe_ctx->pipe_dlg_param.vready_offset, 1879 pipe_ctx->pipe_dlg_param.vstartup_start, 1880 pipe_ctx->pipe_dlg_param.vupdate_offset, 1881 pipe_ctx->pipe_dlg_param.vupdate_width); 1882 1883 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1884 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false); 1885 1886 if (pipe_ctx->prev_odm_pipe == NULL) 1887 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 1888 1889 if (hws->funcs.setup_vupdate_interrupt) 1890 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1891 } 1892 1893 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1894 pipe_ctx->plane_res.hubp, 1895 &pipe_ctx->dlg_regs, 1896 &pipe_ctx->ttu_regs, 1897 &pipe_ctx->rq_regs, 1898 &pipe_ctx->pipe_dlg_param); 1899 } 1900 1901 return true; 1902 } 1903 1904 void dcn20_enable_writeback( 1905 struct dc *dc, 1906 struct dc_writeback_info *wb_info, 1907 struct dc_state *context) 1908 { 1909 struct dwbc *dwb; 1910 struct mcif_wb *mcif_wb; 1911 struct timing_generator *optc; 1912 1913 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1914 ASSERT(wb_info->wb_enabled); 1915 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1916 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1917 1918 /* set the OPTC source mux */ 1919 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 1920 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1921 /* set MCIF_WB buffer and arbitration configuration */ 1922 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1923 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1924 /* Enable MCIF_WB */ 1925 mcif_wb->funcs->enable_mcif(mcif_wb); 1926 /* Enable DWB */ 1927 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1928 /* TODO: add sequence to enable/disable warmup */ 1929 } 1930 1931 void dcn20_disable_writeback( 1932 struct dc *dc, 1933 unsigned int dwb_pipe_inst) 1934 { 1935 struct dwbc *dwb; 1936 struct mcif_wb *mcif_wb; 1937 1938 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1939 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1940 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1941 1942 dwb->funcs->disable(dwb); 1943 mcif_wb->funcs->disable_mcif(mcif_wb); 1944 } 1945 1946 bool dcn20_wait_for_blank_complete( 1947 struct output_pixel_processor *opp) 1948 { 1949 int counter; 1950 1951 for (counter = 0; counter < 1000; counter++) { 1952 if (opp->funcs->dpg_is_blanked(opp)) 1953 break; 1954 1955 udelay(100); 1956 } 1957 1958 if (counter == 1000) { 1959 dm_error("DC: failed to blank crtc!\n"); 1960 return false; 1961 } 1962 1963 return true; 1964 } 1965 1966 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1967 { 1968 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1969 1970 if (!hubp) 1971 return false; 1972 return hubp->funcs->dmdata_status_done(hubp); 1973 } 1974 1975 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1976 { 1977 struct dce_hwseq *hws = dc->hwseq; 1978 1979 if (pipe_ctx->stream_res.dsc) { 1980 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1981 1982 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1983 while (odm_pipe) { 1984 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 1985 odm_pipe = odm_pipe->next_odm_pipe; 1986 } 1987 } 1988 } 1989 1990 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1991 { 1992 struct dce_hwseq *hws = dc->hwseq; 1993 1994 if (pipe_ctx->stream_res.dsc) { 1995 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1996 1997 hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 1998 while (odm_pipe) { 1999 hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 2000 odm_pipe = odm_pipe->next_odm_pipe; 2001 } 2002 } 2003 } 2004 2005 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 2006 { 2007 struct dc_dmdata_attributes attr = { 0 }; 2008 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2009 2010 attr.dmdata_mode = DMDATA_HW_MODE; 2011 attr.dmdata_size = 2012 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 2013 attr.address.quad_part = 2014 pipe_ctx->stream->dmdata_address.quad_part; 2015 attr.dmdata_dl_delta = 0; 2016 attr.dmdata_qos_mode = 0; 2017 attr.dmdata_qos_level = 0; 2018 attr.dmdata_repeat = 1; /* always repeat */ 2019 attr.dmdata_updated = 1; 2020 attr.dmdata_sw_data = NULL; 2021 2022 hubp->funcs->dmdata_set_attributes(hubp, &attr); 2023 } 2024 2025 void dcn20_init_vm_ctx( 2026 struct dce_hwseq *hws, 2027 struct dc *dc, 2028 struct dc_virtual_addr_space_config *va_config, 2029 int vmid) 2030 { 2031 struct dcn_hubbub_virt_addr_config config; 2032 2033 if (vmid == 0) { 2034 ASSERT(0); /* VMID cannot be 0 for vm context */ 2035 return; 2036 } 2037 2038 config.page_table_start_addr = va_config->page_table_start_addr; 2039 config.page_table_end_addr = va_config->page_table_end_addr; 2040 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 2041 config.page_table_depth = va_config->page_table_depth; 2042 config.page_table_base_addr = va_config->page_table_base_addr; 2043 2044 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 2045 } 2046 2047 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 2048 { 2049 struct dcn_hubbub_phys_addr_config config; 2050 2051 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 2052 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 2053 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 2054 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 2055 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 2056 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 2057 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 2058 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 2059 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 2060 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 2061 2062 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 2063 } 2064 2065 static bool patch_address_for_sbs_tb_stereo( 2066 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 2067 { 2068 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2069 bool sec_split = pipe_ctx->top_pipe && 2070 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 2071 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2072 (pipe_ctx->stream->timing.timing_3d_format == 2073 TIMING_3D_FORMAT_SIDE_BY_SIDE || 2074 pipe_ctx->stream->timing.timing_3d_format == 2075 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 2076 *addr = plane_state->address.grph_stereo.left_addr; 2077 plane_state->address.grph_stereo.left_addr = 2078 plane_state->address.grph_stereo.right_addr; 2079 return true; 2080 } 2081 2082 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 2083 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 2084 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 2085 plane_state->address.grph_stereo.right_addr = 2086 plane_state->address.grph_stereo.left_addr; 2087 plane_state->address.grph_stereo.right_meta_addr = 2088 plane_state->address.grph_stereo.left_meta_addr; 2089 } 2090 return false; 2091 } 2092 2093 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 2094 { 2095 bool addr_patched = false; 2096 PHYSICAL_ADDRESS_LOC addr; 2097 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2098 2099 if (plane_state == NULL) 2100 return; 2101 2102 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 2103 2104 // Call Helper to track VMID use 2105 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 2106 2107 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 2108 pipe_ctx->plane_res.hubp, 2109 &plane_state->address, 2110 plane_state->flip_immediate); 2111 2112 plane_state->status.requested_address = plane_state->address; 2113 2114 if (plane_state->flip_immediate) 2115 plane_state->status.current_address = plane_state->address; 2116 2117 if (addr_patched) 2118 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 2119 } 2120 2121 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 2122 struct dc_link_settings *link_settings) 2123 { 2124 struct encoder_unblank_param params = {0}; 2125 struct dc_stream_state *stream = pipe_ctx->stream; 2126 struct dc_link *link = stream->link; 2127 struct dce_hwseq *hws = link->dc->hwseq; 2128 struct pipe_ctx *odm_pipe; 2129 2130 params.opp_cnt = 1; 2131 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 2132 params.opp_cnt++; 2133 } 2134 /* only 3 items below are used by unblank */ 2135 params.timing = pipe_ctx->stream->timing; 2136 2137 params.link_settings.link_rate = link_settings->link_rate; 2138 2139 if (is_dp_128b_132b_signal(pipe_ctx)) { 2140 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 2141 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( 2142 pipe_ctx->stream_res.hpo_dp_stream_enc, 2143 pipe_ctx->stream_res.tg->inst); 2144 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 2145 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 2146 params.timing.pix_clk_100hz /= 2; 2147 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 2148 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 2149 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 2150 } 2151 2152 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 2153 hws->funcs.edp_backlight_control(link, true); 2154 } 2155 } 2156 2157 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 2158 { 2159 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2160 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 2161 2162 if (start_line < 0) 2163 start_line = 0; 2164 2165 if (tg->funcs->setup_vertical_interrupt2) 2166 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2167 } 2168 2169 static void dcn20_reset_back_end_for_pipe( 2170 struct dc *dc, 2171 struct pipe_ctx *pipe_ctx, 2172 struct dc_state *context) 2173 { 2174 int i; 2175 struct dc_link *link; 2176 DC_LOGGER_INIT(dc->ctx->logger); 2177 if (pipe_ctx->stream_res.stream_enc == NULL) { 2178 pipe_ctx->stream = NULL; 2179 return; 2180 } 2181 2182 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2183 link = pipe_ctx->stream->link; 2184 /* DPMS may already disable or */ 2185 /* dpms_off status is incorrect due to fastboot 2186 * feature. When system resume from S4 with second 2187 * screen only, the dpms_off would be true but 2188 * VBIOS lit up eDP, so check link status too. 2189 */ 2190 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2191 core_link_disable_stream(pipe_ctx); 2192 else if (pipe_ctx->stream_res.audio) 2193 dc->hwss.disable_audio_stream(pipe_ctx); 2194 2195 /* free acquired resources */ 2196 if (pipe_ctx->stream_res.audio) { 2197 /*disable az_endpoint*/ 2198 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2199 2200 /*free audio*/ 2201 if (dc->caps.dynamic_audio == true) { 2202 /*we have to dynamic arbitrate the audio endpoints*/ 2203 /*we free the resource, need reset is_audio_acquired*/ 2204 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2205 pipe_ctx->stream_res.audio, false); 2206 pipe_ctx->stream_res.audio = NULL; 2207 } 2208 } 2209 } 2210 else if (pipe_ctx->stream_res.dsc) { 2211 dp_set_dsc_enable(pipe_ctx, false); 2212 } 2213 2214 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2215 * back end share by all pipes and will be disable only when disable 2216 * parent pipe. 2217 */ 2218 if (pipe_ctx->top_pipe == NULL) { 2219 2220 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2221 2222 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2223 2224 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2225 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2226 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2227 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2228 2229 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2230 pipe_ctx->stream_res.tg->funcs->set_drr( 2231 pipe_ctx->stream_res.tg, NULL); 2232 } 2233 2234 for (i = 0; i < dc->res_pool->pipe_count; i++) 2235 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2236 break; 2237 2238 if (i == dc->res_pool->pipe_count) 2239 return; 2240 2241 pipe_ctx->stream = NULL; 2242 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2243 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2244 } 2245 2246 void dcn20_reset_hw_ctx_wrap( 2247 struct dc *dc, 2248 struct dc_state *context) 2249 { 2250 int i; 2251 struct dce_hwseq *hws = dc->hwseq; 2252 2253 /* Reset Back End*/ 2254 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2255 struct pipe_ctx *pipe_ctx_old = 2256 &dc->current_state->res_ctx.pipe_ctx[i]; 2257 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2258 2259 if (!pipe_ctx_old->stream) 2260 continue; 2261 2262 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2263 continue; 2264 2265 if (!pipe_ctx->stream || 2266 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2267 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2268 2269 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2270 if (hws->funcs.enable_stream_gating) 2271 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 2272 if (old_clk) 2273 old_clk->funcs->cs_power_down(old_clk); 2274 } 2275 } 2276 } 2277 2278 void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) 2279 { 2280 struct mpc *mpc = dc->res_pool->mpc; 2281 2282 // input to MPCC is always RGB, by default leave black_color at 0 2283 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) 2284 get_hdr_visual_confirm_color(pipe_ctx, color); 2285 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 2286 get_surface_visual_confirm_color(pipe_ctx, color); 2287 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) 2288 get_mpctree_visual_confirm_color(pipe_ctx, color); 2289 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) 2290 get_surface_tile_visual_confirm_color(pipe_ctx, color); 2291 2292 if (mpc->funcs->set_bg_color) 2293 mpc->funcs->set_bg_color(mpc, color, mpcc_id); 2294 } 2295 2296 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2297 { 2298 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2299 struct mpcc_blnd_cfg blnd_cfg = {0}; 2300 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2301 int mpcc_id; 2302 struct mpcc *new_mpcc; 2303 struct mpc *mpc = dc->res_pool->mpc; 2304 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2305 2306 if (per_pixel_alpha) 2307 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2308 else 2309 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2310 2311 blnd_cfg.overlap_only = false; 2312 blnd_cfg.global_gain = 0xff; 2313 2314 if (pipe_ctx->plane_state->global_alpha) 2315 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2316 else 2317 blnd_cfg.global_alpha = 0xff; 2318 2319 blnd_cfg.background_color_bpc = 4; 2320 blnd_cfg.bottom_gain_mode = 0; 2321 blnd_cfg.top_gain = 0x1f000; 2322 blnd_cfg.bottom_inside_gain = 0x1f000; 2323 blnd_cfg.bottom_outside_gain = 0x1f000; 2324 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 2325 if (pipe_ctx->plane_state->format 2326 == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) 2327 blnd_cfg.pre_multiplied_alpha = false; 2328 2329 /* 2330 * TODO: remove hack 2331 * Note: currently there is a bug in init_hw such that 2332 * on resume from hibernate, BIOS sets up MPCC0, and 2333 * we do mpcc_remove but the mpcc cannot go to idle 2334 * after remove. This cause us to pick mpcc1 here, 2335 * which causes a pstate hang for yet unknown reason. 2336 */ 2337 mpcc_id = hubp->inst; 2338 2339 /* If there is no full update, don't need to touch MPC tree*/ 2340 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2341 !pipe_ctx->update_flags.bits.mpcc) { 2342 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2343 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2344 return; 2345 } 2346 2347 /* check if this MPCC is already being used */ 2348 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2349 /* remove MPCC if being used */ 2350 if (new_mpcc != NULL) 2351 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2352 else 2353 if (dc->debug.sanity_checks) 2354 mpc->funcs->assert_mpcc_idle_before_connect( 2355 dc->res_pool->mpc, mpcc_id); 2356 2357 /* Call MPC to insert new plane */ 2358 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2359 mpc_tree_params, 2360 &blnd_cfg, 2361 NULL, 2362 NULL, 2363 hubp->inst, 2364 mpcc_id); 2365 dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); 2366 2367 ASSERT(new_mpcc != NULL); 2368 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2369 hubp->mpcc_id = mpcc_id; 2370 } 2371 2372 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2373 { 2374 enum dc_lane_count lane_count = 2375 pipe_ctx->stream->link->cur_link_settings.lane_count; 2376 2377 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2378 struct dc_link *link = pipe_ctx->stream->link; 2379 2380 uint32_t active_total_with_borders; 2381 uint32_t early_control = 0; 2382 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2383 struct link_encoder *link_enc; 2384 2385 if (link->is_dig_mapping_flexible && 2386 link->dc->res_pool->funcs->link_encs_assign) 2387 link_enc = link_enc_cfg_get_link_enc_used_by_stream(link->ctx->dc, pipe_ctx->stream); 2388 else 2389 link_enc = link->link_enc; 2390 ASSERT(link_enc); 2391 2392 /* For MST, there are multiply stream go to only one link. 2393 * connect DIG back_end to front_end while enable_stream and 2394 * disconnect them during disable_stream 2395 * BY this, it is logic clean to separate stream and link 2396 */ 2397 if (is_dp_128b_132b_signal(pipe_ctx)) { 2398 if (pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control) 2399 pipe_ctx->stream->ctx->dc->hwseq->funcs.setup_hpo_hw_control( 2400 pipe_ctx->stream->ctx->dc->hwseq, true); 2401 setup_dp_hpo_stream(pipe_ctx, true); 2402 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->enable_stream( 2403 pipe_ctx->stream_res.hpo_dp_stream_enc); 2404 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->map_stream_to_link( 2405 pipe_ctx->stream_res.hpo_dp_stream_enc, 2406 pipe_ctx->stream_res.hpo_dp_stream_enc->inst, 2407 link->hpo_dp_link_enc->inst); 2408 } 2409 2410 if (!is_dp_128b_132b_signal(pipe_ctx) && link_enc) 2411 link_enc->funcs->connect_dig_be_to_fe( 2412 link_enc, pipe_ctx->stream_res.stream_enc->id, true); 2413 2414 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2415 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE); 2416 2417 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2418 if (link->dc->hwss.program_dmdata_engine) 2419 link->dc->hwss.program_dmdata_engine(pipe_ctx); 2420 } 2421 2422 link->dc->hwss.update_info_frame(pipe_ctx); 2423 2424 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2425 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2426 2427 /* enable early control to avoid corruption on DP monitor*/ 2428 active_total_with_borders = 2429 timing->h_addressable 2430 + timing->h_border_left 2431 + timing->h_border_right; 2432 2433 if (lane_count != 0) 2434 early_control = active_total_with_borders % lane_count; 2435 2436 if (early_control == 0) 2437 early_control = lane_count; 2438 2439 tg->funcs->set_early_control(tg, early_control); 2440 2441 /* enable audio only within mode set */ 2442 if (pipe_ctx->stream_res.audio != NULL) { 2443 if (is_dp_128b_132b_signal(pipe_ctx)) 2444 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc); 2445 else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2446 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2447 } 2448 } 2449 2450 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2451 { 2452 struct dc_stream_state *stream = pipe_ctx->stream; 2453 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2454 bool enable = false; 2455 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2456 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2457 ? dmdata_dp 2458 : dmdata_hdmi; 2459 2460 /* if using dynamic meta, don't set up generic infopackets */ 2461 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2462 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2463 enable = true; 2464 } 2465 2466 if (!hubp) 2467 return; 2468 2469 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2470 return; 2471 2472 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2473 hubp->inst, mode); 2474 } 2475 2476 void dcn20_fpga_init_hw(struct dc *dc) 2477 { 2478 int i, j; 2479 struct dce_hwseq *hws = dc->hwseq; 2480 struct resource_pool *res_pool = dc->res_pool; 2481 struct dc_state *context = dc->current_state; 2482 2483 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2484 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2485 2486 // Initialize the dccg 2487 if (res_pool->dccg->funcs->dccg_init) 2488 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2489 2490 //Enable ability to power gate / don't force power on permanently 2491 hws->funcs.enable_power_gating_plane(hws, true); 2492 2493 // Specific to FPGA dccg and registers 2494 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2495 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2496 2497 hws->funcs.dccg_init(hws); 2498 2499 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2500 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2501 if (REG(REFCLK_CNTL)) 2502 REG_WRITE(REFCLK_CNTL, 0); 2503 // 2504 2505 2506 /* Blank pixel data with OPP DPG */ 2507 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2508 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2509 2510 if (tg->funcs->is_tg_enabled(tg)) 2511 dcn20_init_blank(dc, tg); 2512 } 2513 2514 for (i = 0; i < res_pool->timing_generator_count; i++) { 2515 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2516 2517 if (tg->funcs->is_tg_enabled(tg)) 2518 tg->funcs->lock(tg); 2519 } 2520 2521 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2522 struct dpp *dpp = res_pool->dpps[i]; 2523 2524 dpp->funcs->dpp_reset(dpp); 2525 } 2526 2527 /* Reset all MPCC muxes */ 2528 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2529 2530 /* initialize OPP mpc_tree parameter */ 2531 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2532 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2533 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2534 for (j = 0; j < MAX_PIPES; j++) 2535 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2536 } 2537 2538 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2539 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2540 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2541 struct hubp *hubp = dc->res_pool->hubps[i]; 2542 struct dpp *dpp = dc->res_pool->dpps[i]; 2543 2544 pipe_ctx->stream_res.tg = tg; 2545 pipe_ctx->pipe_idx = i; 2546 2547 pipe_ctx->plane_res.hubp = hubp; 2548 pipe_ctx->plane_res.dpp = dpp; 2549 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2550 hubp->mpcc_id = dpp->inst; 2551 hubp->opp_id = OPP_ID_INVALID; 2552 hubp->power_gated = false; 2553 pipe_ctx->stream_res.opp = NULL; 2554 2555 hubp->funcs->hubp_init(hubp); 2556 2557 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2558 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2559 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2560 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2561 /*to do*/ 2562 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2563 } 2564 2565 /* initialize DWB pointer to MCIF_WB */ 2566 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2567 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2568 2569 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2570 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2571 2572 if (tg->funcs->is_tg_enabled(tg)) 2573 tg->funcs->unlock(tg); 2574 } 2575 2576 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2577 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2578 2579 dc->hwss.disable_plane(dc, pipe_ctx); 2580 2581 pipe_ctx->stream_res.tg = NULL; 2582 pipe_ctx->plane_res.hubp = NULL; 2583 } 2584 2585 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2586 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2587 2588 tg->funcs->tg_init(tg); 2589 } 2590 2591 if (dc->res_pool->hubbub->funcs->init_crb) 2592 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2593 } 2594 #ifndef TRIM_FSFT 2595 bool dcn20_optimize_timing_for_fsft(struct dc *dc, 2596 struct dc_crtc_timing *timing, 2597 unsigned int max_input_rate_in_khz) 2598 { 2599 unsigned int old_v_front_porch; 2600 unsigned int old_v_total; 2601 unsigned int max_input_rate_in_100hz; 2602 unsigned long long new_v_total; 2603 2604 max_input_rate_in_100hz = max_input_rate_in_khz * 10; 2605 if (max_input_rate_in_100hz < timing->pix_clk_100hz) 2606 return false; 2607 2608 old_v_total = timing->v_total; 2609 old_v_front_porch = timing->v_front_porch; 2610 2611 timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; 2612 timing->pix_clk_100hz = max_input_rate_in_100hz; 2613 2614 new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); 2615 2616 timing->v_total = new_v_total; 2617 timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); 2618 return true; 2619 } 2620 #endif 2621 2622 void dcn20_set_disp_pattern_generator(const struct dc *dc, 2623 struct pipe_ctx *pipe_ctx, 2624 enum controller_dp_test_pattern test_pattern, 2625 enum controller_dp_color_space color_space, 2626 enum dc_color_depth color_depth, 2627 const struct tg_color *solid_color, 2628 int width, int height, int offset) 2629 { 2630 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 2631 color_space, color_depth, solid_color, width, height, offset); 2632 } 2633