1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 53 #define DC_LOGGER_INIT(logger) 54 55 #define CTX \ 56 hws->ctx 57 #define REG(reg)\ 58 hws->regs->reg 59 60 #undef FN 61 #define FN(reg_name, field_name) \ 62 hws->shifts->field_name, hws->masks->field_name 63 64 static int find_free_gsl_group(const struct dc *dc) 65 { 66 if (dc->res_pool->gsl_groups.gsl_0 == 0) 67 return 1; 68 if (dc->res_pool->gsl_groups.gsl_1 == 0) 69 return 2; 70 if (dc->res_pool->gsl_groups.gsl_2 == 0) 71 return 3; 72 73 return 0; 74 } 75 76 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 77 * This is only used to lock pipes in pipe splitting case with immediate flip 78 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 79 * so we get tearing with freesync since we cannot flip multiple pipes 80 * atomically. 81 * We use GSL for this: 82 * - immediate flip: find first available GSL group if not already assigned 83 * program gsl with that group, set current OTG as master 84 * and always us 0x4 = AND of flip_ready from all pipes 85 * - vsync flip: disable GSL if used 86 * 87 * Groups in stream_res are stored as +1 from HW registers, i.e. 88 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 89 * Using a magic value like -1 would require tracking all inits/resets 90 */ 91 static void dcn20_setup_gsl_group_as_lock( 92 const struct dc *dc, 93 struct pipe_ctx *pipe_ctx, 94 bool enable) 95 { 96 struct gsl_params gsl; 97 int group_idx; 98 99 memset(&gsl, 0, sizeof(struct gsl_params)); 100 101 if (enable) { 102 /* return if group already assigned since GSL was set up 103 * for vsync flip, we would unassign so it can't be "left over" 104 */ 105 if (pipe_ctx->stream_res.gsl_group > 0) 106 return; 107 108 group_idx = find_free_gsl_group(dc); 109 ASSERT(group_idx != 0); 110 pipe_ctx->stream_res.gsl_group = group_idx; 111 112 /* set gsl group reg field and mark resource used */ 113 switch (group_idx) { 114 case 1: 115 gsl.gsl0_en = 1; 116 dc->res_pool->gsl_groups.gsl_0 = 1; 117 break; 118 case 2: 119 gsl.gsl1_en = 1; 120 dc->res_pool->gsl_groups.gsl_1 = 1; 121 break; 122 case 3: 123 gsl.gsl2_en = 1; 124 dc->res_pool->gsl_groups.gsl_2 = 1; 125 break; 126 default: 127 BREAK_TO_DEBUGGER(); 128 return; // invalid case 129 } 130 gsl.gsl_master_en = 1; 131 } else { 132 group_idx = pipe_ctx->stream_res.gsl_group; 133 if (group_idx == 0) 134 return; // if not in use, just return 135 136 pipe_ctx->stream_res.gsl_group = 0; 137 138 /* unset gsl group reg field and mark resource free */ 139 switch (group_idx) { 140 case 1: 141 gsl.gsl0_en = 0; 142 dc->res_pool->gsl_groups.gsl_0 = 0; 143 break; 144 case 2: 145 gsl.gsl1_en = 0; 146 dc->res_pool->gsl_groups.gsl_1 = 0; 147 break; 148 case 3: 149 gsl.gsl2_en = 0; 150 dc->res_pool->gsl_groups.gsl_2 = 0; 151 break; 152 default: 153 BREAK_TO_DEBUGGER(); 154 return; 155 } 156 gsl.gsl_master_en = 0; 157 } 158 159 /* at this point we want to program whether it's to enable or disable */ 160 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 161 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 162 pipe_ctx->stream_res.tg->funcs->set_gsl( 163 pipe_ctx->stream_res.tg, 164 &gsl); 165 166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 167 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 168 } else 169 BREAK_TO_DEBUGGER(); 170 } 171 172 void dcn20_set_flip_control_gsl( 173 struct pipe_ctx *pipe_ctx, 174 bool flip_immediate) 175 { 176 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 177 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 178 pipe_ctx->plane_res.hubp, flip_immediate); 179 180 } 181 182 void dcn20_enable_power_gating_plane( 183 struct dce_hwseq *hws, 184 bool enable) 185 { 186 bool force_on = true; /* disable power gating */ 187 188 if (enable) 189 force_on = false; 190 191 /* DCHUBP0/1/2/3/4/5 */ 192 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 193 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 194 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 195 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 196 if (REG(DOMAIN8_PG_CONFIG)) 197 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 198 if (REG(DOMAIN10_PG_CONFIG)) 199 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 200 201 /* DPP0/1/2/3/4/5 */ 202 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 203 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 204 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 205 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 206 if (REG(DOMAIN9_PG_CONFIG)) 207 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 208 if (REG(DOMAIN11_PG_CONFIG)) 209 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 210 211 /* DCS0/1/2/3/4/5 */ 212 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 213 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 214 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 215 if (REG(DOMAIN19_PG_CONFIG)) 216 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 217 if (REG(DOMAIN20_PG_CONFIG)) 218 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 219 if (REG(DOMAIN21_PG_CONFIG)) 220 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 221 } 222 223 void dcn20_dccg_init(struct dce_hwseq *hws) 224 { 225 /* 226 * set MICROSECOND_TIME_BASE_DIV 227 * 100Mhz refclk -> 0x120264 228 * 27Mhz refclk -> 0x12021b 229 * 48Mhz refclk -> 0x120230 230 * 231 */ 232 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 233 234 /* 235 * set MILLISECOND_TIME_BASE_DIV 236 * 100Mhz refclk -> 0x1186a0 237 * 27Mhz refclk -> 0x106978 238 * 48Mhz refclk -> 0x10bb80 239 * 240 */ 241 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 242 243 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 244 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); 245 } 246 247 void dcn20_disable_vga( 248 struct dce_hwseq *hws) 249 { 250 REG_WRITE(D1VGA_CONTROL, 0); 251 REG_WRITE(D2VGA_CONTROL, 0); 252 REG_WRITE(D3VGA_CONTROL, 0); 253 REG_WRITE(D4VGA_CONTROL, 0); 254 REG_WRITE(D5VGA_CONTROL, 0); 255 REG_WRITE(D6VGA_CONTROL, 0); 256 } 257 258 void dcn20_program_triple_buffer( 259 const struct dc *dc, 260 struct pipe_ctx *pipe_ctx, 261 bool enable_triple_buffer) 262 { 263 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 264 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 265 pipe_ctx->plane_res.hubp, 266 enable_triple_buffer); 267 } 268 } 269 270 /* Blank pixel data during initialization */ 271 void dcn20_init_blank( 272 struct dc *dc, 273 struct timing_generator *tg) 274 { 275 struct dce_hwseq *hws = dc->hwseq; 276 enum dc_color_space color_space; 277 struct tg_color black_color = {0}; 278 struct output_pixel_processor *opp = NULL; 279 struct output_pixel_processor *bottom_opp = NULL; 280 uint32_t num_opps, opp_id_src0, opp_id_src1; 281 uint32_t otg_active_width, otg_active_height; 282 283 /* program opp dpg blank color */ 284 color_space = COLOR_SPACE_SRGB; 285 color_space_to_black_color(dc, color_space, &black_color); 286 287 /* get the OTG active size */ 288 tg->funcs->get_otg_active_size(tg, 289 &otg_active_width, 290 &otg_active_height); 291 292 /* get the OPTC source */ 293 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 294 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); 295 opp = dc->res_pool->opps[opp_id_src0]; 296 297 if (num_opps == 2) { 298 otg_active_width = otg_active_width / 2; 299 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp); 300 bottom_opp = dc->res_pool->opps[opp_id_src1]; 301 } 302 303 opp->funcs->opp_set_disp_pattern_generator( 304 opp, 305 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 306 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 307 COLOR_DEPTH_UNDEFINED, 308 &black_color, 309 otg_active_width, 310 otg_active_height, 311 0); 312 313 if (num_opps == 2) { 314 bottom_opp->funcs->opp_set_disp_pattern_generator( 315 bottom_opp, 316 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 317 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 318 COLOR_DEPTH_UNDEFINED, 319 &black_color, 320 otg_active_width, 321 otg_active_height, 322 0); 323 } 324 325 hws->funcs.wait_for_blank_complete(opp); 326 } 327 328 void dcn20_dsc_pg_control( 329 struct dce_hwseq *hws, 330 unsigned int dsc_inst, 331 bool power_on) 332 { 333 uint32_t power_gate = power_on ? 0 : 1; 334 uint32_t pwr_status = power_on ? 0 : 2; 335 uint32_t org_ip_request_cntl = 0; 336 337 if (hws->ctx->dc->debug.disable_dsc_power_gate) 338 return; 339 340 if (REG(DOMAIN16_PG_CONFIG) == 0) 341 return; 342 343 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 344 if (org_ip_request_cntl == 0) 345 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 346 347 switch (dsc_inst) { 348 case 0: /* DSC0 */ 349 REG_UPDATE(DOMAIN16_PG_CONFIG, 350 DOMAIN16_POWER_GATE, power_gate); 351 352 REG_WAIT(DOMAIN16_PG_STATUS, 353 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 354 1, 1000); 355 break; 356 case 1: /* DSC1 */ 357 REG_UPDATE(DOMAIN17_PG_CONFIG, 358 DOMAIN17_POWER_GATE, power_gate); 359 360 REG_WAIT(DOMAIN17_PG_STATUS, 361 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 362 1, 1000); 363 break; 364 case 2: /* DSC2 */ 365 REG_UPDATE(DOMAIN18_PG_CONFIG, 366 DOMAIN18_POWER_GATE, power_gate); 367 368 REG_WAIT(DOMAIN18_PG_STATUS, 369 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 370 1, 1000); 371 break; 372 case 3: /* DSC3 */ 373 REG_UPDATE(DOMAIN19_PG_CONFIG, 374 DOMAIN19_POWER_GATE, power_gate); 375 376 REG_WAIT(DOMAIN19_PG_STATUS, 377 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 378 1, 1000); 379 break; 380 case 4: /* DSC4 */ 381 REG_UPDATE(DOMAIN20_PG_CONFIG, 382 DOMAIN20_POWER_GATE, power_gate); 383 384 REG_WAIT(DOMAIN20_PG_STATUS, 385 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 386 1, 1000); 387 break; 388 case 5: /* DSC5 */ 389 REG_UPDATE(DOMAIN21_PG_CONFIG, 390 DOMAIN21_POWER_GATE, power_gate); 391 392 REG_WAIT(DOMAIN21_PG_STATUS, 393 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 394 1, 1000); 395 break; 396 default: 397 BREAK_TO_DEBUGGER(); 398 break; 399 } 400 401 if (org_ip_request_cntl == 0) 402 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 403 } 404 405 void dcn20_dpp_pg_control( 406 struct dce_hwseq *hws, 407 unsigned int dpp_inst, 408 bool power_on) 409 { 410 uint32_t power_gate = power_on ? 0 : 1; 411 uint32_t pwr_status = power_on ? 0 : 2; 412 413 if (hws->ctx->dc->debug.disable_dpp_power_gate) 414 return; 415 if (REG(DOMAIN1_PG_CONFIG) == 0) 416 return; 417 418 switch (dpp_inst) { 419 case 0: /* DPP0 */ 420 REG_UPDATE(DOMAIN1_PG_CONFIG, 421 DOMAIN1_POWER_GATE, power_gate); 422 423 REG_WAIT(DOMAIN1_PG_STATUS, 424 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 425 1, 1000); 426 break; 427 case 1: /* DPP1 */ 428 REG_UPDATE(DOMAIN3_PG_CONFIG, 429 DOMAIN3_POWER_GATE, power_gate); 430 431 REG_WAIT(DOMAIN3_PG_STATUS, 432 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 433 1, 1000); 434 break; 435 case 2: /* DPP2 */ 436 REG_UPDATE(DOMAIN5_PG_CONFIG, 437 DOMAIN5_POWER_GATE, power_gate); 438 439 REG_WAIT(DOMAIN5_PG_STATUS, 440 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 441 1, 1000); 442 break; 443 case 3: /* DPP3 */ 444 REG_UPDATE(DOMAIN7_PG_CONFIG, 445 DOMAIN7_POWER_GATE, power_gate); 446 447 REG_WAIT(DOMAIN7_PG_STATUS, 448 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 449 1, 1000); 450 break; 451 case 4: /* DPP4 */ 452 REG_UPDATE(DOMAIN9_PG_CONFIG, 453 DOMAIN9_POWER_GATE, power_gate); 454 455 REG_WAIT(DOMAIN9_PG_STATUS, 456 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 457 1, 1000); 458 break; 459 case 5: /* DPP5 */ 460 /* 461 * Do not power gate DPP5, should be left at HW default, power on permanently. 462 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 463 * reset. 464 * REG_UPDATE(DOMAIN11_PG_CONFIG, 465 * DOMAIN11_POWER_GATE, power_gate); 466 * 467 * REG_WAIT(DOMAIN11_PG_STATUS, 468 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 469 * 1, 1000); 470 */ 471 break; 472 default: 473 BREAK_TO_DEBUGGER(); 474 break; 475 } 476 } 477 478 479 void dcn20_hubp_pg_control( 480 struct dce_hwseq *hws, 481 unsigned int hubp_inst, 482 bool power_on) 483 { 484 uint32_t power_gate = power_on ? 0 : 1; 485 uint32_t pwr_status = power_on ? 0 : 2; 486 487 if (hws->ctx->dc->debug.disable_hubp_power_gate) 488 return; 489 if (REG(DOMAIN0_PG_CONFIG) == 0) 490 return; 491 492 switch (hubp_inst) { 493 case 0: /* DCHUBP0 */ 494 REG_UPDATE(DOMAIN0_PG_CONFIG, 495 DOMAIN0_POWER_GATE, power_gate); 496 497 REG_WAIT(DOMAIN0_PG_STATUS, 498 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 499 1, 1000); 500 break; 501 case 1: /* DCHUBP1 */ 502 REG_UPDATE(DOMAIN2_PG_CONFIG, 503 DOMAIN2_POWER_GATE, power_gate); 504 505 REG_WAIT(DOMAIN2_PG_STATUS, 506 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 507 1, 1000); 508 break; 509 case 2: /* DCHUBP2 */ 510 REG_UPDATE(DOMAIN4_PG_CONFIG, 511 DOMAIN4_POWER_GATE, power_gate); 512 513 REG_WAIT(DOMAIN4_PG_STATUS, 514 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 515 1, 1000); 516 break; 517 case 3: /* DCHUBP3 */ 518 REG_UPDATE(DOMAIN6_PG_CONFIG, 519 DOMAIN6_POWER_GATE, power_gate); 520 521 REG_WAIT(DOMAIN6_PG_STATUS, 522 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 523 1, 1000); 524 break; 525 case 4: /* DCHUBP4 */ 526 REG_UPDATE(DOMAIN8_PG_CONFIG, 527 DOMAIN8_POWER_GATE, power_gate); 528 529 REG_WAIT(DOMAIN8_PG_STATUS, 530 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 531 1, 1000); 532 break; 533 case 5: /* DCHUBP5 */ 534 /* 535 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 536 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 537 * reset. 538 * REG_UPDATE(DOMAIN10_PG_CONFIG, 539 * DOMAIN10_POWER_GATE, power_gate); 540 * 541 * REG_WAIT(DOMAIN10_PG_STATUS, 542 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 543 * 1, 1000); 544 */ 545 break; 546 default: 547 BREAK_TO_DEBUGGER(); 548 break; 549 } 550 } 551 552 553 /* disable HW used by plane. 554 * note: cannot disable until disconnect is complete 555 */ 556 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 557 { 558 struct dce_hwseq *hws = dc->hwseq; 559 struct hubp *hubp = pipe_ctx->plane_res.hubp; 560 struct dpp *dpp = pipe_ctx->plane_res.dpp; 561 562 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 563 564 /* In flip immediate with pipe splitting case GSL is used for 565 * synchronization so we must disable it when the plane is disabled. 566 */ 567 if (pipe_ctx->stream_res.gsl_group != 0) 568 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 569 570 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 571 572 hubp->funcs->hubp_clk_cntl(hubp, false); 573 574 dpp->funcs->dpp_dppclk_control(dpp, false, false); 575 576 hubp->power_gated = true; 577 578 hws->funcs.plane_atomic_power_down(dc, 579 pipe_ctx->plane_res.dpp, 580 pipe_ctx->plane_res.hubp); 581 582 pipe_ctx->stream = NULL; 583 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 584 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 585 pipe_ctx->top_pipe = NULL; 586 pipe_ctx->bottom_pipe = NULL; 587 pipe_ctx->plane_state = NULL; 588 } 589 590 591 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 592 { 593 DC_LOGGER_INIT(dc->ctx->logger); 594 595 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 596 return; 597 598 dcn20_plane_atomic_disable(dc, pipe_ctx); 599 600 DC_LOG_DC("Power down front end %d\n", 601 pipe_ctx->pipe_idx); 602 } 603 604 enum dc_status dcn20_enable_stream_timing( 605 struct pipe_ctx *pipe_ctx, 606 struct dc_state *context, 607 struct dc *dc) 608 { 609 struct dce_hwseq *hws = dc->hwseq; 610 struct dc_stream_state *stream = pipe_ctx->stream; 611 struct drr_params params = {0}; 612 unsigned int event_triggers = 0; 613 struct pipe_ctx *odm_pipe; 614 int opp_cnt = 1; 615 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 616 617 /* by upper caller loop, pipe0 is parent pipe and be called first. 618 * back end is set up by for pipe0. Other children pipe share back end 619 * with pipe 0. No program is needed. 620 */ 621 if (pipe_ctx->top_pipe != NULL) 622 return DC_OK; 623 624 /* TODO check if timing_changed, disable stream if timing changed */ 625 626 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 627 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 628 opp_cnt++; 629 } 630 631 if (opp_cnt > 1) 632 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 633 pipe_ctx->stream_res.tg, 634 opp_inst, opp_cnt, 635 &pipe_ctx->stream->timing); 636 637 /* HW program guide assume display already disable 638 * by unplug sequence. OTG assume stop. 639 */ 640 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 641 642 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 643 pipe_ctx->clock_source, 644 &pipe_ctx->stream_res.pix_clk_params, 645 &pipe_ctx->pll_settings)) { 646 BREAK_TO_DEBUGGER(); 647 return DC_ERROR_UNEXPECTED; 648 } 649 650 pipe_ctx->stream_res.tg->funcs->program_timing( 651 pipe_ctx->stream_res.tg, 652 &stream->timing, 653 pipe_ctx->pipe_dlg_param.vready_offset, 654 pipe_ctx->pipe_dlg_param.vstartup_start, 655 pipe_ctx->pipe_dlg_param.vupdate_offset, 656 pipe_ctx->pipe_dlg_param.vupdate_width, 657 pipe_ctx->stream->signal, 658 true); 659 660 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 661 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 662 odm_pipe->stream_res.opp, 663 true); 664 665 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 666 pipe_ctx->stream_res.opp, 667 true); 668 669 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 670 671 /* VTG is within DCHUB command block. DCFCLK is always on */ 672 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 673 BREAK_TO_DEBUGGER(); 674 return DC_ERROR_UNEXPECTED; 675 } 676 677 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 678 679 params.vertical_total_min = stream->adjust.v_total_min; 680 params.vertical_total_max = stream->adjust.v_total_max; 681 params.vertical_total_mid = stream->adjust.v_total_mid; 682 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 683 if (pipe_ctx->stream_res.tg->funcs->set_drr) 684 pipe_ctx->stream_res.tg->funcs->set_drr( 685 pipe_ctx->stream_res.tg, ¶ms); 686 687 // DRR should set trigger event to monitor surface update event 688 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 689 event_triggers = 0x80; 690 /* Event triggers and num frames initialized for DRR, but can be 691 * later updated for PSR use. Note DRR trigger events are generated 692 * regardless of whether num frames met. 693 */ 694 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 695 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 696 pipe_ctx->stream_res.tg, event_triggers, 2); 697 698 /* TODO program crtc source select for non-virtual signal*/ 699 /* TODO program FMT */ 700 /* TODO setup link_enc */ 701 /* TODO set stream attributes */ 702 /* TODO program audio */ 703 /* TODO enable stream if timing changed */ 704 /* TODO unblank stream if DP */ 705 706 return DC_OK; 707 } 708 709 void dcn20_program_output_csc(struct dc *dc, 710 struct pipe_ctx *pipe_ctx, 711 enum dc_color_space colorspace, 712 uint16_t *matrix, 713 int opp_id) 714 { 715 struct mpc *mpc = dc->res_pool->mpc; 716 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 717 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 718 719 if (mpc->funcs->power_on_mpc_mem_pwr) 720 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 721 722 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 723 if (mpc->funcs->set_output_csc != NULL) 724 mpc->funcs->set_output_csc(mpc, 725 opp_id, 726 matrix, 727 ocsc_mode); 728 } else { 729 if (mpc->funcs->set_ocsc_default != NULL) 730 mpc->funcs->set_ocsc_default(mpc, 731 opp_id, 732 colorspace, 733 ocsc_mode); 734 } 735 } 736 737 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 738 const struct dc_stream_state *stream) 739 { 740 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 741 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 742 struct pwl_params *params = NULL; 743 /* 744 * program OGAM only for the top pipe 745 * if there is a pipe split then fix diagnostic is required: 746 * how to pass OGAM parameter for stream. 747 * if programming for all pipes is required then remove condition 748 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 749 */ 750 if (mpc->funcs->power_on_mpc_mem_pwr) 751 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 752 if (pipe_ctx->top_pipe == NULL 753 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 754 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 755 params = &stream->out_transfer_func->pwl; 756 else if (pipe_ctx->stream->out_transfer_func->type == 757 TF_TYPE_DISTRIBUTED_POINTS && 758 cm_helper_translate_curve_to_hw_format( 759 stream->out_transfer_func, 760 &mpc->blender_params, false)) 761 params = &mpc->blender_params; 762 /* 763 * there is no ROM 764 */ 765 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 766 BREAK_TO_DEBUGGER(); 767 } 768 /* 769 * if above if is not executed then 'params' equal to 0 and set in bypass 770 */ 771 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 772 773 return true; 774 } 775 776 bool dcn20_set_blend_lut( 777 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 778 { 779 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 780 bool result = true; 781 struct pwl_params *blend_lut = NULL; 782 783 if (plane_state->blend_tf) { 784 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 785 blend_lut = &plane_state->blend_tf->pwl; 786 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 787 cm_helper_translate_curve_to_hw_format( 788 plane_state->blend_tf, 789 &dpp_base->regamma_params, false); 790 blend_lut = &dpp_base->regamma_params; 791 } 792 } 793 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 794 795 return result; 796 } 797 798 bool dcn20_set_shaper_3dlut( 799 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 800 { 801 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 802 bool result = true; 803 struct pwl_params *shaper_lut = NULL; 804 805 if (plane_state->in_shaper_func) { 806 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 807 shaper_lut = &plane_state->in_shaper_func->pwl; 808 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 809 cm_helper_translate_curve_to_hw_format( 810 plane_state->in_shaper_func, 811 &dpp_base->shaper_params, true); 812 shaper_lut = &dpp_base->shaper_params; 813 } 814 } 815 816 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 817 if (plane_state->lut3d_func && 818 plane_state->lut3d_func->state.bits.initialized == 1) 819 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 820 &plane_state->lut3d_func->lut_3d); 821 else 822 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 823 824 return result; 825 } 826 827 bool dcn20_set_input_transfer_func(struct dc *dc, 828 struct pipe_ctx *pipe_ctx, 829 const struct dc_plane_state *plane_state) 830 { 831 struct dce_hwseq *hws = dc->hwseq; 832 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 833 const struct dc_transfer_func *tf = NULL; 834 bool result = true; 835 bool use_degamma_ram = false; 836 837 if (dpp_base == NULL || plane_state == NULL) 838 return false; 839 840 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 841 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 842 843 if (plane_state->in_transfer_func) 844 tf = plane_state->in_transfer_func; 845 846 847 if (tf == NULL) { 848 dpp_base->funcs->dpp_set_degamma(dpp_base, 849 IPP_DEGAMMA_MODE_BYPASS); 850 return true; 851 } 852 853 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 854 use_degamma_ram = true; 855 856 if (use_degamma_ram == true) { 857 if (tf->type == TF_TYPE_HWPWL) 858 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 859 &tf->pwl); 860 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 861 cm_helper_translate_curve_to_degamma_hw_format(tf, 862 &dpp_base->degamma_params); 863 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 864 &dpp_base->degamma_params); 865 } 866 return true; 867 } 868 /* handle here the optimized cases when de-gamma ROM could be used. 869 * 870 */ 871 if (tf->type == TF_TYPE_PREDEFINED) { 872 switch (tf->tf) { 873 case TRANSFER_FUNCTION_SRGB: 874 dpp_base->funcs->dpp_set_degamma(dpp_base, 875 IPP_DEGAMMA_MODE_HW_sRGB); 876 break; 877 case TRANSFER_FUNCTION_BT709: 878 dpp_base->funcs->dpp_set_degamma(dpp_base, 879 IPP_DEGAMMA_MODE_HW_xvYCC); 880 break; 881 case TRANSFER_FUNCTION_LINEAR: 882 dpp_base->funcs->dpp_set_degamma(dpp_base, 883 IPP_DEGAMMA_MODE_BYPASS); 884 break; 885 case TRANSFER_FUNCTION_PQ: 886 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 887 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 888 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 889 result = true; 890 break; 891 default: 892 result = false; 893 break; 894 } 895 } else if (tf->type == TF_TYPE_BYPASS) 896 dpp_base->funcs->dpp_set_degamma(dpp_base, 897 IPP_DEGAMMA_MODE_BYPASS); 898 else { 899 /* 900 * if we are here, we did not handle correctly. 901 * fix is required for this use case 902 */ 903 BREAK_TO_DEBUGGER(); 904 dpp_base->funcs->dpp_set_degamma(dpp_base, 905 IPP_DEGAMMA_MODE_BYPASS); 906 } 907 908 return result; 909 } 910 911 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 912 { 913 struct pipe_ctx *odm_pipe; 914 int opp_cnt = 1; 915 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 916 917 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 918 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 919 opp_cnt++; 920 } 921 922 if (opp_cnt > 1) 923 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 924 pipe_ctx->stream_res.tg, 925 opp_inst, opp_cnt, 926 &pipe_ctx->stream->timing); 927 else 928 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 929 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 930 } 931 932 void dcn20_blank_pixel_data( 933 struct dc *dc, 934 struct pipe_ctx *pipe_ctx, 935 bool blank) 936 { 937 struct tg_color black_color = {0}; 938 struct stream_resource *stream_res = &pipe_ctx->stream_res; 939 struct dc_stream_state *stream = pipe_ctx->stream; 940 enum dc_color_space color_space = stream->output_color_space; 941 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 942 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 943 struct pipe_ctx *odm_pipe; 944 int odm_cnt = 1; 945 946 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 947 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 948 949 if (stream->link->test_pattern_enabled) 950 return; 951 952 /* get opp dpg blank color */ 953 color_space_to_black_color(dc, color_space, &black_color); 954 955 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 956 odm_cnt++; 957 958 width = width / odm_cnt; 959 960 if (blank) { 961 if (stream_res->abm) 962 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm); 963 964 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 965 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 966 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 967 } 968 } else { 969 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 970 } 971 972 stream_res->opp->funcs->opp_set_disp_pattern_generator( 973 stream_res->opp, 974 test_pattern, 975 test_pattern_color_space, 976 stream->timing.display_color_depth, 977 &black_color, 978 width, 979 height, 980 0); 981 982 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 983 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( 984 odm_pipe->stream_res.opp, 985 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 986 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 987 test_pattern_color_space, 988 stream->timing.display_color_depth, 989 &black_color, 990 width, 991 height, 992 0); 993 } 994 995 if (!blank) 996 if (stream_res->abm) { 997 stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1); 998 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 999 } 1000 } 1001 1002 1003 static void dcn20_power_on_plane( 1004 struct dce_hwseq *hws, 1005 struct pipe_ctx *pipe_ctx) 1006 { 1007 DC_LOGGER_INIT(hws->ctx->logger); 1008 if (REG(DC_IP_REQUEST_CNTL)) { 1009 REG_SET(DC_IP_REQUEST_CNTL, 0, 1010 IP_REQUEST_EN, 1); 1011 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1012 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1013 REG_SET(DC_IP_REQUEST_CNTL, 0, 1014 IP_REQUEST_EN, 0); 1015 DC_LOG_DEBUG( 1016 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1017 } 1018 } 1019 1020 void dcn20_enable_plane( 1021 struct dc *dc, 1022 struct pipe_ctx *pipe_ctx, 1023 struct dc_state *context) 1024 { 1025 //if (dc->debug.sanity_checks) { 1026 // dcn10_verify_allow_pstate_change_high(dc); 1027 //} 1028 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1029 1030 /* enable DCFCLK current DCHUB */ 1031 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1032 1033 /* initialize HUBP on power up */ 1034 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1035 1036 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1037 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1038 pipe_ctx->stream_res.opp, 1039 true); 1040 1041 /* TODO: enable/disable in dm as per update type. 1042 if (plane_state) { 1043 DC_LOG_DC(dc->ctx->logger, 1044 "Pipe:%d 0x%x: addr hi:0x%x, " 1045 "addr low:0x%x, " 1046 "src: %d, %d, %d," 1047 " %d; dst: %d, %d, %d, %d;\n", 1048 pipe_ctx->pipe_idx, 1049 plane_state, 1050 plane_state->address.grph.addr.high_part, 1051 plane_state->address.grph.addr.low_part, 1052 plane_state->src_rect.x, 1053 plane_state->src_rect.y, 1054 plane_state->src_rect.width, 1055 plane_state->src_rect.height, 1056 plane_state->dst_rect.x, 1057 plane_state->dst_rect.y, 1058 plane_state->dst_rect.width, 1059 plane_state->dst_rect.height); 1060 1061 DC_LOG_DC(dc->ctx->logger, 1062 "Pipe %d: width, height, x, y format:%d\n" 1063 "viewport:%d, %d, %d, %d\n" 1064 "recout: %d, %d, %d, %d\n", 1065 pipe_ctx->pipe_idx, 1066 plane_state->format, 1067 pipe_ctx->plane_res.scl_data.viewport.width, 1068 pipe_ctx->plane_res.scl_data.viewport.height, 1069 pipe_ctx->plane_res.scl_data.viewport.x, 1070 pipe_ctx->plane_res.scl_data.viewport.y, 1071 pipe_ctx->plane_res.scl_data.recout.width, 1072 pipe_ctx->plane_res.scl_data.recout.height, 1073 pipe_ctx->plane_res.scl_data.recout.x, 1074 pipe_ctx->plane_res.scl_data.recout.y); 1075 print_rq_dlg_ttu(dc, pipe_ctx); 1076 } 1077 */ 1078 if (dc->vm_pa_config.valid) { 1079 struct vm_system_aperture_param apt; 1080 1081 apt.sys_default.quad_part = 0; 1082 1083 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1084 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1085 1086 // Program system aperture settings 1087 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1088 } 1089 1090 // if (dc->debug.sanity_checks) { 1091 // dcn10_verify_allow_pstate_change_high(dc); 1092 // } 1093 } 1094 1095 void dcn20_pipe_control_lock( 1096 struct dc *dc, 1097 struct pipe_ctx *pipe, 1098 bool lock) 1099 { 1100 bool flip_immediate = false; 1101 1102 /* use TG master update lock to lock everything on the TG 1103 * therefore only top pipe need to lock 1104 */ 1105 if (!pipe || pipe->top_pipe) 1106 return; 1107 1108 if (pipe->plane_state != NULL) 1109 flip_immediate = pipe->plane_state->flip_immediate; 1110 1111 if (flip_immediate && lock) { 1112 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1113 int i; 1114 1115 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1116 if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) 1117 break; 1118 udelay(1); 1119 } 1120 1121 if (pipe->bottom_pipe != NULL) { 1122 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1123 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp)) 1124 break; 1125 udelay(1); 1126 } 1127 } 1128 } 1129 1130 /* In flip immediate and pipe splitting case, we need to use GSL 1131 * for synchronization. Only do setup on locking and on flip type change. 1132 */ 1133 if (lock && pipe->bottom_pipe != NULL) 1134 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1135 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1136 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1137 1138 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1139 if (lock) 1140 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1141 else 1142 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1143 } else { 1144 if (lock) 1145 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1146 else 1147 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1148 } 1149 } 1150 1151 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1152 { 1153 new_pipe->update_flags.raw = 0; 1154 1155 /* Exit on unchanged, unused pipe */ 1156 if (!old_pipe->plane_state && !new_pipe->plane_state) 1157 return; 1158 /* Detect pipe enable/disable */ 1159 if (!old_pipe->plane_state && new_pipe->plane_state) { 1160 new_pipe->update_flags.bits.enable = 1; 1161 new_pipe->update_flags.bits.mpcc = 1; 1162 new_pipe->update_flags.bits.dppclk = 1; 1163 new_pipe->update_flags.bits.hubp_interdependent = 1; 1164 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1165 new_pipe->update_flags.bits.gamut_remap = 1; 1166 new_pipe->update_flags.bits.scaler = 1; 1167 new_pipe->update_flags.bits.viewport = 1; 1168 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1169 new_pipe->update_flags.bits.odm = 1; 1170 new_pipe->update_flags.bits.global_sync = 1; 1171 } 1172 return; 1173 } 1174 if (old_pipe->plane_state && !new_pipe->plane_state) { 1175 new_pipe->update_flags.bits.disable = 1; 1176 return; 1177 } 1178 1179 /* Detect top pipe only changes */ 1180 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1181 /* Detect odm changes */ 1182 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1183 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1184 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1185 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1186 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1187 new_pipe->update_flags.bits.odm = 1; 1188 1189 /* Detect global sync changes */ 1190 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1191 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1192 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1193 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1194 new_pipe->update_flags.bits.global_sync = 1; 1195 } 1196 1197 /* 1198 * Detect opp / tg change, only set on change, not on enable 1199 * Assume mpcc inst = pipe index, if not this code needs to be updated 1200 * since mpcc is what is affected by these. In fact all of our sequence 1201 * makes this assumption at the moment with how hubp reset is matched to 1202 * same index mpcc reset. 1203 */ 1204 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1205 new_pipe->update_flags.bits.opp_changed = 1; 1206 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1207 new_pipe->update_flags.bits.tg_changed = 1; 1208 1209 /* Detect mpcc blending changes, only dpp inst and bot matter here */ 1210 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1211 || old_pipe->stream_res.opp != new_pipe->stream_res.opp 1212 || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe) 1213 || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe) 1214 || (old_pipe->bottom_pipe && new_pipe->bottom_pipe 1215 && old_pipe->bottom_pipe->plane_res.mpcc_inst 1216 != new_pipe->bottom_pipe->plane_res.mpcc_inst)) 1217 new_pipe->update_flags.bits.mpcc = 1; 1218 1219 /* Detect dppclk change */ 1220 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1221 new_pipe->update_flags.bits.dppclk = 1; 1222 1223 /* Check for scl update */ 1224 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1225 new_pipe->update_flags.bits.scaler = 1; 1226 /* Check for vp update */ 1227 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1228 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1229 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1230 new_pipe->update_flags.bits.viewport = 1; 1231 1232 /* Detect dlg/ttu/rq updates */ 1233 { 1234 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1235 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1236 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1237 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1238 1239 /* Detect pipe interdependent updates */ 1240 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1241 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1242 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1243 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1244 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1245 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1246 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1247 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1248 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1249 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1250 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1251 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1252 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1253 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1254 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1255 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1256 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1257 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1258 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1259 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1260 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1261 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1262 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1263 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1264 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1265 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1266 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1267 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1268 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1269 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1270 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1271 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1272 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1273 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1274 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1275 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1276 new_pipe->update_flags.bits.hubp_interdependent = 1; 1277 } 1278 /* Detect any other updates to ttu/rq/dlg */ 1279 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1280 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1281 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1282 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1283 } 1284 } 1285 1286 static void dcn20_update_dchubp_dpp( 1287 struct dc *dc, 1288 struct pipe_ctx *pipe_ctx, 1289 struct dc_state *context) 1290 { 1291 struct dce_hwseq *hws = dc->hwseq; 1292 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1293 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1294 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1295 bool viewport_changed = false; 1296 1297 if (pipe_ctx->update_flags.bits.dppclk) 1298 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1299 1300 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1301 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1302 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1303 */ 1304 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1305 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1306 1307 hubp->funcs->hubp_setup( 1308 hubp, 1309 &pipe_ctx->dlg_regs, 1310 &pipe_ctx->ttu_regs, 1311 &pipe_ctx->rq_regs, 1312 &pipe_ctx->pipe_dlg_param); 1313 } 1314 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1315 hubp->funcs->hubp_setup_interdependent( 1316 hubp, 1317 &pipe_ctx->dlg_regs, 1318 &pipe_ctx->ttu_regs); 1319 1320 if (pipe_ctx->update_flags.bits.enable || 1321 plane_state->update_flags.bits.bpp_change || 1322 plane_state->update_flags.bits.input_csc_change || 1323 plane_state->update_flags.bits.color_space_change || 1324 plane_state->update_flags.bits.coeff_reduction_change) { 1325 struct dc_bias_and_scale bns_params = {0}; 1326 1327 // program the input csc 1328 dpp->funcs->dpp_setup(dpp, 1329 plane_state->format, 1330 EXPANSION_MODE_ZERO, 1331 plane_state->input_csc_color_matrix, 1332 plane_state->color_space, 1333 NULL); 1334 1335 if (dpp->funcs->dpp_program_bias_and_scale) { 1336 //TODO :for CNVC set scale and bias registers if necessary 1337 build_prescale_params(&bns_params, plane_state); 1338 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1339 } 1340 } 1341 1342 if (pipe_ctx->update_flags.bits.mpcc 1343 || plane_state->update_flags.bits.global_alpha_change 1344 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1345 // MPCC inst is equal to pipe index in practice 1346 int mpcc_inst = hubp->inst; 1347 int opp_inst; 1348 int opp_count = dc->res_pool->pipe_count; 1349 1350 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1351 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1352 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1353 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1354 break; 1355 } 1356 } 1357 hws->funcs.update_mpcc(dc, pipe_ctx); 1358 } 1359 1360 if (pipe_ctx->update_flags.bits.scaler || 1361 plane_state->update_flags.bits.scaling_change || 1362 plane_state->update_flags.bits.position_change || 1363 plane_state->update_flags.bits.per_pixel_alpha_change || 1364 pipe_ctx->stream->update_flags.bits.scaling) { 1365 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1366 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP); 1367 /* scaler configuration */ 1368 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1369 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1370 } 1371 1372 if (pipe_ctx->update_flags.bits.viewport || 1373 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1374 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1375 1376 hubp->funcs->mem_program_viewport( 1377 hubp, 1378 &pipe_ctx->plane_res.scl_data.viewport, 1379 &pipe_ctx->plane_res.scl_data.viewport_c); 1380 viewport_changed = true; 1381 } 1382 1383 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1384 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1385 pipe_ctx->update_flags.bits.scaler || pipe_ctx->update_flags.bits.viewport) 1386 && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1387 dc->hwss.set_cursor_position(pipe_ctx); 1388 dc->hwss.set_cursor_attribute(pipe_ctx); 1389 1390 if (dc->hwss.set_cursor_sdr_white_level) 1391 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1392 } 1393 1394 /* Any updates are handled in dc interface, just need 1395 * to apply existing for plane enable / opp change */ 1396 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1397 || pipe_ctx->stream->update_flags.bits.gamut_remap 1398 || pipe_ctx->stream->update_flags.bits.out_csc) { 1399 /* dpp/cm gamut remap*/ 1400 dc->hwss.program_gamut_remap(pipe_ctx); 1401 1402 /*call the dcn2 method which uses mpc csc*/ 1403 dc->hwss.program_output_csc(dc, 1404 pipe_ctx, 1405 pipe_ctx->stream->output_color_space, 1406 pipe_ctx->stream->csc_color_matrix.matrix, 1407 hubp->opp_id); 1408 } 1409 1410 if (pipe_ctx->update_flags.bits.enable || 1411 pipe_ctx->update_flags.bits.opp_changed || 1412 plane_state->update_flags.bits.pixel_format_change || 1413 plane_state->update_flags.bits.horizontal_mirror_change || 1414 plane_state->update_flags.bits.rotation_change || 1415 plane_state->update_flags.bits.swizzle_change || 1416 plane_state->update_flags.bits.dcc_change || 1417 plane_state->update_flags.bits.bpp_change || 1418 plane_state->update_flags.bits.scaling_change || 1419 plane_state->update_flags.bits.plane_size_change) { 1420 struct plane_size size = plane_state->plane_size; 1421 1422 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1423 hubp->funcs->hubp_program_surface_config( 1424 hubp, 1425 plane_state->format, 1426 &plane_state->tiling_info, 1427 &size, 1428 plane_state->rotation, 1429 &plane_state->dcc, 1430 plane_state->horizontal_mirror, 1431 0); 1432 hubp->power_gated = false; 1433 } 1434 1435 if (hubp->funcs->apply_PLAT_54186_wa && viewport_changed) 1436 hubp->funcs->apply_PLAT_54186_wa(hubp, &plane_state->address); 1437 1438 if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update) 1439 hws->funcs.update_plane_addr(dc, pipe_ctx); 1440 1441 1442 1443 if (pipe_ctx->update_flags.bits.enable) 1444 hubp->funcs->set_blank(hubp, false); 1445 } 1446 1447 1448 static void dcn20_program_pipe( 1449 struct dc *dc, 1450 struct pipe_ctx *pipe_ctx, 1451 struct dc_state *context) 1452 { 1453 struct dce_hwseq *hws = dc->hwseq; 1454 /* Only need to unblank on top pipe */ 1455 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1456 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1457 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1458 1459 if (pipe_ctx->update_flags.bits.global_sync) { 1460 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1461 pipe_ctx->stream_res.tg, 1462 pipe_ctx->pipe_dlg_param.vready_offset, 1463 pipe_ctx->pipe_dlg_param.vstartup_start, 1464 pipe_ctx->pipe_dlg_param.vupdate_offset, 1465 pipe_ctx->pipe_dlg_param.vupdate_width); 1466 1467 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1468 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1469 1470 if (hws->funcs.setup_vupdate_interrupt) 1471 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1472 } 1473 1474 if (pipe_ctx->update_flags.bits.odm) 1475 hws->funcs.update_odm(dc, context, pipe_ctx); 1476 1477 if (pipe_ctx->update_flags.bits.enable) 1478 dcn20_enable_plane(dc, pipe_ctx, context); 1479 1480 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1481 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1482 1483 if (pipe_ctx->update_flags.bits.enable 1484 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1485 hws->funcs.set_hdr_multiplier(pipe_ctx); 1486 1487 if (pipe_ctx->update_flags.bits.enable || 1488 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1489 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1490 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1491 1492 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1493 * only do gamma programming for powering on, internal memcmp to avoid 1494 * updating on slave planes 1495 */ 1496 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1497 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1498 1499 /* If the pipe has been enabled or has a different opp, we 1500 * should reprogram the fmt. This deals with cases where 1501 * interation between mpc and odm combine on different streams 1502 * causes a different pipe to be chosen to odm combine with. 1503 */ 1504 if (pipe_ctx->update_flags.bits.enable 1505 || pipe_ctx->update_flags.bits.opp_changed) { 1506 1507 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1508 pipe_ctx->stream_res.opp, 1509 COLOR_SPACE_YCBCR601, 1510 pipe_ctx->stream->timing.display_color_depth, 1511 pipe_ctx->stream->signal); 1512 1513 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1514 pipe_ctx->stream_res.opp, 1515 &pipe_ctx->stream->bit_depth_params, 1516 &pipe_ctx->stream->clamping); 1517 } 1518 } 1519 1520 void dcn20_program_front_end_for_ctx( 1521 struct dc *dc, 1522 struct dc_state *context) 1523 { 1524 int i; 1525 struct dce_hwseq *hws = dc->hwseq; 1526 DC_LOGGER_INIT(dc->ctx->logger); 1527 1528 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1529 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1530 1531 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1532 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1533 if (dc->hwss.program_triplebuffer != NULL && 1534 !dc->debug.disable_tri_buf) { 1535 /*turn off triple buffer for full update*/ 1536 dc->hwss.program_triplebuffer( 1537 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1538 } 1539 } 1540 } 1541 1542 /* Set pipe update flags and lock pipes */ 1543 for (i = 0; i < dc->res_pool->pipe_count; i++) 1544 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1545 &context->res_ctx.pipe_ctx[i]); 1546 1547 /* OTG blank before disabling all front ends */ 1548 for (i = 0; i < dc->res_pool->pipe_count; i++) 1549 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1550 && !context->res_ctx.pipe_ctx[i].top_pipe 1551 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1552 && context->res_ctx.pipe_ctx[i].stream) 1553 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1554 1555 /* Disconnect mpcc */ 1556 for (i = 0; i < dc->res_pool->pipe_count; i++) 1557 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1558 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1559 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1560 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1561 } 1562 1563 /* 1564 * Program all updated pipes, order matters for mpcc setup. Start with 1565 * top pipe and program all pipes that follow in order 1566 */ 1567 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1568 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1569 1570 if (pipe->plane_state && !pipe->top_pipe) { 1571 while (pipe) { 1572 dcn20_program_pipe(dc, pipe, context); 1573 pipe = pipe->bottom_pipe; 1574 } 1575 /* Program secondary blending tree and writeback pipes */ 1576 pipe = &context->res_ctx.pipe_ctx[i]; 1577 if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0 1578 && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw) 1579 && hws->funcs.program_all_writeback_pipes_in_tree) 1580 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1581 } 1582 } 1583 } 1584 1585 void dcn20_post_unlock_program_front_end( 1586 struct dc *dc, 1587 struct dc_state *context) 1588 { 1589 int i; 1590 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1591 struct dce_hwseq *hwseq = dc->hwseq; 1592 1593 DC_LOGGER_INIT(dc->ctx->logger); 1594 1595 for (i = 0; i < dc->res_pool->pipe_count; i++) 1596 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1597 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1598 1599 /* 1600 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1601 * part of the enable operation otherwise, DM may request an immediate flip which 1602 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1603 * is unsupported on DCN. 1604 */ 1605 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1606 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1607 1608 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1609 struct hubp *hubp = pipe->plane_res.hubp; 1610 int j = 0; 1611 1612 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1613 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1614 mdelay(1); 1615 } 1616 } 1617 1618 /* WA to apply WM setting*/ 1619 if (hwseq->wa.DEGVIDCN21) 1620 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1621 1622 1623 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1624 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1625 1626 if (dc->current_state->stream_status[0].plane_count == 1 && 1627 context->stream_status[0].plane_count > 1) { 1628 1629 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1630 1631 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1632 1633 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1634 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1635 } 1636 } 1637 } 1638 1639 void dcn20_prepare_bandwidth( 1640 struct dc *dc, 1641 struct dc_state *context) 1642 { 1643 struct hubbub *hubbub = dc->res_pool->hubbub; 1644 1645 dc->clk_mgr->funcs->update_clocks( 1646 dc->clk_mgr, 1647 context, 1648 false); 1649 1650 /* program dchubbub watermarks */ 1651 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 1652 &context->bw_ctx.bw.dcn.watermarks, 1653 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1654 false); 1655 } 1656 1657 void dcn20_optimize_bandwidth( 1658 struct dc *dc, 1659 struct dc_state *context) 1660 { 1661 struct hubbub *hubbub = dc->res_pool->hubbub; 1662 1663 if (dc->wm_optimized_required || IS_DIAG_DC(dc->ctx->dce_environment)) { 1664 /* program dchubbub watermarks */ 1665 hubbub->funcs->program_watermarks(hubbub, 1666 &context->bw_ctx.bw.dcn.watermarks, 1667 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1668 true); 1669 dc->wm_optimized_required = false; 1670 } 1671 1672 if (dc->clk_optimized_required || IS_DIAG_DC(dc->ctx->dce_environment)) { 1673 dc->clk_mgr->funcs->update_clocks( 1674 dc->clk_mgr, 1675 context, 1676 true); 1677 dc->clk_optimized_required = false; 1678 } 1679 } 1680 1681 bool dcn20_update_bandwidth( 1682 struct dc *dc, 1683 struct dc_state *context) 1684 { 1685 int i; 1686 struct dce_hwseq *hws = dc->hwseq; 1687 1688 /* recalculate DML parameters */ 1689 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1690 return false; 1691 1692 /* apply updated bandwidth parameters */ 1693 dc->hwss.prepare_bandwidth(dc, context); 1694 1695 /* update hubp configs for all pipes */ 1696 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1697 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1698 1699 if (pipe_ctx->plane_state == NULL) 1700 continue; 1701 1702 if (pipe_ctx->top_pipe == NULL) { 1703 bool blank = !is_pipe_tree_visible(pipe_ctx); 1704 1705 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1706 pipe_ctx->stream_res.tg, 1707 pipe_ctx->pipe_dlg_param.vready_offset, 1708 pipe_ctx->pipe_dlg_param.vstartup_start, 1709 pipe_ctx->pipe_dlg_param.vupdate_offset, 1710 pipe_ctx->pipe_dlg_param.vupdate_width); 1711 1712 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1713 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1714 1715 if (pipe_ctx->prev_odm_pipe == NULL) 1716 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 1717 1718 if (hws->funcs.setup_vupdate_interrupt) 1719 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1720 } 1721 1722 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1723 pipe_ctx->plane_res.hubp, 1724 &pipe_ctx->dlg_regs, 1725 &pipe_ctx->ttu_regs, 1726 &pipe_ctx->rq_regs, 1727 &pipe_ctx->pipe_dlg_param); 1728 } 1729 1730 return true; 1731 } 1732 1733 void dcn20_enable_writeback( 1734 struct dc *dc, 1735 struct dc_writeback_info *wb_info, 1736 struct dc_state *context) 1737 { 1738 struct dwbc *dwb; 1739 struct mcif_wb *mcif_wb; 1740 struct timing_generator *optc; 1741 1742 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1743 ASSERT(wb_info->wb_enabled); 1744 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1745 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1746 1747 /* set the OPTC source mux */ 1748 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 1749 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1750 /* set MCIF_WB buffer and arbitration configuration */ 1751 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1752 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1753 /* Enable MCIF_WB */ 1754 mcif_wb->funcs->enable_mcif(mcif_wb); 1755 /* Enable DWB */ 1756 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1757 /* TODO: add sequence to enable/disable warmup */ 1758 } 1759 1760 void dcn20_disable_writeback( 1761 struct dc *dc, 1762 unsigned int dwb_pipe_inst) 1763 { 1764 struct dwbc *dwb; 1765 struct mcif_wb *mcif_wb; 1766 1767 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1768 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1769 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1770 1771 dwb->funcs->disable(dwb); 1772 mcif_wb->funcs->disable_mcif(mcif_wb); 1773 } 1774 1775 bool dcn20_wait_for_blank_complete( 1776 struct output_pixel_processor *opp) 1777 { 1778 int counter; 1779 1780 for (counter = 0; counter < 1000; counter++) { 1781 if (opp->funcs->dpg_is_blanked(opp)) 1782 break; 1783 1784 udelay(100); 1785 } 1786 1787 if (counter == 1000) { 1788 dm_error("DC: failed to blank crtc!\n"); 1789 return false; 1790 } 1791 1792 return true; 1793 } 1794 1795 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1796 { 1797 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1798 1799 if (!hubp) 1800 return false; 1801 return hubp->funcs->dmdata_status_done(hubp); 1802 } 1803 1804 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1805 { 1806 struct dce_hwseq *hws = dc->hwseq; 1807 1808 if (pipe_ctx->stream_res.dsc) { 1809 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1810 1811 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1812 while (odm_pipe) { 1813 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 1814 odm_pipe = odm_pipe->next_odm_pipe; 1815 } 1816 } 1817 } 1818 1819 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1820 { 1821 struct dce_hwseq *hws = dc->hwseq; 1822 1823 if (pipe_ctx->stream_res.dsc) { 1824 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1825 1826 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 1827 while (odm_pipe) { 1828 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 1829 odm_pipe = odm_pipe->next_odm_pipe; 1830 } 1831 } 1832 } 1833 1834 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 1835 { 1836 struct dc_dmdata_attributes attr = { 0 }; 1837 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1838 1839 attr.dmdata_mode = DMDATA_HW_MODE; 1840 attr.dmdata_size = 1841 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 1842 attr.address.quad_part = 1843 pipe_ctx->stream->dmdata_address.quad_part; 1844 attr.dmdata_dl_delta = 0; 1845 attr.dmdata_qos_mode = 0; 1846 attr.dmdata_qos_level = 0; 1847 attr.dmdata_repeat = 1; /* always repeat */ 1848 attr.dmdata_updated = 1; 1849 attr.dmdata_sw_data = NULL; 1850 1851 hubp->funcs->dmdata_set_attributes(hubp, &attr); 1852 } 1853 1854 void dcn20_init_vm_ctx( 1855 struct dce_hwseq *hws, 1856 struct dc *dc, 1857 struct dc_virtual_addr_space_config *va_config, 1858 int vmid) 1859 { 1860 struct dcn_hubbub_virt_addr_config config; 1861 1862 if (vmid == 0) { 1863 ASSERT(0); /* VMID cannot be 0 for vm context */ 1864 return; 1865 } 1866 1867 config.page_table_start_addr = va_config->page_table_start_addr; 1868 config.page_table_end_addr = va_config->page_table_end_addr; 1869 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 1870 config.page_table_depth = va_config->page_table_depth; 1871 config.page_table_base_addr = va_config->page_table_base_addr; 1872 1873 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 1874 } 1875 1876 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 1877 { 1878 struct dcn_hubbub_phys_addr_config config; 1879 1880 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 1881 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 1882 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 1883 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 1884 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 1885 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 1886 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 1887 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 1888 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 1889 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 1890 1891 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 1892 } 1893 1894 static bool patch_address_for_sbs_tb_stereo( 1895 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 1896 { 1897 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1898 bool sec_split = pipe_ctx->top_pipe && 1899 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 1900 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 1901 (pipe_ctx->stream->timing.timing_3d_format == 1902 TIMING_3D_FORMAT_SIDE_BY_SIDE || 1903 pipe_ctx->stream->timing.timing_3d_format == 1904 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 1905 *addr = plane_state->address.grph_stereo.left_addr; 1906 plane_state->address.grph_stereo.left_addr = 1907 plane_state->address.grph_stereo.right_addr; 1908 return true; 1909 } 1910 1911 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 1912 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 1913 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 1914 plane_state->address.grph_stereo.right_addr = 1915 plane_state->address.grph_stereo.left_addr; 1916 } 1917 return false; 1918 } 1919 1920 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 1921 { 1922 bool addr_patched = false; 1923 PHYSICAL_ADDRESS_LOC addr; 1924 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1925 1926 if (plane_state == NULL) 1927 return; 1928 1929 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 1930 1931 // Call Helper to track VMID use 1932 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 1933 1934 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 1935 pipe_ctx->plane_res.hubp, 1936 &plane_state->address, 1937 plane_state->flip_immediate); 1938 1939 plane_state->status.requested_address = plane_state->address; 1940 1941 if (plane_state->flip_immediate) 1942 plane_state->status.current_address = plane_state->address; 1943 1944 if (addr_patched) 1945 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 1946 } 1947 1948 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 1949 struct dc_link_settings *link_settings) 1950 { 1951 struct encoder_unblank_param params = { { 0 } }; 1952 struct dc_stream_state *stream = pipe_ctx->stream; 1953 struct dc_link *link = stream->link; 1954 struct dce_hwseq *hws = link->dc->hwseq; 1955 struct pipe_ctx *odm_pipe; 1956 1957 params.opp_cnt = 1; 1958 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1959 params.opp_cnt++; 1960 } 1961 /* only 3 items below are used by unblank */ 1962 params.timing = pipe_ctx->stream->timing; 1963 1964 params.link_settings.link_rate = link_settings->link_rate; 1965 1966 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1967 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 1968 params.timing.pix_clk_100hz /= 2; 1969 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1970 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 1971 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 1972 } 1973 1974 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1975 hws->funcs.edp_backlight_control(link, true); 1976 } 1977 } 1978 1979 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 1980 { 1981 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1982 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 1983 1984 if (start_line < 0) 1985 start_line = 0; 1986 1987 if (tg->funcs->setup_vertical_interrupt2) 1988 tg->funcs->setup_vertical_interrupt2(tg, start_line); 1989 } 1990 1991 static void dcn20_reset_back_end_for_pipe( 1992 struct dc *dc, 1993 struct pipe_ctx *pipe_ctx, 1994 struct dc_state *context) 1995 { 1996 int i; 1997 struct dc_link *link; 1998 DC_LOGGER_INIT(dc->ctx->logger); 1999 if (pipe_ctx->stream_res.stream_enc == NULL) { 2000 pipe_ctx->stream = NULL; 2001 return; 2002 } 2003 2004 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2005 link = pipe_ctx->stream->link; 2006 /* DPMS may already disable or */ 2007 /* dpms_off status is incorrect due to fastboot 2008 * feature. When system resume from S4 with second 2009 * screen only, the dpms_off would be true but 2010 * VBIOS lit up eDP, so check link status too. 2011 */ 2012 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2013 core_link_disable_stream(pipe_ctx); 2014 else if (pipe_ctx->stream_res.audio) 2015 dc->hwss.disable_audio_stream(pipe_ctx); 2016 2017 /* free acquired resources */ 2018 if (pipe_ctx->stream_res.audio) { 2019 /*disable az_endpoint*/ 2020 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2021 2022 /*free audio*/ 2023 if (dc->caps.dynamic_audio == true) { 2024 /*we have to dynamic arbitrate the audio endpoints*/ 2025 /*we free the resource, need reset is_audio_acquired*/ 2026 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2027 pipe_ctx->stream_res.audio, false); 2028 pipe_ctx->stream_res.audio = NULL; 2029 } 2030 } 2031 } 2032 else if (pipe_ctx->stream_res.dsc) { 2033 dp_set_dsc_enable(pipe_ctx, false); 2034 } 2035 2036 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2037 * back end share by all pipes and will be disable only when disable 2038 * parent pipe. 2039 */ 2040 if (pipe_ctx->top_pipe == NULL) { 2041 2042 if (pipe_ctx->stream_res.abm) 2043 pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm); 2044 2045 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2046 2047 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2048 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2049 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2050 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2051 2052 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2053 pipe_ctx->stream_res.tg->funcs->set_drr( 2054 pipe_ctx->stream_res.tg, NULL); 2055 } 2056 2057 for (i = 0; i < dc->res_pool->pipe_count; i++) 2058 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2059 break; 2060 2061 if (i == dc->res_pool->pipe_count) 2062 return; 2063 2064 pipe_ctx->stream = NULL; 2065 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2066 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2067 } 2068 2069 void dcn20_reset_hw_ctx_wrap( 2070 struct dc *dc, 2071 struct dc_state *context) 2072 { 2073 int i; 2074 struct dce_hwseq *hws = dc->hwseq; 2075 2076 /* Reset Back End*/ 2077 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2078 struct pipe_ctx *pipe_ctx_old = 2079 &dc->current_state->res_ctx.pipe_ctx[i]; 2080 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2081 2082 if (!pipe_ctx_old->stream) 2083 continue; 2084 2085 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2086 continue; 2087 2088 if (!pipe_ctx->stream || 2089 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2090 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2091 2092 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2093 if (hws->funcs.enable_stream_gating) 2094 hws->funcs.enable_stream_gating(dc, pipe_ctx); 2095 if (old_clk) 2096 old_clk->funcs->cs_power_down(old_clk); 2097 } 2098 } 2099 } 2100 2101 void dcn20_get_mpctree_visual_confirm_color( 2102 struct pipe_ctx *pipe_ctx, 2103 struct tg_color *color) 2104 { 2105 const struct tg_color pipe_colors[6] = { 2106 {MAX_TG_COLOR_VALUE, 0, 0}, // red 2107 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow 2108 {0, MAX_TG_COLOR_VALUE, 0}, // blue 2109 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple 2110 {0, 0, MAX_TG_COLOR_VALUE}, // green 2111 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange 2112 }; 2113 2114 struct pipe_ctx *top_pipe = pipe_ctx; 2115 2116 while (top_pipe->top_pipe) { 2117 top_pipe = top_pipe->top_pipe; 2118 } 2119 2120 *color = pipe_colors[top_pipe->pipe_idx]; 2121 } 2122 2123 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2124 { 2125 struct dce_hwseq *hws = dc->hwseq; 2126 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2127 struct mpcc_blnd_cfg blnd_cfg = { {0} }; 2128 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2129 int mpcc_id; 2130 struct mpcc *new_mpcc; 2131 struct mpc *mpc = dc->res_pool->mpc; 2132 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2133 2134 // input to MPCC is always RGB, by default leave black_color at 0 2135 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { 2136 hws->funcs.get_hdr_visual_confirm_color( 2137 pipe_ctx, &blnd_cfg.black_color); 2138 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { 2139 hws->funcs.get_surface_visual_confirm_color( 2140 pipe_ctx, &blnd_cfg.black_color); 2141 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) { 2142 dcn20_get_mpctree_visual_confirm_color( 2143 pipe_ctx, &blnd_cfg.black_color); 2144 } 2145 2146 if (per_pixel_alpha) 2147 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2148 else 2149 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2150 2151 blnd_cfg.overlap_only = false; 2152 blnd_cfg.global_gain = 0xff; 2153 2154 if (pipe_ctx->plane_state->global_alpha) 2155 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2156 else 2157 blnd_cfg.global_alpha = 0xff; 2158 2159 blnd_cfg.background_color_bpc = 4; 2160 blnd_cfg.bottom_gain_mode = 0; 2161 blnd_cfg.top_gain = 0x1f000; 2162 blnd_cfg.bottom_inside_gain = 0x1f000; 2163 blnd_cfg.bottom_outside_gain = 0x1f000; 2164 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 2165 2166 /* 2167 * TODO: remove hack 2168 * Note: currently there is a bug in init_hw such that 2169 * on resume from hibernate, BIOS sets up MPCC0, and 2170 * we do mpcc_remove but the mpcc cannot go to idle 2171 * after remove. This cause us to pick mpcc1 here, 2172 * which causes a pstate hang for yet unknown reason. 2173 */ 2174 mpcc_id = hubp->inst; 2175 2176 /* check if this MPCC is already being used */ 2177 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2178 /* remove MPCC if being used */ 2179 if (new_mpcc != NULL) 2180 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2181 else 2182 if (dc->debug.sanity_checks) 2183 mpc->funcs->assert_mpcc_idle_before_connect( 2184 dc->res_pool->mpc, mpcc_id); 2185 2186 /* Call MPC to insert new plane */ 2187 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2188 mpc_tree_params, 2189 &blnd_cfg, 2190 NULL, 2191 NULL, 2192 hubp->inst, 2193 mpcc_id); 2194 2195 ASSERT(new_mpcc != NULL); 2196 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2197 hubp->mpcc_id = mpcc_id; 2198 } 2199 2200 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2201 { 2202 enum dc_lane_count lane_count = 2203 pipe_ctx->stream->link->cur_link_settings.lane_count; 2204 2205 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2206 struct dc_link *link = pipe_ctx->stream->link; 2207 2208 uint32_t active_total_with_borders; 2209 uint32_t early_control = 0; 2210 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2211 2212 /* For MST, there are multiply stream go to only one link. 2213 * connect DIG back_end to front_end while enable_stream and 2214 * disconnect them during disable_stream 2215 * BY this, it is logic clean to separate stream and link 2216 */ 2217 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 2218 pipe_ctx->stream_res.stream_enc->id, true); 2219 2220 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2221 if (link->dc->hwss.program_dmdata_engine) 2222 link->dc->hwss.program_dmdata_engine(pipe_ctx); 2223 } 2224 2225 link->dc->hwss.update_info_frame(pipe_ctx); 2226 2227 /* enable early control to avoid corruption on DP monitor*/ 2228 active_total_with_borders = 2229 timing->h_addressable 2230 + timing->h_border_left 2231 + timing->h_border_right; 2232 2233 if (lane_count != 0) 2234 early_control = active_total_with_borders % lane_count; 2235 2236 if (early_control == 0) 2237 early_control = lane_count; 2238 2239 tg->funcs->set_early_control(tg, early_control); 2240 2241 /* enable audio only within mode set */ 2242 if (pipe_ctx->stream_res.audio != NULL) { 2243 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2244 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2245 } 2246 } 2247 2248 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2249 { 2250 struct dc_stream_state *stream = pipe_ctx->stream; 2251 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2252 bool enable = false; 2253 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2254 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2255 ? dmdata_dp 2256 : dmdata_hdmi; 2257 2258 /* if using dynamic meta, don't set up generic infopackets */ 2259 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2260 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2261 enable = true; 2262 } 2263 2264 if (!hubp) 2265 return; 2266 2267 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2268 return; 2269 2270 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2271 hubp->inst, mode); 2272 } 2273 2274 void dcn20_fpga_init_hw(struct dc *dc) 2275 { 2276 int i, j; 2277 struct dce_hwseq *hws = dc->hwseq; 2278 struct resource_pool *res_pool = dc->res_pool; 2279 struct dc_state *context = dc->current_state; 2280 2281 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2282 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2283 2284 // Initialize the dccg 2285 if (res_pool->dccg->funcs->dccg_init) 2286 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2287 2288 //Enable ability to power gate / don't force power on permanently 2289 hws->funcs.enable_power_gating_plane(hws, true); 2290 2291 // Specific to FPGA dccg and registers 2292 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2293 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2294 2295 hws->funcs.dccg_init(hws); 2296 2297 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2298 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2299 REG_WRITE(REFCLK_CNTL, 0); 2300 // 2301 2302 2303 /* Blank pixel data with OPP DPG */ 2304 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2305 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2306 2307 if (tg->funcs->is_tg_enabled(tg)) 2308 dcn20_init_blank(dc, tg); 2309 } 2310 2311 for (i = 0; i < res_pool->timing_generator_count; i++) { 2312 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2313 2314 if (tg->funcs->is_tg_enabled(tg)) 2315 tg->funcs->lock(tg); 2316 } 2317 2318 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2319 struct dpp *dpp = res_pool->dpps[i]; 2320 2321 dpp->funcs->dpp_reset(dpp); 2322 } 2323 2324 /* Reset all MPCC muxes */ 2325 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2326 2327 /* initialize OPP mpc_tree parameter */ 2328 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2329 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2330 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2331 for (j = 0; j < MAX_PIPES; j++) 2332 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2333 } 2334 2335 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2336 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2337 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2338 struct hubp *hubp = dc->res_pool->hubps[i]; 2339 struct dpp *dpp = dc->res_pool->dpps[i]; 2340 2341 pipe_ctx->stream_res.tg = tg; 2342 pipe_ctx->pipe_idx = i; 2343 2344 pipe_ctx->plane_res.hubp = hubp; 2345 pipe_ctx->plane_res.dpp = dpp; 2346 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2347 hubp->mpcc_id = dpp->inst; 2348 hubp->opp_id = OPP_ID_INVALID; 2349 hubp->power_gated = false; 2350 pipe_ctx->stream_res.opp = NULL; 2351 2352 hubp->funcs->hubp_init(hubp); 2353 2354 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2355 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2356 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2357 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2358 /*to do*/ 2359 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2360 } 2361 2362 /* initialize DWB pointer to MCIF_WB */ 2363 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2364 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2365 2366 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2367 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2368 2369 if (tg->funcs->is_tg_enabled(tg)) 2370 tg->funcs->unlock(tg); 2371 } 2372 2373 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2374 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2375 2376 dc->hwss.disable_plane(dc, pipe_ctx); 2377 2378 pipe_ctx->stream_res.tg = NULL; 2379 pipe_ctx->plane_res.hubp = NULL; 2380 } 2381 2382 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2383 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2384 2385 tg->funcs->tg_init(tg); 2386 } 2387 } 2388