1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #include <linux/delay.h> 26 27 #include "dm_services.h" 28 #include "basics/dc_common.h" 29 #include "dm_helpers.h" 30 #include "core_types.h" 31 #include "resource.h" 32 #include "dcn20_resource.h" 33 #include "dcn20_hwseq.h" 34 #include "dce/dce_hwseq.h" 35 #include "dcn20_dsc.h" 36 #include "dcn20_optc.h" 37 #include "abm.h" 38 #include "clk_mgr.h" 39 #include "dmcu.h" 40 #include "hubp.h" 41 #include "timing_generator.h" 42 #include "opp.h" 43 #include "ipp.h" 44 #include "mpc.h" 45 #include "mcif_wb.h" 46 #include "dchubbub.h" 47 #include "reg_helper.h" 48 #include "dcn10/dcn10_cm_common.h" 49 #include "dc_link_dp.h" 50 #include "vm_helper.h" 51 #include "dccg.h" 52 53 #define DC_LOGGER_INIT(logger) 54 55 #define CTX \ 56 hws->ctx 57 #define REG(reg)\ 58 hws->regs->reg 59 60 #undef FN 61 #define FN(reg_name, field_name) \ 62 hws->shifts->field_name, hws->masks->field_name 63 64 static int find_free_gsl_group(const struct dc *dc) 65 { 66 if (dc->res_pool->gsl_groups.gsl_0 == 0) 67 return 1; 68 if (dc->res_pool->gsl_groups.gsl_1 == 0) 69 return 2; 70 if (dc->res_pool->gsl_groups.gsl_2 == 0) 71 return 3; 72 73 return 0; 74 } 75 76 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) 77 * This is only used to lock pipes in pipe splitting case with immediate flip 78 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, 79 * so we get tearing with freesync since we cannot flip multiple pipes 80 * atomically. 81 * We use GSL for this: 82 * - immediate flip: find first available GSL group if not already assigned 83 * program gsl with that group, set current OTG as master 84 * and always us 0x4 = AND of flip_ready from all pipes 85 * - vsync flip: disable GSL if used 86 * 87 * Groups in stream_res are stored as +1 from HW registers, i.e. 88 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 89 * Using a magic value like -1 would require tracking all inits/resets 90 */ 91 static void dcn20_setup_gsl_group_as_lock( 92 const struct dc *dc, 93 struct pipe_ctx *pipe_ctx, 94 bool enable) 95 { 96 struct gsl_params gsl; 97 int group_idx; 98 99 memset(&gsl, 0, sizeof(struct gsl_params)); 100 101 if (enable) { 102 /* return if group already assigned since GSL was set up 103 * for vsync flip, we would unassign so it can't be "left over" 104 */ 105 if (pipe_ctx->stream_res.gsl_group > 0) 106 return; 107 108 group_idx = find_free_gsl_group(dc); 109 ASSERT(group_idx != 0); 110 pipe_ctx->stream_res.gsl_group = group_idx; 111 112 /* set gsl group reg field and mark resource used */ 113 switch (group_idx) { 114 case 1: 115 gsl.gsl0_en = 1; 116 dc->res_pool->gsl_groups.gsl_0 = 1; 117 break; 118 case 2: 119 gsl.gsl1_en = 1; 120 dc->res_pool->gsl_groups.gsl_1 = 1; 121 break; 122 case 3: 123 gsl.gsl2_en = 1; 124 dc->res_pool->gsl_groups.gsl_2 = 1; 125 break; 126 default: 127 BREAK_TO_DEBUGGER(); 128 return; // invalid case 129 } 130 gsl.gsl_master_en = 1; 131 } else { 132 group_idx = pipe_ctx->stream_res.gsl_group; 133 if (group_idx == 0) 134 return; // if not in use, just return 135 136 pipe_ctx->stream_res.gsl_group = 0; 137 138 /* unset gsl group reg field and mark resource free */ 139 switch (group_idx) { 140 case 1: 141 gsl.gsl0_en = 0; 142 dc->res_pool->gsl_groups.gsl_0 = 0; 143 break; 144 case 2: 145 gsl.gsl1_en = 0; 146 dc->res_pool->gsl_groups.gsl_1 = 0; 147 break; 148 case 3: 149 gsl.gsl2_en = 0; 150 dc->res_pool->gsl_groups.gsl_2 = 0; 151 break; 152 default: 153 BREAK_TO_DEBUGGER(); 154 return; 155 } 156 gsl.gsl_master_en = 0; 157 } 158 159 /* at this point we want to program whether it's to enable or disable */ 160 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && 161 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { 162 pipe_ctx->stream_res.tg->funcs->set_gsl( 163 pipe_ctx->stream_res.tg, 164 &gsl); 165 166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( 167 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); 168 } else 169 BREAK_TO_DEBUGGER(); 170 } 171 172 void dcn20_set_flip_control_gsl( 173 struct pipe_ctx *pipe_ctx, 174 bool flip_immediate) 175 { 176 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) 177 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( 178 pipe_ctx->plane_res.hubp, flip_immediate); 179 180 } 181 182 void dcn20_enable_power_gating_plane( 183 struct dce_hwseq *hws, 184 bool enable) 185 { 186 bool force_on = true; /* disable power gating */ 187 188 if (enable) 189 force_on = false; 190 191 /* DCHUBP0/1/2/3/4/5 */ 192 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); 193 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); 194 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); 195 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); 196 if (REG(DOMAIN8_PG_CONFIG)) 197 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 198 if (REG(DOMAIN10_PG_CONFIG)) 199 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); 200 201 /* DPP0/1/2/3/4/5 */ 202 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); 203 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); 204 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); 205 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); 206 if (REG(DOMAIN9_PG_CONFIG)) 207 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 208 if (REG(DOMAIN11_PG_CONFIG)) 209 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); 210 211 /* DCS0/1/2/3/4/5 */ 212 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); 213 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); 214 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); 215 if (REG(DOMAIN19_PG_CONFIG)) 216 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); 217 if (REG(DOMAIN20_PG_CONFIG)) 218 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); 219 if (REG(DOMAIN21_PG_CONFIG)) 220 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); 221 } 222 223 void dcn20_dccg_init(struct dce_hwseq *hws) 224 { 225 /* 226 * set MICROSECOND_TIME_BASE_DIV 227 * 100Mhz refclk -> 0x120264 228 * 27Mhz refclk -> 0x12021b 229 * 48Mhz refclk -> 0x120230 230 * 231 */ 232 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); 233 234 /* 235 * set MILLISECOND_TIME_BASE_DIV 236 * 100Mhz refclk -> 0x1186a0 237 * 27Mhz refclk -> 0x106978 238 * 48Mhz refclk -> 0x10bb80 239 * 240 */ 241 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); 242 243 /* This value is dependent on the hardware pipeline delay so set once per SOC */ 244 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); 245 } 246 247 void dcn20_disable_vga( 248 struct dce_hwseq *hws) 249 { 250 REG_WRITE(D1VGA_CONTROL, 0); 251 REG_WRITE(D2VGA_CONTROL, 0); 252 REG_WRITE(D3VGA_CONTROL, 0); 253 REG_WRITE(D4VGA_CONTROL, 0); 254 REG_WRITE(D5VGA_CONTROL, 0); 255 REG_WRITE(D6VGA_CONTROL, 0); 256 } 257 258 void dcn20_program_triple_buffer( 259 const struct dc *dc, 260 struct pipe_ctx *pipe_ctx, 261 bool enable_triple_buffer) 262 { 263 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { 264 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( 265 pipe_ctx->plane_res.hubp, 266 enable_triple_buffer); 267 } 268 } 269 270 /* Blank pixel data during initialization */ 271 void dcn20_init_blank( 272 struct dc *dc, 273 struct timing_generator *tg) 274 { 275 struct dce_hwseq *hws = dc->hwseq; 276 enum dc_color_space color_space; 277 struct tg_color black_color = {0}; 278 struct output_pixel_processor *opp = NULL; 279 struct output_pixel_processor *bottom_opp = NULL; 280 uint32_t num_opps, opp_id_src0, opp_id_src1; 281 uint32_t otg_active_width, otg_active_height; 282 283 /* program opp dpg blank color */ 284 color_space = COLOR_SPACE_SRGB; 285 color_space_to_black_color(dc, color_space, &black_color); 286 287 /* get the OTG active size */ 288 tg->funcs->get_otg_active_size(tg, 289 &otg_active_width, 290 &otg_active_height); 291 292 /* get the OPTC source */ 293 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); 294 295 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { 296 ASSERT(false); 297 return; 298 } 299 opp = dc->res_pool->opps[opp_id_src0]; 300 301 if (num_opps == 2) { 302 otg_active_width = otg_active_width / 2; 303 304 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { 305 ASSERT(false); 306 return; 307 } 308 bottom_opp = dc->res_pool->opps[opp_id_src1]; 309 } 310 311 opp->funcs->opp_set_disp_pattern_generator( 312 opp, 313 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 314 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 315 COLOR_DEPTH_UNDEFINED, 316 &black_color, 317 otg_active_width, 318 otg_active_height, 319 0); 320 321 if (num_opps == 2) { 322 bottom_opp->funcs->opp_set_disp_pattern_generator( 323 bottom_opp, 324 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, 325 CONTROLLER_DP_COLOR_SPACE_UDEFINED, 326 COLOR_DEPTH_UNDEFINED, 327 &black_color, 328 otg_active_width, 329 otg_active_height, 330 0); 331 } 332 333 hws->funcs.wait_for_blank_complete(opp); 334 } 335 336 void dcn20_dsc_pg_control( 337 struct dce_hwseq *hws, 338 unsigned int dsc_inst, 339 bool power_on) 340 { 341 uint32_t power_gate = power_on ? 0 : 1; 342 uint32_t pwr_status = power_on ? 0 : 2; 343 uint32_t org_ip_request_cntl = 0; 344 345 if (hws->ctx->dc->debug.disable_dsc_power_gate) 346 return; 347 348 if (REG(DOMAIN16_PG_CONFIG) == 0) 349 return; 350 351 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 352 if (org_ip_request_cntl == 0) 353 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 354 355 switch (dsc_inst) { 356 case 0: /* DSC0 */ 357 REG_UPDATE(DOMAIN16_PG_CONFIG, 358 DOMAIN16_POWER_GATE, power_gate); 359 360 REG_WAIT(DOMAIN16_PG_STATUS, 361 DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 362 1, 1000); 363 break; 364 case 1: /* DSC1 */ 365 REG_UPDATE(DOMAIN17_PG_CONFIG, 366 DOMAIN17_POWER_GATE, power_gate); 367 368 REG_WAIT(DOMAIN17_PG_STATUS, 369 DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 370 1, 1000); 371 break; 372 case 2: /* DSC2 */ 373 REG_UPDATE(DOMAIN18_PG_CONFIG, 374 DOMAIN18_POWER_GATE, power_gate); 375 376 REG_WAIT(DOMAIN18_PG_STATUS, 377 DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 378 1, 1000); 379 break; 380 case 3: /* DSC3 */ 381 REG_UPDATE(DOMAIN19_PG_CONFIG, 382 DOMAIN19_POWER_GATE, power_gate); 383 384 REG_WAIT(DOMAIN19_PG_STATUS, 385 DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 386 1, 1000); 387 break; 388 case 4: /* DSC4 */ 389 REG_UPDATE(DOMAIN20_PG_CONFIG, 390 DOMAIN20_POWER_GATE, power_gate); 391 392 REG_WAIT(DOMAIN20_PG_STATUS, 393 DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 394 1, 1000); 395 break; 396 case 5: /* DSC5 */ 397 REG_UPDATE(DOMAIN21_PG_CONFIG, 398 DOMAIN21_POWER_GATE, power_gate); 399 400 REG_WAIT(DOMAIN21_PG_STATUS, 401 DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 402 1, 1000); 403 break; 404 default: 405 BREAK_TO_DEBUGGER(); 406 break; 407 } 408 409 if (org_ip_request_cntl == 0) 410 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 411 } 412 413 void dcn20_dpp_pg_control( 414 struct dce_hwseq *hws, 415 unsigned int dpp_inst, 416 bool power_on) 417 { 418 uint32_t power_gate = power_on ? 0 : 1; 419 uint32_t pwr_status = power_on ? 0 : 2; 420 421 if (hws->ctx->dc->debug.disable_dpp_power_gate) 422 return; 423 if (REG(DOMAIN1_PG_CONFIG) == 0) 424 return; 425 426 switch (dpp_inst) { 427 case 0: /* DPP0 */ 428 REG_UPDATE(DOMAIN1_PG_CONFIG, 429 DOMAIN1_POWER_GATE, power_gate); 430 431 REG_WAIT(DOMAIN1_PG_STATUS, 432 DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 433 1, 1000); 434 break; 435 case 1: /* DPP1 */ 436 REG_UPDATE(DOMAIN3_PG_CONFIG, 437 DOMAIN3_POWER_GATE, power_gate); 438 439 REG_WAIT(DOMAIN3_PG_STATUS, 440 DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 441 1, 1000); 442 break; 443 case 2: /* DPP2 */ 444 REG_UPDATE(DOMAIN5_PG_CONFIG, 445 DOMAIN5_POWER_GATE, power_gate); 446 447 REG_WAIT(DOMAIN5_PG_STATUS, 448 DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 449 1, 1000); 450 break; 451 case 3: /* DPP3 */ 452 REG_UPDATE(DOMAIN7_PG_CONFIG, 453 DOMAIN7_POWER_GATE, power_gate); 454 455 REG_WAIT(DOMAIN7_PG_STATUS, 456 DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 457 1, 1000); 458 break; 459 case 4: /* DPP4 */ 460 REG_UPDATE(DOMAIN9_PG_CONFIG, 461 DOMAIN9_POWER_GATE, power_gate); 462 463 REG_WAIT(DOMAIN9_PG_STATUS, 464 DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 465 1, 1000); 466 break; 467 case 5: /* DPP5 */ 468 /* 469 * Do not power gate DPP5, should be left at HW default, power on permanently. 470 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 471 * reset. 472 * REG_UPDATE(DOMAIN11_PG_CONFIG, 473 * DOMAIN11_POWER_GATE, power_gate); 474 * 475 * REG_WAIT(DOMAIN11_PG_STATUS, 476 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 477 * 1, 1000); 478 */ 479 break; 480 default: 481 BREAK_TO_DEBUGGER(); 482 break; 483 } 484 } 485 486 487 void dcn20_hubp_pg_control( 488 struct dce_hwseq *hws, 489 unsigned int hubp_inst, 490 bool power_on) 491 { 492 uint32_t power_gate = power_on ? 0 : 1; 493 uint32_t pwr_status = power_on ? 0 : 2; 494 495 if (hws->ctx->dc->debug.disable_hubp_power_gate) 496 return; 497 if (REG(DOMAIN0_PG_CONFIG) == 0) 498 return; 499 500 switch (hubp_inst) { 501 case 0: /* DCHUBP0 */ 502 REG_UPDATE(DOMAIN0_PG_CONFIG, 503 DOMAIN0_POWER_GATE, power_gate); 504 505 REG_WAIT(DOMAIN0_PG_STATUS, 506 DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 507 1, 1000); 508 break; 509 case 1: /* DCHUBP1 */ 510 REG_UPDATE(DOMAIN2_PG_CONFIG, 511 DOMAIN2_POWER_GATE, power_gate); 512 513 REG_WAIT(DOMAIN2_PG_STATUS, 514 DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 515 1, 1000); 516 break; 517 case 2: /* DCHUBP2 */ 518 REG_UPDATE(DOMAIN4_PG_CONFIG, 519 DOMAIN4_POWER_GATE, power_gate); 520 521 REG_WAIT(DOMAIN4_PG_STATUS, 522 DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 523 1, 1000); 524 break; 525 case 3: /* DCHUBP3 */ 526 REG_UPDATE(DOMAIN6_PG_CONFIG, 527 DOMAIN6_POWER_GATE, power_gate); 528 529 REG_WAIT(DOMAIN6_PG_STATUS, 530 DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 531 1, 1000); 532 break; 533 case 4: /* DCHUBP4 */ 534 REG_UPDATE(DOMAIN8_PG_CONFIG, 535 DOMAIN8_POWER_GATE, power_gate); 536 537 REG_WAIT(DOMAIN8_PG_STATUS, 538 DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 539 1, 1000); 540 break; 541 case 5: /* DCHUBP5 */ 542 /* 543 * Do not power gate DCHUB5, should be left at HW default, power on permanently. 544 * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard 545 * reset. 546 * REG_UPDATE(DOMAIN10_PG_CONFIG, 547 * DOMAIN10_POWER_GATE, power_gate); 548 * 549 * REG_WAIT(DOMAIN10_PG_STATUS, 550 * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, 551 * 1, 1000); 552 */ 553 break; 554 default: 555 BREAK_TO_DEBUGGER(); 556 break; 557 } 558 } 559 560 561 /* disable HW used by plane. 562 * note: cannot disable until disconnect is complete 563 */ 564 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) 565 { 566 struct dce_hwseq *hws = dc->hwseq; 567 struct hubp *hubp = pipe_ctx->plane_res.hubp; 568 struct dpp *dpp = pipe_ctx->plane_res.dpp; 569 570 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); 571 572 /* In flip immediate with pipe splitting case GSL is used for 573 * synchronization so we must disable it when the plane is disabled. 574 */ 575 if (pipe_ctx->stream_res.gsl_group != 0) 576 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false); 577 578 dc->hwss.set_flip_control_gsl(pipe_ctx, false); 579 580 hubp->funcs->hubp_clk_cntl(hubp, false); 581 582 dpp->funcs->dpp_dppclk_control(dpp, false, false); 583 584 hubp->power_gated = true; 585 586 hws->funcs.plane_atomic_power_down(dc, 587 pipe_ctx->plane_res.dpp, 588 pipe_ctx->plane_res.hubp); 589 590 pipe_ctx->stream = NULL; 591 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res)); 592 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res)); 593 pipe_ctx->top_pipe = NULL; 594 pipe_ctx->bottom_pipe = NULL; 595 pipe_ctx->plane_state = NULL; 596 } 597 598 599 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) 600 { 601 DC_LOGGER_INIT(dc->ctx->logger); 602 603 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) 604 return; 605 606 dcn20_plane_atomic_disable(dc, pipe_ctx); 607 608 DC_LOG_DC("Power down front end %d\n", 609 pipe_ctx->pipe_idx); 610 } 611 612 enum dc_status dcn20_enable_stream_timing( 613 struct pipe_ctx *pipe_ctx, 614 struct dc_state *context, 615 struct dc *dc) 616 { 617 struct dce_hwseq *hws = dc->hwseq; 618 struct dc_stream_state *stream = pipe_ctx->stream; 619 struct drr_params params = {0}; 620 unsigned int event_triggers = 0; 621 struct pipe_ctx *odm_pipe; 622 int opp_cnt = 1; 623 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 624 625 /* by upper caller loop, pipe0 is parent pipe and be called first. 626 * back end is set up by for pipe0. Other children pipe share back end 627 * with pipe 0. No program is needed. 628 */ 629 if (pipe_ctx->top_pipe != NULL) 630 return DC_OK; 631 632 /* TODO check if timing_changed, disable stream if timing changed */ 633 634 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 635 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 636 opp_cnt++; 637 } 638 639 if (opp_cnt > 1) 640 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 641 pipe_ctx->stream_res.tg, 642 opp_inst, opp_cnt, 643 &pipe_ctx->stream->timing); 644 645 /* HW program guide assume display already disable 646 * by unplug sequence. OTG assume stop. 647 */ 648 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); 649 650 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 651 pipe_ctx->clock_source, 652 &pipe_ctx->stream_res.pix_clk_params, 653 &pipe_ctx->pll_settings)) { 654 BREAK_TO_DEBUGGER(); 655 return DC_ERROR_UNEXPECTED; 656 } 657 658 if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) 659 dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); 660 661 pipe_ctx->stream_res.tg->funcs->program_timing( 662 pipe_ctx->stream_res.tg, 663 &stream->timing, 664 pipe_ctx->pipe_dlg_param.vready_offset, 665 pipe_ctx->pipe_dlg_param.vstartup_start, 666 pipe_ctx->pipe_dlg_param.vupdate_offset, 667 pipe_ctx->pipe_dlg_param.vupdate_width, 668 pipe_ctx->stream->signal, 669 true); 670 671 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 672 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( 673 odm_pipe->stream_res.opp, 674 true); 675 676 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 677 pipe_ctx->stream_res.opp, 678 true); 679 680 hws->funcs.blank_pixel_data(dc, pipe_ctx, true); 681 682 /* VTG is within DCHUB command block. DCFCLK is always on */ 683 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { 684 BREAK_TO_DEBUGGER(); 685 return DC_ERROR_UNEXPECTED; 686 } 687 688 hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); 689 690 params.vertical_total_min = stream->adjust.v_total_min; 691 params.vertical_total_max = stream->adjust.v_total_max; 692 params.vertical_total_mid = stream->adjust.v_total_mid; 693 params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; 694 if (pipe_ctx->stream_res.tg->funcs->set_drr) 695 pipe_ctx->stream_res.tg->funcs->set_drr( 696 pipe_ctx->stream_res.tg, ¶ms); 697 698 // DRR should set trigger event to monitor surface update event 699 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 700 event_triggers = 0x80; 701 /* Event triggers and num frames initialized for DRR, but can be 702 * later updated for PSR use. Note DRR trigger events are generated 703 * regardless of whether num frames met. 704 */ 705 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 706 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 707 pipe_ctx->stream_res.tg, event_triggers, 2); 708 709 /* TODO program crtc source select for non-virtual signal*/ 710 /* TODO program FMT */ 711 /* TODO setup link_enc */ 712 /* TODO set stream attributes */ 713 /* TODO program audio */ 714 /* TODO enable stream if timing changed */ 715 /* TODO unblank stream if DP */ 716 717 return DC_OK; 718 } 719 720 void dcn20_program_output_csc(struct dc *dc, 721 struct pipe_ctx *pipe_ctx, 722 enum dc_color_space colorspace, 723 uint16_t *matrix, 724 int opp_id) 725 { 726 struct mpc *mpc = dc->res_pool->mpc; 727 enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; 728 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 729 730 if (mpc->funcs->power_on_mpc_mem_pwr) 731 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 732 733 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 734 if (mpc->funcs->set_output_csc != NULL) 735 mpc->funcs->set_output_csc(mpc, 736 opp_id, 737 matrix, 738 ocsc_mode); 739 } else { 740 if (mpc->funcs->set_ocsc_default != NULL) 741 mpc->funcs->set_ocsc_default(mpc, 742 opp_id, 743 colorspace, 744 ocsc_mode); 745 } 746 } 747 748 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 749 const struct dc_stream_state *stream) 750 { 751 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 752 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 753 struct pwl_params *params = NULL; 754 /* 755 * program OGAM only for the top pipe 756 * if there is a pipe split then fix diagnostic is required: 757 * how to pass OGAM parameter for stream. 758 * if programming for all pipes is required then remove condition 759 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. 760 */ 761 if (mpc->funcs->power_on_mpc_mem_pwr) 762 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true); 763 if (pipe_ctx->top_pipe == NULL 764 && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 765 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 766 params = &stream->out_transfer_func->pwl; 767 else if (pipe_ctx->stream->out_transfer_func->type == 768 TF_TYPE_DISTRIBUTED_POINTS && 769 cm_helper_translate_curve_to_hw_format( 770 stream->out_transfer_func, 771 &mpc->blender_params, false)) 772 params = &mpc->blender_params; 773 /* 774 * there is no ROM 775 */ 776 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 777 BREAK_TO_DEBUGGER(); 778 } 779 /* 780 * if above if is not executed then 'params' equal to 0 and set in bypass 781 */ 782 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 783 784 return true; 785 } 786 787 bool dcn20_set_blend_lut( 788 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 789 { 790 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 791 bool result = true; 792 struct pwl_params *blend_lut = NULL; 793 794 if (plane_state->blend_tf) { 795 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 796 blend_lut = &plane_state->blend_tf->pwl; 797 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 798 cm_helper_translate_curve_to_hw_format( 799 plane_state->blend_tf, 800 &dpp_base->regamma_params, false); 801 blend_lut = &dpp_base->regamma_params; 802 } 803 } 804 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 805 806 return result; 807 } 808 809 bool dcn20_set_shaper_3dlut( 810 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 811 { 812 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 813 bool result = true; 814 struct pwl_params *shaper_lut = NULL; 815 816 if (plane_state->in_shaper_func) { 817 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) 818 shaper_lut = &plane_state->in_shaper_func->pwl; 819 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { 820 cm_helper_translate_curve_to_hw_format( 821 plane_state->in_shaper_func, 822 &dpp_base->shaper_params, true); 823 shaper_lut = &dpp_base->shaper_params; 824 } 825 } 826 827 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); 828 if (plane_state->lut3d_func && 829 plane_state->lut3d_func->state.bits.initialized == 1) 830 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, 831 &plane_state->lut3d_func->lut_3d); 832 else 833 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); 834 835 return result; 836 } 837 838 bool dcn20_set_input_transfer_func(struct dc *dc, 839 struct pipe_ctx *pipe_ctx, 840 const struct dc_plane_state *plane_state) 841 { 842 struct dce_hwseq *hws = dc->hwseq; 843 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 844 const struct dc_transfer_func *tf = NULL; 845 bool result = true; 846 bool use_degamma_ram = false; 847 848 if (dpp_base == NULL || plane_state == NULL) 849 return false; 850 851 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 852 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 853 854 if (plane_state->in_transfer_func) 855 tf = plane_state->in_transfer_func; 856 857 858 if (tf == NULL) { 859 dpp_base->funcs->dpp_set_degamma(dpp_base, 860 IPP_DEGAMMA_MODE_BYPASS); 861 return true; 862 } 863 864 if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) 865 use_degamma_ram = true; 866 867 if (use_degamma_ram == true) { 868 if (tf->type == TF_TYPE_HWPWL) 869 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 870 &tf->pwl); 871 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 872 cm_helper_translate_curve_to_degamma_hw_format(tf, 873 &dpp_base->degamma_params); 874 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, 875 &dpp_base->degamma_params); 876 } 877 return true; 878 } 879 /* handle here the optimized cases when de-gamma ROM could be used. 880 * 881 */ 882 if (tf->type == TF_TYPE_PREDEFINED) { 883 switch (tf->tf) { 884 case TRANSFER_FUNCTION_SRGB: 885 dpp_base->funcs->dpp_set_degamma(dpp_base, 886 IPP_DEGAMMA_MODE_HW_sRGB); 887 break; 888 case TRANSFER_FUNCTION_BT709: 889 dpp_base->funcs->dpp_set_degamma(dpp_base, 890 IPP_DEGAMMA_MODE_HW_xvYCC); 891 break; 892 case TRANSFER_FUNCTION_LINEAR: 893 dpp_base->funcs->dpp_set_degamma(dpp_base, 894 IPP_DEGAMMA_MODE_BYPASS); 895 break; 896 case TRANSFER_FUNCTION_PQ: 897 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); 898 cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); 899 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); 900 result = true; 901 break; 902 default: 903 result = false; 904 break; 905 } 906 } else if (tf->type == TF_TYPE_BYPASS) 907 dpp_base->funcs->dpp_set_degamma(dpp_base, 908 IPP_DEGAMMA_MODE_BYPASS); 909 else { 910 /* 911 * if we are here, we did not handle correctly. 912 * fix is required for this use case 913 */ 914 BREAK_TO_DEBUGGER(); 915 dpp_base->funcs->dpp_set_degamma(dpp_base, 916 IPP_DEGAMMA_MODE_BYPASS); 917 } 918 919 return result; 920 } 921 922 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) 923 { 924 struct pipe_ctx *odm_pipe; 925 int opp_cnt = 1; 926 int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst }; 927 928 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 929 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; 930 opp_cnt++; 931 } 932 933 if (opp_cnt > 1) 934 pipe_ctx->stream_res.tg->funcs->set_odm_combine( 935 pipe_ctx->stream_res.tg, 936 opp_inst, opp_cnt, 937 &pipe_ctx->stream->timing); 938 else 939 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 940 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 941 } 942 943 void dcn20_blank_pixel_data( 944 struct dc *dc, 945 struct pipe_ctx *pipe_ctx, 946 bool blank) 947 { 948 struct tg_color black_color = {0}; 949 struct stream_resource *stream_res = &pipe_ctx->stream_res; 950 struct dc_stream_state *stream = pipe_ctx->stream; 951 enum dc_color_space color_space = stream->output_color_space; 952 enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; 953 enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; 954 struct pipe_ctx *odm_pipe; 955 int odm_cnt = 1; 956 957 int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 958 int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; 959 960 if (stream->link->test_pattern_enabled) 961 return; 962 963 /* get opp dpg blank color */ 964 color_space_to_black_color(dc, color_space, &black_color); 965 966 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 967 odm_cnt++; 968 969 width = width / odm_cnt; 970 971 if (blank) { 972 dc->hwss.set_abm_immediate_disable(pipe_ctx); 973 974 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { 975 test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; 976 test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; 977 } 978 } else { 979 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; 980 } 981 982 stream_res->opp->funcs->opp_set_disp_pattern_generator( 983 stream_res->opp, 984 test_pattern, 985 test_pattern_color_space, 986 stream->timing.display_color_depth, 987 &black_color, 988 width, 989 height, 990 0); 991 992 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 993 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator( 994 odm_pipe->stream_res.opp, 995 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? 996 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, 997 test_pattern_color_space, 998 stream->timing.display_color_depth, 999 &black_color, 1000 width, 1001 height, 1002 0); 1003 } 1004 1005 if (!blank) 1006 if (stream_res->abm) { 1007 dc->hwss.set_pipe(pipe_ctx); 1008 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); 1009 } 1010 } 1011 1012 1013 static void dcn20_power_on_plane( 1014 struct dce_hwseq *hws, 1015 struct pipe_ctx *pipe_ctx) 1016 { 1017 DC_LOGGER_INIT(hws->ctx->logger); 1018 if (REG(DC_IP_REQUEST_CNTL)) { 1019 REG_SET(DC_IP_REQUEST_CNTL, 0, 1020 IP_REQUEST_EN, 1); 1021 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true); 1022 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true); 1023 REG_SET(DC_IP_REQUEST_CNTL, 0, 1024 IP_REQUEST_EN, 0); 1025 DC_LOG_DEBUG( 1026 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst); 1027 } 1028 } 1029 1030 void dcn20_enable_plane( 1031 struct dc *dc, 1032 struct pipe_ctx *pipe_ctx, 1033 struct dc_state *context) 1034 { 1035 //if (dc->debug.sanity_checks) { 1036 // dcn10_verify_allow_pstate_change_high(dc); 1037 //} 1038 dcn20_power_on_plane(dc->hwseq, pipe_ctx); 1039 1040 /* enable DCFCLK current DCHUB */ 1041 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); 1042 1043 /* initialize HUBP on power up */ 1044 pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); 1045 1046 /* make sure OPP_PIPE_CLOCK_EN = 1 */ 1047 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( 1048 pipe_ctx->stream_res.opp, 1049 true); 1050 1051 /* TODO: enable/disable in dm as per update type. 1052 if (plane_state) { 1053 DC_LOG_DC(dc->ctx->logger, 1054 "Pipe:%d 0x%x: addr hi:0x%x, " 1055 "addr low:0x%x, " 1056 "src: %d, %d, %d," 1057 " %d; dst: %d, %d, %d, %d;\n", 1058 pipe_ctx->pipe_idx, 1059 plane_state, 1060 plane_state->address.grph.addr.high_part, 1061 plane_state->address.grph.addr.low_part, 1062 plane_state->src_rect.x, 1063 plane_state->src_rect.y, 1064 plane_state->src_rect.width, 1065 plane_state->src_rect.height, 1066 plane_state->dst_rect.x, 1067 plane_state->dst_rect.y, 1068 plane_state->dst_rect.width, 1069 plane_state->dst_rect.height); 1070 1071 DC_LOG_DC(dc->ctx->logger, 1072 "Pipe %d: width, height, x, y format:%d\n" 1073 "viewport:%d, %d, %d, %d\n" 1074 "recout: %d, %d, %d, %d\n", 1075 pipe_ctx->pipe_idx, 1076 plane_state->format, 1077 pipe_ctx->plane_res.scl_data.viewport.width, 1078 pipe_ctx->plane_res.scl_data.viewport.height, 1079 pipe_ctx->plane_res.scl_data.viewport.x, 1080 pipe_ctx->plane_res.scl_data.viewport.y, 1081 pipe_ctx->plane_res.scl_data.recout.width, 1082 pipe_ctx->plane_res.scl_data.recout.height, 1083 pipe_ctx->plane_res.scl_data.recout.x, 1084 pipe_ctx->plane_res.scl_data.recout.y); 1085 print_rq_dlg_ttu(dc, pipe_ctx); 1086 } 1087 */ 1088 if (dc->vm_pa_config.valid) { 1089 struct vm_system_aperture_param apt; 1090 1091 apt.sys_default.quad_part = 0; 1092 1093 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; 1094 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; 1095 1096 // Program system aperture settings 1097 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); 1098 } 1099 1100 // if (dc->debug.sanity_checks) { 1101 // dcn10_verify_allow_pstate_change_high(dc); 1102 // } 1103 } 1104 1105 void dcn20_pipe_control_lock( 1106 struct dc *dc, 1107 struct pipe_ctx *pipe, 1108 bool lock) 1109 { 1110 bool flip_immediate = false; 1111 1112 /* use TG master update lock to lock everything on the TG 1113 * therefore only top pipe need to lock 1114 */ 1115 if (!pipe || pipe->top_pipe) 1116 return; 1117 1118 if (pipe->plane_state != NULL) 1119 flip_immediate = pipe->plane_state->flip_immediate; 1120 1121 if (flip_immediate && lock) { 1122 const int TIMEOUT_FOR_FLIP_PENDING = 100000; 1123 int i; 1124 1125 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1126 if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) 1127 break; 1128 udelay(1); 1129 } 1130 1131 if (pipe->bottom_pipe != NULL) { 1132 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { 1133 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp)) 1134 break; 1135 udelay(1); 1136 } 1137 } 1138 } 1139 1140 /* In flip immediate and pipe splitting case, we need to use GSL 1141 * for synchronization. Only do setup on locking and on flip type change. 1142 */ 1143 if (lock && pipe->bottom_pipe != NULL) 1144 if ((flip_immediate && pipe->stream_res.gsl_group == 0) || 1145 (!flip_immediate && pipe->stream_res.gsl_group > 0)) 1146 dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); 1147 1148 if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { 1149 if (lock) 1150 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); 1151 else 1152 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); 1153 } else { 1154 if (lock) 1155 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); 1156 else 1157 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); 1158 } 1159 } 1160 1161 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) 1162 { 1163 bool plane_state_update = false; 1164 new_pipe->update_flags.raw = 0; 1165 1166 /* Exit on unchanged, unused pipe */ 1167 if (!old_pipe->plane_state && !new_pipe->plane_state) 1168 return; 1169 1170 /* Detect plane state update */ 1171 if (old_pipe->plane_state && new_pipe->plane_state 1172 && (old_pipe->plane_state != new_pipe->plane_state)) { 1173 plane_state_update = true; 1174 } 1175 /* Detect pipe enable/disable */ 1176 if ((!old_pipe->plane_state && new_pipe->plane_state) || plane_state_update) { 1177 new_pipe->update_flags.bits.enable = 1; 1178 new_pipe->update_flags.bits.mpcc = 1; 1179 new_pipe->update_flags.bits.dppclk = 1; 1180 new_pipe->update_flags.bits.hubp_interdependent = 1; 1181 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1182 new_pipe->update_flags.bits.gamut_remap = 1; 1183 new_pipe->update_flags.bits.scaler = 1; 1184 new_pipe->update_flags.bits.viewport = 1; 1185 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1186 new_pipe->update_flags.bits.odm = 1; 1187 new_pipe->update_flags.bits.global_sync = 1; 1188 } 1189 return; 1190 } 1191 if (old_pipe->plane_state && !new_pipe->plane_state) { 1192 new_pipe->update_flags.bits.disable = 1; 1193 return; 1194 } 1195 1196 /* Detect top pipe only changes */ 1197 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { 1198 /* Detect odm changes */ 1199 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe 1200 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) 1201 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) 1202 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) 1203 || old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1204 new_pipe->update_flags.bits.odm = 1; 1205 1206 /* Detect global sync changes */ 1207 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset 1208 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start 1209 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset 1210 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) 1211 new_pipe->update_flags.bits.global_sync = 1; 1212 } 1213 1214 /* 1215 * Detect opp / tg change, only set on change, not on enable 1216 * Assume mpcc inst = pipe index, if not this code needs to be updated 1217 * since mpcc is what is affected by these. In fact all of our sequence 1218 * makes this assumption at the moment with how hubp reset is matched to 1219 * same index mpcc reset. 1220 */ 1221 if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) 1222 new_pipe->update_flags.bits.opp_changed = 1; 1223 if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) 1224 new_pipe->update_flags.bits.tg_changed = 1; 1225 1226 /* Detect mpcc blending changes, only dpp inst and bot matter here */ 1227 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp 1228 || old_pipe->stream_res.opp != new_pipe->stream_res.opp 1229 || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe) 1230 || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe) 1231 || (old_pipe->bottom_pipe && new_pipe->bottom_pipe 1232 && old_pipe->bottom_pipe->plane_res.mpcc_inst 1233 != new_pipe->bottom_pipe->plane_res.mpcc_inst)) 1234 new_pipe->update_flags.bits.mpcc = 1; 1235 1236 /* Detect dppclk change */ 1237 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1238 new_pipe->update_flags.bits.dppclk = 1; 1239 1240 /* Check for scl update */ 1241 if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))) 1242 new_pipe->update_flags.bits.scaler = 1; 1243 /* Check for vp update */ 1244 if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect)) 1245 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, 1246 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) 1247 new_pipe->update_flags.bits.viewport = 1; 1248 1249 /* Detect dlg/ttu/rq updates */ 1250 { 1251 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; 1252 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; 1253 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; 1254 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; 1255 1256 /* Detect pipe interdependent updates */ 1257 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || 1258 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || 1259 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || 1260 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || 1261 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || 1262 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || 1263 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || 1264 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || 1265 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || 1266 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || 1267 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || 1268 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || 1269 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || 1270 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || 1271 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || 1272 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || 1273 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || 1274 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { 1275 old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; 1276 old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; 1277 old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; 1278 old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; 1279 old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; 1280 old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; 1281 old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; 1282 old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; 1283 old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; 1284 old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; 1285 old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; 1286 old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; 1287 old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; 1288 old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; 1289 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; 1290 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; 1291 old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; 1292 old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; 1293 new_pipe->update_flags.bits.hubp_interdependent = 1; 1294 } 1295 /* Detect any other updates to ttu/rq/dlg */ 1296 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) || 1297 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) || 1298 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))) 1299 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; 1300 } 1301 } 1302 1303 static void dcn20_update_dchubp_dpp( 1304 struct dc *dc, 1305 struct pipe_ctx *pipe_ctx, 1306 struct dc_state *context) 1307 { 1308 struct dce_hwseq *hws = dc->hwseq; 1309 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1310 struct dpp *dpp = pipe_ctx->plane_res.dpp; 1311 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1312 bool viewport_changed = false; 1313 1314 if (pipe_ctx->update_flags.bits.dppclk) 1315 dpp->funcs->dpp_dppclk_control(dpp, false, true); 1316 1317 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG 1318 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. 1319 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG 1320 */ 1321 if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { 1322 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); 1323 1324 hubp->funcs->hubp_setup( 1325 hubp, 1326 &pipe_ctx->dlg_regs, 1327 &pipe_ctx->ttu_regs, 1328 &pipe_ctx->rq_regs, 1329 &pipe_ctx->pipe_dlg_param); 1330 } 1331 if (pipe_ctx->update_flags.bits.hubp_interdependent) 1332 hubp->funcs->hubp_setup_interdependent( 1333 hubp, 1334 &pipe_ctx->dlg_regs, 1335 &pipe_ctx->ttu_regs); 1336 1337 if (pipe_ctx->update_flags.bits.enable || 1338 plane_state->update_flags.bits.bpp_change || 1339 plane_state->update_flags.bits.input_csc_change || 1340 plane_state->update_flags.bits.color_space_change || 1341 plane_state->update_flags.bits.coeff_reduction_change) { 1342 struct dc_bias_and_scale bns_params = {0}; 1343 1344 // program the input csc 1345 dpp->funcs->dpp_setup(dpp, 1346 plane_state->format, 1347 EXPANSION_MODE_ZERO, 1348 plane_state->input_csc_color_matrix, 1349 plane_state->color_space, 1350 NULL); 1351 1352 if (dpp->funcs->dpp_program_bias_and_scale) { 1353 //TODO :for CNVC set scale and bias registers if necessary 1354 build_prescale_params(&bns_params, plane_state); 1355 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); 1356 } 1357 } 1358 1359 if (pipe_ctx->update_flags.bits.mpcc 1360 || plane_state->update_flags.bits.global_alpha_change 1361 || plane_state->update_flags.bits.per_pixel_alpha_change) { 1362 // MPCC inst is equal to pipe index in practice 1363 int mpcc_inst = hubp->inst; 1364 int opp_inst; 1365 int opp_count = dc->res_pool->pipe_count; 1366 1367 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { 1368 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { 1369 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); 1370 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; 1371 break; 1372 } 1373 } 1374 hws->funcs.update_mpcc(dc, pipe_ctx); 1375 } 1376 1377 if (pipe_ctx->update_flags.bits.scaler || 1378 plane_state->update_flags.bits.scaling_change || 1379 plane_state->update_flags.bits.position_change || 1380 plane_state->update_flags.bits.per_pixel_alpha_change || 1381 pipe_ctx->stream->update_flags.bits.scaling) { 1382 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; 1383 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP); 1384 /* scaler configuration */ 1385 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( 1386 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); 1387 } 1388 1389 if (pipe_ctx->update_flags.bits.viewport || 1390 (context == dc->current_state && plane_state->update_flags.bits.position_change) || 1391 (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || 1392 (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { 1393 1394 hubp->funcs->mem_program_viewport( 1395 hubp, 1396 &pipe_ctx->plane_res.scl_data.viewport, 1397 &pipe_ctx->plane_res.scl_data.viewport_c); 1398 viewport_changed = true; 1399 } 1400 1401 /* Any updates are handled in dc interface, just need to apply existing for plane enable */ 1402 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || 1403 pipe_ctx->update_flags.bits.scaler || pipe_ctx->update_flags.bits.viewport) 1404 && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { 1405 dc->hwss.set_cursor_position(pipe_ctx); 1406 dc->hwss.set_cursor_attribute(pipe_ctx); 1407 1408 if (dc->hwss.set_cursor_sdr_white_level) 1409 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 1410 } 1411 1412 /* Any updates are handled in dc interface, just need 1413 * to apply existing for plane enable / opp change */ 1414 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed 1415 || pipe_ctx->stream->update_flags.bits.gamut_remap 1416 || pipe_ctx->stream->update_flags.bits.out_csc) { 1417 /* dpp/cm gamut remap*/ 1418 dc->hwss.program_gamut_remap(pipe_ctx); 1419 1420 /*call the dcn2 method which uses mpc csc*/ 1421 dc->hwss.program_output_csc(dc, 1422 pipe_ctx, 1423 pipe_ctx->stream->output_color_space, 1424 pipe_ctx->stream->csc_color_matrix.matrix, 1425 hubp->opp_id); 1426 } 1427 1428 if (pipe_ctx->update_flags.bits.enable || 1429 pipe_ctx->update_flags.bits.opp_changed || 1430 plane_state->update_flags.bits.pixel_format_change || 1431 plane_state->update_flags.bits.horizontal_mirror_change || 1432 plane_state->update_flags.bits.rotation_change || 1433 plane_state->update_flags.bits.swizzle_change || 1434 plane_state->update_flags.bits.dcc_change || 1435 plane_state->update_flags.bits.bpp_change || 1436 plane_state->update_flags.bits.scaling_change || 1437 plane_state->update_flags.bits.plane_size_change) { 1438 struct plane_size size = plane_state->plane_size; 1439 1440 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; 1441 hubp->funcs->hubp_program_surface_config( 1442 hubp, 1443 plane_state->format, 1444 &plane_state->tiling_info, 1445 &size, 1446 plane_state->rotation, 1447 &plane_state->dcc, 1448 plane_state->horizontal_mirror, 1449 0); 1450 hubp->power_gated = false; 1451 } 1452 1453 if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update) 1454 hws->funcs.update_plane_addr(dc, pipe_ctx); 1455 1456 1457 1458 if (pipe_ctx->update_flags.bits.enable) 1459 hubp->funcs->set_blank(hubp, false); 1460 } 1461 1462 1463 static void dcn20_program_pipe( 1464 struct dc *dc, 1465 struct pipe_ctx *pipe_ctx, 1466 struct dc_state *context) 1467 { 1468 struct dce_hwseq *hws = dc->hwseq; 1469 /* Only need to unblank on top pipe */ 1470 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) 1471 && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) 1472 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); 1473 1474 if (pipe_ctx->update_flags.bits.global_sync) { 1475 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1476 pipe_ctx->stream_res.tg, 1477 pipe_ctx->pipe_dlg_param.vready_offset, 1478 pipe_ctx->pipe_dlg_param.vstartup_start, 1479 pipe_ctx->pipe_dlg_param.vupdate_offset, 1480 pipe_ctx->pipe_dlg_param.vupdate_width); 1481 1482 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1483 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1484 1485 if (hws->funcs.setup_vupdate_interrupt) 1486 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1487 } 1488 1489 if (pipe_ctx->update_flags.bits.odm) 1490 hws->funcs.update_odm(dc, context, pipe_ctx); 1491 1492 if (pipe_ctx->update_flags.bits.enable) { 1493 dcn20_enable_plane(dc, pipe_ctx, context); 1494 if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) 1495 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); 1496 } 1497 1498 if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) 1499 dcn20_update_dchubp_dpp(dc, pipe_ctx, context); 1500 1501 if (pipe_ctx->update_flags.bits.enable 1502 || pipe_ctx->plane_state->update_flags.bits.hdr_mult) 1503 hws->funcs.set_hdr_multiplier(pipe_ctx); 1504 1505 if (pipe_ctx->update_flags.bits.enable || 1506 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 1507 pipe_ctx->plane_state->update_flags.bits.gamma_change) 1508 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 1509 1510 /* dcn10_translate_regamma_to_hw_format takes 750us to finish 1511 * only do gamma programming for powering on, internal memcmp to avoid 1512 * updating on slave planes 1513 */ 1514 if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) 1515 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 1516 1517 /* If the pipe has been enabled or has a different opp, we 1518 * should reprogram the fmt. This deals with cases where 1519 * interation between mpc and odm combine on different streams 1520 * causes a different pipe to be chosen to odm combine with. 1521 */ 1522 if (pipe_ctx->update_flags.bits.enable 1523 || pipe_ctx->update_flags.bits.opp_changed) { 1524 1525 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1526 pipe_ctx->stream_res.opp, 1527 COLOR_SPACE_YCBCR601, 1528 pipe_ctx->stream->timing.display_color_depth, 1529 pipe_ctx->stream->signal); 1530 1531 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1532 pipe_ctx->stream_res.opp, 1533 &pipe_ctx->stream->bit_depth_params, 1534 &pipe_ctx->stream->clamping); 1535 } 1536 } 1537 1538 void dcn20_program_front_end_for_ctx( 1539 struct dc *dc, 1540 struct dc_state *context) 1541 { 1542 int i; 1543 struct dce_hwseq *hws = dc->hwseq; 1544 DC_LOGGER_INIT(dc->ctx->logger); 1545 1546 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1547 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1548 1549 if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { 1550 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); 1551 if (dc->hwss.program_triplebuffer != NULL && 1552 !dc->debug.disable_tri_buf) { 1553 /*turn off triple buffer for full update*/ 1554 dc->hwss.program_triplebuffer( 1555 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); 1556 } 1557 } 1558 } 1559 1560 /* Set pipe update flags and lock pipes */ 1561 for (i = 0; i < dc->res_pool->pipe_count; i++) 1562 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], 1563 &context->res_ctx.pipe_ctx[i]); 1564 1565 /* OTG blank before disabling all front ends */ 1566 for (i = 0; i < dc->res_pool->pipe_count; i++) 1567 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1568 && !context->res_ctx.pipe_ctx[i].top_pipe 1569 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe 1570 && context->res_ctx.pipe_ctx[i].stream) 1571 hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true); 1572 1573 /* Disconnect mpcc */ 1574 for (i = 0; i < dc->res_pool->pipe_count; i++) 1575 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable 1576 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { 1577 hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1578 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); 1579 } 1580 1581 /* 1582 * Program all updated pipes, order matters for mpcc setup. Start with 1583 * top pipe and program all pipes that follow in order 1584 */ 1585 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1586 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1587 1588 if (pipe->plane_state && !pipe->top_pipe) { 1589 while (pipe) { 1590 dcn20_program_pipe(dc, pipe, context); 1591 pipe = pipe->bottom_pipe; 1592 } 1593 /* Program secondary blending tree and writeback pipes */ 1594 pipe = &context->res_ctx.pipe_ctx[i]; 1595 if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0 1596 && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw) 1597 && hws->funcs.program_all_writeback_pipes_in_tree) 1598 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); 1599 } 1600 } 1601 } 1602 1603 void dcn20_post_unlock_program_front_end( 1604 struct dc *dc, 1605 struct dc_state *context) 1606 { 1607 int i; 1608 const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; 1609 struct dce_hwseq *hwseq = dc->hwseq; 1610 1611 DC_LOGGER_INIT(dc->ctx->logger); 1612 1613 for (i = 0; i < dc->res_pool->pipe_count; i++) 1614 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) 1615 dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); 1616 1617 /* 1618 * If we are enabling a pipe, we need to wait for pending clear as this is a critical 1619 * part of the enable operation otherwise, DM may request an immediate flip which 1620 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which 1621 * is unsupported on DCN. 1622 */ 1623 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1624 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1625 1626 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) { 1627 struct hubp *hubp = pipe->plane_res.hubp; 1628 int j = 0; 1629 1630 for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 1631 && hubp->funcs->hubp_is_flip_pending(hubp); j++) 1632 mdelay(1); 1633 } 1634 } 1635 1636 /* WA to apply WM setting*/ 1637 if (hwseq->wa.DEGVIDCN21) 1638 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); 1639 1640 1641 /* WA for stutter underflow during MPO transitions when adding 2nd plane */ 1642 if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { 1643 1644 if (dc->current_state->stream_status[0].plane_count == 1 && 1645 context->stream_status[0].plane_count > 1) { 1646 1647 struct timing_generator *tg = dc->res_pool->timing_generators[0]; 1648 1649 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false); 1650 1651 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true; 1652 hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); 1653 } 1654 } 1655 } 1656 1657 void dcn20_prepare_bandwidth( 1658 struct dc *dc, 1659 struct dc_state *context) 1660 { 1661 struct hubbub *hubbub = dc->res_pool->hubbub; 1662 1663 dc->clk_mgr->funcs->update_clocks( 1664 dc->clk_mgr, 1665 context, 1666 false); 1667 1668 /* program dchubbub watermarks */ 1669 dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, 1670 &context->bw_ctx.bw.dcn.watermarks, 1671 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1672 false); 1673 } 1674 1675 void dcn20_optimize_bandwidth( 1676 struct dc *dc, 1677 struct dc_state *context) 1678 { 1679 struct hubbub *hubbub = dc->res_pool->hubbub; 1680 1681 /* program dchubbub watermarks */ 1682 hubbub->funcs->program_watermarks(hubbub, 1683 &context->bw_ctx.bw.dcn.watermarks, 1684 dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, 1685 true); 1686 1687 dc->clk_mgr->funcs->update_clocks( 1688 dc->clk_mgr, 1689 context, 1690 true); 1691 } 1692 1693 bool dcn20_update_bandwidth( 1694 struct dc *dc, 1695 struct dc_state *context) 1696 { 1697 int i; 1698 struct dce_hwseq *hws = dc->hwseq; 1699 1700 /* recalculate DML parameters */ 1701 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) 1702 return false; 1703 1704 /* apply updated bandwidth parameters */ 1705 dc->hwss.prepare_bandwidth(dc, context); 1706 1707 /* update hubp configs for all pipes */ 1708 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1709 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 1710 1711 if (pipe_ctx->plane_state == NULL) 1712 continue; 1713 1714 if (pipe_ctx->top_pipe == NULL) { 1715 bool blank = !is_pipe_tree_visible(pipe_ctx); 1716 1717 pipe_ctx->stream_res.tg->funcs->program_global_sync( 1718 pipe_ctx->stream_res.tg, 1719 pipe_ctx->pipe_dlg_param.vready_offset, 1720 pipe_ctx->pipe_dlg_param.vstartup_start, 1721 pipe_ctx->pipe_dlg_param.vupdate_offset, 1722 pipe_ctx->pipe_dlg_param.vupdate_width); 1723 1724 pipe_ctx->stream_res.tg->funcs->set_vtg_params( 1725 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 1726 1727 if (pipe_ctx->prev_odm_pipe == NULL) 1728 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); 1729 1730 if (hws->funcs.setup_vupdate_interrupt) 1731 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1732 } 1733 1734 pipe_ctx->plane_res.hubp->funcs->hubp_setup( 1735 pipe_ctx->plane_res.hubp, 1736 &pipe_ctx->dlg_regs, 1737 &pipe_ctx->ttu_regs, 1738 &pipe_ctx->rq_regs, 1739 &pipe_ctx->pipe_dlg_param); 1740 } 1741 1742 return true; 1743 } 1744 1745 void dcn20_enable_writeback( 1746 struct dc *dc, 1747 struct dc_writeback_info *wb_info, 1748 struct dc_state *context) 1749 { 1750 struct dwbc *dwb; 1751 struct mcif_wb *mcif_wb; 1752 struct timing_generator *optc; 1753 1754 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 1755 ASSERT(wb_info->wb_enabled); 1756 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 1757 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 1758 1759 /* set the OPTC source mux */ 1760 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 1761 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 1762 /* set MCIF_WB buffer and arbitration configuration */ 1763 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 1764 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 1765 /* Enable MCIF_WB */ 1766 mcif_wb->funcs->enable_mcif(mcif_wb); 1767 /* Enable DWB */ 1768 dwb->funcs->enable(dwb, &wb_info->dwb_params); 1769 /* TODO: add sequence to enable/disable warmup */ 1770 } 1771 1772 void dcn20_disable_writeback( 1773 struct dc *dc, 1774 unsigned int dwb_pipe_inst) 1775 { 1776 struct dwbc *dwb; 1777 struct mcif_wb *mcif_wb; 1778 1779 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 1780 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 1781 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 1782 1783 dwb->funcs->disable(dwb); 1784 mcif_wb->funcs->disable_mcif(mcif_wb); 1785 } 1786 1787 bool dcn20_wait_for_blank_complete( 1788 struct output_pixel_processor *opp) 1789 { 1790 int counter; 1791 1792 for (counter = 0; counter < 1000; counter++) { 1793 if (opp->funcs->dpg_is_blanked(opp)) 1794 break; 1795 1796 udelay(100); 1797 } 1798 1799 if (counter == 1000) { 1800 dm_error("DC: failed to blank crtc!\n"); 1801 return false; 1802 } 1803 1804 return true; 1805 } 1806 1807 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) 1808 { 1809 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1810 1811 if (!hubp) 1812 return false; 1813 return hubp->funcs->dmdata_status_done(hubp); 1814 } 1815 1816 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1817 { 1818 struct dce_hwseq *hws = dc->hwseq; 1819 1820 if (pipe_ctx->stream_res.dsc) { 1821 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1822 1823 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true); 1824 while (odm_pipe) { 1825 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true); 1826 odm_pipe = odm_pipe->next_odm_pipe; 1827 } 1828 } 1829 } 1830 1831 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) 1832 { 1833 struct dce_hwseq *hws = dc->hwseq; 1834 1835 if (pipe_ctx->stream_res.dsc) { 1836 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1837 1838 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false); 1839 while (odm_pipe) { 1840 dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false); 1841 odm_pipe = odm_pipe->next_odm_pipe; 1842 } 1843 } 1844 } 1845 1846 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) 1847 { 1848 struct dc_dmdata_attributes attr = { 0 }; 1849 struct hubp *hubp = pipe_ctx->plane_res.hubp; 1850 1851 attr.dmdata_mode = DMDATA_HW_MODE; 1852 attr.dmdata_size = 1853 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; 1854 attr.address.quad_part = 1855 pipe_ctx->stream->dmdata_address.quad_part; 1856 attr.dmdata_dl_delta = 0; 1857 attr.dmdata_qos_mode = 0; 1858 attr.dmdata_qos_level = 0; 1859 attr.dmdata_repeat = 1; /* always repeat */ 1860 attr.dmdata_updated = 1; 1861 attr.dmdata_sw_data = NULL; 1862 1863 hubp->funcs->dmdata_set_attributes(hubp, &attr); 1864 } 1865 1866 void dcn20_init_vm_ctx( 1867 struct dce_hwseq *hws, 1868 struct dc *dc, 1869 struct dc_virtual_addr_space_config *va_config, 1870 int vmid) 1871 { 1872 struct dcn_hubbub_virt_addr_config config; 1873 1874 if (vmid == 0) { 1875 ASSERT(0); /* VMID cannot be 0 for vm context */ 1876 return; 1877 } 1878 1879 config.page_table_start_addr = va_config->page_table_start_addr; 1880 config.page_table_end_addr = va_config->page_table_end_addr; 1881 config.page_table_block_size = va_config->page_table_block_size_in_bytes; 1882 config.page_table_depth = va_config->page_table_depth; 1883 config.page_table_base_addr = va_config->page_table_base_addr; 1884 1885 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); 1886 } 1887 1888 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 1889 { 1890 struct dcn_hubbub_phys_addr_config config; 1891 1892 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 1893 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 1894 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 1895 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 1896 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 1897 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 1898 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 1899 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 1900 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 1901 config.page_table_default_page_addr = pa_config->page_table_default_page_addr; 1902 1903 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 1904 } 1905 1906 static bool patch_address_for_sbs_tb_stereo( 1907 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) 1908 { 1909 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1910 bool sec_split = pipe_ctx->top_pipe && 1911 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; 1912 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && 1913 (pipe_ctx->stream->timing.timing_3d_format == 1914 TIMING_3D_FORMAT_SIDE_BY_SIDE || 1915 pipe_ctx->stream->timing.timing_3d_format == 1916 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { 1917 *addr = plane_state->address.grph_stereo.left_addr; 1918 plane_state->address.grph_stereo.left_addr = 1919 plane_state->address.grph_stereo.right_addr; 1920 return true; 1921 } 1922 1923 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && 1924 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { 1925 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; 1926 plane_state->address.grph_stereo.right_addr = 1927 plane_state->address.grph_stereo.left_addr; 1928 } 1929 return false; 1930 } 1931 1932 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) 1933 { 1934 bool addr_patched = false; 1935 PHYSICAL_ADDRESS_LOC addr; 1936 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 1937 1938 if (plane_state == NULL) 1939 return; 1940 1941 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); 1942 1943 // Call Helper to track VMID use 1944 vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); 1945 1946 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( 1947 pipe_ctx->plane_res.hubp, 1948 &plane_state->address, 1949 plane_state->flip_immediate); 1950 1951 plane_state->status.requested_address = plane_state->address; 1952 1953 if (plane_state->flip_immediate) 1954 plane_state->status.current_address = plane_state->address; 1955 1956 if (addr_patched) 1957 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; 1958 } 1959 1960 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, 1961 struct dc_link_settings *link_settings) 1962 { 1963 struct encoder_unblank_param params = { { 0 } }; 1964 struct dc_stream_state *stream = pipe_ctx->stream; 1965 struct dc_link *link = stream->link; 1966 struct dce_hwseq *hws = link->dc->hwseq; 1967 struct pipe_ctx *odm_pipe; 1968 1969 params.opp_cnt = 1; 1970 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 1971 params.opp_cnt++; 1972 } 1973 /* only 3 items below are used by unblank */ 1974 params.timing = pipe_ctx->stream->timing; 1975 1976 params.link_settings.link_rate = link_settings->link_rate; 1977 1978 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1979 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) 1980 params.timing.pix_clk_100hz /= 2; 1981 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( 1982 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); 1983 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); 1984 } 1985 1986 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1987 hws->funcs.edp_backlight_control(link, true); 1988 } 1989 } 1990 1991 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) 1992 { 1993 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1994 int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); 1995 1996 if (start_line < 0) 1997 start_line = 0; 1998 1999 if (tg->funcs->setup_vertical_interrupt2) 2000 tg->funcs->setup_vertical_interrupt2(tg, start_line); 2001 } 2002 2003 static void dcn20_reset_back_end_for_pipe( 2004 struct dc *dc, 2005 struct pipe_ctx *pipe_ctx, 2006 struct dc_state *context) 2007 { 2008 int i; 2009 struct dc_link *link; 2010 DC_LOGGER_INIT(dc->ctx->logger); 2011 if (pipe_ctx->stream_res.stream_enc == NULL) { 2012 pipe_ctx->stream = NULL; 2013 return; 2014 } 2015 2016 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2017 link = pipe_ctx->stream->link; 2018 /* DPMS may already disable or */ 2019 /* dpms_off status is incorrect due to fastboot 2020 * feature. When system resume from S4 with second 2021 * screen only, the dpms_off would be true but 2022 * VBIOS lit up eDP, so check link status too. 2023 */ 2024 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 2025 core_link_disable_stream(pipe_ctx); 2026 else if (pipe_ctx->stream_res.audio) 2027 dc->hwss.disable_audio_stream(pipe_ctx); 2028 2029 /* free acquired resources */ 2030 if (pipe_ctx->stream_res.audio) { 2031 /*disable az_endpoint*/ 2032 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 2033 2034 /*free audio*/ 2035 if (dc->caps.dynamic_audio == true) { 2036 /*we have to dynamic arbitrate the audio endpoints*/ 2037 /*we free the resource, need reset is_audio_acquired*/ 2038 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2039 pipe_ctx->stream_res.audio, false); 2040 pipe_ctx->stream_res.audio = NULL; 2041 } 2042 } 2043 } 2044 else if (pipe_ctx->stream_res.dsc) { 2045 dp_set_dsc_enable(pipe_ctx, false); 2046 } 2047 2048 /* by upper caller loop, parent pipe: pipe0, will be reset last. 2049 * back end share by all pipes and will be disable only when disable 2050 * parent pipe. 2051 */ 2052 if (pipe_ctx->top_pipe == NULL) { 2053 2054 dc->hwss.set_abm_immediate_disable(pipe_ctx); 2055 2056 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 2057 2058 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 2059 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 2060 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 2061 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 2062 2063 if (pipe_ctx->stream_res.tg->funcs->set_drr) 2064 pipe_ctx->stream_res.tg->funcs->set_drr( 2065 pipe_ctx->stream_res.tg, NULL); 2066 } 2067 2068 for (i = 0; i < dc->res_pool->pipe_count; i++) 2069 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) 2070 break; 2071 2072 if (i == dc->res_pool->pipe_count) 2073 return; 2074 2075 pipe_ctx->stream = NULL; 2076 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 2077 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 2078 } 2079 2080 void dcn20_reset_hw_ctx_wrap( 2081 struct dc *dc, 2082 struct dc_state *context) 2083 { 2084 int i; 2085 struct dce_hwseq *hws = dc->hwseq; 2086 2087 /* Reset Back End*/ 2088 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 2089 struct pipe_ctx *pipe_ctx_old = 2090 &dc->current_state->res_ctx.pipe_ctx[i]; 2091 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2092 2093 if (!pipe_ctx_old->stream) 2094 continue; 2095 2096 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 2097 continue; 2098 2099 if (!pipe_ctx->stream || 2100 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2101 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2102 2103 dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 2104 if (hws->funcs.enable_stream_gating) 2105 hws->funcs.enable_stream_gating(dc, pipe_ctx); 2106 if (old_clk) 2107 old_clk->funcs->cs_power_down(old_clk); 2108 } 2109 } 2110 } 2111 2112 void dcn20_get_mpctree_visual_confirm_color( 2113 struct pipe_ctx *pipe_ctx, 2114 struct tg_color *color) 2115 { 2116 const struct tg_color pipe_colors[6] = { 2117 {MAX_TG_COLOR_VALUE, 0, 0}, // red 2118 {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow 2119 {0, MAX_TG_COLOR_VALUE, 0}, // blue 2120 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple 2121 {0, 0, MAX_TG_COLOR_VALUE}, // green 2122 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange 2123 }; 2124 2125 struct pipe_ctx *top_pipe = pipe_ctx; 2126 2127 while (top_pipe->top_pipe) { 2128 top_pipe = top_pipe->top_pipe; 2129 } 2130 2131 *color = pipe_colors[top_pipe->pipe_idx]; 2132 } 2133 2134 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) 2135 { 2136 struct dce_hwseq *hws = dc->hwseq; 2137 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2138 struct mpcc_blnd_cfg blnd_cfg = { {0} }; 2139 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; 2140 int mpcc_id; 2141 struct mpcc *new_mpcc; 2142 struct mpc *mpc = dc->res_pool->mpc; 2143 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); 2144 2145 // input to MPCC is always RGB, by default leave black_color at 0 2146 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { 2147 hws->funcs.get_hdr_visual_confirm_color( 2148 pipe_ctx, &blnd_cfg.black_color); 2149 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { 2150 hws->funcs.get_surface_visual_confirm_color( 2151 pipe_ctx, &blnd_cfg.black_color); 2152 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) { 2153 dcn20_get_mpctree_visual_confirm_color( 2154 pipe_ctx, &blnd_cfg.black_color); 2155 } 2156 2157 if (per_pixel_alpha) 2158 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; 2159 else 2160 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; 2161 2162 blnd_cfg.overlap_only = false; 2163 blnd_cfg.global_gain = 0xff; 2164 2165 if (pipe_ctx->plane_state->global_alpha) 2166 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; 2167 else 2168 blnd_cfg.global_alpha = 0xff; 2169 2170 blnd_cfg.background_color_bpc = 4; 2171 blnd_cfg.bottom_gain_mode = 0; 2172 blnd_cfg.top_gain = 0x1f000; 2173 blnd_cfg.bottom_inside_gain = 0x1f000; 2174 blnd_cfg.bottom_outside_gain = 0x1f000; 2175 blnd_cfg.pre_multiplied_alpha = per_pixel_alpha; 2176 2177 /* 2178 * TODO: remove hack 2179 * Note: currently there is a bug in init_hw such that 2180 * on resume from hibernate, BIOS sets up MPCC0, and 2181 * we do mpcc_remove but the mpcc cannot go to idle 2182 * after remove. This cause us to pick mpcc1 here, 2183 * which causes a pstate hang for yet unknown reason. 2184 */ 2185 mpcc_id = hubp->inst; 2186 2187 /* If there is no full update, don't need to touch MPC tree*/ 2188 if (!pipe_ctx->plane_state->update_flags.bits.full_update && 2189 !pipe_ctx->update_flags.bits.mpcc) { 2190 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); 2191 return; 2192 } 2193 2194 /* check if this MPCC is already being used */ 2195 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); 2196 /* remove MPCC if being used */ 2197 if (new_mpcc != NULL) 2198 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); 2199 else 2200 if (dc->debug.sanity_checks) 2201 mpc->funcs->assert_mpcc_idle_before_connect( 2202 dc->res_pool->mpc, mpcc_id); 2203 2204 /* Call MPC to insert new plane */ 2205 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, 2206 mpc_tree_params, 2207 &blnd_cfg, 2208 NULL, 2209 NULL, 2210 hubp->inst, 2211 mpcc_id); 2212 2213 ASSERT(new_mpcc != NULL); 2214 hubp->opp_id = pipe_ctx->stream_res.opp->inst; 2215 hubp->mpcc_id = mpcc_id; 2216 } 2217 2218 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 2219 { 2220 enum dc_lane_count lane_count = 2221 pipe_ctx->stream->link->cur_link_settings.lane_count; 2222 2223 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 2224 struct dc_link *link = pipe_ctx->stream->link; 2225 2226 uint32_t active_total_with_borders; 2227 uint32_t early_control = 0; 2228 struct timing_generator *tg = pipe_ctx->stream_res.tg; 2229 2230 /* For MST, there are multiply stream go to only one link. 2231 * connect DIG back_end to front_end while enable_stream and 2232 * disconnect them during disable_stream 2233 * BY this, it is logic clean to separate stream and link 2234 */ 2235 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 2236 pipe_ctx->stream_res.stream_enc->id, true); 2237 2238 if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { 2239 if (link->dc->hwss.program_dmdata_engine) 2240 link->dc->hwss.program_dmdata_engine(pipe_ctx); 2241 } 2242 2243 link->dc->hwss.update_info_frame(pipe_ctx); 2244 2245 /* enable early control to avoid corruption on DP monitor*/ 2246 active_total_with_borders = 2247 timing->h_addressable 2248 + timing->h_border_left 2249 + timing->h_border_right; 2250 2251 if (lane_count != 0) 2252 early_control = active_total_with_borders % lane_count; 2253 2254 if (early_control == 0) 2255 early_control = lane_count; 2256 2257 tg->funcs->set_early_control(tg, early_control); 2258 2259 /* enable audio only within mode set */ 2260 if (pipe_ctx->stream_res.audio != NULL) { 2261 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2262 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); 2263 } 2264 } 2265 2266 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 2267 { 2268 struct dc_stream_state *stream = pipe_ctx->stream; 2269 struct hubp *hubp = pipe_ctx->plane_res.hubp; 2270 bool enable = false; 2271 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 2272 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 2273 ? dmdata_dp 2274 : dmdata_hdmi; 2275 2276 /* if using dynamic meta, don't set up generic infopackets */ 2277 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 2278 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 2279 enable = true; 2280 } 2281 2282 if (!hubp) 2283 return; 2284 2285 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 2286 return; 2287 2288 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 2289 hubp->inst, mode); 2290 } 2291 2292 void dcn20_fpga_init_hw(struct dc *dc) 2293 { 2294 int i, j; 2295 struct dce_hwseq *hws = dc->hwseq; 2296 struct resource_pool *res_pool = dc->res_pool; 2297 struct dc_state *context = dc->current_state; 2298 2299 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 2300 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 2301 2302 // Initialize the dccg 2303 if (res_pool->dccg->funcs->dccg_init) 2304 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 2305 2306 //Enable ability to power gate / don't force power on permanently 2307 hws->funcs.enable_power_gating_plane(hws, true); 2308 2309 // Specific to FPGA dccg and registers 2310 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); 2311 REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); 2312 2313 hws->funcs.dccg_init(hws); 2314 2315 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); 2316 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 2317 if (REG(REFCLK_CNTL)) 2318 REG_WRITE(REFCLK_CNTL, 0); 2319 // 2320 2321 2322 /* Blank pixel data with OPP DPG */ 2323 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2324 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2325 2326 if (tg->funcs->is_tg_enabled(tg)) 2327 dcn20_init_blank(dc, tg); 2328 } 2329 2330 for (i = 0; i < res_pool->timing_generator_count; i++) { 2331 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2332 2333 if (tg->funcs->is_tg_enabled(tg)) 2334 tg->funcs->lock(tg); 2335 } 2336 2337 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2338 struct dpp *dpp = res_pool->dpps[i]; 2339 2340 dpp->funcs->dpp_reset(dpp); 2341 } 2342 2343 /* Reset all MPCC muxes */ 2344 res_pool->mpc->funcs->mpc_init(res_pool->mpc); 2345 2346 /* initialize OPP mpc_tree parameter */ 2347 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { 2348 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; 2349 res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2350 for (j = 0; j < MAX_PIPES; j++) 2351 res_pool->opps[i]->mpcc_disconnect_pending[j] = false; 2352 } 2353 2354 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2355 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2356 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2357 struct hubp *hubp = dc->res_pool->hubps[i]; 2358 struct dpp *dpp = dc->res_pool->dpps[i]; 2359 2360 pipe_ctx->stream_res.tg = tg; 2361 pipe_ctx->pipe_idx = i; 2362 2363 pipe_ctx->plane_res.hubp = hubp; 2364 pipe_ctx->plane_res.dpp = dpp; 2365 pipe_ctx->plane_res.mpcc_inst = dpp->inst; 2366 hubp->mpcc_id = dpp->inst; 2367 hubp->opp_id = OPP_ID_INVALID; 2368 hubp->power_gated = false; 2369 pipe_ctx->stream_res.opp = NULL; 2370 2371 hubp->funcs->hubp_init(hubp); 2372 2373 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; 2374 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; 2375 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; 2376 pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; 2377 /*to do*/ 2378 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); 2379 } 2380 2381 /* initialize DWB pointer to MCIF_WB */ 2382 for (i = 0; i < res_pool->res_cap->num_dwb; i++) 2383 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; 2384 2385 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2386 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2387 2388 if (tg->funcs->is_tg_enabled(tg)) 2389 tg->funcs->unlock(tg); 2390 } 2391 2392 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2393 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2394 2395 dc->hwss.disable_plane(dc, pipe_ctx); 2396 2397 pipe_ctx->stream_res.tg = NULL; 2398 pipe_ctx->plane_res.hubp = NULL; 2399 } 2400 2401 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 2402 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 2403 2404 tg->funcs->tg_init(tg); 2405 } 2406 } 2407