1 /* 2 * Copyright 2012-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn20_hubp.h" 27 28 #include "dm_services.h" 29 #include "dce_calcs.h" 30 #include "reg_helper.h" 31 #include "basics/conversion.h" 32 33 #define DC_LOGGER_INIT(logger) 34 35 #define REG(reg)\ 36 hubp2->hubp_regs->reg 37 38 #define CTX \ 39 hubp2->base.ctx 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 44 45 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 46 struct vm_system_aperture_param *apt) 47 { 48 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 49 50 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 51 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 52 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 53 54 // The format of default addr is 48:12 of the 48 bit addr 55 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 56 57 // The format of high/low are 48:18 of the 48 bit addr 58 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 59 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 60 61 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 62 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ 63 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 64 65 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 66 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 67 68 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 69 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 70 71 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 72 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 73 74 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 75 ENABLE_L1_TLB, 1, 76 SYSTEM_ACCESS_MODE, 0x3); 77 } 78 79 void hubp2_program_deadline( 80 struct hubp *hubp, 81 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 82 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 83 { 84 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 85 86 /* DLG - Per hubp */ 87 REG_SET_2(BLANK_OFFSET_0, 0, 88 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 89 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 90 91 REG_SET(BLANK_OFFSET_1, 0, 92 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 93 94 REG_SET(DST_DIMENSIONS, 0, 95 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 96 97 REG_SET_2(DST_AFTER_SCALER, 0, 98 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 99 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 100 101 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 102 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 103 104 /* DLG - Per luma/chroma */ 105 REG_SET(VBLANK_PARAMETERS_1, 0, 106 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 107 108 if (REG(NOM_PARAMETERS_0)) 109 REG_SET(NOM_PARAMETERS_0, 0, 110 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 111 112 if (REG(NOM_PARAMETERS_1)) 113 REG_SET(NOM_PARAMETERS_1, 0, 114 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 115 116 REG_SET(NOM_PARAMETERS_4, 0, 117 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 118 119 REG_SET(NOM_PARAMETERS_5, 0, 120 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 121 122 REG_SET_2(PER_LINE_DELIVERY, 0, 123 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 124 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 125 126 REG_SET(VBLANK_PARAMETERS_2, 0, 127 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 128 129 if (REG(NOM_PARAMETERS_2)) 130 REG_SET(NOM_PARAMETERS_2, 0, 131 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 132 133 if (REG(NOM_PARAMETERS_3)) 134 REG_SET(NOM_PARAMETERS_3, 0, 135 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 136 137 REG_SET(NOM_PARAMETERS_6, 0, 138 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 139 140 REG_SET(NOM_PARAMETERS_7, 0, 141 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 142 143 /* TTU - per hubp */ 144 REG_SET_2(DCN_TTU_QOS_WM, 0, 145 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 146 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 147 148 /* TTU - per luma/chroma */ 149 /* Assumed surf0 is luma and 1 is chroma */ 150 151 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 152 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 153 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 154 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 155 156 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 157 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 158 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 159 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 160 161 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 162 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 163 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 164 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 165 166 REG_SET(FLIP_PARAMETERS_1, 0, 167 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 168 } 169 170 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 171 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 172 { 173 uint32_t value = 0; 174 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 175 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ 176 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 177 /* 178 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) 179 <= OTG_V_BLANK_END 180 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 181 else 182 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 183 */ 184 if (pipe_dest->htotal != 0) { 185 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width 186 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 187 value = 1; 188 } else 189 value = 0; 190 } 191 192 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); 193 } 194 195 static void hubp2_program_requestor(struct hubp *hubp, 196 struct _vcs_dpi_display_rq_regs_st *rq_regs) 197 { 198 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 199 200 REG_UPDATE(HUBPRET_CONTROL, 201 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 202 REG_SET_4(DCN_EXPANSION_MODE, 0, 203 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 204 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 205 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 206 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 207 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 208 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 209 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 210 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 211 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 212 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 213 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 214 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 215 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 216 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 217 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 218 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 219 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 220 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 221 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 222 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 223 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 224 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 225 } 226 227 static void hubp2_setup( 228 struct hubp *hubp, 229 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 230 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 231 struct _vcs_dpi_display_rq_regs_st *rq_regs, 232 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 233 { 234 /* otg is locked when this func is called. Register are double buffered. 235 * disable the requestors is not needed 236 */ 237 238 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 239 hubp2_program_requestor(hubp, rq_regs); 240 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 241 242 } 243 244 void hubp2_setup_interdependent( 245 struct hubp *hubp, 246 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 247 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 248 { 249 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 250 251 REG_SET_2(PREFETCH_SETTINGS, 0, 252 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 253 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 254 255 REG_SET(PREFETCH_SETTINGS_C, 0, 256 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 257 258 REG_SET_2(VBLANK_PARAMETERS_0, 0, 259 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 260 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 261 262 REG_SET_2(FLIP_PARAMETERS_0, 0, 263 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, 264 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); 265 266 REG_SET(VBLANK_PARAMETERS_3, 0, 267 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 268 269 REG_SET(VBLANK_PARAMETERS_4, 0, 270 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 271 272 REG_SET(FLIP_PARAMETERS_2, 0, 273 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); 274 275 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 276 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 277 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 278 279 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 280 REFCYC_PER_REQ_DELIVERY_PRE, 281 ttu_attr->refcyc_per_req_delivery_pre_l); 282 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 283 REFCYC_PER_REQ_DELIVERY_PRE, 284 ttu_attr->refcyc_per_req_delivery_pre_c); 285 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 286 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 287 REG_SET(DCN_CUR1_TTU_CNTL1, 0, 288 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); 289 290 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 291 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 292 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 293 } 294 295 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: 296 * NUM_BANKS 297 * NUM_SE 298 * NUM_RB_PER_SE 299 * RB_ALIGNED 300 * Other things can be defaulted, since they never change: 301 * PIPE_ALIGNED = 0 302 * META_LINEAR = 0 303 * In GFX10, only these apply: 304 * PIPE_INTERLEAVE 305 * NUM_PIPES 306 * MAX_COMPRESSED_FRAGS 307 * SW_MODE 308 */ 309 static void hubp2_program_tiling( 310 struct dcn20_hubp *hubp2, 311 const union dc_tiling_info *info, 312 const enum surface_pixel_format pixel_format) 313 { 314 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 315 NUM_PIPES, log_2(info->gfx9.num_pipes), 316 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 317 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 318 319 REG_UPDATE_4(DCSURF_TILING_CONFIG, 320 SW_MODE, info->gfx9.swizzle, 321 META_LINEAR, 0, 322 RB_ALIGNED, 0, 323 PIPE_ALIGNED, 0); 324 } 325 326 void hubp2_program_size( 327 struct hubp *hubp, 328 enum surface_pixel_format format, 329 const struct plane_size *plane_size, 330 struct dc_plane_dcc_param *dcc) 331 { 332 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 333 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 334 bool use_pitch_c = false; 335 336 /* Program data and meta surface pitch (calculation from addrlib) 337 * 444 or 420 luma 338 */ 339 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 340 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; 341 use_pitch_c = use_pitch_c 342 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 343 if (use_pitch_c) { 344 ASSERT(plane_size->chroma_pitch != 0); 345 /* Chroma pitch zero can cause system hang! */ 346 347 pitch = plane_size->surface_pitch - 1; 348 meta_pitch = dcc->meta_pitch - 1; 349 pitch_c = plane_size->chroma_pitch - 1; 350 meta_pitch_c = dcc->meta_pitch_c - 1; 351 } else { 352 pitch = plane_size->surface_pitch - 1; 353 meta_pitch = dcc->meta_pitch - 1; 354 pitch_c = 0; 355 meta_pitch_c = 0; 356 } 357 358 if (!dcc->enable) { 359 meta_pitch = 0; 360 meta_pitch_c = 0; 361 } 362 363 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 364 PITCH, pitch, META_PITCH, meta_pitch); 365 366 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; 367 use_pitch_c = use_pitch_c 368 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 369 if (use_pitch_c) 370 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 371 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 372 } 373 374 void hubp2_program_rotation( 375 struct hubp *hubp, 376 enum dc_rotation_angle rotation, 377 bool horizontal_mirror) 378 { 379 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 380 uint32_t mirror; 381 382 383 if (horizontal_mirror) 384 mirror = 1; 385 else 386 mirror = 0; 387 388 /* Program rotation angle and horz mirror - no mirror */ 389 if (rotation == ROTATION_ANGLE_0) 390 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 391 ROTATION_ANGLE, 0, 392 H_MIRROR_EN, mirror); 393 else if (rotation == ROTATION_ANGLE_90) 394 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 395 ROTATION_ANGLE, 1, 396 H_MIRROR_EN, mirror); 397 else if (rotation == ROTATION_ANGLE_180) 398 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 399 ROTATION_ANGLE, 2, 400 H_MIRROR_EN, mirror); 401 else if (rotation == ROTATION_ANGLE_270) 402 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 403 ROTATION_ANGLE, 3, 404 H_MIRROR_EN, mirror); 405 } 406 407 void hubp2_dcc_control(struct hubp *hubp, bool enable, 408 enum hubp_ind_block_size independent_64b_blks) 409 { 410 uint32_t dcc_en = enable ? 1 : 0; 411 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 412 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 413 414 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 415 PRIMARY_SURFACE_DCC_EN, dcc_en, 416 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 417 SECONDARY_SURFACE_DCC_EN, dcc_en, 418 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 419 } 420 421 void hubp2_program_pixel_format( 422 struct hubp *hubp, 423 enum surface_pixel_format format) 424 { 425 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 426 uint32_t red_bar = 3; 427 uint32_t blue_bar = 2; 428 429 /* swap for ABGR format */ 430 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 431 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 432 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 433 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 434 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 435 red_bar = 2; 436 blue_bar = 3; 437 } 438 439 REG_UPDATE_2(HUBPRET_CONTROL, 440 CROSSBAR_SRC_CB_B, blue_bar, 441 CROSSBAR_SRC_CR_R, red_bar); 442 443 /* Mapping is same as ipp programming (cnvc) */ 444 445 switch (format) { 446 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 447 REG_UPDATE(DCSURF_SURFACE_CONFIG, 448 SURFACE_PIXEL_FORMAT, 1); 449 break; 450 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 451 REG_UPDATE(DCSURF_SURFACE_CONFIG, 452 SURFACE_PIXEL_FORMAT, 3); 453 break; 454 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 455 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 456 REG_UPDATE(DCSURF_SURFACE_CONFIG, 457 SURFACE_PIXEL_FORMAT, 8); 458 break; 459 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 460 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 461 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 462 REG_UPDATE(DCSURF_SURFACE_CONFIG, 463 SURFACE_PIXEL_FORMAT, 10); 464 break; 465 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 466 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ 467 REG_UPDATE(DCSURF_SURFACE_CONFIG, 468 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 469 break; 470 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 471 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 472 REG_UPDATE(DCSURF_SURFACE_CONFIG, 473 SURFACE_PIXEL_FORMAT, 24); 474 break; 475 476 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 477 REG_UPDATE(DCSURF_SURFACE_CONFIG, 478 SURFACE_PIXEL_FORMAT, 65); 479 break; 480 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 481 REG_UPDATE(DCSURF_SURFACE_CONFIG, 482 SURFACE_PIXEL_FORMAT, 64); 483 break; 484 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 485 REG_UPDATE(DCSURF_SURFACE_CONFIG, 486 SURFACE_PIXEL_FORMAT, 67); 487 break; 488 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 489 REG_UPDATE(DCSURF_SURFACE_CONFIG, 490 SURFACE_PIXEL_FORMAT, 66); 491 break; 492 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 493 REG_UPDATE(DCSURF_SURFACE_CONFIG, 494 SURFACE_PIXEL_FORMAT, 12); 495 break; 496 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 497 REG_UPDATE(DCSURF_SURFACE_CONFIG, 498 SURFACE_PIXEL_FORMAT, 112); 499 break; 500 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 501 REG_UPDATE(DCSURF_SURFACE_CONFIG, 502 SURFACE_PIXEL_FORMAT, 113); 503 break; 504 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 505 REG_UPDATE(DCSURF_SURFACE_CONFIG, 506 SURFACE_PIXEL_FORMAT, 114); 507 break; 508 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 509 REG_UPDATE(DCSURF_SURFACE_CONFIG, 510 SURFACE_PIXEL_FORMAT, 118); 511 break; 512 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 513 REG_UPDATE(DCSURF_SURFACE_CONFIG, 514 SURFACE_PIXEL_FORMAT, 119); 515 break; 516 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 517 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 518 SURFACE_PIXEL_FORMAT, 116, 519 ALPHA_PLANE_EN, 0); 520 break; 521 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 522 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 523 SURFACE_PIXEL_FORMAT, 116, 524 ALPHA_PLANE_EN, 1); 525 break; 526 default: 527 BREAK_TO_DEBUGGER(); 528 break; 529 } 530 531 /* don't see the need of program the xbar in DCN 1.0 */ 532 } 533 534 void hubp2_program_surface_config( 535 struct hubp *hubp, 536 enum surface_pixel_format format, 537 union dc_tiling_info *tiling_info, 538 struct plane_size *plane_size, 539 enum dc_rotation_angle rotation, 540 struct dc_plane_dcc_param *dcc, 541 bool horizontal_mirror, 542 unsigned int compat_level) 543 { 544 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 545 546 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 547 hubp2_program_tiling(hubp2, tiling_info, format); 548 hubp2_program_size(hubp, format, plane_size, dcc); 549 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 550 hubp2_program_pixel_format(hubp, format); 551 } 552 553 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 554 unsigned int cursor_width, 555 enum dc_cursor_color_format cursor_mode) 556 { 557 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 558 559 if (cursor_mode == CURSOR_MODE_MONO) 560 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 561 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || 562 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 563 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 564 if (cursor_width >= 1 && cursor_width <= 32) 565 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 566 else if (cursor_width >= 33 && cursor_width <= 64) 567 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 568 else if (cursor_width >= 65 && cursor_width <= 128) 569 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 570 else if (cursor_width >= 129 && cursor_width <= 256) 571 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 572 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || 573 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { 574 if (cursor_width >= 1 && cursor_width <= 16) 575 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 576 else if (cursor_width >= 17 && cursor_width <= 32) 577 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 578 else if (cursor_width >= 33 && cursor_width <= 64) 579 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 580 else if (cursor_width >= 65 && cursor_width <= 128) 581 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 582 else if (cursor_width >= 129 && cursor_width <= 256) 583 line_per_chunk = CURSOR_LINE_PER_CHUNK_1; 584 } 585 586 return line_per_chunk; 587 } 588 589 void hubp2_cursor_set_attributes( 590 struct hubp *hubp, 591 const struct dc_cursor_attributes *attr) 592 { 593 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 594 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 595 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 596 attr->width, attr->color_format); 597 598 hubp->curs_attr = *attr; 599 600 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 601 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 602 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 603 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 604 605 REG_UPDATE_2(CURSOR_SIZE, 606 CURSOR_WIDTH, attr->width, 607 CURSOR_HEIGHT, attr->height); 608 609 REG_UPDATE_4(CURSOR_CONTROL, 610 CURSOR_MODE, attr->color_format, 611 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 612 CURSOR_PITCH, hw_pitch, 613 CURSOR_LINES_PER_CHUNK, lpc); 614 615 REG_SET_2(CURSOR_SETTINGS, 0, 616 /* no shift of the cursor HDL schedule */ 617 CURSOR0_DST_Y_OFFSET, 0, 618 /* used to shift the cursor chunk request deadline */ 619 CURSOR0_CHUNK_HDL_ADJUST, 3); 620 } 621 622 void hubp2_dmdata_set_attributes( 623 struct hubp *hubp, 624 const struct dc_dmdata_attributes *attr) 625 { 626 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 627 628 if (attr->dmdata_mode == DMDATA_HW_MODE) { 629 /* set to HW mode */ 630 REG_UPDATE(DMDATA_CNTL, 631 DMDATA_MODE, 1); 632 633 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ 634 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); 635 636 /* toggle DMDATA_UPDATED and set repeat and size */ 637 REG_UPDATE(DMDATA_CNTL, 638 DMDATA_UPDATED, 0); 639 REG_UPDATE_3(DMDATA_CNTL, 640 DMDATA_UPDATED, 1, 641 DMDATA_REPEAT, attr->dmdata_repeat, 642 DMDATA_SIZE, attr->dmdata_size); 643 644 /* set DMDATA address */ 645 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); 646 REG_UPDATE(DMDATA_ADDRESS_HIGH, 647 DMDATA_ADDRESS_HIGH, attr->address.high_part); 648 649 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); 650 651 } else { 652 /* set to SW mode before loading data */ 653 REG_SET(DMDATA_CNTL, 0, 654 DMDATA_MODE, 0); 655 /* toggle DMDATA_SW_UPDATED to start loading sequence */ 656 REG_UPDATE(DMDATA_SW_CNTL, 657 DMDATA_SW_UPDATED, 0); 658 REG_UPDATE_3(DMDATA_SW_CNTL, 659 DMDATA_SW_UPDATED, 1, 660 DMDATA_SW_REPEAT, attr->dmdata_repeat, 661 DMDATA_SW_SIZE, attr->dmdata_size); 662 /* load data into hubp dmdata buffer */ 663 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); 664 } 665 666 /* Note that DL_DELTA must be programmed if we want to use TTU mode */ 667 REG_SET_3(DMDATA_QOS_CNTL, 0, 668 DMDATA_QOS_MODE, attr->dmdata_qos_mode, 669 DMDATA_QOS_LEVEL, attr->dmdata_qos_level, 670 DMDATA_DL_DELTA, attr->dmdata_dl_delta); 671 } 672 673 void hubp2_dmdata_load( 674 struct hubp *hubp, 675 uint32_t dmdata_sw_size, 676 const uint32_t *dmdata_sw_data) 677 { 678 int i; 679 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 680 681 /* load dmdata into HUBP buffer in SW mode */ 682 for (i = 0; i < dmdata_sw_size / 4; i++) 683 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); 684 } 685 686 bool hubp2_dmdata_status_done(struct hubp *hubp) 687 { 688 uint32_t status; 689 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 690 691 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); 692 return (status == 1); 693 } 694 695 bool hubp2_program_surface_flip_and_addr( 696 struct hubp *hubp, 697 const struct dc_plane_address *address, 698 bool flip_immediate) 699 { 700 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 701 702 //program flip type 703 REG_UPDATE(DCSURF_FLIP_CONTROL, 704 SURFACE_FLIP_TYPE, flip_immediate); 705 706 // Program VMID reg 707 REG_UPDATE(VMID_SETTINGS_0, 708 VMID, address->vmid); 709 710 711 /* HW automatically latch rest of address register on write to 712 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 713 * 714 * program high first and then the low addr, order matters! 715 */ 716 switch (address->type) { 717 case PLN_ADDR_TYPE_GRAPHICS: 718 /* DCN1.0 does not support const color 719 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 720 * base on address->grph.dcc_const_color 721 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 722 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 723 */ 724 725 if (address->grph.addr.quad_part == 0) 726 break; 727 728 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 729 PRIMARY_SURFACE_TMZ, address->tmz_surface, 730 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 731 732 if (address->grph.meta_addr.quad_part != 0) { 733 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 734 PRIMARY_META_SURFACE_ADDRESS_HIGH, 735 address->grph.meta_addr.high_part); 736 737 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 738 PRIMARY_META_SURFACE_ADDRESS, 739 address->grph.meta_addr.low_part); 740 } 741 742 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 743 PRIMARY_SURFACE_ADDRESS_HIGH, 744 address->grph.addr.high_part); 745 746 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 747 PRIMARY_SURFACE_ADDRESS, 748 address->grph.addr.low_part); 749 break; 750 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 751 if (address->video_progressive.luma_addr.quad_part == 0 752 || address->video_progressive.chroma_addr.quad_part == 0) 753 break; 754 755 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 756 PRIMARY_SURFACE_TMZ, address->tmz_surface, 757 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 758 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 759 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 760 761 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 762 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 763 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 764 address->video_progressive.chroma_meta_addr.high_part); 765 766 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 767 PRIMARY_META_SURFACE_ADDRESS_C, 768 address->video_progressive.chroma_meta_addr.low_part); 769 770 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 771 PRIMARY_META_SURFACE_ADDRESS_HIGH, 772 address->video_progressive.luma_meta_addr.high_part); 773 774 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 775 PRIMARY_META_SURFACE_ADDRESS, 776 address->video_progressive.luma_meta_addr.low_part); 777 } 778 779 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 780 PRIMARY_SURFACE_ADDRESS_HIGH_C, 781 address->video_progressive.chroma_addr.high_part); 782 783 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 784 PRIMARY_SURFACE_ADDRESS_C, 785 address->video_progressive.chroma_addr.low_part); 786 787 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 788 PRIMARY_SURFACE_ADDRESS_HIGH, 789 address->video_progressive.luma_addr.high_part); 790 791 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 792 PRIMARY_SURFACE_ADDRESS, 793 address->video_progressive.luma_addr.low_part); 794 break; 795 case PLN_ADDR_TYPE_GRPH_STEREO: 796 if (address->grph_stereo.left_addr.quad_part == 0) 797 break; 798 if (address->grph_stereo.right_addr.quad_part == 0) 799 break; 800 801 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 802 PRIMARY_SURFACE_TMZ, address->tmz_surface, 803 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 804 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 805 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 806 SECONDARY_SURFACE_TMZ, address->tmz_surface, 807 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 808 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 809 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 810 811 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 812 813 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 814 SECONDARY_META_SURFACE_ADDRESS_HIGH, 815 address->grph_stereo.right_meta_addr.high_part); 816 817 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 818 SECONDARY_META_SURFACE_ADDRESS, 819 address->grph_stereo.right_meta_addr.low_part); 820 } 821 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 822 823 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 824 PRIMARY_META_SURFACE_ADDRESS_HIGH, 825 address->grph_stereo.left_meta_addr.high_part); 826 827 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 828 PRIMARY_META_SURFACE_ADDRESS, 829 address->grph_stereo.left_meta_addr.low_part); 830 } 831 832 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 833 SECONDARY_SURFACE_ADDRESS_HIGH, 834 address->grph_stereo.right_addr.high_part); 835 836 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 837 SECONDARY_SURFACE_ADDRESS, 838 address->grph_stereo.right_addr.low_part); 839 840 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 841 PRIMARY_SURFACE_ADDRESS_HIGH, 842 address->grph_stereo.left_addr.high_part); 843 844 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 845 PRIMARY_SURFACE_ADDRESS, 846 address->grph_stereo.left_addr.low_part); 847 break; 848 default: 849 BREAK_TO_DEBUGGER(); 850 break; 851 } 852 853 hubp->request_address = *address; 854 855 return true; 856 } 857 858 void hubp2_enable_triplebuffer( 859 struct hubp *hubp, 860 bool enable) 861 { 862 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 863 uint32_t triple_buffer_en = 0; 864 bool tri_buffer_en; 865 866 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 867 tri_buffer_en = (triple_buffer_en == 1); 868 if (tri_buffer_en != enable) { 869 REG_UPDATE(DCSURF_FLIP_CONTROL2, 870 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); 871 } 872 } 873 874 bool hubp2_is_triplebuffer_enabled( 875 struct hubp *hubp) 876 { 877 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 878 uint32_t triple_buffer_en = 0; 879 880 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 881 882 return (bool)triple_buffer_en; 883 } 884 885 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) 886 { 887 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 888 889 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); 890 } 891 892 bool hubp2_is_flip_pending(struct hubp *hubp) 893 { 894 uint32_t flip_pending = 0; 895 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 896 struct dc_plane_address earliest_inuse_address; 897 898 if (hubp && hubp->power_gated) 899 return false; 900 901 REG_GET(DCSURF_FLIP_CONTROL, 902 SURFACE_FLIP_PENDING, &flip_pending); 903 904 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 905 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 906 907 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 908 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 909 910 if (flip_pending) 911 return true; 912 913 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 914 return true; 915 916 return false; 917 } 918 919 void hubp2_set_blank(struct hubp *hubp, bool blank) 920 { 921 hubp2_set_blank_regs(hubp, blank); 922 923 if (blank) { 924 hubp->mpcc_id = 0xf; 925 hubp->opp_id = OPP_ID_INVALID; 926 } 927 } 928 929 void hubp2_set_blank_regs(struct hubp *hubp, bool blank) 930 { 931 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 932 uint32_t blank_en = blank ? 1 : 0; 933 934 if (blank) { 935 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 936 937 if (reg_val) { 938 /* init sequence workaround: in case HUBP is 939 * power gated, this wait would timeout. 940 * 941 * we just wrote reg_val to non-0, if it stay 0 942 * it means HUBP is gated 943 */ 944 REG_WAIT(DCHUBP_CNTL, 945 HUBP_NO_OUTSTANDING_REQ, 1, 946 1, 100000); 947 } 948 } 949 950 REG_UPDATE_2(DCHUBP_CNTL, 951 HUBP_BLANK_EN, blank_en, 952 HUBP_TTU_DISABLE, 0); 953 } 954 955 void hubp2_cursor_set_position( 956 struct hubp *hubp, 957 const struct dc_cursor_position *pos, 958 const struct dc_cursor_mi_param *param) 959 { 960 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 961 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 962 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 963 int x_hotspot = pos->x_hotspot; 964 int y_hotspot = pos->y_hotspot; 965 int cursor_height = (int)hubp->curs_attr.height; 966 int cursor_width = (int)hubp->curs_attr.width; 967 uint32_t dst_x_offset; 968 uint32_t cur_en = pos->enable ? 1 : 0; 969 970 /* 971 * Guard aganst cursor_set_position() from being called with invalid 972 * attributes 973 * 974 * TODO: Look at combining cursor_set_position() and 975 * cursor_set_attributes() into cursor_update() 976 */ 977 if (hubp->curs_attr.address.quad_part == 0) 978 return; 979 980 // Rotated cursor width/height and hotspots tweaks for offset calculation 981 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 982 swap(cursor_height, cursor_width); 983 if (param->rotation == ROTATION_ANGLE_90) { 984 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; 985 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; 986 } 987 } else if (param->rotation == ROTATION_ANGLE_180) { 988 src_x_offset = pos->x - param->viewport.x; 989 src_y_offset = pos->y - param->viewport.y; 990 } 991 992 if (param->mirror) { 993 x_hotspot = param->viewport.width - x_hotspot; 994 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 995 } 996 997 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 998 dst_x_offset *= param->ref_clk_khz; 999 dst_x_offset /= param->pixel_clk_khz; 1000 1001 ASSERT(param->h_scale_ratio.value); 1002 1003 if (param->h_scale_ratio.value) 1004 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1005 dc_fixpt_from_int(dst_x_offset), 1006 param->h_scale_ratio)); 1007 1008 if (src_x_offset >= (int)param->viewport.width) 1009 cur_en = 0; /* not visible beyond right edge*/ 1010 1011 if (src_x_offset + cursor_width <= 0) 1012 cur_en = 0; /* not visible beyond left edge*/ 1013 1014 if (src_y_offset >= (int)param->viewport.height) 1015 cur_en = 0; /* not visible beyond bottom edge*/ 1016 1017 if (src_y_offset + cursor_height <= 0) 1018 cur_en = 0; /* not visible beyond top edge*/ 1019 1020 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1021 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1022 1023 REG_UPDATE(CURSOR_CONTROL, 1024 CURSOR_ENABLE, cur_en); 1025 1026 REG_SET_2(CURSOR_POSITION, 0, 1027 CURSOR_X_POSITION, pos->x, 1028 CURSOR_Y_POSITION, pos->y); 1029 1030 REG_SET_2(CURSOR_HOT_SPOT, 0, 1031 CURSOR_HOT_SPOT_X, x_hotspot, 1032 CURSOR_HOT_SPOT_Y, y_hotspot); 1033 1034 REG_SET(CURSOR_DST_OFFSET, 0, 1035 CURSOR_DST_X_OFFSET, dst_x_offset); 1036 /* TODO Handle surface pixel formats other than 4:4:4 */ 1037 } 1038 1039 void hubp2_clk_cntl(struct hubp *hubp, bool enable) 1040 { 1041 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1042 uint32_t clk_enable = enable ? 1 : 0; 1043 1044 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1045 } 1046 1047 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1048 { 1049 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1050 1051 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1052 } 1053 1054 void hubp2_clear_underflow(struct hubp *hubp) 1055 { 1056 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1057 1058 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 1059 } 1060 1061 void hubp2_read_state_common(struct hubp *hubp) 1062 { 1063 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1064 struct dcn_hubp_state *s = &hubp2->state; 1065 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 1066 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 1067 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1068 1069 /* Requester */ 1070 REG_GET(HUBPRET_CONTROL, 1071 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 1072 REG_GET_4(DCN_EXPANSION_MODE, 1073 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 1074 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 1075 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1076 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1077 1078 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 1079 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); 1080 1081 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 1082 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); 1083 1084 /* DLG - Per hubp */ 1085 REG_GET_2(BLANK_OFFSET_0, 1086 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 1087 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 1088 1089 REG_GET(BLANK_OFFSET_1, 1090 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 1091 1092 REG_GET(DST_DIMENSIONS, 1093 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 1094 1095 REG_GET_2(DST_AFTER_SCALER, 1096 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 1097 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 1098 1099 if (REG(PREFETCH_SETTINS)) 1100 REG_GET_2(PREFETCH_SETTINS, 1101 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1102 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1103 else 1104 REG_GET_2(PREFETCH_SETTINGS, 1105 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1106 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1107 1108 REG_GET_2(VBLANK_PARAMETERS_0, 1109 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 1110 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 1111 1112 REG_GET(REF_FREQ_TO_PIX_FREQ, 1113 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 1114 1115 /* DLG - Per luma/chroma */ 1116 REG_GET(VBLANK_PARAMETERS_1, 1117 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 1118 1119 REG_GET(VBLANK_PARAMETERS_3, 1120 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 1121 1122 if (REG(NOM_PARAMETERS_0)) 1123 REG_GET(NOM_PARAMETERS_0, 1124 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 1125 1126 if (REG(NOM_PARAMETERS_1)) 1127 REG_GET(NOM_PARAMETERS_1, 1128 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 1129 1130 REG_GET(NOM_PARAMETERS_4, 1131 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 1132 1133 REG_GET(NOM_PARAMETERS_5, 1134 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 1135 1136 REG_GET_2(PER_LINE_DELIVERY_PRE, 1137 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1138 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 1139 1140 REG_GET_2(PER_LINE_DELIVERY, 1141 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 1142 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 1143 1144 if (REG(PREFETCH_SETTINS_C)) 1145 REG_GET(PREFETCH_SETTINS_C, 1146 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1147 else 1148 REG_GET(PREFETCH_SETTINGS_C, 1149 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1150 1151 REG_GET(VBLANK_PARAMETERS_2, 1152 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 1153 1154 REG_GET(VBLANK_PARAMETERS_4, 1155 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 1156 1157 if (REG(NOM_PARAMETERS_2)) 1158 REG_GET(NOM_PARAMETERS_2, 1159 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1160 1161 if (REG(NOM_PARAMETERS_3)) 1162 REG_GET(NOM_PARAMETERS_3, 1163 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1164 1165 REG_GET(NOM_PARAMETERS_6, 1166 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1167 1168 REG_GET(NOM_PARAMETERS_7, 1169 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1170 1171 /* TTU - per hubp */ 1172 REG_GET_2(DCN_TTU_QOS_WM, 1173 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1174 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1175 1176 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1177 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1178 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1179 1180 /* TTU - per luma/chroma */ 1181 /* Assumed surf0 is luma and 1 is chroma */ 1182 1183 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1184 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1185 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1186 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1187 1188 REG_GET(DCN_SURF0_TTU_CNTL1, 1189 REFCYC_PER_REQ_DELIVERY_PRE, 1190 &ttu_attr->refcyc_per_req_delivery_pre_l); 1191 1192 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1193 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1194 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1195 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1196 1197 REG_GET(DCN_SURF1_TTU_CNTL1, 1198 REFCYC_PER_REQ_DELIVERY_PRE, 1199 &ttu_attr->refcyc_per_req_delivery_pre_c); 1200 1201 /* Rest of hubp */ 1202 REG_GET(DCSURF_SURFACE_CONFIG, 1203 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1204 1205 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1206 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1207 1208 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1209 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1210 1211 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1212 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1213 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1214 1215 REG_GET_2(DCSURF_SURFACE_CONFIG, 1216 ROTATION_ANGLE, &s->rotation_angle, 1217 H_MIRROR_EN, &s->h_mirror_en); 1218 1219 REG_GET(DCSURF_TILING_CONFIG, 1220 SW_MODE, &s->sw_mode); 1221 1222 REG_GET(DCSURF_SURFACE_CONTROL, 1223 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1224 1225 REG_GET_3(DCHUBP_CNTL, 1226 HUBP_BLANK_EN, &s->blank_en, 1227 HUBP_TTU_DISABLE, &s->ttu_disable, 1228 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1229 1230 REG_GET(HUBP_CLK_CNTL, 1231 HUBP_CLOCK_ENABLE, &s->clock_en); 1232 1233 REG_GET(DCN_GLOBAL_TTU_CNTL, 1234 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1235 1236 REG_GET_2(DCN_TTU_QOS_WM, 1237 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1238 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1239 1240 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1241 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1242 1243 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1244 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1245 1246 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1247 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1248 1249 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1250 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1251 } 1252 1253 void hubp2_read_state(struct hubp *hubp) 1254 { 1255 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1256 struct dcn_hubp_state *s = &hubp2->state; 1257 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1258 1259 hubp2_read_state_common(hubp); 1260 1261 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1262 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1263 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1264 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1265 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1266 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1267 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1268 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1269 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1270 1271 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1272 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1273 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1274 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1275 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1276 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1277 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1278 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1279 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1280 1281 } 1282 1283 static void hubp2_validate_dml_output(struct hubp *hubp, 1284 struct dc_context *ctx, 1285 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 1286 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 1287 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 1288 { 1289 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1290 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 1291 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 1292 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 1293 DC_LOGGER_INIT(ctx->logger); 1294 DC_LOG_DEBUG("DML Validation | Running Validation"); 1295 1296 /* Requestor Regs */ 1297 REG_GET(HUBPRET_CONTROL, 1298 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 1299 REG_GET_4(DCN_EXPANSION_MODE, 1300 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 1301 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 1302 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 1303 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 1304 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1305 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 1306 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 1307 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 1308 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 1309 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 1310 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 1311 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 1312 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 1313 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1314 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 1315 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 1316 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 1317 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 1318 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 1319 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size, 1320 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 1321 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 1322 1323 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 1324 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1325 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 1326 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 1327 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1328 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 1329 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 1330 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1331 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 1332 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 1333 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1334 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 1335 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 1336 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1337 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 1338 1339 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 1340 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 1341 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 1342 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 1343 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 1344 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 1345 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 1346 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1347 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 1348 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 1349 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1350 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 1351 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 1352 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1353 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 1354 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 1355 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1356 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 1357 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 1358 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 1359 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 1360 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 1361 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 1362 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 1363 1364 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 1365 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1366 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 1367 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 1368 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1369 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 1370 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 1371 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1372 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 1373 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 1374 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1375 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 1376 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 1377 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1378 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 1379 if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size) 1380 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1381 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size); 1382 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 1383 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 1384 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 1385 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 1386 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 1387 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 1388 1389 /* DLG - Per hubp */ 1390 REG_GET_2(BLANK_OFFSET_0, 1391 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 1392 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 1393 REG_GET(BLANK_OFFSET_1, 1394 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 1395 REG_GET(DST_DIMENSIONS, 1396 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 1397 REG_GET_2(DST_AFTER_SCALER, 1398 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 1399 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 1400 REG_GET(REF_FREQ_TO_PIX_FREQ, 1401 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 1402 1403 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 1404 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 1405 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 1406 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 1407 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 1408 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 1409 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 1410 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 1411 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 1412 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 1413 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 1414 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 1415 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 1416 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 1417 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 1418 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 1419 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 1420 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 1421 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 1422 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 1423 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 1424 1425 /* DLG - Per luma/chroma */ 1426 REG_GET(VBLANK_PARAMETERS_1, 1427 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 1428 if (REG(NOM_PARAMETERS_0)) 1429 REG_GET(NOM_PARAMETERS_0, 1430 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 1431 if (REG(NOM_PARAMETERS_1)) 1432 REG_GET(NOM_PARAMETERS_1, 1433 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 1434 REG_GET(NOM_PARAMETERS_4, 1435 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 1436 REG_GET(NOM_PARAMETERS_5, 1437 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 1438 REG_GET_2(PER_LINE_DELIVERY, 1439 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 1440 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 1441 REG_GET_2(PER_LINE_DELIVERY_PRE, 1442 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 1443 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 1444 REG_GET(VBLANK_PARAMETERS_2, 1445 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 1446 if (REG(NOM_PARAMETERS_2)) 1447 REG_GET(NOM_PARAMETERS_2, 1448 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 1449 if (REG(NOM_PARAMETERS_3)) 1450 REG_GET(NOM_PARAMETERS_3, 1451 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 1452 REG_GET(NOM_PARAMETERS_6, 1453 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 1454 REG_GET(NOM_PARAMETERS_7, 1455 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 1456 REG_GET(VBLANK_PARAMETERS_3, 1457 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 1458 REG_GET(VBLANK_PARAMETERS_4, 1459 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 1460 1461 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 1462 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 1463 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 1464 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 1465 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 1466 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 1467 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 1468 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 1469 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 1470 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 1471 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 1472 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 1473 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 1474 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 1475 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 1476 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 1477 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 1478 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 1479 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 1480 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 1481 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 1482 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 1483 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 1484 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 1485 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 1486 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 1487 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 1488 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 1489 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 1490 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 1491 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 1492 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 1493 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 1494 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 1495 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 1496 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 1497 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 1498 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 1499 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 1500 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 1501 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 1502 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 1503 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 1504 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 1505 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 1506 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 1507 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 1508 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 1509 1510 /* TTU - per hubp */ 1511 REG_GET_2(DCN_TTU_QOS_WM, 1512 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 1513 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 1514 1515 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 1516 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 1517 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 1518 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 1519 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 1520 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 1521 1522 /* TTU - per luma/chroma */ 1523 /* Assumed surf0 is luma and 1 is chroma */ 1524 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1525 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 1526 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 1527 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 1528 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1529 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 1530 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 1531 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 1532 REG_GET_3(DCN_CUR0_TTU_CNTL0, 1533 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 1534 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 1535 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 1536 REG_GET(FLIP_PARAMETERS_1, 1537 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 1538 REG_GET(DCN_CUR0_TTU_CNTL1, 1539 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 1540 REG_GET(DCN_CUR1_TTU_CNTL1, 1541 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 1542 REG_GET(DCN_SURF0_TTU_CNTL1, 1543 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 1544 REG_GET(DCN_SURF1_TTU_CNTL1, 1545 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 1546 1547 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 1548 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1549 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 1550 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 1551 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1552 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 1553 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 1554 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1555 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 1556 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 1557 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1558 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 1559 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 1560 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1561 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 1562 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 1563 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1564 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 1565 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 1566 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1567 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 1568 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 1569 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1570 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 1571 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 1572 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1573 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 1574 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 1575 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 1576 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 1577 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 1578 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1579 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 1580 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 1581 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1582 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 1583 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 1584 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1585 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 1586 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 1587 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1588 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 1589 } 1590 1591 static struct hubp_funcs dcn20_hubp_funcs = { 1592 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 1593 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 1594 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 1595 .hubp_program_surface_config = hubp2_program_surface_config, 1596 .hubp_is_flip_pending = hubp2_is_flip_pending, 1597 .hubp_setup = hubp2_setup, 1598 .hubp_setup_interdependent = hubp2_setup_interdependent, 1599 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, 1600 .set_blank = hubp2_set_blank, 1601 .set_blank_regs = hubp2_set_blank_regs, 1602 .dcc_control = hubp2_dcc_control, 1603 .mem_program_viewport = min_set_viewport, 1604 .set_cursor_attributes = hubp2_cursor_set_attributes, 1605 .set_cursor_position = hubp2_cursor_set_position, 1606 .hubp_clk_cntl = hubp2_clk_cntl, 1607 .hubp_vtg_sel = hubp2_vtg_sel, 1608 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 1609 .dmdata_load = hubp2_dmdata_load, 1610 .dmdata_status_done = hubp2_dmdata_status_done, 1611 .hubp_read_state = hubp2_read_state, 1612 .hubp_clear_underflow = hubp2_clear_underflow, 1613 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1614 .hubp_init = hubp1_init, 1615 .validate_dml_output = hubp2_validate_dml_output, 1616 .hubp_in_blank = hubp1_in_blank, 1617 .hubp_soft_reset = hubp1_soft_reset, 1618 .hubp_set_flip_int = hubp1_set_flip_int, 1619 }; 1620 1621 1622 bool hubp2_construct( 1623 struct dcn20_hubp *hubp2, 1624 struct dc_context *ctx, 1625 uint32_t inst, 1626 const struct dcn_hubp2_registers *hubp_regs, 1627 const struct dcn_hubp2_shift *hubp_shift, 1628 const struct dcn_hubp2_mask *hubp_mask) 1629 { 1630 hubp2->base.funcs = &dcn20_hubp_funcs; 1631 hubp2->base.ctx = ctx; 1632 hubp2->hubp_regs = hubp_regs; 1633 hubp2->hubp_shift = hubp_shift; 1634 hubp2->hubp_mask = hubp_mask; 1635 hubp2->base.inst = inst; 1636 hubp2->base.opp_id = OPP_ID_INVALID; 1637 hubp2->base.mpcc_id = 0xf; 1638 1639 return true; 1640 } 1641