1 /* 2 * Copyright 2012-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn20_hubp.h" 27 28 #include "dm_services.h" 29 #include "dce_calcs.h" 30 #include "reg_helper.h" 31 #include "basics/conversion.h" 32 33 #define DC_LOGGER_INIT(logger) 34 35 #define REG(reg)\ 36 hubp2->hubp_regs->reg 37 38 #define CTX \ 39 hubp2->base.ctx 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 44 45 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 46 struct vm_system_aperture_param *apt) 47 { 48 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 49 50 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 51 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 52 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 53 54 // The format of default addr is 48:12 of the 48 bit addr 55 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 56 57 // The format of high/low are 48:18 of the 48 bit addr 58 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 59 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 60 61 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 62 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ 63 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 64 65 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 66 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 67 68 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 69 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 70 71 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 72 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 73 74 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 75 ENABLE_L1_TLB, 1, 76 SYSTEM_ACCESS_MODE, 0x3); 77 } 78 79 void hubp2_program_deadline( 80 struct hubp *hubp, 81 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 82 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 83 { 84 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 85 86 /* DLG - Per hubp */ 87 REG_SET_2(BLANK_OFFSET_0, 0, 88 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 89 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 90 91 REG_SET(BLANK_OFFSET_1, 0, 92 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 93 94 REG_SET(DST_DIMENSIONS, 0, 95 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 96 97 REG_SET_2(DST_AFTER_SCALER, 0, 98 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 99 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 100 101 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 102 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 103 104 /* DLG - Per luma/chroma */ 105 REG_SET(VBLANK_PARAMETERS_1, 0, 106 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 107 108 if (REG(NOM_PARAMETERS_0)) 109 REG_SET(NOM_PARAMETERS_0, 0, 110 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 111 112 if (REG(NOM_PARAMETERS_1)) 113 REG_SET(NOM_PARAMETERS_1, 0, 114 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 115 116 REG_SET(NOM_PARAMETERS_4, 0, 117 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 118 119 REG_SET(NOM_PARAMETERS_5, 0, 120 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 121 122 REG_SET_2(PER_LINE_DELIVERY, 0, 123 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 124 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 125 126 REG_SET(VBLANK_PARAMETERS_2, 0, 127 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 128 129 if (REG(NOM_PARAMETERS_2)) 130 REG_SET(NOM_PARAMETERS_2, 0, 131 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 132 133 if (REG(NOM_PARAMETERS_3)) 134 REG_SET(NOM_PARAMETERS_3, 0, 135 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 136 137 REG_SET(NOM_PARAMETERS_6, 0, 138 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 139 140 REG_SET(NOM_PARAMETERS_7, 0, 141 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 142 143 /* TTU - per hubp */ 144 REG_SET_2(DCN_TTU_QOS_WM, 0, 145 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 146 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 147 148 /* TTU - per luma/chroma */ 149 /* Assumed surf0 is luma and 1 is chroma */ 150 151 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 152 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 153 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 154 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 155 156 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 157 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 158 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 159 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 160 161 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 162 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 163 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 164 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 165 166 REG_SET(FLIP_PARAMETERS_1, 0, 167 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 168 } 169 170 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 171 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 172 { 173 uint32_t value = 0; 174 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 175 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ 176 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 177 /* 178 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) 179 <= OTG_V_BLANK_END 180 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 181 else 182 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 183 */ 184 if (pipe_dest->htotal != 0) { 185 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width 186 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 187 value = 1; 188 } else 189 value = 0; 190 } 191 192 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); 193 } 194 195 void hubp2_program_requestor( 196 struct hubp *hubp, 197 struct _vcs_dpi_display_rq_regs_st *rq_regs) 198 { 199 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 200 201 REG_UPDATE(HUBPRET_CONTROL, 202 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 203 REG_SET_4(DCN_EXPANSION_MODE, 0, 204 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 205 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 206 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 207 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 208 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 209 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 210 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 211 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 212 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 213 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 214 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 215 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 216 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 217 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 218 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 219 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 220 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 221 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 222 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 223 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 224 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 225 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 226 } 227 228 static void hubp2_setup( 229 struct hubp *hubp, 230 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 231 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 232 struct _vcs_dpi_display_rq_regs_st *rq_regs, 233 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 234 { 235 /* otg is locked when this func is called. Register are double buffered. 236 * disable the requestors is not needed 237 */ 238 239 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 240 hubp2_program_requestor(hubp, rq_regs); 241 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 242 243 } 244 245 void hubp2_setup_interdependent( 246 struct hubp *hubp, 247 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 248 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 249 { 250 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 251 252 REG_SET_2(PREFETCH_SETTINGS, 0, 253 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 254 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 255 256 REG_SET(PREFETCH_SETTINGS_C, 0, 257 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 258 259 REG_SET_2(VBLANK_PARAMETERS_0, 0, 260 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 261 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 262 263 REG_SET_2(FLIP_PARAMETERS_0, 0, 264 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, 265 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); 266 267 REG_SET(VBLANK_PARAMETERS_3, 0, 268 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 269 270 REG_SET(VBLANK_PARAMETERS_4, 0, 271 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 272 273 REG_SET(FLIP_PARAMETERS_2, 0, 274 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); 275 276 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 277 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 278 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 279 280 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 281 REFCYC_PER_REQ_DELIVERY_PRE, 282 ttu_attr->refcyc_per_req_delivery_pre_l); 283 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 284 REFCYC_PER_REQ_DELIVERY_PRE, 285 ttu_attr->refcyc_per_req_delivery_pre_c); 286 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 287 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 288 REG_SET(DCN_CUR1_TTU_CNTL1, 0, 289 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); 290 291 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 292 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 293 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 294 } 295 296 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: 297 * NUM_BANKS 298 * NUM_SE 299 * NUM_RB_PER_SE 300 * RB_ALIGNED 301 * Other things can be defaulted, since they never change: 302 * PIPE_ALIGNED = 0 303 * META_LINEAR = 0 304 * In GFX10, only these apply: 305 * PIPE_INTERLEAVE 306 * NUM_PIPES 307 * MAX_COMPRESSED_FRAGS 308 * SW_MODE 309 */ 310 static void hubp2_program_tiling( 311 struct dcn20_hubp *hubp2, 312 const union dc_tiling_info *info, 313 const enum surface_pixel_format pixel_format) 314 { 315 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 316 NUM_PIPES, log_2(info->gfx9.num_pipes), 317 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 318 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 319 320 REG_UPDATE_4(DCSURF_TILING_CONFIG, 321 SW_MODE, info->gfx9.swizzle, 322 META_LINEAR, 0, 323 RB_ALIGNED, 0, 324 PIPE_ALIGNED, 0); 325 } 326 327 void hubp2_program_size( 328 struct hubp *hubp, 329 enum surface_pixel_format format, 330 const struct plane_size *plane_size, 331 struct dc_plane_dcc_param *dcc) 332 { 333 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 334 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 335 bool use_pitch_c = false; 336 337 /* Program data and meta surface pitch (calculation from addrlib) 338 * 444 or 420 luma 339 */ 340 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 341 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; 342 use_pitch_c = use_pitch_c 343 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 344 if (use_pitch_c) { 345 ASSERT(plane_size->chroma_pitch != 0); 346 /* Chroma pitch zero can cause system hang! */ 347 348 pitch = plane_size->surface_pitch - 1; 349 meta_pitch = dcc->meta_pitch - 1; 350 pitch_c = plane_size->chroma_pitch - 1; 351 meta_pitch_c = dcc->meta_pitch_c - 1; 352 } else { 353 pitch = plane_size->surface_pitch - 1; 354 meta_pitch = dcc->meta_pitch - 1; 355 pitch_c = 0; 356 meta_pitch_c = 0; 357 } 358 359 if (!dcc->enable) { 360 meta_pitch = 0; 361 meta_pitch_c = 0; 362 } 363 364 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 365 PITCH, pitch, META_PITCH, meta_pitch); 366 367 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; 368 use_pitch_c = use_pitch_c 369 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 370 if (use_pitch_c) 371 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 372 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 373 } 374 375 void hubp2_program_rotation( 376 struct hubp *hubp, 377 enum dc_rotation_angle rotation, 378 bool horizontal_mirror) 379 { 380 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 381 uint32_t mirror; 382 383 384 if (horizontal_mirror) 385 mirror = 1; 386 else 387 mirror = 0; 388 389 /* Program rotation angle and horz mirror - no mirror */ 390 if (rotation == ROTATION_ANGLE_0) 391 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 392 ROTATION_ANGLE, 0, 393 H_MIRROR_EN, mirror); 394 else if (rotation == ROTATION_ANGLE_90) 395 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 396 ROTATION_ANGLE, 1, 397 H_MIRROR_EN, mirror); 398 else if (rotation == ROTATION_ANGLE_180) 399 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 400 ROTATION_ANGLE, 2, 401 H_MIRROR_EN, mirror); 402 else if (rotation == ROTATION_ANGLE_270) 403 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 404 ROTATION_ANGLE, 3, 405 H_MIRROR_EN, mirror); 406 } 407 408 void hubp2_dcc_control(struct hubp *hubp, bool enable, 409 enum hubp_ind_block_size independent_64b_blks) 410 { 411 uint32_t dcc_en = enable ? 1 : 0; 412 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 413 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 414 415 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 416 PRIMARY_SURFACE_DCC_EN, dcc_en, 417 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 418 SECONDARY_SURFACE_DCC_EN, dcc_en, 419 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 420 } 421 422 void hubp2_program_pixel_format( 423 struct hubp *hubp, 424 enum surface_pixel_format format) 425 { 426 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 427 uint32_t red_bar = 3; 428 uint32_t blue_bar = 2; 429 430 /* swap for ABGR format */ 431 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 432 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 433 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 434 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 435 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 436 red_bar = 2; 437 blue_bar = 3; 438 } 439 440 REG_UPDATE_2(HUBPRET_CONTROL, 441 CROSSBAR_SRC_CB_B, blue_bar, 442 CROSSBAR_SRC_CR_R, red_bar); 443 444 /* Mapping is same as ipp programming (cnvc) */ 445 446 switch (format) { 447 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 448 REG_UPDATE(DCSURF_SURFACE_CONFIG, 449 SURFACE_PIXEL_FORMAT, 1); 450 break; 451 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 452 REG_UPDATE(DCSURF_SURFACE_CONFIG, 453 SURFACE_PIXEL_FORMAT, 3); 454 break; 455 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 456 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 457 REG_UPDATE(DCSURF_SURFACE_CONFIG, 458 SURFACE_PIXEL_FORMAT, 8); 459 break; 460 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 461 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 462 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 463 REG_UPDATE(DCSURF_SURFACE_CONFIG, 464 SURFACE_PIXEL_FORMAT, 10); 465 break; 466 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 467 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ 468 REG_UPDATE(DCSURF_SURFACE_CONFIG, 469 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 470 break; 471 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 472 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 473 REG_UPDATE(DCSURF_SURFACE_CONFIG, 474 SURFACE_PIXEL_FORMAT, 24); 475 break; 476 477 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 478 REG_UPDATE(DCSURF_SURFACE_CONFIG, 479 SURFACE_PIXEL_FORMAT, 65); 480 break; 481 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 482 REG_UPDATE(DCSURF_SURFACE_CONFIG, 483 SURFACE_PIXEL_FORMAT, 64); 484 break; 485 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 486 REG_UPDATE(DCSURF_SURFACE_CONFIG, 487 SURFACE_PIXEL_FORMAT, 67); 488 break; 489 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 490 REG_UPDATE(DCSURF_SURFACE_CONFIG, 491 SURFACE_PIXEL_FORMAT, 66); 492 break; 493 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 494 REG_UPDATE(DCSURF_SURFACE_CONFIG, 495 SURFACE_PIXEL_FORMAT, 12); 496 break; 497 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 498 REG_UPDATE(DCSURF_SURFACE_CONFIG, 499 SURFACE_PIXEL_FORMAT, 112); 500 break; 501 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 502 REG_UPDATE(DCSURF_SURFACE_CONFIG, 503 SURFACE_PIXEL_FORMAT, 113); 504 break; 505 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 506 REG_UPDATE(DCSURF_SURFACE_CONFIG, 507 SURFACE_PIXEL_FORMAT, 114); 508 break; 509 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 510 REG_UPDATE(DCSURF_SURFACE_CONFIG, 511 SURFACE_PIXEL_FORMAT, 118); 512 break; 513 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 514 REG_UPDATE(DCSURF_SURFACE_CONFIG, 515 SURFACE_PIXEL_FORMAT, 119); 516 break; 517 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 518 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 519 SURFACE_PIXEL_FORMAT, 116, 520 ALPHA_PLANE_EN, 0); 521 break; 522 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 523 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 524 SURFACE_PIXEL_FORMAT, 116, 525 ALPHA_PLANE_EN, 1); 526 break; 527 default: 528 BREAK_TO_DEBUGGER(); 529 break; 530 } 531 532 /* don't see the need of program the xbar in DCN 1.0 */ 533 } 534 535 void hubp2_program_surface_config( 536 struct hubp *hubp, 537 enum surface_pixel_format format, 538 union dc_tiling_info *tiling_info, 539 struct plane_size *plane_size, 540 enum dc_rotation_angle rotation, 541 struct dc_plane_dcc_param *dcc, 542 bool horizontal_mirror, 543 unsigned int compat_level) 544 { 545 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 546 547 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 548 hubp2_program_tiling(hubp2, tiling_info, format); 549 hubp2_program_size(hubp, format, plane_size, dcc); 550 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 551 hubp2_program_pixel_format(hubp, format); 552 } 553 554 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 555 unsigned int cursor_width, 556 enum dc_cursor_color_format cursor_mode) 557 { 558 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 559 560 if (cursor_mode == CURSOR_MODE_MONO) 561 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 562 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || 563 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 564 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 565 if (cursor_width >= 1 && cursor_width <= 32) 566 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 567 else if (cursor_width >= 33 && cursor_width <= 64) 568 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 569 else if (cursor_width >= 65 && cursor_width <= 128) 570 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 571 else if (cursor_width >= 129 && cursor_width <= 256) 572 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 573 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || 574 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { 575 if (cursor_width >= 1 && cursor_width <= 16) 576 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 577 else if (cursor_width >= 17 && cursor_width <= 32) 578 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 579 else if (cursor_width >= 33 && cursor_width <= 64) 580 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 581 else if (cursor_width >= 65 && cursor_width <= 128) 582 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 583 else if (cursor_width >= 129 && cursor_width <= 256) 584 line_per_chunk = CURSOR_LINE_PER_CHUNK_1; 585 } 586 587 return line_per_chunk; 588 } 589 590 void hubp2_cursor_set_attributes( 591 struct hubp *hubp, 592 const struct dc_cursor_attributes *attr) 593 { 594 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 595 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 596 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 597 attr->width, attr->color_format); 598 599 hubp->curs_attr = *attr; 600 601 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 602 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 603 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 604 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 605 606 REG_UPDATE_2(CURSOR_SIZE, 607 CURSOR_WIDTH, attr->width, 608 CURSOR_HEIGHT, attr->height); 609 610 REG_UPDATE_4(CURSOR_CONTROL, 611 CURSOR_MODE, attr->color_format, 612 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 613 CURSOR_PITCH, hw_pitch, 614 CURSOR_LINES_PER_CHUNK, lpc); 615 616 REG_SET_2(CURSOR_SETTINGS, 0, 617 /* no shift of the cursor HDL schedule */ 618 CURSOR0_DST_Y_OFFSET, 0, 619 /* used to shift the cursor chunk request deadline */ 620 CURSOR0_CHUNK_HDL_ADJUST, 3); 621 } 622 623 void hubp2_dmdata_set_attributes( 624 struct hubp *hubp, 625 const struct dc_dmdata_attributes *attr) 626 { 627 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 628 629 if (attr->dmdata_mode == DMDATA_HW_MODE) { 630 /* set to HW mode */ 631 REG_UPDATE(DMDATA_CNTL, 632 DMDATA_MODE, 1); 633 634 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ 635 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); 636 637 /* toggle DMDATA_UPDATED and set repeat and size */ 638 REG_UPDATE(DMDATA_CNTL, 639 DMDATA_UPDATED, 0); 640 REG_UPDATE_3(DMDATA_CNTL, 641 DMDATA_UPDATED, 1, 642 DMDATA_REPEAT, attr->dmdata_repeat, 643 DMDATA_SIZE, attr->dmdata_size); 644 645 /* set DMDATA address */ 646 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); 647 REG_UPDATE(DMDATA_ADDRESS_HIGH, 648 DMDATA_ADDRESS_HIGH, attr->address.high_part); 649 650 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); 651 652 } else { 653 /* set to SW mode before loading data */ 654 REG_SET(DMDATA_CNTL, 0, 655 DMDATA_MODE, 0); 656 /* toggle DMDATA_SW_UPDATED to start loading sequence */ 657 REG_UPDATE(DMDATA_SW_CNTL, 658 DMDATA_SW_UPDATED, 0); 659 REG_UPDATE_3(DMDATA_SW_CNTL, 660 DMDATA_SW_UPDATED, 1, 661 DMDATA_SW_REPEAT, attr->dmdata_repeat, 662 DMDATA_SW_SIZE, attr->dmdata_size); 663 /* load data into hubp dmdata buffer */ 664 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); 665 } 666 667 /* Note that DL_DELTA must be programmed if we want to use TTU mode */ 668 REG_SET_3(DMDATA_QOS_CNTL, 0, 669 DMDATA_QOS_MODE, attr->dmdata_qos_mode, 670 DMDATA_QOS_LEVEL, attr->dmdata_qos_level, 671 DMDATA_DL_DELTA, attr->dmdata_dl_delta); 672 } 673 674 void hubp2_dmdata_load( 675 struct hubp *hubp, 676 uint32_t dmdata_sw_size, 677 const uint32_t *dmdata_sw_data) 678 { 679 int i; 680 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 681 682 /* load dmdata into HUBP buffer in SW mode */ 683 for (i = 0; i < dmdata_sw_size / 4; i++) 684 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); 685 } 686 687 bool hubp2_dmdata_status_done(struct hubp *hubp) 688 { 689 uint32_t status; 690 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 691 692 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); 693 return (status == 1); 694 } 695 696 bool hubp2_program_surface_flip_and_addr( 697 struct hubp *hubp, 698 const struct dc_plane_address *address, 699 bool flip_immediate) 700 { 701 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 702 703 //program flip type 704 REG_UPDATE(DCSURF_FLIP_CONTROL, 705 SURFACE_FLIP_TYPE, flip_immediate); 706 707 // Program VMID reg 708 REG_UPDATE(VMID_SETTINGS_0, 709 VMID, address->vmid); 710 711 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 712 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 713 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 714 715 } else { 716 // turn off stereo if not in stereo 717 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 718 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 719 } 720 721 722 723 /* HW automatically latch rest of address register on write to 724 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 725 * 726 * program high first and then the low addr, order matters! 727 */ 728 switch (address->type) { 729 case PLN_ADDR_TYPE_GRAPHICS: 730 /* DCN1.0 does not support const color 731 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 732 * base on address->grph.dcc_const_color 733 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 734 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 735 */ 736 737 if (address->grph.addr.quad_part == 0) 738 break; 739 740 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 741 PRIMARY_SURFACE_TMZ, address->tmz_surface, 742 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 743 744 if (address->grph.meta_addr.quad_part != 0) { 745 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 746 PRIMARY_META_SURFACE_ADDRESS_HIGH, 747 address->grph.meta_addr.high_part); 748 749 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 750 PRIMARY_META_SURFACE_ADDRESS, 751 address->grph.meta_addr.low_part); 752 } 753 754 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 755 PRIMARY_SURFACE_ADDRESS_HIGH, 756 address->grph.addr.high_part); 757 758 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 759 PRIMARY_SURFACE_ADDRESS, 760 address->grph.addr.low_part); 761 break; 762 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 763 if (address->video_progressive.luma_addr.quad_part == 0 764 || address->video_progressive.chroma_addr.quad_part == 0) 765 break; 766 767 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 768 PRIMARY_SURFACE_TMZ, address->tmz_surface, 769 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 770 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 771 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 772 773 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 774 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 775 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 776 address->video_progressive.chroma_meta_addr.high_part); 777 778 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 779 PRIMARY_META_SURFACE_ADDRESS_C, 780 address->video_progressive.chroma_meta_addr.low_part); 781 782 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 783 PRIMARY_META_SURFACE_ADDRESS_HIGH, 784 address->video_progressive.luma_meta_addr.high_part); 785 786 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 787 PRIMARY_META_SURFACE_ADDRESS, 788 address->video_progressive.luma_meta_addr.low_part); 789 } 790 791 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 792 PRIMARY_SURFACE_ADDRESS_HIGH_C, 793 address->video_progressive.chroma_addr.high_part); 794 795 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 796 PRIMARY_SURFACE_ADDRESS_C, 797 address->video_progressive.chroma_addr.low_part); 798 799 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 800 PRIMARY_SURFACE_ADDRESS_HIGH, 801 address->video_progressive.luma_addr.high_part); 802 803 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 804 PRIMARY_SURFACE_ADDRESS, 805 address->video_progressive.luma_addr.low_part); 806 break; 807 case PLN_ADDR_TYPE_GRPH_STEREO: 808 if (address->grph_stereo.left_addr.quad_part == 0) 809 break; 810 if (address->grph_stereo.right_addr.quad_part == 0) 811 break; 812 813 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 814 PRIMARY_SURFACE_TMZ, address->tmz_surface, 815 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 816 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 817 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 818 SECONDARY_SURFACE_TMZ, address->tmz_surface, 819 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 820 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 821 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 822 823 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 824 825 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 826 SECONDARY_META_SURFACE_ADDRESS_HIGH, 827 address->grph_stereo.right_meta_addr.high_part); 828 829 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 830 SECONDARY_META_SURFACE_ADDRESS, 831 address->grph_stereo.right_meta_addr.low_part); 832 } 833 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 834 835 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 836 PRIMARY_META_SURFACE_ADDRESS_HIGH, 837 address->grph_stereo.left_meta_addr.high_part); 838 839 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 840 PRIMARY_META_SURFACE_ADDRESS, 841 address->grph_stereo.left_meta_addr.low_part); 842 } 843 844 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 845 SECONDARY_SURFACE_ADDRESS_HIGH, 846 address->grph_stereo.right_addr.high_part); 847 848 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 849 SECONDARY_SURFACE_ADDRESS, 850 address->grph_stereo.right_addr.low_part); 851 852 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 853 PRIMARY_SURFACE_ADDRESS_HIGH, 854 address->grph_stereo.left_addr.high_part); 855 856 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 857 PRIMARY_SURFACE_ADDRESS, 858 address->grph_stereo.left_addr.low_part); 859 break; 860 default: 861 BREAK_TO_DEBUGGER(); 862 break; 863 } 864 865 hubp->request_address = *address; 866 867 return true; 868 } 869 870 void hubp2_enable_triplebuffer( 871 struct hubp *hubp, 872 bool enable) 873 { 874 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 875 uint32_t triple_buffer_en = 0; 876 bool tri_buffer_en; 877 878 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 879 tri_buffer_en = (triple_buffer_en == 1); 880 if (tri_buffer_en != enable) { 881 REG_UPDATE(DCSURF_FLIP_CONTROL2, 882 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); 883 } 884 } 885 886 bool hubp2_is_triplebuffer_enabled( 887 struct hubp *hubp) 888 { 889 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 890 uint32_t triple_buffer_en = 0; 891 892 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 893 894 return (bool)triple_buffer_en; 895 } 896 897 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) 898 { 899 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 900 901 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); 902 } 903 904 bool hubp2_is_flip_pending(struct hubp *hubp) 905 { 906 uint32_t flip_pending = 0; 907 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 908 struct dc_plane_address earliest_inuse_address; 909 910 if (hubp && hubp->power_gated) 911 return false; 912 913 REG_GET(DCSURF_FLIP_CONTROL, 914 SURFACE_FLIP_PENDING, &flip_pending); 915 916 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 917 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 918 919 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 920 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 921 922 if (flip_pending) 923 return true; 924 925 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 926 return true; 927 928 return false; 929 } 930 931 void hubp2_set_blank(struct hubp *hubp, bool blank) 932 { 933 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 934 uint32_t blank_en = blank ? 1 : 0; 935 936 REG_UPDATE_2(DCHUBP_CNTL, 937 HUBP_BLANK_EN, blank_en, 938 HUBP_TTU_DISABLE, blank_en); 939 940 if (blank) { 941 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 942 943 if (reg_val) { 944 /* init sequence workaround: in case HUBP is 945 * power gated, this wait would timeout. 946 * 947 * we just wrote reg_val to non-0, if it stay 0 948 * it means HUBP is gated 949 */ 950 REG_WAIT(DCHUBP_CNTL, 951 HUBP_NO_OUTSTANDING_REQ, 1, 952 1, 200); 953 } 954 955 hubp->mpcc_id = 0xf; 956 hubp->opp_id = OPP_ID_INVALID; 957 } 958 } 959 960 void hubp2_cursor_set_position( 961 struct hubp *hubp, 962 const struct dc_cursor_position *pos, 963 const struct dc_cursor_mi_param *param) 964 { 965 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 966 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 967 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 968 int x_hotspot = pos->x_hotspot; 969 int y_hotspot = pos->y_hotspot; 970 int cursor_height = (int)hubp->curs_attr.height; 971 int cursor_width = (int)hubp->curs_attr.width; 972 uint32_t dst_x_offset; 973 uint32_t cur_en = pos->enable ? 1 : 0; 974 975 /* 976 * Guard aganst cursor_set_position() from being called with invalid 977 * attributes 978 * 979 * TODO: Look at combining cursor_set_position() and 980 * cursor_set_attributes() into cursor_update() 981 */ 982 if (hubp->curs_attr.address.quad_part == 0) 983 return; 984 985 // Rotated cursor width/height and hotspots tweaks for offset calculation 986 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 987 swap(cursor_height, cursor_width); 988 if (param->rotation == ROTATION_ANGLE_90) { 989 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; 990 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; 991 } 992 } else if (param->rotation == ROTATION_ANGLE_180) { 993 src_x_offset = pos->x - param->viewport.x; 994 src_y_offset = pos->y - param->viewport.y; 995 } 996 997 if (param->mirror) { 998 x_hotspot = param->viewport.width - x_hotspot; 999 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 1000 } 1001 1002 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1003 dst_x_offset *= param->ref_clk_khz; 1004 dst_x_offset /= param->pixel_clk_khz; 1005 1006 ASSERT(param->h_scale_ratio.value); 1007 1008 if (param->h_scale_ratio.value) 1009 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1010 dc_fixpt_from_int(dst_x_offset), 1011 param->h_scale_ratio)); 1012 1013 if (src_x_offset >= (int)param->viewport.width) 1014 cur_en = 0; /* not visible beyond right edge*/ 1015 1016 if (src_x_offset + cursor_width <= 0) 1017 cur_en = 0; /* not visible beyond left edge*/ 1018 1019 if (src_y_offset >= (int)param->viewport.height) 1020 cur_en = 0; /* not visible beyond bottom edge*/ 1021 1022 if (src_y_offset + cursor_height <= 0) 1023 cur_en = 0; /* not visible beyond top edge*/ 1024 1025 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1026 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1027 1028 REG_UPDATE(CURSOR_CONTROL, 1029 CURSOR_ENABLE, cur_en); 1030 1031 REG_SET_2(CURSOR_POSITION, 0, 1032 CURSOR_X_POSITION, pos->x, 1033 CURSOR_Y_POSITION, pos->y); 1034 1035 REG_SET_2(CURSOR_HOT_SPOT, 0, 1036 CURSOR_HOT_SPOT_X, x_hotspot, 1037 CURSOR_HOT_SPOT_Y, y_hotspot); 1038 1039 REG_SET(CURSOR_DST_OFFSET, 0, 1040 CURSOR_DST_X_OFFSET, dst_x_offset); 1041 /* TODO Handle surface pixel formats other than 4:4:4 */ 1042 } 1043 1044 void hubp2_clk_cntl(struct hubp *hubp, bool enable) 1045 { 1046 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1047 uint32_t clk_enable = enable ? 1 : 0; 1048 1049 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1050 } 1051 1052 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1053 { 1054 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1055 1056 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1057 } 1058 1059 void hubp2_clear_underflow(struct hubp *hubp) 1060 { 1061 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1062 1063 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 1064 } 1065 1066 void hubp2_read_state_common(struct hubp *hubp) 1067 { 1068 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1069 struct dcn_hubp_state *s = &hubp2->state; 1070 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 1071 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 1072 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1073 1074 /* Requester */ 1075 REG_GET(HUBPRET_CONTROL, 1076 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 1077 REG_GET_4(DCN_EXPANSION_MODE, 1078 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 1079 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 1080 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1081 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1082 1083 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 1084 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); 1085 1086 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 1087 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); 1088 1089 /* DLG - Per hubp */ 1090 REG_GET_2(BLANK_OFFSET_0, 1091 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 1092 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 1093 1094 REG_GET(BLANK_OFFSET_1, 1095 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 1096 1097 REG_GET(DST_DIMENSIONS, 1098 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 1099 1100 REG_GET_2(DST_AFTER_SCALER, 1101 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 1102 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 1103 1104 if (REG(PREFETCH_SETTINS)) 1105 REG_GET_2(PREFETCH_SETTINS, 1106 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1107 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1108 else 1109 REG_GET_2(PREFETCH_SETTINGS, 1110 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1111 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1112 1113 REG_GET_2(VBLANK_PARAMETERS_0, 1114 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 1115 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 1116 1117 REG_GET(REF_FREQ_TO_PIX_FREQ, 1118 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 1119 1120 /* DLG - Per luma/chroma */ 1121 REG_GET(VBLANK_PARAMETERS_1, 1122 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 1123 1124 REG_GET(VBLANK_PARAMETERS_3, 1125 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 1126 1127 if (REG(NOM_PARAMETERS_0)) 1128 REG_GET(NOM_PARAMETERS_0, 1129 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 1130 1131 if (REG(NOM_PARAMETERS_1)) 1132 REG_GET(NOM_PARAMETERS_1, 1133 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 1134 1135 REG_GET(NOM_PARAMETERS_4, 1136 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 1137 1138 REG_GET(NOM_PARAMETERS_5, 1139 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 1140 1141 REG_GET_2(PER_LINE_DELIVERY_PRE, 1142 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1143 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 1144 1145 REG_GET_2(PER_LINE_DELIVERY, 1146 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 1147 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 1148 1149 if (REG(PREFETCH_SETTINS_C)) 1150 REG_GET(PREFETCH_SETTINS_C, 1151 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1152 else 1153 REG_GET(PREFETCH_SETTINGS_C, 1154 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1155 1156 REG_GET(VBLANK_PARAMETERS_2, 1157 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 1158 1159 REG_GET(VBLANK_PARAMETERS_4, 1160 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 1161 1162 if (REG(NOM_PARAMETERS_2)) 1163 REG_GET(NOM_PARAMETERS_2, 1164 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1165 1166 if (REG(NOM_PARAMETERS_3)) 1167 REG_GET(NOM_PARAMETERS_3, 1168 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1169 1170 REG_GET(NOM_PARAMETERS_6, 1171 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1172 1173 REG_GET(NOM_PARAMETERS_7, 1174 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1175 1176 /* TTU - per hubp */ 1177 REG_GET_2(DCN_TTU_QOS_WM, 1178 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1179 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1180 1181 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1182 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1183 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1184 1185 /* TTU - per luma/chroma */ 1186 /* Assumed surf0 is luma and 1 is chroma */ 1187 1188 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1189 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1190 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1191 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1192 1193 REG_GET(DCN_SURF0_TTU_CNTL1, 1194 REFCYC_PER_REQ_DELIVERY_PRE, 1195 &ttu_attr->refcyc_per_req_delivery_pre_l); 1196 1197 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1198 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1199 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1200 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1201 1202 REG_GET(DCN_SURF1_TTU_CNTL1, 1203 REFCYC_PER_REQ_DELIVERY_PRE, 1204 &ttu_attr->refcyc_per_req_delivery_pre_c); 1205 1206 /* Rest of hubp */ 1207 REG_GET(DCSURF_SURFACE_CONFIG, 1208 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1209 1210 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1211 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1212 1213 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1214 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1215 1216 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1217 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1218 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1219 1220 REG_GET_2(DCSURF_SURFACE_CONFIG, 1221 ROTATION_ANGLE, &s->rotation_angle, 1222 H_MIRROR_EN, &s->h_mirror_en); 1223 1224 REG_GET(DCSURF_TILING_CONFIG, 1225 SW_MODE, &s->sw_mode); 1226 1227 REG_GET(DCSURF_SURFACE_CONTROL, 1228 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1229 1230 REG_GET_3(DCHUBP_CNTL, 1231 HUBP_BLANK_EN, &s->blank_en, 1232 HUBP_TTU_DISABLE, &s->ttu_disable, 1233 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1234 1235 REG_GET(HUBP_CLK_CNTL, 1236 HUBP_CLOCK_ENABLE, &s->clock_en); 1237 1238 REG_GET(DCN_GLOBAL_TTU_CNTL, 1239 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1240 1241 REG_GET_2(DCN_TTU_QOS_WM, 1242 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1243 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1244 1245 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1246 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1247 1248 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1249 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1250 1251 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1252 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1253 1254 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1255 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1256 } 1257 1258 void hubp2_read_state(struct hubp *hubp) 1259 { 1260 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1261 struct dcn_hubp_state *s = &hubp2->state; 1262 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1263 1264 hubp2_read_state_common(hubp); 1265 1266 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1267 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1268 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1269 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1270 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1271 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1272 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1273 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1274 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1275 1276 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1277 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1278 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1279 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1280 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1281 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1282 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1283 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1284 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1285 1286 } 1287 1288 void hubp2_validate_dml_output(struct hubp *hubp, 1289 struct dc_context *ctx, 1290 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 1291 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 1292 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 1293 { 1294 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1295 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 1296 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 1297 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 1298 DC_LOGGER_INIT(ctx->logger); 1299 DC_LOG_DEBUG("DML Validation | Running Validation"); 1300 1301 /* Requestor Regs */ 1302 REG_GET(HUBPRET_CONTROL, 1303 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 1304 REG_GET_4(DCN_EXPANSION_MODE, 1305 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 1306 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 1307 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 1308 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 1309 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1310 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 1311 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 1312 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 1313 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 1314 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 1315 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 1316 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 1317 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 1318 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1319 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 1320 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 1321 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 1322 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 1323 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 1324 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size, 1325 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 1326 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 1327 1328 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 1329 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1330 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 1331 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 1332 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1333 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 1334 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 1335 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1336 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 1337 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 1338 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1339 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 1340 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 1341 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1342 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 1343 1344 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 1345 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 1346 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 1347 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 1348 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 1349 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 1350 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 1351 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1352 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 1353 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 1354 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1355 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 1356 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 1357 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1358 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 1359 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 1360 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1361 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 1362 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 1363 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 1364 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 1365 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 1366 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 1367 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 1368 1369 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 1370 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1371 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 1372 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 1373 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1374 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 1375 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 1376 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1377 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 1378 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 1379 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1380 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 1381 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 1382 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1383 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 1384 if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size) 1385 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1386 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size); 1387 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 1388 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 1389 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 1390 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 1391 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 1392 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 1393 1394 /* DLG - Per hubp */ 1395 REG_GET_2(BLANK_OFFSET_0, 1396 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 1397 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 1398 REG_GET(BLANK_OFFSET_1, 1399 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 1400 REG_GET(DST_DIMENSIONS, 1401 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 1402 REG_GET_2(DST_AFTER_SCALER, 1403 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 1404 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 1405 REG_GET(REF_FREQ_TO_PIX_FREQ, 1406 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 1407 1408 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 1409 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 1410 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 1411 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 1412 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 1413 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 1414 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 1415 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 1416 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 1417 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 1418 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 1419 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 1420 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 1421 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 1422 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 1423 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 1424 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 1425 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 1426 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 1427 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 1428 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 1429 1430 /* DLG - Per luma/chroma */ 1431 REG_GET(VBLANK_PARAMETERS_1, 1432 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 1433 if (REG(NOM_PARAMETERS_0)) 1434 REG_GET(NOM_PARAMETERS_0, 1435 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 1436 if (REG(NOM_PARAMETERS_1)) 1437 REG_GET(NOM_PARAMETERS_1, 1438 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 1439 REG_GET(NOM_PARAMETERS_4, 1440 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 1441 REG_GET(NOM_PARAMETERS_5, 1442 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 1443 REG_GET_2(PER_LINE_DELIVERY, 1444 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 1445 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 1446 REG_GET_2(PER_LINE_DELIVERY_PRE, 1447 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 1448 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 1449 REG_GET(VBLANK_PARAMETERS_2, 1450 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 1451 if (REG(NOM_PARAMETERS_2)) 1452 REG_GET(NOM_PARAMETERS_2, 1453 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 1454 if (REG(NOM_PARAMETERS_3)) 1455 REG_GET(NOM_PARAMETERS_3, 1456 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 1457 REG_GET(NOM_PARAMETERS_6, 1458 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 1459 REG_GET(NOM_PARAMETERS_7, 1460 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 1461 REG_GET(VBLANK_PARAMETERS_3, 1462 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 1463 REG_GET(VBLANK_PARAMETERS_4, 1464 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 1465 1466 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 1467 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 1468 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 1469 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 1470 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 1471 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 1472 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 1473 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 1474 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 1475 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 1476 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 1477 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 1478 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 1479 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 1480 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 1481 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 1482 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 1483 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 1484 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 1485 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 1486 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 1487 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 1488 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 1489 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 1490 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 1491 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 1492 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 1493 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 1494 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 1495 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 1496 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 1497 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 1498 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 1499 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 1500 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 1501 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 1502 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 1503 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 1504 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 1505 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 1506 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 1507 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 1508 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 1509 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 1510 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 1511 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 1512 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 1513 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 1514 1515 /* TTU - per hubp */ 1516 REG_GET_2(DCN_TTU_QOS_WM, 1517 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 1518 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 1519 1520 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 1521 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 1522 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 1523 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 1524 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 1525 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 1526 1527 /* TTU - per luma/chroma */ 1528 /* Assumed surf0 is luma and 1 is chroma */ 1529 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1530 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 1531 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 1532 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 1533 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1534 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 1535 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 1536 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 1537 REG_GET_3(DCN_CUR0_TTU_CNTL0, 1538 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 1539 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 1540 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 1541 REG_GET(FLIP_PARAMETERS_1, 1542 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 1543 REG_GET(DCN_CUR0_TTU_CNTL1, 1544 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 1545 REG_GET(DCN_CUR1_TTU_CNTL1, 1546 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 1547 REG_GET(DCN_SURF0_TTU_CNTL1, 1548 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 1549 REG_GET(DCN_SURF1_TTU_CNTL1, 1550 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 1551 1552 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 1553 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1554 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 1555 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 1556 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1557 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 1558 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 1559 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1560 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 1561 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 1562 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1563 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 1564 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 1565 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1566 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 1567 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 1568 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1569 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 1570 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 1571 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1572 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 1573 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 1574 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1575 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 1576 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 1577 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1578 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 1579 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 1580 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 1581 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 1582 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 1583 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1584 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 1585 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 1586 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1587 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 1588 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 1589 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1590 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 1591 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 1592 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1593 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 1594 } 1595 1596 static struct hubp_funcs dcn20_hubp_funcs = { 1597 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 1598 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 1599 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 1600 .hubp_program_surface_config = hubp2_program_surface_config, 1601 .hubp_is_flip_pending = hubp2_is_flip_pending, 1602 .hubp_setup = hubp2_setup, 1603 .hubp_setup_interdependent = hubp2_setup_interdependent, 1604 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, 1605 .set_blank = hubp2_set_blank, 1606 .dcc_control = hubp2_dcc_control, 1607 .mem_program_viewport = min_set_viewport, 1608 .set_cursor_attributes = hubp2_cursor_set_attributes, 1609 .set_cursor_position = hubp2_cursor_set_position, 1610 .hubp_clk_cntl = hubp2_clk_cntl, 1611 .hubp_vtg_sel = hubp2_vtg_sel, 1612 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 1613 .dmdata_load = hubp2_dmdata_load, 1614 .dmdata_status_done = hubp2_dmdata_status_done, 1615 .hubp_read_state = hubp2_read_state, 1616 .hubp_clear_underflow = hubp2_clear_underflow, 1617 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1618 .hubp_init = hubp1_init, 1619 .validate_dml_output = hubp2_validate_dml_output, 1620 .hubp_in_blank = hubp1_in_blank, 1621 .hubp_soft_reset = hubp1_soft_reset, 1622 .hubp_set_flip_int = hubp1_set_flip_int, 1623 }; 1624 1625 1626 bool hubp2_construct( 1627 struct dcn20_hubp *hubp2, 1628 struct dc_context *ctx, 1629 uint32_t inst, 1630 const struct dcn_hubp2_registers *hubp_regs, 1631 const struct dcn_hubp2_shift *hubp_shift, 1632 const struct dcn_hubp2_mask *hubp_mask) 1633 { 1634 hubp2->base.funcs = &dcn20_hubp_funcs; 1635 hubp2->base.ctx = ctx; 1636 hubp2->hubp_regs = hubp_regs; 1637 hubp2->hubp_shift = hubp_shift; 1638 hubp2->hubp_mask = hubp_mask; 1639 hubp2->base.inst = inst; 1640 hubp2->base.opp_id = OPP_ID_INVALID; 1641 hubp2->base.mpcc_id = 0xf; 1642 1643 return true; 1644 } 1645