1 /*
2  * Copyright 2012-2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dcn20_hubp.h"
27 
28 #include "dm_services.h"
29 #include "dce_calcs.h"
30 #include "reg_helper.h"
31 #include "basics/conversion.h"
32 
33 #define DC_LOGGER_INIT(logger)
34 
35 #define REG(reg)\
36 	hubp2->hubp_regs->reg
37 
38 #define CTX \
39 	hubp2->base.ctx
40 
41 #undef FN
42 #define FN(reg_name, field_name) \
43 	hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
44 
45 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
46 		struct vm_system_aperture_param *apt)
47 {
48 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
49 
50 	PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
51 	PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
52 	PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
53 
54 	// The format of default addr is 48:12 of the 48 bit addr
55 	mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
56 
57 	// The format of high/low are 48:18 of the 48 bit addr
58 	mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
59 	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
60 
61 	REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
62 		DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
63 		DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
64 
65 	REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
66 			DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
67 
68 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
69 			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
70 
71 	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
72 			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
73 
74 	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
75 			ENABLE_L1_TLB, 1,
76 			SYSTEM_ACCESS_MODE, 0x3);
77 }
78 
79 void hubp2_program_deadline(
80 		struct hubp *hubp,
81 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
82 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
83 {
84 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
85 
86 	/* DLG - Per hubp */
87 	REG_SET_2(BLANK_OFFSET_0, 0,
88 		REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
89 		DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
90 
91 	REG_SET(BLANK_OFFSET_1, 0,
92 		MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
93 
94 	REG_SET(DST_DIMENSIONS, 0,
95 		REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
96 
97 	REG_SET_2(DST_AFTER_SCALER, 0,
98 		REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
99 		DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
100 
101 	REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
102 		REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
103 
104 	/* DLG - Per luma/chroma */
105 	REG_SET(VBLANK_PARAMETERS_1, 0,
106 		REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
107 
108 	if (REG(NOM_PARAMETERS_0))
109 		REG_SET(NOM_PARAMETERS_0, 0,
110 			DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
111 
112 	if (REG(NOM_PARAMETERS_1))
113 		REG_SET(NOM_PARAMETERS_1, 0,
114 			REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
115 
116 	REG_SET(NOM_PARAMETERS_4, 0,
117 		DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
118 
119 	REG_SET(NOM_PARAMETERS_5, 0,
120 		REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
121 
122 	REG_SET_2(PER_LINE_DELIVERY, 0,
123 		REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
124 		REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
125 
126 	REG_SET(VBLANK_PARAMETERS_2, 0,
127 		REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
128 
129 	if (REG(NOM_PARAMETERS_2))
130 		REG_SET(NOM_PARAMETERS_2, 0,
131 			DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
132 
133 	if (REG(NOM_PARAMETERS_3))
134 		REG_SET(NOM_PARAMETERS_3, 0,
135 			REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
136 
137 	REG_SET(NOM_PARAMETERS_6, 0,
138 		DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
139 
140 	REG_SET(NOM_PARAMETERS_7, 0,
141 		REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
142 
143 	/* TTU - per hubp */
144 	REG_SET_2(DCN_TTU_QOS_WM, 0,
145 		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
146 		QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
147 
148 	/* TTU - per luma/chroma */
149 	/* Assumed surf0 is luma and 1 is chroma */
150 
151 	REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
152 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
153 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
154 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
155 
156 	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
157 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
158 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
159 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
160 
161 	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
162 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
163 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
164 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
165 
166 	REG_SET(FLIP_PARAMETERS_1, 0,
167 		REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
168 }
169 
170 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
171 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
172 {
173 	uint32_t value = 0;
174 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
175 	/* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */
176 	REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
177 	/*
178 	if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)
179 	<= OTG_V_BLANK_END
180 		Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1
181 	else
182 		Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0
183 	*/
184 	if (pipe_dest->htotal != 0) {
185 		if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
186 			+ pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
187 			value = 1;
188 		} else
189 			value = 0;
190 	}
191 
192 	REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
193 }
194 
195 static void hubp2_program_requestor(struct hubp *hubp,
196 				    struct _vcs_dpi_display_rq_regs_st *rq_regs)
197 {
198 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
199 
200 	REG_UPDATE(HUBPRET_CONTROL,
201 			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
202 	REG_SET_4(DCN_EXPANSION_MODE, 0,
203 			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
204 			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
205 			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
206 			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
207 	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
208 		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
209 		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
210 		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
211 		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
212 		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
213 		MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
214 		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
215 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
216 	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
217 		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
218 		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
219 		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
220 		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
221 		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
222 		MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
223 		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
224 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
225 }
226 
227 static void hubp2_setup(
228 		struct hubp *hubp,
229 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
230 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
231 		struct _vcs_dpi_display_rq_regs_st *rq_regs,
232 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
233 {
234 	/* otg is locked when this func is called. Register are double buffered.
235 	 * disable the requestors is not needed
236 	 */
237 
238 	hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
239 	hubp2_program_requestor(hubp, rq_regs);
240 	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
241 
242 }
243 
244 void hubp2_setup_interdependent(
245 		struct hubp *hubp,
246 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
247 		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
248 {
249 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
250 
251 	REG_SET_2(PREFETCH_SETTINGS, 0,
252 			DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
253 			VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
254 
255 	REG_SET(PREFETCH_SETTINGS_C, 0,
256 			VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
257 
258 	REG_SET_2(VBLANK_PARAMETERS_0, 0,
259 		DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
260 		DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
261 
262 	REG_SET_2(FLIP_PARAMETERS_0, 0,
263 		DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip,
264 		DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);
265 
266 	REG_SET(VBLANK_PARAMETERS_3, 0,
267 		REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
268 
269 	REG_SET(VBLANK_PARAMETERS_4, 0,
270 		REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
271 
272 	REG_SET(FLIP_PARAMETERS_2, 0,
273 		REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l);
274 
275 	REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
276 		REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
277 		REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
278 
279 	REG_SET(DCN_SURF0_TTU_CNTL1, 0,
280 		REFCYC_PER_REQ_DELIVERY_PRE,
281 		ttu_attr->refcyc_per_req_delivery_pre_l);
282 	REG_SET(DCN_SURF1_TTU_CNTL1, 0,
283 		REFCYC_PER_REQ_DELIVERY_PRE,
284 		ttu_attr->refcyc_per_req_delivery_pre_c);
285 	REG_SET(DCN_CUR0_TTU_CNTL1, 0,
286 		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
287 	REG_SET(DCN_CUR1_TTU_CNTL1, 0,
288 		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1);
289 
290 	REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
291 		MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
292 		QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
293 }
294 
295 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used:
296  *	NUM_BANKS
297  *	NUM_SE
298  *	NUM_RB_PER_SE
299  *	RB_ALIGNED
300  * Other things can be defaulted, since they never change:
301  *	PIPE_ALIGNED = 0
302  *	META_LINEAR = 0
303  * In GFX10, only these apply:
304  *	PIPE_INTERLEAVE
305  *	NUM_PIPES
306  *	MAX_COMPRESSED_FRAGS
307  *	SW_MODE
308  */
309 static void hubp2_program_tiling(
310 	struct dcn20_hubp *hubp2,
311 	const union dc_tiling_info *info,
312 	const enum surface_pixel_format pixel_format)
313 {
314 	REG_UPDATE_3(DCSURF_ADDR_CONFIG,
315 			NUM_PIPES, log_2(info->gfx9.num_pipes),
316 			PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
317 			MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
318 
319 	REG_UPDATE_4(DCSURF_TILING_CONFIG,
320 			SW_MODE, info->gfx9.swizzle,
321 			META_LINEAR, 0,
322 			RB_ALIGNED, 0,
323 			PIPE_ALIGNED, 0);
324 }
325 
326 void hubp2_program_size(
327 	struct hubp *hubp,
328 	enum surface_pixel_format format,
329 	const struct plane_size *plane_size,
330 	struct dc_plane_dcc_param *dcc)
331 {
332 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
333 	uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
334 	bool use_pitch_c = false;
335 
336 	/* Program data and meta surface pitch (calculation from addrlib)
337 	 * 444 or 420 luma
338 	 */
339 	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
340 		&& format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
341 	use_pitch_c = use_pitch_c
342 		|| (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
343 	if (use_pitch_c) {
344 		ASSERT(plane_size->chroma_pitch != 0);
345 		/* Chroma pitch zero can cause system hang! */
346 
347 		pitch = plane_size->surface_pitch - 1;
348 		meta_pitch = dcc->meta_pitch - 1;
349 		pitch_c = plane_size->chroma_pitch - 1;
350 		meta_pitch_c = dcc->meta_pitch_c - 1;
351 	} else {
352 		pitch = plane_size->surface_pitch - 1;
353 		meta_pitch = dcc->meta_pitch - 1;
354 		pitch_c = 0;
355 		meta_pitch_c = 0;
356 	}
357 
358 	if (!dcc->enable) {
359 		meta_pitch = 0;
360 		meta_pitch_c = 0;
361 	}
362 
363 	REG_UPDATE_2(DCSURF_SURFACE_PITCH,
364 			PITCH, pitch, META_PITCH, meta_pitch);
365 
366 	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
367 	use_pitch_c = use_pitch_c
368 		|| (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
369 	if (use_pitch_c)
370 		REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
371 			PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
372 }
373 
374 void hubp2_program_rotation(
375 	struct hubp *hubp,
376 	enum dc_rotation_angle rotation,
377 	bool horizontal_mirror)
378 {
379 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
380 	uint32_t mirror;
381 
382 
383 	if (horizontal_mirror)
384 		mirror = 1;
385 	else
386 		mirror = 0;
387 
388 	/* Program rotation angle and horz mirror - no mirror */
389 	if (rotation == ROTATION_ANGLE_0)
390 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
391 				ROTATION_ANGLE, 0,
392 				H_MIRROR_EN, mirror);
393 	else if (rotation == ROTATION_ANGLE_90)
394 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
395 				ROTATION_ANGLE, 1,
396 				H_MIRROR_EN, mirror);
397 	else if (rotation == ROTATION_ANGLE_180)
398 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
399 				ROTATION_ANGLE, 2,
400 				H_MIRROR_EN, mirror);
401 	else if (rotation == ROTATION_ANGLE_270)
402 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
403 				ROTATION_ANGLE, 3,
404 				H_MIRROR_EN, mirror);
405 }
406 
407 void hubp2_dcc_control(struct hubp *hubp, bool enable,
408 		enum hubp_ind_block_size independent_64b_blks)
409 {
410 	uint32_t dcc_en = enable ? 1 : 0;
411 	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
412 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
413 
414 	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
415 			PRIMARY_SURFACE_DCC_EN, dcc_en,
416 			PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
417 			SECONDARY_SURFACE_DCC_EN, dcc_en,
418 			SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
419 }
420 
421 void hubp2_program_pixel_format(
422 	struct hubp *hubp,
423 	enum surface_pixel_format format)
424 {
425 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
426 	uint32_t red_bar = 3;
427 	uint32_t blue_bar = 2;
428 
429 	/* swap for ABGR format */
430 	if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
431 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
432 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
433 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616
434 			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
435 		red_bar = 2;
436 		blue_bar = 3;
437 	}
438 
439 	REG_UPDATE_2(HUBPRET_CONTROL,
440 			CROSSBAR_SRC_CB_B, blue_bar,
441 			CROSSBAR_SRC_CR_R, red_bar);
442 
443 	/* Mapping is same as ipp programming (cnvc) */
444 
445 	switch (format)	{
446 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
447 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
448 				SURFACE_PIXEL_FORMAT, 1);
449 		break;
450 	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
451 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
452 				SURFACE_PIXEL_FORMAT, 3);
453 		break;
454 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
455 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
456 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
457 				SURFACE_PIXEL_FORMAT, 8);
458 		break;
459 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
460 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
461 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
462 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
463 				SURFACE_PIXEL_FORMAT, 10);
464 		break;
465 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
466 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/
467 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
468 				SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */
469 		break;
470 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
471 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
472 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
473 				SURFACE_PIXEL_FORMAT, 24);
474 		break;
475 
476 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
477 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
478 				SURFACE_PIXEL_FORMAT, 65);
479 		break;
480 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
481 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
482 				SURFACE_PIXEL_FORMAT, 64);
483 		break;
484 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
485 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
486 				SURFACE_PIXEL_FORMAT, 67);
487 		break;
488 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
489 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
490 				SURFACE_PIXEL_FORMAT, 66);
491 		break;
492 	case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
493 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
494 				SURFACE_PIXEL_FORMAT, 12);
495 		break;
496 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
497 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
498 				SURFACE_PIXEL_FORMAT, 112);
499 		break;
500 	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
501 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
502 				SURFACE_PIXEL_FORMAT, 113);
503 		break;
504 	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
505 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
506 				SURFACE_PIXEL_FORMAT, 114);
507 		break;
508 	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
509 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
510 				SURFACE_PIXEL_FORMAT, 118);
511 		break;
512 	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
513 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
514 				SURFACE_PIXEL_FORMAT, 119);
515 		break;
516 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
517 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
518 				SURFACE_PIXEL_FORMAT, 116,
519 				ALPHA_PLANE_EN, 0);
520 		break;
521 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
522 		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
523 				SURFACE_PIXEL_FORMAT, 116,
524 				ALPHA_PLANE_EN, 1);
525 		break;
526 	default:
527 		BREAK_TO_DEBUGGER();
528 		break;
529 	}
530 
531 	/* don't see the need of program the xbar in DCN 1.0 */
532 }
533 
534 void hubp2_program_surface_config(
535 	struct hubp *hubp,
536 	enum surface_pixel_format format,
537 	union dc_tiling_info *tiling_info,
538 	struct plane_size *plane_size,
539 	enum dc_rotation_angle rotation,
540 	struct dc_plane_dcc_param *dcc,
541 	bool horizontal_mirror,
542 	unsigned int compat_level)
543 {
544 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
545 
546 	hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
547 	hubp2_program_tiling(hubp2, tiling_info, format);
548 	hubp2_program_size(hubp, format, plane_size, dcc);
549 	hubp2_program_rotation(hubp, rotation, horizontal_mirror);
550 	hubp2_program_pixel_format(hubp, format);
551 }
552 
553 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
554 	unsigned int cursor_width,
555 	enum dc_cursor_color_format cursor_mode)
556 {
557 	enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
558 
559 	if (cursor_mode == CURSOR_MODE_MONO)
560 		line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
561 	else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND ||
562 		 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
563 		 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
564 		if (cursor_width >= 1   && cursor_width <= 32)
565 			line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
566 		else if (cursor_width >= 33  && cursor_width <= 64)
567 			line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
568 		else if (cursor_width >= 65  && cursor_width <= 128)
569 			line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
570 		else if (cursor_width >= 129 && cursor_width <= 256)
571 			line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
572 	} else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED ||
573 		   cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) {
574 		if (cursor_width >= 1   && cursor_width <= 16)
575 			line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
576 		else if (cursor_width >= 17  && cursor_width <= 32)
577 			line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
578 		else if (cursor_width >= 33  && cursor_width <= 64)
579 			line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
580 		else if (cursor_width >= 65 && cursor_width <= 128)
581 			line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
582 		else if (cursor_width >= 129 && cursor_width <= 256)
583 			line_per_chunk = CURSOR_LINE_PER_CHUNK_1;
584 	}
585 
586 	return line_per_chunk;
587 }
588 
589 void hubp2_cursor_set_attributes(
590 		struct hubp *hubp,
591 		const struct dc_cursor_attributes *attr)
592 {
593 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
594 	enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
595 	enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
596 			attr->width, attr->color_format);
597 
598 	hubp->curs_attr = *attr;
599 
600 	REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
601 			CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
602 	REG_UPDATE(CURSOR_SURFACE_ADDRESS,
603 			CURSOR_SURFACE_ADDRESS, attr->address.low_part);
604 
605 	REG_UPDATE_2(CURSOR_SIZE,
606 			CURSOR_WIDTH, attr->width,
607 			CURSOR_HEIGHT, attr->height);
608 
609 	REG_UPDATE_4(CURSOR_CONTROL,
610 			CURSOR_MODE, attr->color_format,
611 			CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
612 			CURSOR_PITCH, hw_pitch,
613 			CURSOR_LINES_PER_CHUNK, lpc);
614 
615 	REG_SET_2(CURSOR_SETTINGS, 0,
616 			/* no shift of the cursor HDL schedule */
617 			CURSOR0_DST_Y_OFFSET, 0,
618 			 /* used to shift the cursor chunk request deadline */
619 			CURSOR0_CHUNK_HDL_ADJUST, 3);
620 
621 	hubp->att.SURFACE_ADDR_HIGH  = attr->address.high_part;
622 	hubp->att.SURFACE_ADDR       = attr->address.low_part;
623 	hubp->att.size.bits.width    = attr->width;
624 	hubp->att.size.bits.height   = attr->height;
625 	hubp->att.cur_ctl.bits.mode  = attr->color_format;
626 
627 	hubp->cur_rect.w = attr->width;
628 	hubp->cur_rect.h = attr->height;
629 
630 	hubp->att.cur_ctl.bits.pitch = hw_pitch;
631 	hubp->att.cur_ctl.bits.line_per_chunk = lpc;
632 	hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;
633 	hubp->att.settings.bits.dst_y_offset  = 0;
634 	hubp->att.settings.bits.chunk_hdl_adjust = 3;
635 }
636 
637 void hubp2_dmdata_set_attributes(
638 		struct hubp *hubp,
639 		const struct dc_dmdata_attributes *attr)
640 {
641 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
642 
643 	if (attr->dmdata_mode == DMDATA_HW_MODE) {
644 		/* set to HW mode */
645 		REG_UPDATE(DMDATA_CNTL,
646 				DMDATA_MODE, 1);
647 
648 		/* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
649 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
650 
651 		/* toggle DMDATA_UPDATED and set repeat and size */
652 		REG_UPDATE(DMDATA_CNTL,
653 				DMDATA_UPDATED, 0);
654 		REG_UPDATE_3(DMDATA_CNTL,
655 				DMDATA_UPDATED, 1,
656 				DMDATA_REPEAT, attr->dmdata_repeat,
657 				DMDATA_SIZE, attr->dmdata_size);
658 
659 		/* set DMDATA address */
660 		REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
661 		REG_UPDATE(DMDATA_ADDRESS_HIGH,
662 				DMDATA_ADDRESS_HIGH, attr->address.high_part);
663 
664 		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
665 
666 	} else {
667 		/* set to SW mode before loading data */
668 		REG_SET(DMDATA_CNTL, 0,
669 				DMDATA_MODE, 0);
670 		/* toggle DMDATA_SW_UPDATED to start loading sequence */
671 		REG_UPDATE(DMDATA_SW_CNTL,
672 				DMDATA_SW_UPDATED, 0);
673 		REG_UPDATE_3(DMDATA_SW_CNTL,
674 				DMDATA_SW_UPDATED, 1,
675 				DMDATA_SW_REPEAT, attr->dmdata_repeat,
676 				DMDATA_SW_SIZE, attr->dmdata_size);
677 		/* load data into hubp dmdata buffer */
678 		hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);
679 	}
680 
681 	/* Note that DL_DELTA must be programmed if we want to use TTU mode */
682 	REG_SET_3(DMDATA_QOS_CNTL, 0,
683 			DMDATA_QOS_MODE, attr->dmdata_qos_mode,
684 			DMDATA_QOS_LEVEL, attr->dmdata_qos_level,
685 			DMDATA_DL_DELTA, attr->dmdata_dl_delta);
686 }
687 
688 void hubp2_dmdata_load(
689 		struct hubp *hubp,
690 		uint32_t dmdata_sw_size,
691 		const uint32_t *dmdata_sw_data)
692 {
693 	int i;
694 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
695 
696 	/* load dmdata into HUBP buffer in SW mode */
697 	for (i = 0; i < dmdata_sw_size / 4; i++)
698 		REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);
699 }
700 
701 bool hubp2_dmdata_status_done(struct hubp *hubp)
702 {
703 	uint32_t status;
704 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
705 
706 	REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);
707 	return (status == 1);
708 }
709 
710 bool hubp2_program_surface_flip_and_addr(
711 	struct hubp *hubp,
712 	const struct dc_plane_address *address,
713 	bool flip_immediate)
714 {
715 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
716 
717 	//program flip type
718 	REG_UPDATE(DCSURF_FLIP_CONTROL,
719 			SURFACE_FLIP_TYPE, flip_immediate);
720 
721 	// Program VMID reg
722 	REG_UPDATE(VMID_SETTINGS_0,
723 			VMID, address->vmid);
724 
725 
726 	/* HW automatically latch rest of address register on write to
727 	 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
728 	 *
729 	 * program high first and then the low addr, order matters!
730 	 */
731 	switch (address->type) {
732 	case PLN_ADDR_TYPE_GRAPHICS:
733 		/* DCN1.0 does not support const color
734 		 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
735 		 * base on address->grph.dcc_const_color
736 		 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
737 		 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
738 		 */
739 
740 		if (address->grph.addr.quad_part == 0)
741 			break;
742 
743 		REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
744 				PRIMARY_SURFACE_TMZ, address->tmz_surface,
745 				PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
746 
747 		if (address->grph.meta_addr.quad_part != 0) {
748 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
749 					PRIMARY_META_SURFACE_ADDRESS_HIGH,
750 					address->grph.meta_addr.high_part);
751 
752 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
753 					PRIMARY_META_SURFACE_ADDRESS,
754 					address->grph.meta_addr.low_part);
755 		}
756 
757 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
758 				PRIMARY_SURFACE_ADDRESS_HIGH,
759 				address->grph.addr.high_part);
760 
761 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
762 				PRIMARY_SURFACE_ADDRESS,
763 				address->grph.addr.low_part);
764 		break;
765 	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
766 		if (address->video_progressive.luma_addr.quad_part == 0
767 				|| address->video_progressive.chroma_addr.quad_part == 0)
768 			break;
769 
770 		REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
771 				PRIMARY_SURFACE_TMZ, address->tmz_surface,
772 				PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
773 				PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
774 				PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
775 
776 		if (address->video_progressive.luma_meta_addr.quad_part != 0) {
777 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
778 					PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
779 					address->video_progressive.chroma_meta_addr.high_part);
780 
781 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
782 					PRIMARY_META_SURFACE_ADDRESS_C,
783 					address->video_progressive.chroma_meta_addr.low_part);
784 
785 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
786 					PRIMARY_META_SURFACE_ADDRESS_HIGH,
787 					address->video_progressive.luma_meta_addr.high_part);
788 
789 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
790 					PRIMARY_META_SURFACE_ADDRESS,
791 					address->video_progressive.luma_meta_addr.low_part);
792 		}
793 
794 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
795 				PRIMARY_SURFACE_ADDRESS_HIGH_C,
796 				address->video_progressive.chroma_addr.high_part);
797 
798 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
799 				PRIMARY_SURFACE_ADDRESS_C,
800 				address->video_progressive.chroma_addr.low_part);
801 
802 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
803 				PRIMARY_SURFACE_ADDRESS_HIGH,
804 				address->video_progressive.luma_addr.high_part);
805 
806 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
807 				PRIMARY_SURFACE_ADDRESS,
808 				address->video_progressive.luma_addr.low_part);
809 		break;
810 	case PLN_ADDR_TYPE_GRPH_STEREO:
811 		if (address->grph_stereo.left_addr.quad_part == 0)
812 			break;
813 		if (address->grph_stereo.right_addr.quad_part == 0)
814 			break;
815 
816 		REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
817 				PRIMARY_SURFACE_TMZ, address->tmz_surface,
818 				PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
819 				PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
820 				PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
821 				SECONDARY_SURFACE_TMZ, address->tmz_surface,
822 				SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
823 				SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
824 				SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
825 
826 		if (address->grph_stereo.right_meta_addr.quad_part != 0) {
827 
828 			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
829 					SECONDARY_META_SURFACE_ADDRESS_HIGH,
830 					address->grph_stereo.right_meta_addr.high_part);
831 
832 			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
833 					SECONDARY_META_SURFACE_ADDRESS,
834 					address->grph_stereo.right_meta_addr.low_part);
835 		}
836 		if (address->grph_stereo.left_meta_addr.quad_part != 0) {
837 
838 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
839 					PRIMARY_META_SURFACE_ADDRESS_HIGH,
840 					address->grph_stereo.left_meta_addr.high_part);
841 
842 			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
843 					PRIMARY_META_SURFACE_ADDRESS,
844 					address->grph_stereo.left_meta_addr.low_part);
845 		}
846 
847 		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
848 				SECONDARY_SURFACE_ADDRESS_HIGH,
849 				address->grph_stereo.right_addr.high_part);
850 
851 		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
852 				SECONDARY_SURFACE_ADDRESS,
853 				address->grph_stereo.right_addr.low_part);
854 
855 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
856 				PRIMARY_SURFACE_ADDRESS_HIGH,
857 				address->grph_stereo.left_addr.high_part);
858 
859 		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
860 				PRIMARY_SURFACE_ADDRESS,
861 				address->grph_stereo.left_addr.low_part);
862 		break;
863 	default:
864 		BREAK_TO_DEBUGGER();
865 		break;
866 	}
867 
868 	hubp->request_address = *address;
869 
870 	return true;
871 }
872 
873 void hubp2_enable_triplebuffer(
874 	struct hubp *hubp,
875 	bool enable)
876 {
877 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
878 	uint32_t triple_buffer_en = 0;
879 	bool tri_buffer_en;
880 
881 	REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
882 	tri_buffer_en = (triple_buffer_en == 1);
883 	if (tri_buffer_en != enable) {
884 		REG_UPDATE(DCSURF_FLIP_CONTROL2,
885 			SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE);
886 	}
887 }
888 
889 bool hubp2_is_triplebuffer_enabled(
890 	struct hubp *hubp)
891 {
892 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
893 	uint32_t triple_buffer_en = 0;
894 
895 	REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
896 
897 	return (bool)triple_buffer_en;
898 }
899 
900 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)
901 {
902 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
903 
904 	REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
905 }
906 
907 bool hubp2_is_flip_pending(struct hubp *hubp)
908 {
909 	uint32_t flip_pending = 0;
910 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
911 	struct dc_plane_address earliest_inuse_address;
912 
913 	if (hubp && hubp->power_gated)
914 		return false;
915 
916 	REG_GET(DCSURF_FLIP_CONTROL,
917 			SURFACE_FLIP_PENDING, &flip_pending);
918 
919 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
920 			SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
921 
922 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
923 			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
924 
925 	if (flip_pending)
926 		return true;
927 
928 	if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
929 		return true;
930 
931 	return false;
932 }
933 
934 void hubp2_set_blank(struct hubp *hubp, bool blank)
935 {
936 	hubp2_set_blank_regs(hubp, blank);
937 
938 	if (blank) {
939 		hubp->mpcc_id = 0xf;
940 		hubp->opp_id = OPP_ID_INVALID;
941 	}
942 }
943 
944 void hubp2_set_blank_regs(struct hubp *hubp, bool blank)
945 {
946 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
947 	uint32_t blank_en = blank ? 1 : 0;
948 
949 	if (blank) {
950 		uint32_t reg_val = REG_READ(DCHUBP_CNTL);
951 
952 		if (reg_val) {
953 			/* init sequence workaround: in case HUBP is
954 			 * power gated, this wait would timeout.
955 			 *
956 			 * we just wrote reg_val to non-0, if it stay 0
957 			 * it means HUBP is gated
958 			 */
959 			REG_WAIT(DCHUBP_CNTL,
960 					HUBP_NO_OUTSTANDING_REQ, 1,
961 					1, 100000);
962 		}
963 	}
964 
965 	REG_UPDATE_2(DCHUBP_CNTL,
966 			HUBP_BLANK_EN, blank_en,
967 			HUBP_TTU_DISABLE, 0);
968 }
969 
970 void hubp2_cursor_set_position(
971 		struct hubp *hubp,
972 		const struct dc_cursor_position *pos,
973 		const struct dc_cursor_mi_param *param)
974 {
975 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
976 	int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
977 	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
978 	int x_hotspot = pos->x_hotspot;
979 	int y_hotspot = pos->y_hotspot;
980 	int cursor_height = (int)hubp->curs_attr.height;
981 	int cursor_width = (int)hubp->curs_attr.width;
982 	uint32_t dst_x_offset;
983 	uint32_t cur_en = pos->enable ? 1 : 0;
984 
985 	hubp->curs_pos = *pos;
986 
987 	/*
988 	 * Guard aganst cursor_set_position() from being called with invalid
989 	 * attributes
990 	 *
991 	 * TODO: Look at combining cursor_set_position() and
992 	 * cursor_set_attributes() into cursor_update()
993 	 */
994 	if (hubp->curs_attr.address.quad_part == 0)
995 		return;
996 
997 	// Rotated cursor width/height and hotspots tweaks for offset calculation
998 	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
999 		swap(cursor_height, cursor_width);
1000 		if (param->rotation == ROTATION_ANGLE_90) {
1001 			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
1002 			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
1003 		}
1004 	} else if (param->rotation == ROTATION_ANGLE_180) {
1005 		if (!param->mirror)
1006 			src_x_offset = pos->x - param->viewport.x;
1007 
1008 		src_y_offset = pos->y - param->viewport.y;
1009 	}
1010 
1011 	dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1012 	dst_x_offset *= param->ref_clk_khz;
1013 	dst_x_offset /= param->pixel_clk_khz;
1014 
1015 	ASSERT(param->h_scale_ratio.value);
1016 
1017 	if (param->h_scale_ratio.value)
1018 		dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1019 				dc_fixpt_from_int(dst_x_offset),
1020 				param->h_scale_ratio));
1021 
1022 	if (src_x_offset >= (int)param->viewport.width)
1023 		cur_en = 0;  /* not visible beyond right edge*/
1024 
1025 	if (src_x_offset + cursor_width <= 0)
1026 		cur_en = 0;  /* not visible beyond left edge*/
1027 
1028 	if (src_y_offset >= (int)param->viewport.height)
1029 		cur_en = 0;  /* not visible beyond bottom edge*/
1030 
1031 	if (src_y_offset + cursor_height <= 0)
1032 		cur_en = 0;  /* not visible beyond top edge*/
1033 
1034 	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1035 		hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1036 
1037 	REG_UPDATE(CURSOR_CONTROL,
1038 			CURSOR_ENABLE, cur_en);
1039 
1040 	REG_SET_2(CURSOR_POSITION, 0,
1041 			CURSOR_X_POSITION, pos->x,
1042 			CURSOR_Y_POSITION, pos->y);
1043 
1044 	REG_SET_2(CURSOR_HOT_SPOT, 0,
1045 			CURSOR_HOT_SPOT_X, x_hotspot,
1046 			CURSOR_HOT_SPOT_Y, y_hotspot);
1047 
1048 	REG_SET(CURSOR_DST_OFFSET, 0,
1049 			CURSOR_DST_X_OFFSET, dst_x_offset);
1050 	/* TODO Handle surface pixel formats other than 4:4:4 */
1051 	/* Cursor Position Register Config */
1052 	hubp->pos.cur_ctl.bits.cur_enable = cur_en;
1053 	hubp->pos.position.bits.x_pos = pos->x;
1054 	hubp->pos.position.bits.y_pos = pos->y;
1055 	hubp->pos.hot_spot.bits.x_hot = x_hotspot;
1056 	hubp->pos.hot_spot.bits.y_hot = y_hotspot;
1057 	hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset;
1058 	/* Cursor Rectangle Cache
1059 	 * Cursor bitmaps have different hotspot values
1060 	 * There's a possibility that the above logic returns a negative value,
1061 	 * so we clamp them to 0
1062 	 */
1063 	if (src_x_offset < 0)
1064 		src_x_offset = 0;
1065 	if (src_y_offset < 0)
1066 		src_y_offset = 0;
1067 	/* Save necessary cursor info x, y position. w, h is saved in attribute func. */
1068 	hubp->cur_rect.x = src_x_offset + param->viewport.x;
1069 	hubp->cur_rect.y = src_y_offset + param->viewport.y;
1070 }
1071 
1072 void hubp2_clk_cntl(struct hubp *hubp, bool enable)
1073 {
1074 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1075 	uint32_t clk_enable = enable ? 1 : 0;
1076 
1077 	REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1078 }
1079 
1080 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1081 {
1082 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1083 
1084 	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1085 }
1086 
1087 void hubp2_clear_underflow(struct hubp *hubp)
1088 {
1089 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1090 
1091 	REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
1092 }
1093 
1094 void hubp2_read_state_common(struct hubp *hubp)
1095 {
1096 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1097 	struct dcn_hubp_state *s = &hubp2->state;
1098 	struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
1099 	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
1100 	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1101 
1102 	/* Requester */
1103 	REG_GET(HUBPRET_CONTROL,
1104 			DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
1105 	REG_GET_4(DCN_EXPANSION_MODE,
1106 			DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
1107 			PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
1108 			MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
1109 			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
1110 
1111 	REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR,
1112 			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr);
1113 
1114 	REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR,
1115 			MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr);
1116 
1117 	/* DLG - Per hubp */
1118 	REG_GET_2(BLANK_OFFSET_0,
1119 		REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
1120 		DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
1121 
1122 	REG_GET(BLANK_OFFSET_1,
1123 		MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
1124 
1125 	REG_GET(DST_DIMENSIONS,
1126 		REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
1127 
1128 	REG_GET_2(DST_AFTER_SCALER,
1129 		REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
1130 		DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
1131 
1132 	if (REG(PREFETCH_SETTINS))
1133 		REG_GET_2(PREFETCH_SETTINS,
1134 			DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1135 			VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1136 	else
1137 		REG_GET_2(PREFETCH_SETTINGS,
1138 			DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1139 			VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1140 
1141 	REG_GET_2(VBLANK_PARAMETERS_0,
1142 		DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
1143 		DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
1144 
1145 	REG_GET(REF_FREQ_TO_PIX_FREQ,
1146 		REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
1147 
1148 	/* DLG - Per luma/chroma */
1149 	REG_GET(VBLANK_PARAMETERS_1,
1150 		REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
1151 
1152 	REG_GET(VBLANK_PARAMETERS_3,
1153 		REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
1154 
1155 	if (REG(NOM_PARAMETERS_0))
1156 		REG_GET(NOM_PARAMETERS_0,
1157 			DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
1158 
1159 	if (REG(NOM_PARAMETERS_1))
1160 		REG_GET(NOM_PARAMETERS_1,
1161 			REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
1162 
1163 	REG_GET(NOM_PARAMETERS_4,
1164 		DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
1165 
1166 	REG_GET(NOM_PARAMETERS_5,
1167 		REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
1168 
1169 	REG_GET_2(PER_LINE_DELIVERY_PRE,
1170 		REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
1171 		REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
1172 
1173 	REG_GET_2(PER_LINE_DELIVERY,
1174 		REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
1175 		REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
1176 
1177 	if (REG(PREFETCH_SETTINS_C))
1178 		REG_GET(PREFETCH_SETTINS_C,
1179 			VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1180 	else
1181 		REG_GET(PREFETCH_SETTINGS_C,
1182 			VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1183 
1184 	REG_GET(VBLANK_PARAMETERS_2,
1185 		REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
1186 
1187 	REG_GET(VBLANK_PARAMETERS_4,
1188 		REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
1189 
1190 	if (REG(NOM_PARAMETERS_2))
1191 		REG_GET(NOM_PARAMETERS_2,
1192 			DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
1193 
1194 	if (REG(NOM_PARAMETERS_3))
1195 		REG_GET(NOM_PARAMETERS_3,
1196 			REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
1197 
1198 	REG_GET(NOM_PARAMETERS_6,
1199 		DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
1200 
1201 	REG_GET(NOM_PARAMETERS_7,
1202 		REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
1203 
1204 	/* TTU - per hubp */
1205 	REG_GET_2(DCN_TTU_QOS_WM,
1206 		QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
1207 		QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1208 
1209 	REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1210 		MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1211 		QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
1212 
1213 	/* TTU - per luma/chroma */
1214 	/* Assumed surf0 is luma and 1 is chroma */
1215 
1216 	REG_GET_3(DCN_SURF0_TTU_CNTL0,
1217 		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1218 		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1219 		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1220 
1221 	REG_GET(DCN_SURF0_TTU_CNTL1,
1222 		REFCYC_PER_REQ_DELIVERY_PRE,
1223 		&ttu_attr->refcyc_per_req_delivery_pre_l);
1224 
1225 	REG_GET_3(DCN_SURF1_TTU_CNTL0,
1226 		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1227 		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1228 		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1229 
1230 	REG_GET(DCN_SURF1_TTU_CNTL1,
1231 		REFCYC_PER_REQ_DELIVERY_PRE,
1232 		&ttu_attr->refcyc_per_req_delivery_pre_c);
1233 
1234 	/* Rest of hubp */
1235 	REG_GET(DCSURF_SURFACE_CONFIG,
1236 			SURFACE_PIXEL_FORMAT, &s->pixel_format);
1237 
1238 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1239 			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1240 
1241 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1242 			SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1243 
1244 	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1245 			PRI_VIEWPORT_WIDTH, &s->viewport_width,
1246 			PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1247 
1248 	REG_GET_2(DCSURF_SURFACE_CONFIG,
1249 			ROTATION_ANGLE, &s->rotation_angle,
1250 			H_MIRROR_EN, &s->h_mirror_en);
1251 
1252 	REG_GET(DCSURF_TILING_CONFIG,
1253 			SW_MODE, &s->sw_mode);
1254 
1255 	REG_GET(DCSURF_SURFACE_CONTROL,
1256 			PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1257 
1258 	REG_GET_3(DCHUBP_CNTL,
1259 			HUBP_BLANK_EN, &s->blank_en,
1260 			HUBP_TTU_DISABLE, &s->ttu_disable,
1261 			HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1262 
1263 	REG_GET(HUBP_CLK_CNTL,
1264 			HUBP_CLOCK_ENABLE, &s->clock_en);
1265 
1266 	REG_GET(DCN_GLOBAL_TTU_CNTL,
1267 			MIN_TTU_VBLANK, &s->min_ttu_vblank);
1268 
1269 	REG_GET_2(DCN_TTU_QOS_WM,
1270 			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1271 			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1272 
1273 	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS,
1274 			PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo);
1275 
1276 	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH,
1277 			PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi);
1278 
1279 	REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS,
1280 			PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo);
1281 
1282 	REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH,
1283 			PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi);
1284 }
1285 
1286 void hubp2_read_state(struct hubp *hubp)
1287 {
1288 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1289 	struct dcn_hubp_state *s = &hubp2->state;
1290 	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1291 
1292 	hubp2_read_state_common(hubp);
1293 
1294 	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1295 		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1296 		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1297 		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1298 		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1299 		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1300 		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1301 		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1302 		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1303 
1304 	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1305 		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1306 		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1307 		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1308 		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1309 		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1310 		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1311 		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1312 		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1313 
1314 }
1315 
1316 static void hubp2_validate_dml_output(struct hubp *hubp,
1317 		struct dc_context *ctx,
1318 		struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
1319 		struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
1320 		struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
1321 {
1322 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1323 	struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
1324 	struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
1325 	struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
1326 	DC_LOGGER_INIT(ctx->logger);
1327 	DC_LOG_DEBUG("DML Validation | Running Validation");
1328 
1329 	/* Requestor Regs */
1330 	REG_GET(HUBPRET_CONTROL,
1331 		DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
1332 	REG_GET_4(DCN_EXPANSION_MODE,
1333 		DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
1334 		PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
1335 		MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
1336 		CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
1337 	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1338 		CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
1339 		MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
1340 		META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
1341 		MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
1342 		DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
1343 		MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
1344 		SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
1345 		PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
1346 	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1347 		CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
1348 		MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
1349 		META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
1350 		MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
1351 		DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
1352 		MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,
1353 		SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
1354 		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
1355 
1356 	if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
1357 		DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
1358 				dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
1359 	if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
1360 		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1361 				dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
1362 	if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
1363 		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1364 				dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
1365 	if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
1366 		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
1367 				dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
1368 	if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
1369 		DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1370 				dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
1371 
1372 	if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
1373 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u  Actual: %u\n",
1374 				dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
1375 	if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
1376 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1377 				dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
1378 	if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
1379 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1380 				dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
1381 	if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
1382 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1383 				dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
1384 	if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
1385 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
1386 				dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
1387 	if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
1388 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
1389 				dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
1390 	if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
1391 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u  Actual: %u\n",
1392 				dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
1393 	if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
1394 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u  Actual: %u\n",
1395 				dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
1396 
1397 	if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
1398 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1399 				dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
1400 	if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
1401 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1402 				dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
1403 	if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
1404 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1405 				dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
1406 	if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
1407 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1408 				dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
1409 	if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
1410 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
1411 				dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
1412 	if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)
1413 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
1414 				dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);
1415 	if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
1416 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u  Actual: %u\n",
1417 				dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
1418 	if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
1419 		DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u  Actual: %u\n",
1420 				dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
1421 
1422 	/* DLG - Per hubp */
1423 	REG_GET_2(BLANK_OFFSET_0,
1424 		REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
1425 		DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
1426 	REG_GET(BLANK_OFFSET_1,
1427 		MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
1428 	REG_GET(DST_DIMENSIONS,
1429 		REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
1430 	REG_GET_2(DST_AFTER_SCALER,
1431 		REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
1432 		DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
1433 	REG_GET(REF_FREQ_TO_PIX_FREQ,
1434 		REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
1435 
1436 	if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
1437 		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u  Actual: %u\n",
1438 				dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
1439 	if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
1440 		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u  Actual: %u\n",
1441 				dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
1442 	if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
1443 		DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u  Actual: %u\n",
1444 				dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
1445 	if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
1446 		DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u  Actual: %u\n",
1447 				dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
1448 	if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
1449 		DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u  Actual: %u\n",
1450 				dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
1451 	if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
1452 		DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u  Actual: %u\n",
1453 				dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
1454 	if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
1455 		DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u  Actual: %u\n",
1456 				dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
1457 
1458 	/* DLG - Per luma/chroma */
1459 	REG_GET(VBLANK_PARAMETERS_1,
1460 		REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
1461 	if (REG(NOM_PARAMETERS_0))
1462 		REG_GET(NOM_PARAMETERS_0,
1463 			DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
1464 	if (REG(NOM_PARAMETERS_1))
1465 		REG_GET(NOM_PARAMETERS_1,
1466 			REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
1467 	REG_GET(NOM_PARAMETERS_4,
1468 		DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
1469 	REG_GET(NOM_PARAMETERS_5,
1470 		REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
1471 	REG_GET_2(PER_LINE_DELIVERY,
1472 		REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
1473 		REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
1474 	REG_GET_2(PER_LINE_DELIVERY_PRE,
1475 		REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
1476 		REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
1477 	REG_GET(VBLANK_PARAMETERS_2,
1478 		REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
1479 	if (REG(NOM_PARAMETERS_2))
1480 		REG_GET(NOM_PARAMETERS_2,
1481 			DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
1482 	if (REG(NOM_PARAMETERS_3))
1483 		REG_GET(NOM_PARAMETERS_3,
1484 			REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
1485 	REG_GET(NOM_PARAMETERS_6,
1486 		DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
1487 	REG_GET(NOM_PARAMETERS_7,
1488 		REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
1489 	REG_GET(VBLANK_PARAMETERS_3,
1490 			REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
1491 	REG_GET(VBLANK_PARAMETERS_4,
1492 			REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
1493 
1494 	if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
1495 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u  Actual: %u\n",
1496 				dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
1497 	if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
1498 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u  Actual: %u\n",
1499 				dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
1500 	if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
1501 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u  Actual: %u\n",
1502 				dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
1503 	if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
1504 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u  Actual: %u\n",
1505 				dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
1506 	if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
1507 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u  Actual: %u\n",
1508 				dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
1509 	if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
1510 		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u  Actual: %u\n",
1511 				dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
1512 	if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
1513 		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u  Actual: %u\n",
1514 				dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
1515 	if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
1516 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u  Actual: %u\n",
1517 				dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
1518 	if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
1519 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u  Actual: %u\n",
1520 				dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
1521 	if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
1522 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u  Actual: %u\n",
1523 				dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
1524 	if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
1525 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u  Actual: %u\n",
1526 				dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
1527 	if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
1528 		DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u  Actual: %u\n",
1529 				dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
1530 	if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
1531 		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u  Actual: %u\n",
1532 				dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
1533 	if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
1534 		DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u  Actual: %u\n",
1535 				dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
1536 	if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
1537 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u  Actual: %u\n",
1538 				dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
1539 	if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
1540 		DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u  Actual: %u\n",
1541 				dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
1542 
1543 	/* TTU - per hubp */
1544 	REG_GET_2(DCN_TTU_QOS_WM,
1545 		QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
1546 		QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
1547 
1548 	if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
1549 		DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u  Actual: %u\n",
1550 				dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
1551 	if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
1552 		DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u  Actual: %u\n",
1553 				dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
1554 
1555 	/* TTU - per luma/chroma */
1556 	/* Assumed surf0 is luma and 1 is chroma */
1557 	REG_GET_3(DCN_SURF0_TTU_CNTL0,
1558 		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
1559 		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
1560 		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
1561 	REG_GET_3(DCN_SURF1_TTU_CNTL0,
1562 		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
1563 		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
1564 		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
1565 	REG_GET_3(DCN_CUR0_TTU_CNTL0,
1566 		REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
1567 		QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
1568 		QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
1569 	REG_GET(FLIP_PARAMETERS_1,
1570 		REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
1571 	REG_GET(DCN_CUR0_TTU_CNTL1,
1572 			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
1573 	REG_GET(DCN_CUR1_TTU_CNTL1,
1574 			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
1575 	REG_GET(DCN_SURF0_TTU_CNTL1,
1576 			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
1577 	REG_GET(DCN_SURF1_TTU_CNTL1,
1578 			REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
1579 
1580 	if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
1581 		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1582 				dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
1583 	if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
1584 		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1585 				dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
1586 	if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
1587 		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1588 				dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
1589 	if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
1590 		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1591 				dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
1592 	if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
1593 		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1594 				dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
1595 	if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
1596 		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1597 				dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
1598 	if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
1599 		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1600 				dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
1601 	if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
1602 		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1603 				dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
1604 	if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
1605 		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1606 				dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
1607 	if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
1608 		DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u  Actual: %u\n",
1609 				dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
1610 	if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
1611 		DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1612 				dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
1613 	if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
1614 		DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1615 				dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
1616 	if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
1617 		DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1618 				dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
1619 	if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
1620 		DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1621 				dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
1622 }
1623 
1624 static struct hubp_funcs dcn20_hubp_funcs = {
1625 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
1626 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
1627 	.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
1628 	.hubp_program_surface_config = hubp2_program_surface_config,
1629 	.hubp_is_flip_pending = hubp2_is_flip_pending,
1630 	.hubp_setup = hubp2_setup,
1631 	.hubp_setup_interdependent = hubp2_setup_interdependent,
1632 	.hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
1633 	.set_blank = hubp2_set_blank,
1634 	.set_blank_regs = hubp2_set_blank_regs,
1635 	.dcc_control = hubp2_dcc_control,
1636 	.mem_program_viewport = min_set_viewport,
1637 	.set_cursor_attributes	= hubp2_cursor_set_attributes,
1638 	.set_cursor_position	= hubp2_cursor_set_position,
1639 	.hubp_clk_cntl = hubp2_clk_cntl,
1640 	.hubp_vtg_sel = hubp2_vtg_sel,
1641 	.dmdata_set_attributes = hubp2_dmdata_set_attributes,
1642 	.dmdata_load = hubp2_dmdata_load,
1643 	.dmdata_status_done = hubp2_dmdata_status_done,
1644 	.hubp_read_state = hubp2_read_state,
1645 	.hubp_clear_underflow = hubp2_clear_underflow,
1646 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
1647 	.hubp_init = hubp1_init,
1648 	.validate_dml_output = hubp2_validate_dml_output,
1649 	.hubp_in_blank = hubp1_in_blank,
1650 	.hubp_soft_reset = hubp1_soft_reset,
1651 	.hubp_set_flip_int = hubp1_set_flip_int,
1652 };
1653 
1654 
1655 bool hubp2_construct(
1656 	struct dcn20_hubp *hubp2,
1657 	struct dc_context *ctx,
1658 	uint32_t inst,
1659 	const struct dcn_hubp2_registers *hubp_regs,
1660 	const struct dcn_hubp2_shift *hubp_shift,
1661 	const struct dcn_hubp2_mask *hubp_mask)
1662 {
1663 	hubp2->base.funcs = &dcn20_hubp_funcs;
1664 	hubp2->base.ctx = ctx;
1665 	hubp2->hubp_regs = hubp_regs;
1666 	hubp2->hubp_shift = hubp_shift;
1667 	hubp2->hubp_mask = hubp_mask;
1668 	hubp2->base.inst = inst;
1669 	hubp2->base.opp_id = OPP_ID_INVALID;
1670 	hubp2->base.mpcc_id = 0xf;
1671 
1672 	return true;
1673 }
1674