1 /* 2 * Copyright 2012-17 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn20_hubp.h" 27 28 #include "dm_services.h" 29 #include "dce_calcs.h" 30 #include "reg_helper.h" 31 #include "basics/conversion.h" 32 33 #define REG(reg)\ 34 hubp2->hubp_regs->reg 35 36 #define CTX \ 37 hubp2->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 42 43 void hubp2_update_dchub( 44 struct hubp *hubp, 45 struct dchub_init_data *dh_data) 46 { 47 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 48 if (REG(DCN_VM_FB_LOCATION_TOP) == 0) 49 return; 50 51 switch (dh_data->fb_mode) { 52 case FRAME_BUFFER_MODE_ZFB_ONLY: 53 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ 54 REG_UPDATE(DCN_VM_FB_LOCATION_TOP, 55 FB_TOP, 0); 56 57 REG_UPDATE(DCN_VM_FB_LOCATION_BASE, 58 FB_BASE, 0xFFFFFF); 59 60 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ 61 REG_UPDATE(DCN_VM_AGP_BASE, 62 AGP_BASE, dh_data->zfb_phys_addr_base >> 24); 63 64 /*This field defines the bottom range of the AGP aperture and represents the 24*/ 65 /*MSBs, bits [47:24] of the 48 address bits*/ 66 REG_UPDATE(DCN_VM_AGP_BOT, 67 AGP_BOT, dh_data->zfb_mc_base_addr >> 24); 68 69 /*This field defines the top range of the AGP aperture and represents the 24*/ 70 /*MSBs, bits [47:24] of the 48 address bits*/ 71 REG_UPDATE(DCN_VM_AGP_TOP, 72 AGP_TOP, (dh_data->zfb_mc_base_addr + 73 dh_data->zfb_size_in_byte - 1) >> 24); 74 break; 75 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: 76 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ 77 78 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ 79 REG_UPDATE(DCN_VM_AGP_BASE, 80 AGP_BASE, dh_data->zfb_phys_addr_base >> 24); 81 82 /*This field defines the bottom range of the AGP aperture and represents the 24*/ 83 /*MSBs, bits [47:24] of the 48 address bits*/ 84 REG_UPDATE(DCN_VM_AGP_BOT, 85 AGP_BOT, dh_data->zfb_mc_base_addr >> 24); 86 87 /*This field defines the top range of the AGP aperture and represents the 24*/ 88 /*MSBs, bits [47:24] of the 48 address bits*/ 89 REG_UPDATE(DCN_VM_AGP_TOP, 90 AGP_TOP, (dh_data->zfb_mc_base_addr + 91 dh_data->zfb_size_in_byte - 1) >> 24); 92 break; 93 case FRAME_BUFFER_MODE_LOCAL_ONLY: 94 /*Should not touch FB LOCATION (should be done by VBIOS)*/ 95 96 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/ 97 REG_UPDATE(DCN_VM_AGP_BASE, 98 AGP_BASE, 0); 99 100 /*This field defines the bottom range of the AGP aperture and represents the 24*/ 101 /*MSBs, bits [47:24] of the 48 address bits*/ 102 REG_UPDATE(DCN_VM_AGP_BOT, 103 AGP_BOT, 0xFFFFFF); 104 105 /*This field defines the top range of the AGP aperture and represents the 24*/ 106 /*MSBs, bits [47:24] of the 48 address bits*/ 107 REG_UPDATE(DCN_VM_AGP_TOP, 108 AGP_TOP, 0); 109 break; 110 default: 111 break; 112 } 113 114 dh_data->dchub_initialzied = true; 115 dh_data->dchub_info_valid = false; 116 } 117 118 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 119 struct vm_system_aperture_param *apt) 120 { 121 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 122 123 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 124 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 125 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 126 127 // The format of default addr is 48:12 of the 48 bit addr 128 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 129 130 // The format of high/low are 48:18 of the 48 bit addr 131 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 132 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 133 134 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 135 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ 136 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 137 138 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 139 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 140 141 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 142 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 143 144 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 145 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 146 147 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 148 ENABLE_L1_TLB, 1, 149 SYSTEM_ACCESS_MODE, 0x3); 150 } 151 152 void hubp2_program_deadline( 153 struct hubp *hubp, 154 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 155 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 156 { 157 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 158 159 /* DLG - Per hubp */ 160 REG_SET_2(BLANK_OFFSET_0, 0, 161 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 162 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 163 164 REG_SET(BLANK_OFFSET_1, 0, 165 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 166 167 REG_SET(DST_DIMENSIONS, 0, 168 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 169 170 REG_SET_2(DST_AFTER_SCALER, 0, 171 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 172 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 173 174 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 175 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 176 177 /* DLG - Per luma/chroma */ 178 REG_SET(VBLANK_PARAMETERS_1, 0, 179 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 180 181 if (REG(NOM_PARAMETERS_0)) 182 REG_SET(NOM_PARAMETERS_0, 0, 183 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 184 185 if (REG(NOM_PARAMETERS_1)) 186 REG_SET(NOM_PARAMETERS_1, 0, 187 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 188 189 REG_SET(NOM_PARAMETERS_4, 0, 190 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 191 192 REG_SET(NOM_PARAMETERS_5, 0, 193 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 194 195 REG_SET_2(PER_LINE_DELIVERY, 0, 196 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 197 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 198 199 REG_SET(VBLANK_PARAMETERS_2, 0, 200 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 201 202 if (REG(NOM_PARAMETERS_2)) 203 REG_SET(NOM_PARAMETERS_2, 0, 204 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 205 206 if (REG(NOM_PARAMETERS_3)) 207 REG_SET(NOM_PARAMETERS_3, 0, 208 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 209 210 REG_SET(NOM_PARAMETERS_6, 0, 211 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 212 213 REG_SET(NOM_PARAMETERS_7, 0, 214 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 215 216 /* TTU - per hubp */ 217 REG_SET_2(DCN_TTU_QOS_WM, 0, 218 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 219 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 220 221 /* TTU - per luma/chroma */ 222 /* Assumed surf0 is luma and 1 is chroma */ 223 224 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 225 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 226 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 227 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 228 229 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 230 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 231 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 232 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 233 234 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 235 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 236 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 237 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 238 239 REG_SET(FLIP_PARAMETERS_1, 0, 240 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 241 } 242 243 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 244 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 245 { 246 uint32_t value = 0; 247 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 248 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ 249 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 250 /* 251 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) 252 <= OTG_V_BLANK_END 253 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 254 else 255 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 256 */ 257 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width 258 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 259 value = 1; 260 } else 261 value = 0; 262 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); 263 } 264 265 void hubp2_program_requestor( 266 struct hubp *hubp, 267 struct _vcs_dpi_display_rq_regs_st *rq_regs) 268 { 269 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 270 271 REG_UPDATE(HUBPRET_CONTROL, 272 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 273 REG_SET_4(DCN_EXPANSION_MODE, 0, 274 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 275 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 276 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 277 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 278 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 279 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 280 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 281 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 282 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 283 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 284 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 285 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 286 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 287 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 288 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 289 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 290 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 291 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 292 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 293 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 294 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 295 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 296 } 297 298 static void hubp2_setup( 299 struct hubp *hubp, 300 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 301 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 302 struct _vcs_dpi_display_rq_regs_st *rq_regs, 303 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 304 { 305 /* otg is locked when this func is called. Register are double buffered. 306 * disable the requestors is not needed 307 */ 308 309 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 310 hubp2_program_requestor(hubp, rq_regs); 311 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 312 313 } 314 315 void hubp2_setup_interdependent( 316 struct hubp *hubp, 317 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 318 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 319 { 320 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 321 322 REG_SET_2(PREFETCH_SETTINGS, 0, 323 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 324 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 325 326 REG_SET(PREFETCH_SETTINGS_C, 0, 327 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 328 329 REG_SET_2(VBLANK_PARAMETERS_0, 0, 330 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 331 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 332 333 REG_SET_2(FLIP_PARAMETERS_0, 0, 334 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, 335 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); 336 337 REG_SET(VBLANK_PARAMETERS_3, 0, 338 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 339 340 REG_SET(VBLANK_PARAMETERS_4, 0, 341 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 342 343 REG_SET(FLIP_PARAMETERS_2, 0, 344 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); 345 346 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 347 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 348 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 349 350 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 351 REFCYC_PER_REQ_DELIVERY_PRE, 352 ttu_attr->refcyc_per_req_delivery_pre_l); 353 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 354 REFCYC_PER_REQ_DELIVERY_PRE, 355 ttu_attr->refcyc_per_req_delivery_pre_c); 356 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 357 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 358 REG_SET(DCN_CUR1_TTU_CNTL1, 0, 359 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); 360 361 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 362 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 363 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 364 } 365 366 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: 367 * NUM_BANKS 368 * NUM_SE 369 * NUM_RB_PER_SE 370 * RB_ALIGNED 371 * Other things can be defaulted, since they never change: 372 * PIPE_ALIGNED = 0 373 * META_LINEAR = 0 374 * In GFX10, only these apply: 375 * PIPE_INTERLEAVE 376 * NUM_PIPES 377 * MAX_COMPRESSED_FRAGS 378 * SW_MODE 379 */ 380 static void hubp2_program_tiling( 381 struct dcn20_hubp *hubp2, 382 const union dc_tiling_info *info, 383 const enum surface_pixel_format pixel_format) 384 { 385 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 386 NUM_PIPES, log_2(info->gfx9.num_pipes), 387 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 388 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 389 390 REG_UPDATE_4(DCSURF_TILING_CONFIG, 391 SW_MODE, info->gfx9.swizzle, 392 META_LINEAR, 0, 393 RB_ALIGNED, 0, 394 PIPE_ALIGNED, 0); 395 } 396 397 void hubp2_program_size( 398 struct hubp *hubp, 399 enum surface_pixel_format format, 400 const union plane_size *plane_size, 401 struct dc_plane_dcc_param *dcc) 402 { 403 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 404 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 405 406 /* Program data and meta surface pitch (calculation from addrlib) 407 * 444 or 420 luma 408 */ 409 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) { 410 ASSERT(plane_size->video.chroma_pitch != 0); 411 /* Chroma pitch zero can cause system hang! */ 412 413 pitch = plane_size->video.luma_pitch - 1; 414 meta_pitch = dcc->video.meta_pitch_l - 1; 415 pitch_c = plane_size->video.chroma_pitch - 1; 416 meta_pitch_c = dcc->video.meta_pitch_c - 1; 417 } else { 418 pitch = plane_size->grph.surface_pitch - 1; 419 meta_pitch = dcc->grph.meta_pitch - 1; 420 pitch_c = 0; 421 meta_pitch_c = 0; 422 } 423 424 if (!dcc->enable) { 425 meta_pitch = 0; 426 meta_pitch_c = 0; 427 } 428 429 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 430 PITCH, pitch, META_PITCH, meta_pitch); 431 432 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 433 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 434 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 435 } 436 437 void hubp2_program_rotation( 438 struct hubp *hubp, 439 enum dc_rotation_angle rotation, 440 bool horizontal_mirror) 441 { 442 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 443 uint32_t mirror; 444 445 446 if (horizontal_mirror) 447 mirror = 1; 448 else 449 mirror = 0; 450 451 /* Program rotation angle and horz mirror - no mirror */ 452 if (rotation == ROTATION_ANGLE_0) 453 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 454 ROTATION_ANGLE, 0, 455 H_MIRROR_EN, mirror); 456 else if (rotation == ROTATION_ANGLE_90) 457 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 458 ROTATION_ANGLE, 1, 459 H_MIRROR_EN, mirror); 460 else if (rotation == ROTATION_ANGLE_180) 461 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 462 ROTATION_ANGLE, 2, 463 H_MIRROR_EN, mirror); 464 else if (rotation == ROTATION_ANGLE_270) 465 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 466 ROTATION_ANGLE, 3, 467 H_MIRROR_EN, mirror); 468 } 469 470 void hubp2_dcc_control(struct hubp *hubp, bool enable, 471 bool independent_64b_blks) 472 { 473 uint32_t dcc_en = enable ? 1 : 0; 474 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 475 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 476 477 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 478 PRIMARY_SURFACE_DCC_EN, dcc_en, 479 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 480 SECONDARY_SURFACE_DCC_EN, dcc_en, 481 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 482 } 483 484 void hubp2_program_pixel_format( 485 struct hubp *hubp, 486 enum surface_pixel_format format) 487 { 488 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 489 uint32_t red_bar = 3; 490 uint32_t blue_bar = 2; 491 492 /* swap for ABGR format */ 493 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 494 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 495 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 496 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 497 red_bar = 2; 498 blue_bar = 3; 499 } 500 501 REG_UPDATE_2(HUBPRET_CONTROL, 502 CROSSBAR_SRC_CB_B, blue_bar, 503 CROSSBAR_SRC_CR_R, red_bar); 504 505 /* Mapping is same as ipp programming (cnvc) */ 506 507 switch (format) { 508 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 509 REG_UPDATE(DCSURF_SURFACE_CONFIG, 510 SURFACE_PIXEL_FORMAT, 1); 511 break; 512 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 513 REG_UPDATE(DCSURF_SURFACE_CONFIG, 514 SURFACE_PIXEL_FORMAT, 3); 515 break; 516 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 517 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 518 REG_UPDATE(DCSURF_SURFACE_CONFIG, 519 SURFACE_PIXEL_FORMAT, 8); 520 break; 521 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 522 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 523 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 524 REG_UPDATE(DCSURF_SURFACE_CONFIG, 525 SURFACE_PIXEL_FORMAT, 10); 526 break; 527 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 528 REG_UPDATE(DCSURF_SURFACE_CONFIG, 529 SURFACE_PIXEL_FORMAT, 22); 530 break; 531 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 532 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 533 REG_UPDATE(DCSURF_SURFACE_CONFIG, 534 SURFACE_PIXEL_FORMAT, 24); 535 break; 536 537 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 538 REG_UPDATE(DCSURF_SURFACE_CONFIG, 539 SURFACE_PIXEL_FORMAT, 65); 540 break; 541 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 542 REG_UPDATE(DCSURF_SURFACE_CONFIG, 543 SURFACE_PIXEL_FORMAT, 64); 544 break; 545 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 546 REG_UPDATE(DCSURF_SURFACE_CONFIG, 547 SURFACE_PIXEL_FORMAT, 67); 548 break; 549 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 550 REG_UPDATE(DCSURF_SURFACE_CONFIG, 551 SURFACE_PIXEL_FORMAT, 66); 552 break; 553 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 554 REG_UPDATE(DCSURF_SURFACE_CONFIG, 555 SURFACE_PIXEL_FORMAT, 12); 556 break; 557 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 558 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 559 REG_UPDATE(DCSURF_SURFACE_CONFIG, 560 SURFACE_PIXEL_FORMAT, 112); 561 break; 562 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 563 REG_UPDATE(DCSURF_SURFACE_CONFIG, 564 SURFACE_PIXEL_FORMAT, 113); 565 break; 566 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 567 REG_UPDATE(DCSURF_SURFACE_CONFIG, 568 SURFACE_PIXEL_FORMAT, 114); 569 break; 570 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 571 REG_UPDATE(DCSURF_SURFACE_CONFIG, 572 SURFACE_PIXEL_FORMAT, 118); 573 break; 574 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 575 REG_UPDATE(DCSURF_SURFACE_CONFIG, 576 SURFACE_PIXEL_FORMAT, 119); 577 break; 578 #endif 579 default: 580 BREAK_TO_DEBUGGER(); 581 break; 582 } 583 584 /* don't see the need of program the xbar in DCN 1.0 */ 585 } 586 587 void hubp2_program_surface_config( 588 struct hubp *hubp, 589 enum surface_pixel_format format, 590 union dc_tiling_info *tiling_info, 591 union plane_size *plane_size, 592 enum dc_rotation_angle rotation, 593 struct dc_plane_dcc_param *dcc, 594 bool horizontal_mirror, 595 unsigned int compat_level) 596 { 597 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 598 599 hubp2_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks); 600 hubp2_program_tiling(hubp2, tiling_info, format); 601 hubp2_program_size(hubp, format, plane_size, dcc); 602 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 603 hubp2_program_pixel_format(hubp, format); 604 } 605 606 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 607 unsigned int cursor_width, 608 enum dc_cursor_color_format cursor_mode) 609 { 610 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 611 612 if (cursor_mode == CURSOR_MODE_MONO) 613 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 614 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || 615 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 616 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 617 if (cursor_width >= 1 && cursor_width <= 32) 618 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 619 else if (cursor_width >= 33 && cursor_width <= 64) 620 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 621 else if (cursor_width >= 65 && cursor_width <= 128) 622 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 623 else if (cursor_width >= 129 && cursor_width <= 256) 624 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 625 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || 626 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { 627 if (cursor_width >= 1 && cursor_width <= 16) 628 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 629 else if (cursor_width >= 17 && cursor_width <= 32) 630 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 631 else if (cursor_width >= 33 && cursor_width <= 64) 632 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 633 else if (cursor_width >= 65 && cursor_width <= 128) 634 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 635 else if (cursor_width >= 129 && cursor_width <= 256) 636 line_per_chunk = CURSOR_LINE_PER_CHUNK_1; 637 } 638 639 return line_per_chunk; 640 } 641 642 void hubp2_cursor_set_attributes( 643 struct hubp *hubp, 644 const struct dc_cursor_attributes *attr) 645 { 646 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 647 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 648 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 649 attr->width, attr->color_format); 650 651 hubp->curs_attr = *attr; 652 653 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 654 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 655 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 656 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 657 658 REG_UPDATE_2(CURSOR_SIZE, 659 CURSOR_WIDTH, attr->width, 660 CURSOR_HEIGHT, attr->height); 661 662 REG_UPDATE_4(CURSOR_CONTROL, 663 CURSOR_MODE, attr->color_format, 664 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 665 CURSOR_PITCH, hw_pitch, 666 CURSOR_LINES_PER_CHUNK, lpc); 667 668 REG_SET_2(CURSOR_SETTINGS, 0, 669 /* no shift of the cursor HDL schedule */ 670 CURSOR0_DST_Y_OFFSET, 0, 671 /* used to shift the cursor chunk request deadline */ 672 CURSOR0_CHUNK_HDL_ADJUST, 3); 673 } 674 675 void hubp2_dmdata_set_attributes( 676 struct hubp *hubp, 677 const struct dc_dmdata_attributes *attr) 678 { 679 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 680 681 if (attr->dmdata_mode == DMDATA_HW_MODE) { 682 /* set to HW mode */ 683 REG_UPDATE(DMDATA_CNTL, 684 DMDATA_MODE, 1); 685 686 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ 687 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); 688 689 /* toggle DMDATA_UPDATED and set repeat and size */ 690 REG_UPDATE(DMDATA_CNTL, 691 DMDATA_UPDATED, 0); 692 REG_UPDATE_3(DMDATA_CNTL, 693 DMDATA_UPDATED, 1, 694 DMDATA_REPEAT, attr->dmdata_repeat, 695 DMDATA_SIZE, attr->dmdata_size); 696 697 /* set DMDATA address */ 698 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); 699 REG_UPDATE(DMDATA_ADDRESS_HIGH, 700 DMDATA_ADDRESS_HIGH, attr->address.high_part); 701 702 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); 703 704 } else { 705 /* set to SW mode before loading data */ 706 REG_SET(DMDATA_CNTL, 0, 707 DMDATA_MODE, 0); 708 /* toggle DMDATA_SW_UPDATED to start loading sequence */ 709 REG_UPDATE(DMDATA_SW_CNTL, 710 DMDATA_SW_UPDATED, 0); 711 REG_UPDATE_3(DMDATA_SW_CNTL, 712 DMDATA_SW_UPDATED, 1, 713 DMDATA_SW_REPEAT, attr->dmdata_repeat, 714 DMDATA_SW_SIZE, attr->dmdata_size); 715 /* load data into hubp dmdata buffer */ 716 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); 717 } 718 719 /* Note that DL_DELTA must be programmed if we want to use TTU mode */ 720 REG_SET_3(DMDATA_QOS_CNTL, 0, 721 DMDATA_QOS_MODE, attr->dmdata_qos_mode, 722 DMDATA_QOS_LEVEL, attr->dmdata_qos_level, 723 DMDATA_DL_DELTA, attr->dmdata_dl_delta); 724 } 725 726 void hubp2_dmdata_load( 727 struct hubp *hubp, 728 uint32_t dmdata_sw_size, 729 const uint32_t *dmdata_sw_data) 730 { 731 int i; 732 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 733 734 /* load dmdata into HUBP buffer in SW mode */ 735 for (i = 0; i < dmdata_sw_size / 4; i++) 736 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); 737 } 738 739 bool hubp2_dmdata_status_done(struct hubp *hubp) 740 { 741 uint32_t status; 742 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 743 744 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); 745 return (status == 1); 746 } 747 748 bool hubp2_program_surface_flip_and_addr( 749 struct hubp *hubp, 750 const struct dc_plane_address *address, 751 bool flip_immediate) 752 { 753 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 754 755 //program flip type 756 REG_UPDATE(DCSURF_FLIP_CONTROL, 757 SURFACE_FLIP_TYPE, flip_immediate); 758 759 // Program VMID reg 760 REG_UPDATE(VMID_SETTINGS_0, 761 VMID, address->vmid); 762 763 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 764 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 765 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 766 767 } else { 768 // turn off stereo if not in stereo 769 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 770 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 771 } 772 773 774 775 /* HW automatically latch rest of address register on write to 776 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 777 * 778 * program high first and then the low addr, order matters! 779 */ 780 switch (address->type) { 781 case PLN_ADDR_TYPE_GRAPHICS: 782 /* DCN1.0 does not support const color 783 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 784 * base on address->grph.dcc_const_color 785 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 786 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 787 */ 788 789 if (address->grph.addr.quad_part == 0) 790 break; 791 792 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 793 PRIMARY_SURFACE_TMZ, address->tmz_surface, 794 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 795 796 if (address->grph.meta_addr.quad_part != 0) { 797 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 798 PRIMARY_META_SURFACE_ADDRESS_HIGH, 799 address->grph.meta_addr.high_part); 800 801 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 802 PRIMARY_META_SURFACE_ADDRESS, 803 address->grph.meta_addr.low_part); 804 } 805 806 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 807 PRIMARY_SURFACE_ADDRESS_HIGH, 808 address->grph.addr.high_part); 809 810 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 811 PRIMARY_SURFACE_ADDRESS, 812 address->grph.addr.low_part); 813 break; 814 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 815 if (address->video_progressive.luma_addr.quad_part == 0 816 || address->video_progressive.chroma_addr.quad_part == 0) 817 break; 818 819 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 820 PRIMARY_SURFACE_TMZ, address->tmz_surface, 821 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 822 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 823 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 824 825 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 826 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 827 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 828 address->video_progressive.chroma_meta_addr.high_part); 829 830 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 831 PRIMARY_META_SURFACE_ADDRESS_C, 832 address->video_progressive.chroma_meta_addr.low_part); 833 834 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 835 PRIMARY_META_SURFACE_ADDRESS_HIGH, 836 address->video_progressive.luma_meta_addr.high_part); 837 838 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 839 PRIMARY_META_SURFACE_ADDRESS, 840 address->video_progressive.luma_meta_addr.low_part); 841 } 842 843 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 844 PRIMARY_SURFACE_ADDRESS_HIGH_C, 845 address->video_progressive.chroma_addr.high_part); 846 847 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 848 PRIMARY_SURFACE_ADDRESS_C, 849 address->video_progressive.chroma_addr.low_part); 850 851 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 852 PRIMARY_SURFACE_ADDRESS_HIGH, 853 address->video_progressive.luma_addr.high_part); 854 855 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 856 PRIMARY_SURFACE_ADDRESS, 857 address->video_progressive.luma_addr.low_part); 858 break; 859 case PLN_ADDR_TYPE_GRPH_STEREO: 860 if (address->grph_stereo.left_addr.quad_part == 0) 861 break; 862 if (address->grph_stereo.right_addr.quad_part == 0) 863 break; 864 865 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 866 PRIMARY_SURFACE_TMZ, address->tmz_surface, 867 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 868 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 869 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 870 SECONDARY_SURFACE_TMZ, address->tmz_surface, 871 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 872 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 873 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 874 875 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 876 877 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 878 SECONDARY_META_SURFACE_ADDRESS_HIGH, 879 address->grph_stereo.right_meta_addr.high_part); 880 881 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 882 SECONDARY_META_SURFACE_ADDRESS, 883 address->grph_stereo.right_meta_addr.low_part); 884 } 885 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 886 887 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 888 PRIMARY_META_SURFACE_ADDRESS_HIGH, 889 address->grph_stereo.left_meta_addr.high_part); 890 891 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 892 PRIMARY_META_SURFACE_ADDRESS, 893 address->grph_stereo.left_meta_addr.low_part); 894 } 895 896 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 897 SECONDARY_SURFACE_ADDRESS_HIGH, 898 address->grph_stereo.right_addr.high_part); 899 900 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 901 SECONDARY_SURFACE_ADDRESS, 902 address->grph_stereo.right_addr.low_part); 903 904 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 905 PRIMARY_SURFACE_ADDRESS_HIGH, 906 address->grph_stereo.left_addr.high_part); 907 908 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 909 PRIMARY_SURFACE_ADDRESS, 910 address->grph_stereo.left_addr.low_part); 911 break; 912 default: 913 BREAK_TO_DEBUGGER(); 914 break; 915 } 916 917 hubp->request_address = *address; 918 919 return true; 920 } 921 922 void hubp2_enable_triplebuffer( 923 struct hubp *hubp, 924 bool enable) 925 { 926 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 927 uint32_t triple_buffer_en = 0; 928 bool tri_buffer_en; 929 930 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 931 tri_buffer_en = (triple_buffer_en == 1); 932 if (tri_buffer_en != enable) { 933 REG_UPDATE(DCSURF_FLIP_CONTROL2, 934 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); 935 } 936 } 937 938 bool hubp2_is_triplebuffer_enabled( 939 struct hubp *hubp) 940 { 941 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 942 uint32_t triple_buffer_en = 0; 943 944 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 945 946 return (bool)triple_buffer_en; 947 } 948 949 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) 950 { 951 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 952 953 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); 954 } 955 956 bool hubp2_is_flip_pending(struct hubp *hubp) 957 { 958 uint32_t flip_pending = 0; 959 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 960 struct dc_plane_address earliest_inuse_address; 961 962 REG_GET(DCSURF_FLIP_CONTROL, 963 SURFACE_FLIP_PENDING, &flip_pending); 964 965 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 966 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 967 968 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 969 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 970 971 if (flip_pending) 972 return true; 973 974 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 975 return true; 976 977 return false; 978 } 979 980 void hubp2_set_blank(struct hubp *hubp, bool blank) 981 { 982 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 983 uint32_t blank_en = blank ? 1 : 0; 984 985 REG_UPDATE_2(DCHUBP_CNTL, 986 HUBP_BLANK_EN, blank_en, 987 HUBP_TTU_DISABLE, blank_en); 988 989 if (blank) { 990 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 991 992 if (reg_val) { 993 /* init sequence workaround: in case HUBP is 994 * power gated, this wait would timeout. 995 * 996 * we just wrote reg_val to non-0, if it stay 0 997 * it means HUBP is gated 998 */ 999 REG_WAIT(DCHUBP_CNTL, 1000 HUBP_NO_OUTSTANDING_REQ, 1, 1001 1, 200); 1002 } 1003 1004 hubp->mpcc_id = 0xf; 1005 hubp->opp_id = OPP_ID_INVALID; 1006 } 1007 } 1008 1009 void hubp2_cursor_set_position( 1010 struct hubp *hubp, 1011 const struct dc_cursor_position *pos, 1012 const struct dc_cursor_mi_param *param) 1013 { 1014 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1015 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 1016 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 1017 int x_hotspot = pos->x_hotspot; 1018 int y_hotspot = pos->y_hotspot; 1019 uint32_t dst_x_offset; 1020 uint32_t cur_en = pos->enable ? 1 : 0; 1021 1022 /* 1023 * Guard aganst cursor_set_position() from being called with invalid 1024 * attributes 1025 * 1026 * TODO: Look at combining cursor_set_position() and 1027 * cursor_set_attributes() into cursor_update() 1028 */ 1029 if (hubp->curs_attr.address.quad_part == 0) 1030 return; 1031 1032 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 1033 src_x_offset = pos->y - pos->y_hotspot - param->viewport.x; 1034 y_hotspot = pos->x_hotspot; 1035 x_hotspot = pos->y_hotspot; 1036 } 1037 1038 if (param->mirror) { 1039 x_hotspot = param->viewport.width - x_hotspot; 1040 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 1041 } 1042 1043 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1044 dst_x_offset *= param->ref_clk_khz; 1045 dst_x_offset /= param->pixel_clk_khz; 1046 1047 ASSERT(param->h_scale_ratio.value); 1048 1049 if (param->h_scale_ratio.value) 1050 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1051 dc_fixpt_from_int(dst_x_offset), 1052 param->h_scale_ratio)); 1053 1054 if (src_x_offset >= (int)param->viewport.width) 1055 cur_en = 0; /* not visible beyond right edge*/ 1056 1057 if (src_x_offset + (int)hubp->curs_attr.width <= 0) 1058 cur_en = 0; /* not visible beyond left edge*/ 1059 1060 if (src_y_offset >= (int)param->viewport.height) 1061 cur_en = 0; /* not visible beyond bottom edge*/ 1062 1063 if (src_y_offset + (int)hubp->curs_attr.height <= 0) 1064 cur_en = 0; /* not visible beyond top edge*/ 1065 1066 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1067 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1068 1069 REG_UPDATE(CURSOR_CONTROL, 1070 CURSOR_ENABLE, cur_en); 1071 1072 REG_SET_2(CURSOR_POSITION, 0, 1073 CURSOR_X_POSITION, pos->x, 1074 CURSOR_Y_POSITION, pos->y); 1075 1076 REG_SET_2(CURSOR_HOT_SPOT, 0, 1077 CURSOR_HOT_SPOT_X, x_hotspot, 1078 CURSOR_HOT_SPOT_Y, y_hotspot); 1079 1080 REG_SET(CURSOR_DST_OFFSET, 0, 1081 CURSOR_DST_X_OFFSET, dst_x_offset); 1082 /* TODO Handle surface pixel formats other than 4:4:4 */ 1083 } 1084 1085 void hubp2_clk_cntl(struct hubp *hubp, bool enable) 1086 { 1087 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1088 uint32_t clk_enable = enable ? 1 : 0; 1089 1090 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1091 } 1092 1093 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1094 { 1095 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1096 1097 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1098 } 1099 1100 void hubp2_clear_underflow(struct hubp *hubp) 1101 { 1102 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1103 1104 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 1105 } 1106 1107 void hubp2_read_state_common(struct hubp *hubp) 1108 { 1109 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1110 struct dcn_hubp_state *s = &hubp2->state; 1111 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 1112 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 1113 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1114 1115 /* Requester */ 1116 REG_GET(HUBPRET_CONTROL, 1117 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 1118 REG_GET_4(DCN_EXPANSION_MODE, 1119 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 1120 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 1121 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1122 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1123 1124 /* DLG - Per hubp */ 1125 REG_GET_2(BLANK_OFFSET_0, 1126 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 1127 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 1128 1129 REG_GET(BLANK_OFFSET_1, 1130 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 1131 1132 REG_GET(DST_DIMENSIONS, 1133 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 1134 1135 REG_GET_2(DST_AFTER_SCALER, 1136 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 1137 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 1138 1139 if (REG(PREFETCH_SETTINS)) 1140 REG_GET_2(PREFETCH_SETTINS, 1141 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1142 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1143 else 1144 REG_GET_2(PREFETCH_SETTINGS, 1145 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1146 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1147 1148 REG_GET_2(VBLANK_PARAMETERS_0, 1149 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 1150 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 1151 1152 REG_GET(REF_FREQ_TO_PIX_FREQ, 1153 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 1154 1155 /* DLG - Per luma/chroma */ 1156 REG_GET(VBLANK_PARAMETERS_1, 1157 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 1158 1159 REG_GET(VBLANK_PARAMETERS_3, 1160 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 1161 1162 if (REG(NOM_PARAMETERS_0)) 1163 REG_GET(NOM_PARAMETERS_0, 1164 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 1165 1166 if (REG(NOM_PARAMETERS_1)) 1167 REG_GET(NOM_PARAMETERS_1, 1168 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 1169 1170 REG_GET(NOM_PARAMETERS_4, 1171 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 1172 1173 REG_GET(NOM_PARAMETERS_5, 1174 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 1175 1176 REG_GET_2(PER_LINE_DELIVERY_PRE, 1177 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1178 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 1179 1180 REG_GET_2(PER_LINE_DELIVERY, 1181 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 1182 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 1183 1184 if (REG(PREFETCH_SETTINS_C)) 1185 REG_GET(PREFETCH_SETTINS_C, 1186 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1187 else 1188 REG_GET(PREFETCH_SETTINGS_C, 1189 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1190 1191 REG_GET(VBLANK_PARAMETERS_2, 1192 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 1193 1194 REG_GET(VBLANK_PARAMETERS_4, 1195 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 1196 1197 if (REG(NOM_PARAMETERS_2)) 1198 REG_GET(NOM_PARAMETERS_2, 1199 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1200 1201 if (REG(NOM_PARAMETERS_3)) 1202 REG_GET(NOM_PARAMETERS_3, 1203 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1204 1205 REG_GET(NOM_PARAMETERS_6, 1206 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1207 1208 REG_GET(NOM_PARAMETERS_7, 1209 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1210 1211 /* TTU - per hubp */ 1212 REG_GET_2(DCN_TTU_QOS_WM, 1213 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1214 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1215 1216 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1217 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1218 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1219 1220 /* TTU - per luma/chroma */ 1221 /* Assumed surf0 is luma and 1 is chroma */ 1222 1223 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1224 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1225 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1226 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1227 1228 REG_GET(DCN_SURF0_TTU_CNTL1, 1229 REFCYC_PER_REQ_DELIVERY_PRE, 1230 &ttu_attr->refcyc_per_req_delivery_pre_l); 1231 1232 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1233 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1234 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1235 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1236 1237 REG_GET(DCN_SURF1_TTU_CNTL1, 1238 REFCYC_PER_REQ_DELIVERY_PRE, 1239 &ttu_attr->refcyc_per_req_delivery_pre_c); 1240 1241 /* Rest of hubp */ 1242 REG_GET(DCSURF_SURFACE_CONFIG, 1243 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1244 1245 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1246 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1247 1248 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1249 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1250 1251 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1252 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1253 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1254 1255 REG_GET_2(DCSURF_SURFACE_CONFIG, 1256 ROTATION_ANGLE, &s->rotation_angle, 1257 H_MIRROR_EN, &s->h_mirror_en); 1258 1259 REG_GET(DCSURF_TILING_CONFIG, 1260 SW_MODE, &s->sw_mode); 1261 1262 REG_GET(DCSURF_SURFACE_CONTROL, 1263 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1264 1265 REG_GET_3(DCHUBP_CNTL, 1266 HUBP_BLANK_EN, &s->blank_en, 1267 HUBP_TTU_DISABLE, &s->ttu_disable, 1268 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1269 1270 REG_GET(DCN_GLOBAL_TTU_CNTL, 1271 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1272 1273 REG_GET_2(DCN_TTU_QOS_WM, 1274 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1275 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1276 1277 } 1278 1279 void hubp2_read_state(struct hubp *hubp) 1280 { 1281 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1282 struct dcn_hubp_state *s = &hubp2->state; 1283 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1284 1285 hubp2_read_state_common(hubp); 1286 1287 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1288 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1289 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1290 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1291 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1292 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1293 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1294 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1295 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1296 1297 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1298 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1299 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1300 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1301 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1302 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1303 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1304 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1305 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1306 1307 } 1308 1309 static struct hubp_funcs dcn20_hubp_funcs = { 1310 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 1311 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 1312 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 1313 .hubp_program_surface_config = hubp2_program_surface_config, 1314 .hubp_is_flip_pending = hubp2_is_flip_pending, 1315 .hubp_setup = hubp2_setup, 1316 .hubp_setup_interdependent = hubp2_setup_interdependent, 1317 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, 1318 .set_blank = hubp2_set_blank, 1319 .dcc_control = hubp2_dcc_control, 1320 .hubp_update_dchub = hubp2_update_dchub, 1321 .mem_program_viewport = min_set_viewport, 1322 .set_cursor_attributes = hubp2_cursor_set_attributes, 1323 .set_cursor_position = hubp2_cursor_set_position, 1324 .hubp_clk_cntl = hubp2_clk_cntl, 1325 .hubp_vtg_sel = hubp2_vtg_sel, 1326 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 1327 .dmdata_load = hubp2_dmdata_load, 1328 .dmdata_status_done = hubp2_dmdata_status_done, 1329 .hubp_read_state = hubp2_read_state, 1330 .hubp_clear_underflow = hubp2_clear_underflow, 1331 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1332 .hubp_init = hubp1_init, 1333 }; 1334 1335 1336 bool hubp2_construct( 1337 struct dcn20_hubp *hubp2, 1338 struct dc_context *ctx, 1339 uint32_t inst, 1340 const struct dcn_hubp2_registers *hubp_regs, 1341 const struct dcn_hubp2_shift *hubp_shift, 1342 const struct dcn_hubp2_mask *hubp_mask) 1343 { 1344 hubp2->base.funcs = &dcn20_hubp_funcs; 1345 hubp2->base.ctx = ctx; 1346 hubp2->hubp_regs = hubp_regs; 1347 hubp2->hubp_shift = hubp_shift; 1348 hubp2->hubp_mask = hubp_mask; 1349 hubp2->base.inst = inst; 1350 hubp2->base.opp_id = OPP_ID_INVALID; 1351 hubp2->base.mpcc_id = 0xf; 1352 1353 return true; 1354 } 1355