1 /* 2 * Copyright 2012-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn20_hubp.h" 27 28 #include "dm_services.h" 29 #include "dce_calcs.h" 30 #include "reg_helper.h" 31 #include "basics/conversion.h" 32 33 #define DC_LOGGER_INIT(logger) 34 35 #define REG(reg)\ 36 hubp2->hubp_regs->reg 37 38 #define CTX \ 39 hubp2->base.ctx 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 44 45 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 46 struct vm_system_aperture_param *apt) 47 { 48 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 49 50 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 51 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 52 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 53 54 // The format of default addr is 48:12 of the 48 bit addr 55 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 56 57 // The format of high/low are 48:18 of the 48 bit addr 58 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 59 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 60 61 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 62 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ 63 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 64 65 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 66 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 67 68 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 69 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 70 71 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 72 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 73 74 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 75 ENABLE_L1_TLB, 1, 76 SYSTEM_ACCESS_MODE, 0x3); 77 } 78 79 void hubp2_program_deadline( 80 struct hubp *hubp, 81 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 82 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 83 { 84 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 85 86 /* DLG - Per hubp */ 87 REG_SET_2(BLANK_OFFSET_0, 0, 88 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 89 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 90 91 REG_SET(BLANK_OFFSET_1, 0, 92 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 93 94 REG_SET(DST_DIMENSIONS, 0, 95 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 96 97 REG_SET_2(DST_AFTER_SCALER, 0, 98 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 99 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 100 101 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 102 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 103 104 /* DLG - Per luma/chroma */ 105 REG_SET(VBLANK_PARAMETERS_1, 0, 106 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 107 108 if (REG(NOM_PARAMETERS_0)) 109 REG_SET(NOM_PARAMETERS_0, 0, 110 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 111 112 if (REG(NOM_PARAMETERS_1)) 113 REG_SET(NOM_PARAMETERS_1, 0, 114 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 115 116 REG_SET(NOM_PARAMETERS_4, 0, 117 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 118 119 REG_SET(NOM_PARAMETERS_5, 0, 120 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 121 122 REG_SET_2(PER_LINE_DELIVERY, 0, 123 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 124 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 125 126 REG_SET(VBLANK_PARAMETERS_2, 0, 127 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 128 129 if (REG(NOM_PARAMETERS_2)) 130 REG_SET(NOM_PARAMETERS_2, 0, 131 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 132 133 if (REG(NOM_PARAMETERS_3)) 134 REG_SET(NOM_PARAMETERS_3, 0, 135 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 136 137 REG_SET(NOM_PARAMETERS_6, 0, 138 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 139 140 REG_SET(NOM_PARAMETERS_7, 0, 141 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 142 143 /* TTU - per hubp */ 144 REG_SET_2(DCN_TTU_QOS_WM, 0, 145 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 146 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 147 148 /* TTU - per luma/chroma */ 149 /* Assumed surf0 is luma and 1 is chroma */ 150 151 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 152 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 153 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 154 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 155 156 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 157 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 158 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 159 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 160 161 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 162 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 163 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 164 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 165 166 REG_SET(FLIP_PARAMETERS_1, 0, 167 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 168 } 169 170 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 171 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 172 { 173 uint32_t value = 0; 174 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 175 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ 176 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 177 /* 178 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) 179 <= OTG_V_BLANK_END 180 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 181 else 182 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 183 */ 184 if (pipe_dest->htotal != 0) { 185 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width 186 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 187 value = 1; 188 } else 189 value = 0; 190 } 191 192 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); 193 } 194 195 static void hubp2_program_requestor(struct hubp *hubp, 196 struct _vcs_dpi_display_rq_regs_st *rq_regs) 197 { 198 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 199 200 REG_UPDATE(HUBPRET_CONTROL, 201 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 202 REG_SET_4(DCN_EXPANSION_MODE, 0, 203 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 204 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 205 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 206 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 207 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 208 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 209 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 210 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 211 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 212 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 213 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 214 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 215 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 216 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 217 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 218 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 219 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 220 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 221 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 222 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 223 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 224 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 225 } 226 227 static void hubp2_setup( 228 struct hubp *hubp, 229 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 230 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 231 struct _vcs_dpi_display_rq_regs_st *rq_regs, 232 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 233 { 234 /* otg is locked when this func is called. Register are double buffered. 235 * disable the requestors is not needed 236 */ 237 238 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 239 hubp2_program_requestor(hubp, rq_regs); 240 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 241 242 } 243 244 void hubp2_setup_interdependent( 245 struct hubp *hubp, 246 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 247 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 248 { 249 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 250 251 REG_SET_2(PREFETCH_SETTINGS, 0, 252 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 253 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 254 255 REG_SET(PREFETCH_SETTINGS_C, 0, 256 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 257 258 REG_SET_2(VBLANK_PARAMETERS_0, 0, 259 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 260 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 261 262 REG_SET_2(FLIP_PARAMETERS_0, 0, 263 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, 264 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); 265 266 REG_SET(VBLANK_PARAMETERS_3, 0, 267 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 268 269 REG_SET(VBLANK_PARAMETERS_4, 0, 270 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 271 272 REG_SET(FLIP_PARAMETERS_2, 0, 273 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); 274 275 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 276 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 277 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 278 279 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 280 REFCYC_PER_REQ_DELIVERY_PRE, 281 ttu_attr->refcyc_per_req_delivery_pre_l); 282 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 283 REFCYC_PER_REQ_DELIVERY_PRE, 284 ttu_attr->refcyc_per_req_delivery_pre_c); 285 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 286 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 287 REG_SET(DCN_CUR1_TTU_CNTL1, 0, 288 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); 289 290 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 291 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 292 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 293 } 294 295 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: 296 * NUM_BANKS 297 * NUM_SE 298 * NUM_RB_PER_SE 299 * RB_ALIGNED 300 * Other things can be defaulted, since they never change: 301 * PIPE_ALIGNED = 0 302 * META_LINEAR = 0 303 * In GFX10, only these apply: 304 * PIPE_INTERLEAVE 305 * NUM_PIPES 306 * MAX_COMPRESSED_FRAGS 307 * SW_MODE 308 */ 309 static void hubp2_program_tiling( 310 struct dcn20_hubp *hubp2, 311 const union dc_tiling_info *info, 312 const enum surface_pixel_format pixel_format) 313 { 314 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 315 NUM_PIPES, log_2(info->gfx9.num_pipes), 316 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 317 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 318 319 REG_UPDATE_4(DCSURF_TILING_CONFIG, 320 SW_MODE, info->gfx9.swizzle, 321 META_LINEAR, 0, 322 RB_ALIGNED, 0, 323 PIPE_ALIGNED, 0); 324 } 325 326 void hubp2_program_size( 327 struct hubp *hubp, 328 enum surface_pixel_format format, 329 const struct plane_size *plane_size, 330 struct dc_plane_dcc_param *dcc) 331 { 332 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 333 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 334 bool use_pitch_c = false; 335 336 /* Program data and meta surface pitch (calculation from addrlib) 337 * 444 or 420 luma 338 */ 339 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 340 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; 341 use_pitch_c = use_pitch_c 342 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 343 if (use_pitch_c) { 344 ASSERT(plane_size->chroma_pitch != 0); 345 /* Chroma pitch zero can cause system hang! */ 346 347 pitch = plane_size->surface_pitch - 1; 348 meta_pitch = dcc->meta_pitch - 1; 349 pitch_c = plane_size->chroma_pitch - 1; 350 meta_pitch_c = dcc->meta_pitch_c - 1; 351 } else { 352 pitch = plane_size->surface_pitch - 1; 353 meta_pitch = dcc->meta_pitch - 1; 354 pitch_c = 0; 355 meta_pitch_c = 0; 356 } 357 358 if (!dcc->enable) { 359 meta_pitch = 0; 360 meta_pitch_c = 0; 361 } 362 363 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 364 PITCH, pitch, META_PITCH, meta_pitch); 365 366 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; 367 use_pitch_c = use_pitch_c 368 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA); 369 if (use_pitch_c) 370 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 371 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 372 } 373 374 void hubp2_program_rotation( 375 struct hubp *hubp, 376 enum dc_rotation_angle rotation, 377 bool horizontal_mirror) 378 { 379 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 380 uint32_t mirror; 381 382 383 if (horizontal_mirror) 384 mirror = 1; 385 else 386 mirror = 0; 387 388 /* Program rotation angle and horz mirror - no mirror */ 389 if (rotation == ROTATION_ANGLE_0) 390 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 391 ROTATION_ANGLE, 0, 392 H_MIRROR_EN, mirror); 393 else if (rotation == ROTATION_ANGLE_90) 394 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 395 ROTATION_ANGLE, 1, 396 H_MIRROR_EN, mirror); 397 else if (rotation == ROTATION_ANGLE_180) 398 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 399 ROTATION_ANGLE, 2, 400 H_MIRROR_EN, mirror); 401 else if (rotation == ROTATION_ANGLE_270) 402 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 403 ROTATION_ANGLE, 3, 404 H_MIRROR_EN, mirror); 405 } 406 407 void hubp2_dcc_control(struct hubp *hubp, bool enable, 408 enum hubp_ind_block_size independent_64b_blks) 409 { 410 uint32_t dcc_en = enable ? 1 : 0; 411 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 412 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 413 414 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 415 PRIMARY_SURFACE_DCC_EN, dcc_en, 416 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 417 SECONDARY_SURFACE_DCC_EN, dcc_en, 418 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 419 } 420 421 void hubp2_program_pixel_format( 422 struct hubp *hubp, 423 enum surface_pixel_format format) 424 { 425 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 426 uint32_t red_bar = 3; 427 uint32_t blue_bar = 2; 428 429 /* swap for ABGR format */ 430 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 431 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 432 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 433 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 434 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 435 red_bar = 2; 436 blue_bar = 3; 437 } 438 439 REG_UPDATE_2(HUBPRET_CONTROL, 440 CROSSBAR_SRC_CB_B, blue_bar, 441 CROSSBAR_SRC_CR_R, red_bar); 442 443 /* Mapping is same as ipp programming (cnvc) */ 444 445 switch (format) { 446 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 447 REG_UPDATE(DCSURF_SURFACE_CONFIG, 448 SURFACE_PIXEL_FORMAT, 1); 449 break; 450 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 451 REG_UPDATE(DCSURF_SURFACE_CONFIG, 452 SURFACE_PIXEL_FORMAT, 3); 453 break; 454 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 455 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 456 REG_UPDATE(DCSURF_SURFACE_CONFIG, 457 SURFACE_PIXEL_FORMAT, 8); 458 break; 459 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 460 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 461 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 462 REG_UPDATE(DCSURF_SURFACE_CONFIG, 463 SURFACE_PIXEL_FORMAT, 10); 464 break; 465 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 466 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /*we use crossbar already*/ 467 REG_UPDATE(DCSURF_SURFACE_CONFIG, 468 SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ 469 break; 470 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 471 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 472 REG_UPDATE(DCSURF_SURFACE_CONFIG, 473 SURFACE_PIXEL_FORMAT, 24); 474 break; 475 476 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 477 REG_UPDATE(DCSURF_SURFACE_CONFIG, 478 SURFACE_PIXEL_FORMAT, 65); 479 break; 480 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 481 REG_UPDATE(DCSURF_SURFACE_CONFIG, 482 SURFACE_PIXEL_FORMAT, 64); 483 break; 484 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 485 REG_UPDATE(DCSURF_SURFACE_CONFIG, 486 SURFACE_PIXEL_FORMAT, 67); 487 break; 488 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 489 REG_UPDATE(DCSURF_SURFACE_CONFIG, 490 SURFACE_PIXEL_FORMAT, 66); 491 break; 492 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 493 REG_UPDATE(DCSURF_SURFACE_CONFIG, 494 SURFACE_PIXEL_FORMAT, 12); 495 break; 496 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 497 REG_UPDATE(DCSURF_SURFACE_CONFIG, 498 SURFACE_PIXEL_FORMAT, 112); 499 break; 500 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 501 REG_UPDATE(DCSURF_SURFACE_CONFIG, 502 SURFACE_PIXEL_FORMAT, 113); 503 break; 504 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 505 REG_UPDATE(DCSURF_SURFACE_CONFIG, 506 SURFACE_PIXEL_FORMAT, 114); 507 break; 508 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 509 REG_UPDATE(DCSURF_SURFACE_CONFIG, 510 SURFACE_PIXEL_FORMAT, 118); 511 break; 512 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 513 REG_UPDATE(DCSURF_SURFACE_CONFIG, 514 SURFACE_PIXEL_FORMAT, 119); 515 break; 516 case SURFACE_PIXEL_FORMAT_GRPH_RGBE: 517 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 518 SURFACE_PIXEL_FORMAT, 116, 519 ALPHA_PLANE_EN, 0); 520 break; 521 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: 522 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 523 SURFACE_PIXEL_FORMAT, 116, 524 ALPHA_PLANE_EN, 1); 525 break; 526 default: 527 BREAK_TO_DEBUGGER(); 528 break; 529 } 530 531 /* don't see the need of program the xbar in DCN 1.0 */ 532 } 533 534 void hubp2_program_surface_config( 535 struct hubp *hubp, 536 enum surface_pixel_format format, 537 union dc_tiling_info *tiling_info, 538 struct plane_size *plane_size, 539 enum dc_rotation_angle rotation, 540 struct dc_plane_dcc_param *dcc, 541 bool horizontal_mirror, 542 unsigned int compat_level) 543 { 544 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 545 546 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 547 hubp2_program_tiling(hubp2, tiling_info, format); 548 hubp2_program_size(hubp, format, plane_size, dcc); 549 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 550 hubp2_program_pixel_format(hubp, format); 551 } 552 553 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 554 unsigned int cursor_width, 555 enum dc_cursor_color_format cursor_mode) 556 { 557 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 558 559 if (cursor_mode == CURSOR_MODE_MONO) 560 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 561 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || 562 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 563 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 564 if (cursor_width >= 1 && cursor_width <= 32) 565 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 566 else if (cursor_width >= 33 && cursor_width <= 64) 567 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 568 else if (cursor_width >= 65 && cursor_width <= 128) 569 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 570 else if (cursor_width >= 129 && cursor_width <= 256) 571 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 572 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || 573 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { 574 if (cursor_width >= 1 && cursor_width <= 16) 575 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 576 else if (cursor_width >= 17 && cursor_width <= 32) 577 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 578 else if (cursor_width >= 33 && cursor_width <= 64) 579 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 580 else if (cursor_width >= 65 && cursor_width <= 128) 581 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 582 else if (cursor_width >= 129 && cursor_width <= 256) 583 line_per_chunk = CURSOR_LINE_PER_CHUNK_1; 584 } 585 586 return line_per_chunk; 587 } 588 589 void hubp2_cursor_set_attributes( 590 struct hubp *hubp, 591 const struct dc_cursor_attributes *attr) 592 { 593 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 594 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 595 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 596 attr->width, attr->color_format); 597 598 hubp->curs_attr = *attr; 599 600 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 601 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 602 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 603 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 604 605 REG_UPDATE_2(CURSOR_SIZE, 606 CURSOR_WIDTH, attr->width, 607 CURSOR_HEIGHT, attr->height); 608 609 REG_UPDATE_4(CURSOR_CONTROL, 610 CURSOR_MODE, attr->color_format, 611 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 612 CURSOR_PITCH, hw_pitch, 613 CURSOR_LINES_PER_CHUNK, lpc); 614 615 REG_SET_2(CURSOR_SETTINGS, 0, 616 /* no shift of the cursor HDL schedule */ 617 CURSOR0_DST_Y_OFFSET, 0, 618 /* used to shift the cursor chunk request deadline */ 619 CURSOR0_CHUNK_HDL_ADJUST, 3); 620 621 hubp->att.SURFACE_ADDR_HIGH = attr->address.high_part; 622 hubp->att.SURFACE_ADDR = attr->address.low_part; 623 hubp->att.size.bits.width = attr->width; 624 hubp->att.size.bits.height = attr->height; 625 hubp->att.cur_ctl.bits.mode = attr->color_format; 626 hubp->att.cur_ctl.bits.pitch = hw_pitch; 627 hubp->att.cur_ctl.bits.line_per_chunk = lpc; 628 hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION; 629 hubp->att.settings.bits.dst_y_offset = 0; 630 hubp->att.settings.bits.chunk_hdl_adjust = 3; 631 } 632 633 void hubp2_dmdata_set_attributes( 634 struct hubp *hubp, 635 const struct dc_dmdata_attributes *attr) 636 { 637 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 638 639 if (attr->dmdata_mode == DMDATA_HW_MODE) { 640 /* set to HW mode */ 641 REG_UPDATE(DMDATA_CNTL, 642 DMDATA_MODE, 1); 643 644 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ 645 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); 646 647 /* toggle DMDATA_UPDATED and set repeat and size */ 648 REG_UPDATE(DMDATA_CNTL, 649 DMDATA_UPDATED, 0); 650 REG_UPDATE_3(DMDATA_CNTL, 651 DMDATA_UPDATED, 1, 652 DMDATA_REPEAT, attr->dmdata_repeat, 653 DMDATA_SIZE, attr->dmdata_size); 654 655 /* set DMDATA address */ 656 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); 657 REG_UPDATE(DMDATA_ADDRESS_HIGH, 658 DMDATA_ADDRESS_HIGH, attr->address.high_part); 659 660 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); 661 662 } else { 663 /* set to SW mode before loading data */ 664 REG_SET(DMDATA_CNTL, 0, 665 DMDATA_MODE, 0); 666 /* toggle DMDATA_SW_UPDATED to start loading sequence */ 667 REG_UPDATE(DMDATA_SW_CNTL, 668 DMDATA_SW_UPDATED, 0); 669 REG_UPDATE_3(DMDATA_SW_CNTL, 670 DMDATA_SW_UPDATED, 1, 671 DMDATA_SW_REPEAT, attr->dmdata_repeat, 672 DMDATA_SW_SIZE, attr->dmdata_size); 673 /* load data into hubp dmdata buffer */ 674 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); 675 } 676 677 /* Note that DL_DELTA must be programmed if we want to use TTU mode */ 678 REG_SET_3(DMDATA_QOS_CNTL, 0, 679 DMDATA_QOS_MODE, attr->dmdata_qos_mode, 680 DMDATA_QOS_LEVEL, attr->dmdata_qos_level, 681 DMDATA_DL_DELTA, attr->dmdata_dl_delta); 682 } 683 684 void hubp2_dmdata_load( 685 struct hubp *hubp, 686 uint32_t dmdata_sw_size, 687 const uint32_t *dmdata_sw_data) 688 { 689 int i; 690 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 691 692 /* load dmdata into HUBP buffer in SW mode */ 693 for (i = 0; i < dmdata_sw_size / 4; i++) 694 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); 695 } 696 697 bool hubp2_dmdata_status_done(struct hubp *hubp) 698 { 699 uint32_t status; 700 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 701 702 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); 703 return (status == 1); 704 } 705 706 bool hubp2_program_surface_flip_and_addr( 707 struct hubp *hubp, 708 const struct dc_plane_address *address, 709 bool flip_immediate) 710 { 711 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 712 713 //program flip type 714 REG_UPDATE(DCSURF_FLIP_CONTROL, 715 SURFACE_FLIP_TYPE, flip_immediate); 716 717 // Program VMID reg 718 REG_UPDATE(VMID_SETTINGS_0, 719 VMID, address->vmid); 720 721 722 /* HW automatically latch rest of address register on write to 723 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 724 * 725 * program high first and then the low addr, order matters! 726 */ 727 switch (address->type) { 728 case PLN_ADDR_TYPE_GRAPHICS: 729 /* DCN1.0 does not support const color 730 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 731 * base on address->grph.dcc_const_color 732 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 733 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 734 */ 735 736 if (address->grph.addr.quad_part == 0) 737 break; 738 739 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 740 PRIMARY_SURFACE_TMZ, address->tmz_surface, 741 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 742 743 if (address->grph.meta_addr.quad_part != 0) { 744 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 745 PRIMARY_META_SURFACE_ADDRESS_HIGH, 746 address->grph.meta_addr.high_part); 747 748 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 749 PRIMARY_META_SURFACE_ADDRESS, 750 address->grph.meta_addr.low_part); 751 } 752 753 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 754 PRIMARY_SURFACE_ADDRESS_HIGH, 755 address->grph.addr.high_part); 756 757 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 758 PRIMARY_SURFACE_ADDRESS, 759 address->grph.addr.low_part); 760 break; 761 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 762 if (address->video_progressive.luma_addr.quad_part == 0 763 || address->video_progressive.chroma_addr.quad_part == 0) 764 break; 765 766 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 767 PRIMARY_SURFACE_TMZ, address->tmz_surface, 768 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 769 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 770 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 771 772 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 773 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 774 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 775 address->video_progressive.chroma_meta_addr.high_part); 776 777 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 778 PRIMARY_META_SURFACE_ADDRESS_C, 779 address->video_progressive.chroma_meta_addr.low_part); 780 781 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 782 PRIMARY_META_SURFACE_ADDRESS_HIGH, 783 address->video_progressive.luma_meta_addr.high_part); 784 785 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 786 PRIMARY_META_SURFACE_ADDRESS, 787 address->video_progressive.luma_meta_addr.low_part); 788 } 789 790 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 791 PRIMARY_SURFACE_ADDRESS_HIGH_C, 792 address->video_progressive.chroma_addr.high_part); 793 794 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 795 PRIMARY_SURFACE_ADDRESS_C, 796 address->video_progressive.chroma_addr.low_part); 797 798 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 799 PRIMARY_SURFACE_ADDRESS_HIGH, 800 address->video_progressive.luma_addr.high_part); 801 802 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 803 PRIMARY_SURFACE_ADDRESS, 804 address->video_progressive.luma_addr.low_part); 805 break; 806 case PLN_ADDR_TYPE_GRPH_STEREO: 807 if (address->grph_stereo.left_addr.quad_part == 0) 808 break; 809 if (address->grph_stereo.right_addr.quad_part == 0) 810 break; 811 812 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 813 PRIMARY_SURFACE_TMZ, address->tmz_surface, 814 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 815 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 816 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 817 SECONDARY_SURFACE_TMZ, address->tmz_surface, 818 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 819 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 820 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 821 822 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 823 824 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 825 SECONDARY_META_SURFACE_ADDRESS_HIGH, 826 address->grph_stereo.right_meta_addr.high_part); 827 828 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 829 SECONDARY_META_SURFACE_ADDRESS, 830 address->grph_stereo.right_meta_addr.low_part); 831 } 832 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 833 834 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 835 PRIMARY_META_SURFACE_ADDRESS_HIGH, 836 address->grph_stereo.left_meta_addr.high_part); 837 838 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 839 PRIMARY_META_SURFACE_ADDRESS, 840 address->grph_stereo.left_meta_addr.low_part); 841 } 842 843 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 844 SECONDARY_SURFACE_ADDRESS_HIGH, 845 address->grph_stereo.right_addr.high_part); 846 847 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 848 SECONDARY_SURFACE_ADDRESS, 849 address->grph_stereo.right_addr.low_part); 850 851 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 852 PRIMARY_SURFACE_ADDRESS_HIGH, 853 address->grph_stereo.left_addr.high_part); 854 855 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 856 PRIMARY_SURFACE_ADDRESS, 857 address->grph_stereo.left_addr.low_part); 858 break; 859 default: 860 BREAK_TO_DEBUGGER(); 861 break; 862 } 863 864 hubp->request_address = *address; 865 866 return true; 867 } 868 869 void hubp2_enable_triplebuffer( 870 struct hubp *hubp, 871 bool enable) 872 { 873 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 874 uint32_t triple_buffer_en = 0; 875 bool tri_buffer_en; 876 877 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 878 tri_buffer_en = (triple_buffer_en == 1); 879 if (tri_buffer_en != enable) { 880 REG_UPDATE(DCSURF_FLIP_CONTROL2, 881 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); 882 } 883 } 884 885 bool hubp2_is_triplebuffer_enabled( 886 struct hubp *hubp) 887 { 888 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 889 uint32_t triple_buffer_en = 0; 890 891 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 892 893 return (bool)triple_buffer_en; 894 } 895 896 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) 897 { 898 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 899 900 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); 901 } 902 903 bool hubp2_is_flip_pending(struct hubp *hubp) 904 { 905 uint32_t flip_pending = 0; 906 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 907 struct dc_plane_address earliest_inuse_address; 908 909 if (hubp && hubp->power_gated) 910 return false; 911 912 REG_GET(DCSURF_FLIP_CONTROL, 913 SURFACE_FLIP_PENDING, &flip_pending); 914 915 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 916 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 917 918 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 919 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 920 921 if (flip_pending) 922 return true; 923 924 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 925 return true; 926 927 return false; 928 } 929 930 void hubp2_set_blank(struct hubp *hubp, bool blank) 931 { 932 hubp2_set_blank_regs(hubp, blank); 933 934 if (blank) { 935 hubp->mpcc_id = 0xf; 936 hubp->opp_id = OPP_ID_INVALID; 937 } 938 } 939 940 void hubp2_set_blank_regs(struct hubp *hubp, bool blank) 941 { 942 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 943 uint32_t blank_en = blank ? 1 : 0; 944 945 if (blank) { 946 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 947 948 if (reg_val) { 949 /* init sequence workaround: in case HUBP is 950 * power gated, this wait would timeout. 951 * 952 * we just wrote reg_val to non-0, if it stay 0 953 * it means HUBP is gated 954 */ 955 REG_WAIT(DCHUBP_CNTL, 956 HUBP_NO_OUTSTANDING_REQ, 1, 957 1, 100000); 958 } 959 } 960 961 REG_UPDATE_2(DCHUBP_CNTL, 962 HUBP_BLANK_EN, blank_en, 963 HUBP_TTU_DISABLE, 0); 964 } 965 966 void hubp2_cursor_set_position( 967 struct hubp *hubp, 968 const struct dc_cursor_position *pos, 969 const struct dc_cursor_mi_param *param) 970 { 971 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 972 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 973 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 974 int x_hotspot = pos->x_hotspot; 975 int y_hotspot = pos->y_hotspot; 976 int cursor_height = (int)hubp->curs_attr.height; 977 int cursor_width = (int)hubp->curs_attr.width; 978 uint32_t dst_x_offset; 979 uint32_t cur_en = pos->enable ? 1 : 0; 980 981 hubp->curs_pos = *pos; 982 983 /* 984 * Guard aganst cursor_set_position() from being called with invalid 985 * attributes 986 * 987 * TODO: Look at combining cursor_set_position() and 988 * cursor_set_attributes() into cursor_update() 989 */ 990 if (hubp->curs_attr.address.quad_part == 0) 991 return; 992 993 // Rotated cursor width/height and hotspots tweaks for offset calculation 994 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 995 swap(cursor_height, cursor_width); 996 if (param->rotation == ROTATION_ANGLE_90) { 997 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; 998 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; 999 } 1000 } else if (param->rotation == ROTATION_ANGLE_180) { 1001 if (!param->mirror) 1002 src_x_offset = pos->x - param->viewport.x; 1003 1004 src_y_offset = pos->y - param->viewport.y; 1005 } 1006 1007 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 1008 dst_x_offset *= param->ref_clk_khz; 1009 dst_x_offset /= param->pixel_clk_khz; 1010 1011 ASSERT(param->h_scale_ratio.value); 1012 1013 if (param->h_scale_ratio.value) 1014 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 1015 dc_fixpt_from_int(dst_x_offset), 1016 param->h_scale_ratio)); 1017 1018 if (src_x_offset >= (int)param->viewport.width) 1019 cur_en = 0; /* not visible beyond right edge*/ 1020 1021 if (src_x_offset + cursor_width <= 0) 1022 cur_en = 0; /* not visible beyond left edge*/ 1023 1024 if (src_y_offset >= (int)param->viewport.height) 1025 cur_en = 0; /* not visible beyond bottom edge*/ 1026 1027 if (src_y_offset + cursor_height <= 0) 1028 cur_en = 0; /* not visible beyond top edge*/ 1029 1030 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1031 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1032 1033 REG_UPDATE(CURSOR_CONTROL, 1034 CURSOR_ENABLE, cur_en); 1035 1036 REG_SET_2(CURSOR_POSITION, 0, 1037 CURSOR_X_POSITION, pos->x, 1038 CURSOR_Y_POSITION, pos->y); 1039 1040 REG_SET_2(CURSOR_HOT_SPOT, 0, 1041 CURSOR_HOT_SPOT_X, x_hotspot, 1042 CURSOR_HOT_SPOT_Y, y_hotspot); 1043 1044 REG_SET(CURSOR_DST_OFFSET, 0, 1045 CURSOR_DST_X_OFFSET, dst_x_offset); 1046 /* TODO Handle surface pixel formats other than 4:4:4 */ 1047 /* Cursor Position Register Config */ 1048 hubp->pos.cur_ctl.bits.cur_enable = cur_en; 1049 hubp->pos.position.bits.x_pos = pos->x; 1050 hubp->pos.position.bits.y_pos = pos->y; 1051 hubp->pos.hot_spot.bits.x_hot = x_hotspot; 1052 hubp->pos.hot_spot.bits.y_hot = y_hotspot; 1053 hubp->pos.dst_offset.bits.dst_x_offset = dst_x_offset; 1054 /* Cursor Rectangle Cache 1055 * Cursor bitmaps have different hotspot values 1056 * There's a possibility that the above logic returns a negative value, 1057 * so we clamp them to 0 1058 */ 1059 if (src_x_offset < 0) 1060 src_x_offset = 0; 1061 if (src_y_offset < 0) 1062 src_y_offset = 0; 1063 /* Save necessary cursor info x, y position. w, h is saved in attribute func. */ 1064 hubp->cur_rect.x = src_x_offset + param->viewport.x; 1065 hubp->cur_rect.y = src_y_offset + param->viewport.y; 1066 } 1067 1068 void hubp2_clk_cntl(struct hubp *hubp, bool enable) 1069 { 1070 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1071 uint32_t clk_enable = enable ? 1 : 0; 1072 1073 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1074 } 1075 1076 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1077 { 1078 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1079 1080 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1081 } 1082 1083 void hubp2_clear_underflow(struct hubp *hubp) 1084 { 1085 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1086 1087 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 1088 } 1089 1090 void hubp2_read_state_common(struct hubp *hubp) 1091 { 1092 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1093 struct dcn_hubp_state *s = &hubp2->state; 1094 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 1095 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 1096 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1097 1098 /* Requester */ 1099 REG_GET(HUBPRET_CONTROL, 1100 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 1101 REG_GET_4(DCN_EXPANSION_MODE, 1102 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 1103 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 1104 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1105 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1106 1107 REG_GET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 1108 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, &rq_regs->aperture_high_addr); 1109 1110 REG_GET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 1111 MC_VM_SYSTEM_APERTURE_LOW_ADDR, &rq_regs->aperture_low_addr); 1112 1113 /* DLG - Per hubp */ 1114 REG_GET_2(BLANK_OFFSET_0, 1115 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 1116 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 1117 1118 REG_GET(BLANK_OFFSET_1, 1119 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 1120 1121 REG_GET(DST_DIMENSIONS, 1122 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 1123 1124 REG_GET_2(DST_AFTER_SCALER, 1125 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 1126 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 1127 1128 if (REG(PREFETCH_SETTINS)) 1129 REG_GET_2(PREFETCH_SETTINS, 1130 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1131 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1132 else 1133 REG_GET_2(PREFETCH_SETTINGS, 1134 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1135 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1136 1137 REG_GET_2(VBLANK_PARAMETERS_0, 1138 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 1139 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 1140 1141 REG_GET(REF_FREQ_TO_PIX_FREQ, 1142 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 1143 1144 /* DLG - Per luma/chroma */ 1145 REG_GET(VBLANK_PARAMETERS_1, 1146 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 1147 1148 REG_GET(VBLANK_PARAMETERS_3, 1149 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 1150 1151 if (REG(NOM_PARAMETERS_0)) 1152 REG_GET(NOM_PARAMETERS_0, 1153 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 1154 1155 if (REG(NOM_PARAMETERS_1)) 1156 REG_GET(NOM_PARAMETERS_1, 1157 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 1158 1159 REG_GET(NOM_PARAMETERS_4, 1160 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 1161 1162 REG_GET(NOM_PARAMETERS_5, 1163 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 1164 1165 REG_GET_2(PER_LINE_DELIVERY_PRE, 1166 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1167 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 1168 1169 REG_GET_2(PER_LINE_DELIVERY, 1170 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 1171 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 1172 1173 if (REG(PREFETCH_SETTINS_C)) 1174 REG_GET(PREFETCH_SETTINS_C, 1175 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1176 else 1177 REG_GET(PREFETCH_SETTINGS_C, 1178 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1179 1180 REG_GET(VBLANK_PARAMETERS_2, 1181 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 1182 1183 REG_GET(VBLANK_PARAMETERS_4, 1184 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 1185 1186 if (REG(NOM_PARAMETERS_2)) 1187 REG_GET(NOM_PARAMETERS_2, 1188 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1189 1190 if (REG(NOM_PARAMETERS_3)) 1191 REG_GET(NOM_PARAMETERS_3, 1192 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1193 1194 REG_GET(NOM_PARAMETERS_6, 1195 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1196 1197 REG_GET(NOM_PARAMETERS_7, 1198 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1199 1200 /* TTU - per hubp */ 1201 REG_GET_2(DCN_TTU_QOS_WM, 1202 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1203 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1204 1205 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1206 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1207 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1208 1209 /* TTU - per luma/chroma */ 1210 /* Assumed surf0 is luma and 1 is chroma */ 1211 1212 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1213 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1214 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1215 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1216 1217 REG_GET(DCN_SURF0_TTU_CNTL1, 1218 REFCYC_PER_REQ_DELIVERY_PRE, 1219 &ttu_attr->refcyc_per_req_delivery_pre_l); 1220 1221 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1222 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1223 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1224 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1225 1226 REG_GET(DCN_SURF1_TTU_CNTL1, 1227 REFCYC_PER_REQ_DELIVERY_PRE, 1228 &ttu_attr->refcyc_per_req_delivery_pre_c); 1229 1230 /* Rest of hubp */ 1231 REG_GET(DCSURF_SURFACE_CONFIG, 1232 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1233 1234 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1235 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1236 1237 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1238 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1239 1240 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1241 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1242 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1243 1244 REG_GET_2(DCSURF_SURFACE_CONFIG, 1245 ROTATION_ANGLE, &s->rotation_angle, 1246 H_MIRROR_EN, &s->h_mirror_en); 1247 1248 REG_GET(DCSURF_TILING_CONFIG, 1249 SW_MODE, &s->sw_mode); 1250 1251 REG_GET(DCSURF_SURFACE_CONTROL, 1252 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1253 1254 REG_GET_3(DCHUBP_CNTL, 1255 HUBP_BLANK_EN, &s->blank_en, 1256 HUBP_TTU_DISABLE, &s->ttu_disable, 1257 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1258 1259 REG_GET(HUBP_CLK_CNTL, 1260 HUBP_CLOCK_ENABLE, &s->clock_en); 1261 1262 REG_GET(DCN_GLOBAL_TTU_CNTL, 1263 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1264 1265 REG_GET_2(DCN_TTU_QOS_WM, 1266 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1267 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1268 1269 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS, 1270 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_lo); 1271 1272 REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 1273 PRIMARY_SURFACE_ADDRESS, &s->primary_surface_addr_hi); 1274 1275 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 1276 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_lo); 1277 1278 REG_GET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 1279 PRIMARY_META_SURFACE_ADDRESS, &s->primary_meta_addr_hi); 1280 } 1281 1282 void hubp2_read_state(struct hubp *hubp) 1283 { 1284 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1285 struct dcn_hubp_state *s = &hubp2->state; 1286 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1287 1288 hubp2_read_state_common(hubp); 1289 1290 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1291 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1292 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1293 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1294 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1295 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1296 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1297 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1298 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1299 1300 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1301 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1302 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1303 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1304 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1305 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1306 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1307 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1308 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1309 1310 } 1311 1312 static void hubp2_validate_dml_output(struct hubp *hubp, 1313 struct dc_context *ctx, 1314 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs, 1315 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr, 1316 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr) 1317 { 1318 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1319 struct _vcs_dpi_display_rq_regs_st rq_regs = {0}; 1320 struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0}; 1321 struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0}; 1322 DC_LOGGER_INIT(ctx->logger); 1323 DC_LOG_DEBUG("DML Validation | Running Validation"); 1324 1325 /* Requestor Regs */ 1326 REG_GET(HUBPRET_CONTROL, 1327 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address); 1328 REG_GET_4(DCN_EXPANSION_MODE, 1329 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode, 1330 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode, 1331 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode, 1332 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode); 1333 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1334 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, 1335 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size, 1336 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size, 1337 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size, 1338 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size, 1339 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size, 1340 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, 1341 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear); 1342 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1343 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size, 1344 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size, 1345 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size, 1346 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size, 1347 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size, 1348 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size, 1349 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height, 1350 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear); 1351 1352 if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address) 1353 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1354 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address); 1355 if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode) 1356 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1357 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode); 1358 if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode) 1359 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1360 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode); 1361 if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode) 1362 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u Actual: %u\n", 1363 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode); 1364 if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode) 1365 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u Actual: %u\n", 1366 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode); 1367 1368 if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size) 1369 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u Actual: %u\n", 1370 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size); 1371 if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size) 1372 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u Actual: %u\n", 1373 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size); 1374 if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size) 1375 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1376 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size); 1377 if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size) 1378 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u Actual: %u\n", 1379 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size); 1380 if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size) 1381 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1382 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size); 1383 if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size) 1384 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u Actual: %u\n", 1385 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size); 1386 if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height) 1387 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u Actual: %u\n", 1388 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height); 1389 if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear) 1390 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u Actual: %u\n", 1391 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear); 1392 1393 if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size) 1394 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1395 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size); 1396 if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size) 1397 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1398 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size); 1399 if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size) 1400 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1401 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size); 1402 if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size) 1403 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u Actual: %u\n", 1404 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size); 1405 if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size) 1406 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1407 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size); 1408 if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size) 1409 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u Actual: %u\n", 1410 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size); 1411 if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height) 1412 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u Actual: %u\n", 1413 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height); 1414 if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear) 1415 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u Actual: %u\n", 1416 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear); 1417 1418 /* DLG - Per hubp */ 1419 REG_GET_2(BLANK_OFFSET_0, 1420 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end, 1421 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end); 1422 REG_GET(BLANK_OFFSET_1, 1423 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start); 1424 REG_GET(DST_DIMENSIONS, 1425 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal); 1426 REG_GET_2(DST_AFTER_SCALER, 1427 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler, 1428 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler); 1429 REG_GET(REF_FREQ_TO_PIX_FREQ, 1430 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq); 1431 1432 if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end) 1433 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u Actual: %u\n", 1434 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end); 1435 if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end) 1436 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u Actual: %u\n", 1437 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end); 1438 if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start) 1439 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u Actual: %u\n", 1440 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start); 1441 if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal) 1442 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u Actual: %u\n", 1443 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal); 1444 if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler) 1445 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u Actual: %u\n", 1446 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler); 1447 if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler) 1448 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u Actual: %u\n", 1449 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler); 1450 if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq) 1451 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u Actual: %u\n", 1452 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq); 1453 1454 /* DLG - Per luma/chroma */ 1455 REG_GET(VBLANK_PARAMETERS_1, 1456 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l); 1457 if (REG(NOM_PARAMETERS_0)) 1458 REG_GET(NOM_PARAMETERS_0, 1459 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l); 1460 if (REG(NOM_PARAMETERS_1)) 1461 REG_GET(NOM_PARAMETERS_1, 1462 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l); 1463 REG_GET(NOM_PARAMETERS_4, 1464 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l); 1465 REG_GET(NOM_PARAMETERS_5, 1466 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l); 1467 REG_GET_2(PER_LINE_DELIVERY, 1468 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l, 1469 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c); 1470 REG_GET_2(PER_LINE_DELIVERY_PRE, 1471 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l, 1472 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c); 1473 REG_GET(VBLANK_PARAMETERS_2, 1474 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c); 1475 if (REG(NOM_PARAMETERS_2)) 1476 REG_GET(NOM_PARAMETERS_2, 1477 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c); 1478 if (REG(NOM_PARAMETERS_3)) 1479 REG_GET(NOM_PARAMETERS_3, 1480 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c); 1481 REG_GET(NOM_PARAMETERS_6, 1482 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c); 1483 REG_GET(NOM_PARAMETERS_7, 1484 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c); 1485 REG_GET(VBLANK_PARAMETERS_3, 1486 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); 1487 REG_GET(VBLANK_PARAMETERS_4, 1488 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c); 1489 1490 if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l) 1491 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u Actual: %u\n", 1492 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l); 1493 if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l) 1494 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u Actual: %u\n", 1495 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l); 1496 if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l) 1497 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u Actual: %u\n", 1498 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l); 1499 if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l) 1500 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u Actual: %u\n", 1501 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l); 1502 if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l) 1503 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u Actual: %u\n", 1504 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l); 1505 if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l) 1506 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u Actual: %u\n", 1507 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l); 1508 if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c) 1509 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u Actual: %u\n", 1510 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c); 1511 if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c) 1512 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u Actual: %u\n", 1513 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c); 1514 if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c) 1515 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u Actual: %u\n", 1516 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c); 1517 if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c) 1518 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u Actual: %u\n", 1519 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c); 1520 if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c) 1521 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u Actual: %u\n", 1522 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c); 1523 if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c) 1524 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u Actual: %u\n", 1525 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c); 1526 if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l) 1527 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u Actual: %u\n", 1528 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l); 1529 if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c) 1530 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u Actual: %u\n", 1531 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c); 1532 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) 1533 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u Actual: %u\n", 1534 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); 1535 if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c) 1536 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u Actual: %u\n", 1537 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c); 1538 1539 /* TTU - per hubp */ 1540 REG_GET_2(DCN_TTU_QOS_WM, 1541 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm, 1542 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm); 1543 1544 if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm) 1545 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u Actual: %u\n", 1546 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm); 1547 if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm) 1548 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u Actual: %u\n", 1549 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm); 1550 1551 /* TTU - per luma/chroma */ 1552 /* Assumed surf0 is luma and 1 is chroma */ 1553 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1554 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l, 1555 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l, 1556 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l); 1557 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1558 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c, 1559 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c, 1560 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c); 1561 REG_GET_3(DCN_CUR0_TTU_CNTL0, 1562 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0, 1563 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0, 1564 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0); 1565 REG_GET(FLIP_PARAMETERS_1, 1566 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l); 1567 REG_GET(DCN_CUR0_TTU_CNTL1, 1568 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0); 1569 REG_GET(DCN_CUR1_TTU_CNTL1, 1570 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1); 1571 REG_GET(DCN_SURF0_TTU_CNTL1, 1572 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l); 1573 REG_GET(DCN_SURF1_TTU_CNTL1, 1574 REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c); 1575 1576 if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l) 1577 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1578 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l); 1579 if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l) 1580 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1581 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l); 1582 if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l) 1583 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1584 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l); 1585 if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c) 1586 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1587 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c); 1588 if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c) 1589 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1590 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c); 1591 if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c) 1592 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1593 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c); 1594 if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0) 1595 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u Actual: %u\n", 1596 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0); 1597 if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0) 1598 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u Actual: %u\n", 1599 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0); 1600 if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0) 1601 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u Actual: %u\n", 1602 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0); 1603 if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l) 1604 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u Actual: %u\n", 1605 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l); 1606 if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0) 1607 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1608 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0); 1609 if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1) 1610 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1611 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1); 1612 if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l) 1613 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1614 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l); 1615 if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c) 1616 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u Actual: %u\n", 1617 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c); 1618 } 1619 1620 static struct hubp_funcs dcn20_hubp_funcs = { 1621 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 1622 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 1623 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 1624 .hubp_program_surface_config = hubp2_program_surface_config, 1625 .hubp_is_flip_pending = hubp2_is_flip_pending, 1626 .hubp_setup = hubp2_setup, 1627 .hubp_setup_interdependent = hubp2_setup_interdependent, 1628 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, 1629 .set_blank = hubp2_set_blank, 1630 .set_blank_regs = hubp2_set_blank_regs, 1631 .dcc_control = hubp2_dcc_control, 1632 .mem_program_viewport = min_set_viewport, 1633 .set_cursor_attributes = hubp2_cursor_set_attributes, 1634 .set_cursor_position = hubp2_cursor_set_position, 1635 .hubp_clk_cntl = hubp2_clk_cntl, 1636 .hubp_vtg_sel = hubp2_vtg_sel, 1637 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 1638 .dmdata_load = hubp2_dmdata_load, 1639 .dmdata_status_done = hubp2_dmdata_status_done, 1640 .hubp_read_state = hubp2_read_state, 1641 .hubp_clear_underflow = hubp2_clear_underflow, 1642 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1643 .hubp_init = hubp1_init, 1644 .validate_dml_output = hubp2_validate_dml_output, 1645 .hubp_in_blank = hubp1_in_blank, 1646 .hubp_soft_reset = hubp1_soft_reset, 1647 .hubp_set_flip_int = hubp1_set_flip_int, 1648 }; 1649 1650 1651 bool hubp2_construct( 1652 struct dcn20_hubp *hubp2, 1653 struct dc_context *ctx, 1654 uint32_t inst, 1655 const struct dcn_hubp2_registers *hubp_regs, 1656 const struct dcn_hubp2_shift *hubp_shift, 1657 const struct dcn_hubp2_mask *hubp_mask) 1658 { 1659 hubp2->base.funcs = &dcn20_hubp_funcs; 1660 hubp2->base.ctx = ctx; 1661 hubp2->hubp_regs = hubp_regs; 1662 hubp2->hubp_shift = hubp_shift; 1663 hubp2->hubp_mask = hubp_mask; 1664 hubp2->base.inst = inst; 1665 hubp2->base.opp_id = OPP_ID_INVALID; 1666 hubp2->base.mpcc_id = 0xf; 1667 1668 return true; 1669 } 1670