1 /* 2 * Copyright 2012-17 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn20_hubp.h" 27 28 #include "dm_services.h" 29 #include "dce_calcs.h" 30 #include "reg_helper.h" 31 #include "basics/conversion.h" 32 33 #define REG(reg)\ 34 hubp2->hubp_regs->reg 35 36 #define CTX \ 37 hubp2->base.ctx 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name 42 43 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, 44 struct vm_system_aperture_param *apt) 45 { 46 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 47 48 PHYSICAL_ADDRESS_LOC mc_vm_apt_default; 49 PHYSICAL_ADDRESS_LOC mc_vm_apt_low; 50 PHYSICAL_ADDRESS_LOC mc_vm_apt_high; 51 52 // The format of default addr is 48:12 of the 48 bit addr 53 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12; 54 55 // The format of high/low are 48:18 of the 48 bit addr 56 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18; 57 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18; 58 59 REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 60 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */ 61 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); 62 63 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 64 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part); 65 66 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, 67 MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part); 68 69 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, 70 MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part); 71 72 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, 73 ENABLE_L1_TLB, 1, 74 SYSTEM_ACCESS_MODE, 0x3); 75 } 76 77 void hubp2_program_deadline( 78 struct hubp *hubp, 79 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 80 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 81 { 82 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 83 84 /* DLG - Per hubp */ 85 REG_SET_2(BLANK_OFFSET_0, 0, 86 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, 87 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); 88 89 REG_SET(BLANK_OFFSET_1, 0, 90 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); 91 92 REG_SET(DST_DIMENSIONS, 0, 93 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); 94 95 REG_SET_2(DST_AFTER_SCALER, 0, 96 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, 97 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); 98 99 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, 100 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); 101 102 /* DLG - Per luma/chroma */ 103 REG_SET(VBLANK_PARAMETERS_1, 0, 104 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); 105 106 if (REG(NOM_PARAMETERS_0)) 107 REG_SET(NOM_PARAMETERS_0, 0, 108 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); 109 110 if (REG(NOM_PARAMETERS_1)) 111 REG_SET(NOM_PARAMETERS_1, 0, 112 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); 113 114 REG_SET(NOM_PARAMETERS_4, 0, 115 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); 116 117 REG_SET(NOM_PARAMETERS_5, 0, 118 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); 119 120 REG_SET_2(PER_LINE_DELIVERY, 0, 121 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, 122 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); 123 124 REG_SET(VBLANK_PARAMETERS_2, 0, 125 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); 126 127 if (REG(NOM_PARAMETERS_2)) 128 REG_SET(NOM_PARAMETERS_2, 0, 129 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); 130 131 if (REG(NOM_PARAMETERS_3)) 132 REG_SET(NOM_PARAMETERS_3, 0, 133 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); 134 135 REG_SET(NOM_PARAMETERS_6, 0, 136 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); 137 138 REG_SET(NOM_PARAMETERS_7, 0, 139 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); 140 141 /* TTU - per hubp */ 142 REG_SET_2(DCN_TTU_QOS_WM, 0, 143 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, 144 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); 145 146 /* TTU - per luma/chroma */ 147 /* Assumed surf0 is luma and 1 is chroma */ 148 149 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, 150 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, 151 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, 152 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); 153 154 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, 155 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, 156 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, 157 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); 158 159 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, 160 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, 161 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, 162 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); 163 164 REG_SET(FLIP_PARAMETERS_1, 0, 165 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); 166 } 167 168 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, 169 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 170 { 171 uint32_t value = 0; 172 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 173 /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */ 174 REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8); 175 /* 176 if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal) 177 <= OTG_V_BLANK_END 178 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1 179 else 180 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0 181 */ 182 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width 183 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { 184 value = 1; 185 } else 186 value = 0; 187 REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value); 188 } 189 190 void hubp2_program_requestor( 191 struct hubp *hubp, 192 struct _vcs_dpi_display_rq_regs_st *rq_regs) 193 { 194 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 195 196 REG_UPDATE(HUBPRET_CONTROL, 197 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); 198 REG_SET_4(DCN_EXPANSION_MODE, 0, 199 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, 200 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, 201 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, 202 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); 203 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, 204 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, 205 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, 206 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, 207 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, 208 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, 209 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, 210 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, 211 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); 212 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0, 213 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, 214 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, 215 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, 216 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, 217 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, 218 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size, 219 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, 220 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); 221 } 222 223 static void hubp2_setup( 224 struct hubp *hubp, 225 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 226 struct _vcs_dpi_display_ttu_regs_st *ttu_attr, 227 struct _vcs_dpi_display_rq_regs_st *rq_regs, 228 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) 229 { 230 /* otg is locked when this func is called. Register are double buffered. 231 * disable the requestors is not needed 232 */ 233 234 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); 235 hubp2_program_requestor(hubp, rq_regs); 236 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); 237 238 } 239 240 void hubp2_setup_interdependent( 241 struct hubp *hubp, 242 struct _vcs_dpi_display_dlg_regs_st *dlg_attr, 243 struct _vcs_dpi_display_ttu_regs_st *ttu_attr) 244 { 245 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 246 247 REG_SET_2(PREFETCH_SETTINGS, 0, 248 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch, 249 VRATIO_PREFETCH, dlg_attr->vratio_prefetch); 250 251 REG_SET(PREFETCH_SETTINGS_C, 0, 252 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c); 253 254 REG_SET_2(VBLANK_PARAMETERS_0, 0, 255 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank, 256 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank); 257 258 REG_SET_2(FLIP_PARAMETERS_0, 0, 259 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip, 260 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip); 261 262 REG_SET(VBLANK_PARAMETERS_3, 0, 263 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); 264 265 REG_SET(VBLANK_PARAMETERS_4, 0, 266 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c); 267 268 REG_SET(FLIP_PARAMETERS_2, 0, 269 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l); 270 271 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, 272 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, 273 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c); 274 275 REG_SET(DCN_SURF0_TTU_CNTL1, 0, 276 REFCYC_PER_REQ_DELIVERY_PRE, 277 ttu_attr->refcyc_per_req_delivery_pre_l); 278 REG_SET(DCN_SURF1_TTU_CNTL1, 0, 279 REFCYC_PER_REQ_DELIVERY_PRE, 280 ttu_attr->refcyc_per_req_delivery_pre_c); 281 REG_SET(DCN_CUR0_TTU_CNTL1, 0, 282 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0); 283 REG_SET(DCN_CUR1_TTU_CNTL1, 0, 284 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1); 285 286 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, 287 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank, 288 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip); 289 } 290 291 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used: 292 * NUM_BANKS 293 * NUM_SE 294 * NUM_RB_PER_SE 295 * RB_ALIGNED 296 * Other things can be defaulted, since they never change: 297 * PIPE_ALIGNED = 0 298 * META_LINEAR = 0 299 * In GFX10, only these apply: 300 * PIPE_INTERLEAVE 301 * NUM_PIPES 302 * MAX_COMPRESSED_FRAGS 303 * SW_MODE 304 */ 305 static void hubp2_program_tiling( 306 struct dcn20_hubp *hubp2, 307 const union dc_tiling_info *info, 308 const enum surface_pixel_format pixel_format) 309 { 310 REG_UPDATE_3(DCSURF_ADDR_CONFIG, 311 NUM_PIPES, log_2(info->gfx9.num_pipes), 312 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, 313 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); 314 315 REG_UPDATE_4(DCSURF_TILING_CONFIG, 316 SW_MODE, info->gfx9.swizzle, 317 META_LINEAR, 0, 318 RB_ALIGNED, 0, 319 PIPE_ALIGNED, 0); 320 } 321 322 void hubp2_program_size( 323 struct hubp *hubp, 324 enum surface_pixel_format format, 325 const struct plane_size *plane_size, 326 struct dc_plane_dcc_param *dcc) 327 { 328 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 329 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; 330 bool use_pitch_c = false; 331 332 /* Program data and meta surface pitch (calculation from addrlib) 333 * 444 or 420 luma 334 */ 335 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 336 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END; 337 if (use_pitch_c) { 338 ASSERT(plane_size->chroma_pitch != 0); 339 /* Chroma pitch zero can cause system hang! */ 340 341 pitch = plane_size->surface_pitch - 1; 342 meta_pitch = dcc->meta_pitch - 1; 343 pitch_c = plane_size->chroma_pitch - 1; 344 meta_pitch_c = dcc->meta_pitch_c - 1; 345 } else { 346 pitch = plane_size->surface_pitch - 1; 347 meta_pitch = dcc->meta_pitch - 1; 348 pitch_c = 0; 349 meta_pitch_c = 0; 350 } 351 352 if (!dcc->enable) { 353 meta_pitch = 0; 354 meta_pitch_c = 0; 355 } 356 357 REG_UPDATE_2(DCSURF_SURFACE_PITCH, 358 PITCH, pitch, META_PITCH, meta_pitch); 359 360 use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN; 361 if (use_pitch_c) 362 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C, 363 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c); 364 } 365 366 void hubp2_program_rotation( 367 struct hubp *hubp, 368 enum dc_rotation_angle rotation, 369 bool horizontal_mirror) 370 { 371 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 372 uint32_t mirror; 373 374 375 if (horizontal_mirror) 376 mirror = 1; 377 else 378 mirror = 0; 379 380 /* Program rotation angle and horz mirror - no mirror */ 381 if (rotation == ROTATION_ANGLE_0) 382 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 383 ROTATION_ANGLE, 0, 384 H_MIRROR_EN, mirror); 385 else if (rotation == ROTATION_ANGLE_90) 386 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 387 ROTATION_ANGLE, 1, 388 H_MIRROR_EN, mirror); 389 else if (rotation == ROTATION_ANGLE_180) 390 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 391 ROTATION_ANGLE, 2, 392 H_MIRROR_EN, mirror); 393 else if (rotation == ROTATION_ANGLE_270) 394 REG_UPDATE_2(DCSURF_SURFACE_CONFIG, 395 ROTATION_ANGLE, 3, 396 H_MIRROR_EN, mirror); 397 } 398 399 void hubp2_dcc_control(struct hubp *hubp, bool enable, 400 enum hubp_ind_block_size independent_64b_blks) 401 { 402 uint32_t dcc_en = enable ? 1 : 0; 403 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0; 404 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 405 406 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 407 PRIMARY_SURFACE_DCC_EN, dcc_en, 408 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk, 409 SECONDARY_SURFACE_DCC_EN, dcc_en, 410 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk); 411 } 412 413 void hubp2_program_pixel_format( 414 struct hubp *hubp, 415 enum surface_pixel_format format) 416 { 417 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 418 uint32_t red_bar = 3; 419 uint32_t blue_bar = 2; 420 421 /* swap for ABGR format */ 422 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 423 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 424 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS 425 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { 426 red_bar = 2; 427 blue_bar = 3; 428 } 429 430 REG_UPDATE_2(HUBPRET_CONTROL, 431 CROSSBAR_SRC_CB_B, blue_bar, 432 CROSSBAR_SRC_CR_R, red_bar); 433 434 /* Mapping is same as ipp programming (cnvc) */ 435 436 switch (format) { 437 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 438 REG_UPDATE(DCSURF_SURFACE_CONFIG, 439 SURFACE_PIXEL_FORMAT, 1); 440 break; 441 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 442 REG_UPDATE(DCSURF_SURFACE_CONFIG, 443 SURFACE_PIXEL_FORMAT, 3); 444 break; 445 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 446 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 447 REG_UPDATE(DCSURF_SURFACE_CONFIG, 448 SURFACE_PIXEL_FORMAT, 8); 449 break; 450 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 451 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 452 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: 453 REG_UPDATE(DCSURF_SURFACE_CONFIG, 454 SURFACE_PIXEL_FORMAT, 10); 455 break; 456 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 457 REG_UPDATE(DCSURF_SURFACE_CONFIG, 458 SURFACE_PIXEL_FORMAT, 22); 459 break; 460 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 461 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ 462 REG_UPDATE(DCSURF_SURFACE_CONFIG, 463 SURFACE_PIXEL_FORMAT, 24); 464 break; 465 466 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 467 REG_UPDATE(DCSURF_SURFACE_CONFIG, 468 SURFACE_PIXEL_FORMAT, 65); 469 break; 470 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 471 REG_UPDATE(DCSURF_SURFACE_CONFIG, 472 SURFACE_PIXEL_FORMAT, 64); 473 break; 474 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 475 REG_UPDATE(DCSURF_SURFACE_CONFIG, 476 SURFACE_PIXEL_FORMAT, 67); 477 break; 478 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 479 REG_UPDATE(DCSURF_SURFACE_CONFIG, 480 SURFACE_PIXEL_FORMAT, 66); 481 break; 482 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 483 REG_UPDATE(DCSURF_SURFACE_CONFIG, 484 SURFACE_PIXEL_FORMAT, 12); 485 break; 486 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 487 REG_UPDATE(DCSURF_SURFACE_CONFIG, 488 SURFACE_PIXEL_FORMAT, 112); 489 break; 490 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 491 REG_UPDATE(DCSURF_SURFACE_CONFIG, 492 SURFACE_PIXEL_FORMAT, 113); 493 break; 494 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 495 REG_UPDATE(DCSURF_SURFACE_CONFIG, 496 SURFACE_PIXEL_FORMAT, 114); 497 break; 498 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 499 REG_UPDATE(DCSURF_SURFACE_CONFIG, 500 SURFACE_PIXEL_FORMAT, 118); 501 break; 502 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 503 REG_UPDATE(DCSURF_SURFACE_CONFIG, 504 SURFACE_PIXEL_FORMAT, 119); 505 break; 506 default: 507 BREAK_TO_DEBUGGER(); 508 break; 509 } 510 511 /* don't see the need of program the xbar in DCN 1.0 */ 512 } 513 514 void hubp2_program_surface_config( 515 struct hubp *hubp, 516 enum surface_pixel_format format, 517 union dc_tiling_info *tiling_info, 518 struct plane_size *plane_size, 519 enum dc_rotation_angle rotation, 520 struct dc_plane_dcc_param *dcc, 521 bool horizontal_mirror, 522 unsigned int compat_level) 523 { 524 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 525 526 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); 527 hubp2_program_tiling(hubp2, tiling_info, format); 528 hubp2_program_size(hubp, format, plane_size, dcc); 529 hubp2_program_rotation(hubp, rotation, horizontal_mirror); 530 hubp2_program_pixel_format(hubp, format); 531 } 532 533 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( 534 unsigned int cursor_width, 535 enum dc_cursor_color_format cursor_mode) 536 { 537 enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 538 539 if (cursor_mode == CURSOR_MODE_MONO) 540 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 541 else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND || 542 cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 543 cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 544 if (cursor_width >= 1 && cursor_width <= 32) 545 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 546 else if (cursor_width >= 33 && cursor_width <= 64) 547 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 548 else if (cursor_width >= 65 && cursor_width <= 128) 549 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 550 else if (cursor_width >= 129 && cursor_width <= 256) 551 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 552 } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED || 553 cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) { 554 if (cursor_width >= 1 && cursor_width <= 16) 555 line_per_chunk = CURSOR_LINE_PER_CHUNK_16; 556 else if (cursor_width >= 17 && cursor_width <= 32) 557 line_per_chunk = CURSOR_LINE_PER_CHUNK_8; 558 else if (cursor_width >= 33 && cursor_width <= 64) 559 line_per_chunk = CURSOR_LINE_PER_CHUNK_4; 560 else if (cursor_width >= 65 && cursor_width <= 128) 561 line_per_chunk = CURSOR_LINE_PER_CHUNK_2; 562 else if (cursor_width >= 129 && cursor_width <= 256) 563 line_per_chunk = CURSOR_LINE_PER_CHUNK_1; 564 } 565 566 return line_per_chunk; 567 } 568 569 void hubp2_cursor_set_attributes( 570 struct hubp *hubp, 571 const struct dc_cursor_attributes *attr) 572 { 573 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 574 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); 575 enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk( 576 attr->width, attr->color_format); 577 578 hubp->curs_attr = *attr; 579 580 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH, 581 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); 582 REG_UPDATE(CURSOR_SURFACE_ADDRESS, 583 CURSOR_SURFACE_ADDRESS, attr->address.low_part); 584 585 REG_UPDATE_2(CURSOR_SIZE, 586 CURSOR_WIDTH, attr->width, 587 CURSOR_HEIGHT, attr->height); 588 589 REG_UPDATE_4(CURSOR_CONTROL, 590 CURSOR_MODE, attr->color_format, 591 CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION, 592 CURSOR_PITCH, hw_pitch, 593 CURSOR_LINES_PER_CHUNK, lpc); 594 595 REG_SET_2(CURSOR_SETTINGS, 0, 596 /* no shift of the cursor HDL schedule */ 597 CURSOR0_DST_Y_OFFSET, 0, 598 /* used to shift the cursor chunk request deadline */ 599 CURSOR0_CHUNK_HDL_ADJUST, 3); 600 } 601 602 void hubp2_dmdata_set_attributes( 603 struct hubp *hubp, 604 const struct dc_dmdata_attributes *attr) 605 { 606 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 607 608 if (attr->dmdata_mode == DMDATA_HW_MODE) { 609 /* set to HW mode */ 610 REG_UPDATE(DMDATA_CNTL, 611 DMDATA_MODE, 1); 612 613 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */ 614 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1); 615 616 /* toggle DMDATA_UPDATED and set repeat and size */ 617 REG_UPDATE(DMDATA_CNTL, 618 DMDATA_UPDATED, 0); 619 REG_UPDATE_3(DMDATA_CNTL, 620 DMDATA_UPDATED, 1, 621 DMDATA_REPEAT, attr->dmdata_repeat, 622 DMDATA_SIZE, attr->dmdata_size); 623 624 /* set DMDATA address */ 625 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part); 626 REG_UPDATE(DMDATA_ADDRESS_HIGH, 627 DMDATA_ADDRESS_HIGH, attr->address.high_part); 628 629 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0); 630 631 } else { 632 /* set to SW mode before loading data */ 633 REG_SET(DMDATA_CNTL, 0, 634 DMDATA_MODE, 0); 635 /* toggle DMDATA_SW_UPDATED to start loading sequence */ 636 REG_UPDATE(DMDATA_SW_CNTL, 637 DMDATA_SW_UPDATED, 0); 638 REG_UPDATE_3(DMDATA_SW_CNTL, 639 DMDATA_SW_UPDATED, 1, 640 DMDATA_SW_REPEAT, attr->dmdata_repeat, 641 DMDATA_SW_SIZE, attr->dmdata_size); 642 /* load data into hubp dmdata buffer */ 643 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data); 644 } 645 646 /* Note that DL_DELTA must be programmed if we want to use TTU mode */ 647 REG_SET_3(DMDATA_QOS_CNTL, 0, 648 DMDATA_QOS_MODE, attr->dmdata_qos_mode, 649 DMDATA_QOS_LEVEL, attr->dmdata_qos_level, 650 DMDATA_DL_DELTA, attr->dmdata_dl_delta); 651 } 652 653 void hubp2_dmdata_load( 654 struct hubp *hubp, 655 uint32_t dmdata_sw_size, 656 const uint32_t *dmdata_sw_data) 657 { 658 int i; 659 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 660 661 /* load dmdata into HUBP buffer in SW mode */ 662 for (i = 0; i < dmdata_sw_size / 4; i++) 663 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]); 664 } 665 666 bool hubp2_dmdata_status_done(struct hubp *hubp) 667 { 668 uint32_t status; 669 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 670 671 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); 672 return (status == 1); 673 } 674 675 bool hubp2_program_surface_flip_and_addr( 676 struct hubp *hubp, 677 const struct dc_plane_address *address, 678 bool flip_immediate) 679 { 680 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 681 682 //program flip type 683 REG_UPDATE(DCSURF_FLIP_CONTROL, 684 SURFACE_FLIP_TYPE, flip_immediate); 685 686 // Program VMID reg 687 REG_UPDATE(VMID_SETTINGS_0, 688 VMID, address->vmid); 689 690 if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { 691 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1); 692 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); 693 694 } else { 695 // turn off stereo if not in stereo 696 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); 697 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); 698 } 699 700 701 702 /* HW automatically latch rest of address register on write to 703 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used 704 * 705 * program high first and then the low addr, order matters! 706 */ 707 switch (address->type) { 708 case PLN_ADDR_TYPE_GRAPHICS: 709 /* DCN1.0 does not support const color 710 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 711 * base on address->grph.dcc_const_color 712 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma 713 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma 714 */ 715 716 if (address->grph.addr.quad_part == 0) 717 break; 718 719 REG_UPDATE_2(DCSURF_SURFACE_CONTROL, 720 PRIMARY_SURFACE_TMZ, address->tmz_surface, 721 PRIMARY_META_SURFACE_TMZ, address->tmz_surface); 722 723 if (address->grph.meta_addr.quad_part != 0) { 724 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 725 PRIMARY_META_SURFACE_ADDRESS_HIGH, 726 address->grph.meta_addr.high_part); 727 728 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 729 PRIMARY_META_SURFACE_ADDRESS, 730 address->grph.meta_addr.low_part); 731 } 732 733 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 734 PRIMARY_SURFACE_ADDRESS_HIGH, 735 address->grph.addr.high_part); 736 737 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 738 PRIMARY_SURFACE_ADDRESS, 739 address->grph.addr.low_part); 740 break; 741 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: 742 if (address->video_progressive.luma_addr.quad_part == 0 743 || address->video_progressive.chroma_addr.quad_part == 0) 744 break; 745 746 REG_UPDATE_4(DCSURF_SURFACE_CONTROL, 747 PRIMARY_SURFACE_TMZ, address->tmz_surface, 748 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 749 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 750 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); 751 752 if (address->video_progressive.luma_meta_addr.quad_part != 0) { 753 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, 754 PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 755 address->video_progressive.chroma_meta_addr.high_part); 756 757 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, 758 PRIMARY_META_SURFACE_ADDRESS_C, 759 address->video_progressive.chroma_meta_addr.low_part); 760 761 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 762 PRIMARY_META_SURFACE_ADDRESS_HIGH, 763 address->video_progressive.luma_meta_addr.high_part); 764 765 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 766 PRIMARY_META_SURFACE_ADDRESS, 767 address->video_progressive.luma_meta_addr.low_part); 768 } 769 770 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, 771 PRIMARY_SURFACE_ADDRESS_HIGH_C, 772 address->video_progressive.chroma_addr.high_part); 773 774 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, 775 PRIMARY_SURFACE_ADDRESS_C, 776 address->video_progressive.chroma_addr.low_part); 777 778 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 779 PRIMARY_SURFACE_ADDRESS_HIGH, 780 address->video_progressive.luma_addr.high_part); 781 782 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 783 PRIMARY_SURFACE_ADDRESS, 784 address->video_progressive.luma_addr.low_part); 785 break; 786 case PLN_ADDR_TYPE_GRPH_STEREO: 787 if (address->grph_stereo.left_addr.quad_part == 0) 788 break; 789 if (address->grph_stereo.right_addr.quad_part == 0) 790 break; 791 792 REG_UPDATE_8(DCSURF_SURFACE_CONTROL, 793 PRIMARY_SURFACE_TMZ, address->tmz_surface, 794 PRIMARY_SURFACE_TMZ_C, address->tmz_surface, 795 PRIMARY_META_SURFACE_TMZ, address->tmz_surface, 796 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, 797 SECONDARY_SURFACE_TMZ, address->tmz_surface, 798 SECONDARY_SURFACE_TMZ_C, address->tmz_surface, 799 SECONDARY_META_SURFACE_TMZ, address->tmz_surface, 800 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); 801 802 if (address->grph_stereo.right_meta_addr.quad_part != 0) { 803 804 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, 805 SECONDARY_META_SURFACE_ADDRESS_HIGH, 806 address->grph_stereo.right_meta_addr.high_part); 807 808 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, 809 SECONDARY_META_SURFACE_ADDRESS, 810 address->grph_stereo.right_meta_addr.low_part); 811 } 812 if (address->grph_stereo.left_meta_addr.quad_part != 0) { 813 814 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, 815 PRIMARY_META_SURFACE_ADDRESS_HIGH, 816 address->grph_stereo.left_meta_addr.high_part); 817 818 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, 819 PRIMARY_META_SURFACE_ADDRESS, 820 address->grph_stereo.left_meta_addr.low_part); 821 } 822 823 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, 824 SECONDARY_SURFACE_ADDRESS_HIGH, 825 address->grph_stereo.right_addr.high_part); 826 827 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, 828 SECONDARY_SURFACE_ADDRESS, 829 address->grph_stereo.right_addr.low_part); 830 831 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, 832 PRIMARY_SURFACE_ADDRESS_HIGH, 833 address->grph_stereo.left_addr.high_part); 834 835 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, 836 PRIMARY_SURFACE_ADDRESS, 837 address->grph_stereo.left_addr.low_part); 838 break; 839 default: 840 BREAK_TO_DEBUGGER(); 841 break; 842 } 843 844 hubp->request_address = *address; 845 846 return true; 847 } 848 849 void hubp2_enable_triplebuffer( 850 struct hubp *hubp, 851 bool enable) 852 { 853 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 854 uint32_t triple_buffer_en = 0; 855 bool tri_buffer_en; 856 857 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 858 tri_buffer_en = (triple_buffer_en == 1); 859 if (tri_buffer_en != enable) { 860 REG_UPDATE(DCSURF_FLIP_CONTROL2, 861 SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE); 862 } 863 } 864 865 bool hubp2_is_triplebuffer_enabled( 866 struct hubp *hubp) 867 { 868 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 869 uint32_t triple_buffer_en = 0; 870 871 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); 872 873 return (bool)triple_buffer_en; 874 } 875 876 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable) 877 { 878 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 879 880 REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0); 881 } 882 883 bool hubp2_is_flip_pending(struct hubp *hubp) 884 { 885 uint32_t flip_pending = 0; 886 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 887 struct dc_plane_address earliest_inuse_address; 888 889 REG_GET(DCSURF_FLIP_CONTROL, 890 SURFACE_FLIP_PENDING, &flip_pending); 891 892 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 893 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); 894 895 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 896 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); 897 898 if (flip_pending) 899 return true; 900 901 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) 902 return true; 903 904 return false; 905 } 906 907 void hubp2_set_blank(struct hubp *hubp, bool blank) 908 { 909 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 910 uint32_t blank_en = blank ? 1 : 0; 911 912 REG_UPDATE_2(DCHUBP_CNTL, 913 HUBP_BLANK_EN, blank_en, 914 HUBP_TTU_DISABLE, blank_en); 915 916 if (blank) { 917 uint32_t reg_val = REG_READ(DCHUBP_CNTL); 918 919 if (reg_val) { 920 /* init sequence workaround: in case HUBP is 921 * power gated, this wait would timeout. 922 * 923 * we just wrote reg_val to non-0, if it stay 0 924 * it means HUBP is gated 925 */ 926 REG_WAIT(DCHUBP_CNTL, 927 HUBP_NO_OUTSTANDING_REQ, 1, 928 1, 200); 929 } 930 931 hubp->mpcc_id = 0xf; 932 hubp->opp_id = OPP_ID_INVALID; 933 } 934 } 935 936 void hubp2_cursor_set_position( 937 struct hubp *hubp, 938 const struct dc_cursor_position *pos, 939 const struct dc_cursor_mi_param *param) 940 { 941 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 942 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 943 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 944 int x_hotspot = pos->x_hotspot; 945 int y_hotspot = pos->y_hotspot; 946 int cursor_height = (int)hubp->curs_attr.height; 947 int cursor_width = (int)hubp->curs_attr.width; 948 uint32_t dst_x_offset; 949 uint32_t cur_en = pos->enable ? 1 : 0; 950 951 /* 952 * Guard aganst cursor_set_position() from being called with invalid 953 * attributes 954 * 955 * TODO: Look at combining cursor_set_position() and 956 * cursor_set_attributes() into cursor_update() 957 */ 958 if (hubp->curs_attr.address.quad_part == 0) 959 return; 960 961 // Rotated cursor width/height and hotspots tweaks for offset calculation 962 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 963 swap(cursor_height, cursor_width); 964 if (param->rotation == ROTATION_ANGLE_90) { 965 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; 966 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; 967 } 968 } else if (param->rotation == ROTATION_ANGLE_180) { 969 src_x_offset = pos->x - param->viewport.x; 970 src_y_offset = pos->y - param->viewport.y; 971 } 972 973 if (param->mirror) { 974 x_hotspot = param->viewport.width - x_hotspot; 975 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset; 976 } 977 978 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0; 979 dst_x_offset *= param->ref_clk_khz; 980 dst_x_offset /= param->pixel_clk_khz; 981 982 ASSERT(param->h_scale_ratio.value); 983 984 if (param->h_scale_ratio.value) 985 dst_x_offset = dc_fixpt_floor(dc_fixpt_div( 986 dc_fixpt_from_int(dst_x_offset), 987 param->h_scale_ratio)); 988 989 if (src_x_offset >= (int)param->viewport.width) 990 cur_en = 0; /* not visible beyond right edge*/ 991 992 if (src_x_offset + cursor_width <= 0) 993 cur_en = 0; /* not visible beyond left edge*/ 994 995 if (src_y_offset >= (int)param->viewport.height) 996 cur_en = 0; /* not visible beyond bottom edge*/ 997 998 if (src_y_offset + cursor_height <= 0) 999 cur_en = 0; /* not visible beyond top edge*/ 1000 1001 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0) 1002 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr); 1003 1004 REG_UPDATE(CURSOR_CONTROL, 1005 CURSOR_ENABLE, cur_en); 1006 1007 REG_SET_2(CURSOR_POSITION, 0, 1008 CURSOR_X_POSITION, pos->x, 1009 CURSOR_Y_POSITION, pos->y); 1010 1011 REG_SET_2(CURSOR_HOT_SPOT, 0, 1012 CURSOR_HOT_SPOT_X, x_hotspot, 1013 CURSOR_HOT_SPOT_Y, y_hotspot); 1014 1015 REG_SET(CURSOR_DST_OFFSET, 0, 1016 CURSOR_DST_X_OFFSET, dst_x_offset); 1017 /* TODO Handle surface pixel formats other than 4:4:4 */ 1018 } 1019 1020 void hubp2_clk_cntl(struct hubp *hubp, bool enable) 1021 { 1022 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1023 uint32_t clk_enable = enable ? 1 : 0; 1024 1025 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); 1026 } 1027 1028 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst) 1029 { 1030 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1031 1032 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); 1033 } 1034 1035 void hubp2_clear_underflow(struct hubp *hubp) 1036 { 1037 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1038 1039 REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1); 1040 } 1041 1042 void hubp2_read_state_common(struct hubp *hubp) 1043 { 1044 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1045 struct dcn_hubp_state *s = &hubp2->state; 1046 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr; 1047 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr; 1048 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1049 1050 /* Requester */ 1051 REG_GET(HUBPRET_CONTROL, 1052 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address); 1053 REG_GET_4(DCN_EXPANSION_MODE, 1054 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode, 1055 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode, 1056 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode, 1057 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode); 1058 1059 /* DLG - Per hubp */ 1060 REG_GET_2(BLANK_OFFSET_0, 1061 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end, 1062 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end); 1063 1064 REG_GET(BLANK_OFFSET_1, 1065 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start); 1066 1067 REG_GET(DST_DIMENSIONS, 1068 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal); 1069 1070 REG_GET_2(DST_AFTER_SCALER, 1071 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler, 1072 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler); 1073 1074 if (REG(PREFETCH_SETTINS)) 1075 REG_GET_2(PREFETCH_SETTINS, 1076 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1077 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1078 else 1079 REG_GET_2(PREFETCH_SETTINGS, 1080 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch, 1081 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch); 1082 1083 REG_GET_2(VBLANK_PARAMETERS_0, 1084 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank, 1085 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank); 1086 1087 REG_GET(REF_FREQ_TO_PIX_FREQ, 1088 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq); 1089 1090 /* DLG - Per luma/chroma */ 1091 REG_GET(VBLANK_PARAMETERS_1, 1092 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l); 1093 1094 REG_GET(VBLANK_PARAMETERS_3, 1095 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); 1096 1097 if (REG(NOM_PARAMETERS_0)) 1098 REG_GET(NOM_PARAMETERS_0, 1099 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l); 1100 1101 if (REG(NOM_PARAMETERS_1)) 1102 REG_GET(NOM_PARAMETERS_1, 1103 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l); 1104 1105 REG_GET(NOM_PARAMETERS_4, 1106 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l); 1107 1108 REG_GET(NOM_PARAMETERS_5, 1109 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l); 1110 1111 REG_GET_2(PER_LINE_DELIVERY_PRE, 1112 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, 1113 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c); 1114 1115 REG_GET_2(PER_LINE_DELIVERY, 1116 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l, 1117 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c); 1118 1119 if (REG(PREFETCH_SETTINS_C)) 1120 REG_GET(PREFETCH_SETTINS_C, 1121 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1122 else 1123 REG_GET(PREFETCH_SETTINGS_C, 1124 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c); 1125 1126 REG_GET(VBLANK_PARAMETERS_2, 1127 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c); 1128 1129 REG_GET(VBLANK_PARAMETERS_4, 1130 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c); 1131 1132 if (REG(NOM_PARAMETERS_2)) 1133 REG_GET(NOM_PARAMETERS_2, 1134 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c); 1135 1136 if (REG(NOM_PARAMETERS_3)) 1137 REG_GET(NOM_PARAMETERS_3, 1138 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c); 1139 1140 REG_GET(NOM_PARAMETERS_6, 1141 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c); 1142 1143 REG_GET(NOM_PARAMETERS_7, 1144 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c); 1145 1146 /* TTU - per hubp */ 1147 REG_GET_2(DCN_TTU_QOS_WM, 1148 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm, 1149 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm); 1150 1151 REG_GET_2(DCN_GLOBAL_TTU_CNTL, 1152 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank, 1153 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip); 1154 1155 /* TTU - per luma/chroma */ 1156 /* Assumed surf0 is luma and 1 is chroma */ 1157 1158 REG_GET_3(DCN_SURF0_TTU_CNTL0, 1159 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l, 1160 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l, 1161 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l); 1162 1163 REG_GET(DCN_SURF0_TTU_CNTL1, 1164 REFCYC_PER_REQ_DELIVERY_PRE, 1165 &ttu_attr->refcyc_per_req_delivery_pre_l); 1166 1167 REG_GET_3(DCN_SURF1_TTU_CNTL0, 1168 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c, 1169 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c, 1170 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c); 1171 1172 REG_GET(DCN_SURF1_TTU_CNTL1, 1173 REFCYC_PER_REQ_DELIVERY_PRE, 1174 &ttu_attr->refcyc_per_req_delivery_pre_c); 1175 1176 /* Rest of hubp */ 1177 REG_GET(DCSURF_SURFACE_CONFIG, 1178 SURFACE_PIXEL_FORMAT, &s->pixel_format); 1179 1180 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, 1181 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi); 1182 1183 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, 1184 SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo); 1185 1186 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 1187 PRI_VIEWPORT_WIDTH, &s->viewport_width, 1188 PRI_VIEWPORT_HEIGHT, &s->viewport_height); 1189 1190 REG_GET_2(DCSURF_SURFACE_CONFIG, 1191 ROTATION_ANGLE, &s->rotation_angle, 1192 H_MIRROR_EN, &s->h_mirror_en); 1193 1194 REG_GET(DCSURF_TILING_CONFIG, 1195 SW_MODE, &s->sw_mode); 1196 1197 REG_GET(DCSURF_SURFACE_CONTROL, 1198 PRIMARY_SURFACE_DCC_EN, &s->dcc_en); 1199 1200 REG_GET_3(DCHUBP_CNTL, 1201 HUBP_BLANK_EN, &s->blank_en, 1202 HUBP_TTU_DISABLE, &s->ttu_disable, 1203 HUBP_UNDERFLOW_STATUS, &s->underflow_status); 1204 1205 REG_GET(DCN_GLOBAL_TTU_CNTL, 1206 MIN_TTU_VBLANK, &s->min_ttu_vblank); 1207 1208 REG_GET_2(DCN_TTU_QOS_WM, 1209 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm, 1210 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm); 1211 1212 } 1213 1214 void hubp2_read_state(struct hubp *hubp) 1215 { 1216 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); 1217 struct dcn_hubp_state *s = &hubp2->state; 1218 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; 1219 1220 hubp2_read_state_common(hubp); 1221 1222 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG, 1223 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, 1224 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, 1225 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, 1226 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size, 1227 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, 1228 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size, 1229 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, 1230 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear); 1231 1232 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C, 1233 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, 1234 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, 1235 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size, 1236 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size, 1237 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size, 1238 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size, 1239 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, 1240 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear); 1241 1242 } 1243 1244 static struct hubp_funcs dcn20_hubp_funcs = { 1245 .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, 1246 .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, 1247 .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr, 1248 .hubp_program_surface_config = hubp2_program_surface_config, 1249 .hubp_is_flip_pending = hubp2_is_flip_pending, 1250 .hubp_setup = hubp2_setup, 1251 .hubp_setup_interdependent = hubp2_setup_interdependent, 1252 .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings, 1253 .set_blank = hubp2_set_blank, 1254 .dcc_control = hubp2_dcc_control, 1255 .mem_program_viewport = min_set_viewport, 1256 .set_cursor_attributes = hubp2_cursor_set_attributes, 1257 .set_cursor_position = hubp2_cursor_set_position, 1258 .hubp_clk_cntl = hubp2_clk_cntl, 1259 .hubp_vtg_sel = hubp2_vtg_sel, 1260 .dmdata_set_attributes = hubp2_dmdata_set_attributes, 1261 .dmdata_load = hubp2_dmdata_load, 1262 .dmdata_status_done = hubp2_dmdata_status_done, 1263 .hubp_read_state = hubp2_read_state, 1264 .hubp_clear_underflow = hubp2_clear_underflow, 1265 .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, 1266 .hubp_init = hubp1_init, 1267 }; 1268 1269 1270 bool hubp2_construct( 1271 struct dcn20_hubp *hubp2, 1272 struct dc_context *ctx, 1273 uint32_t inst, 1274 const struct dcn_hubp2_registers *hubp_regs, 1275 const struct dcn_hubp2_shift *hubp_shift, 1276 const struct dcn_hubp2_mask *hubp_mask) 1277 { 1278 hubp2->base.funcs = &dcn20_hubp_funcs; 1279 hubp2->base.ctx = ctx; 1280 hubp2->hubp_regs = hubp_regs; 1281 hubp2->hubp_shift = hubp_shift; 1282 hubp2->hubp_mask = hubp_mask; 1283 hubp2->base.inst = inst; 1284 hubp2->base.opp_id = OPP_ID_INVALID; 1285 hubp2->base.mpcc_id = 0xf; 1286 1287 return true; 1288 } 1289