1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dcn20_hubbub.h" 28 #include "reg_helper.h" 29 #include "clk_mgr.h" 30 31 #define REG(reg)\ 32 hubbub1->regs->reg 33 34 #define CTX \ 35 hubbub1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 hubbub1->shifts->field_name, hubbub1->masks->field_name 40 41 #define REG(reg)\ 42 hubbub1->regs->reg 43 44 #define CTX \ 45 hubbub1->base.ctx 46 47 #undef FN 48 #define FN(reg_name, field_name) \ 49 hubbub1->shifts->field_name, hubbub1->masks->field_name 50 51 #ifdef NUM_VMID 52 #undef NUM_VMID 53 #endif 54 #define NUM_VMID 16 55 56 bool hubbub2_dcc_support_swizzle( 57 enum swizzle_mode_values swizzle, 58 unsigned int bytes_per_element, 59 enum segment_order *segment_order_horz, 60 enum segment_order *segment_order_vert) 61 { 62 bool standard_swizzle = false; 63 bool display_swizzle = false; 64 bool render_swizzle = false; 65 66 switch (swizzle) { 67 case DC_SW_4KB_S: 68 case DC_SW_64KB_S: 69 case DC_SW_VAR_S: 70 case DC_SW_4KB_S_X: 71 case DC_SW_64KB_S_X: 72 case DC_SW_VAR_S_X: 73 standard_swizzle = true; 74 break; 75 case DC_SW_64KB_R_X: 76 render_swizzle = true; 77 break; 78 case DC_SW_4KB_D: 79 case DC_SW_64KB_D: 80 case DC_SW_VAR_D: 81 case DC_SW_4KB_D_X: 82 case DC_SW_64KB_D_X: 83 case DC_SW_VAR_D_X: 84 display_swizzle = true; 85 break; 86 default: 87 break; 88 } 89 90 if (standard_swizzle) { 91 if (bytes_per_element == 1) { 92 *segment_order_horz = segment_order__contiguous; 93 *segment_order_vert = segment_order__na; 94 return true; 95 } 96 if (bytes_per_element == 2) { 97 *segment_order_horz = segment_order__non_contiguous; 98 *segment_order_vert = segment_order__contiguous; 99 return true; 100 } 101 if (bytes_per_element == 4) { 102 *segment_order_horz = segment_order__non_contiguous; 103 *segment_order_vert = segment_order__contiguous; 104 return true; 105 } 106 if (bytes_per_element == 8) { 107 *segment_order_horz = segment_order__na; 108 *segment_order_vert = segment_order__contiguous; 109 return true; 110 } 111 } 112 if (render_swizzle) { 113 if (bytes_per_element == 2) { 114 *segment_order_horz = segment_order__contiguous; 115 *segment_order_vert = segment_order__contiguous; 116 return true; 117 } 118 if (bytes_per_element == 4) { 119 *segment_order_horz = segment_order__non_contiguous; 120 *segment_order_vert = segment_order__contiguous; 121 return true; 122 } 123 if (bytes_per_element == 8) { 124 *segment_order_horz = segment_order__contiguous; 125 *segment_order_vert = segment_order__non_contiguous; 126 return true; 127 } 128 } 129 if (display_swizzle && bytes_per_element == 8) { 130 *segment_order_horz = segment_order__contiguous; 131 *segment_order_vert = segment_order__non_contiguous; 132 return true; 133 } 134 135 return false; 136 } 137 138 bool hubbub2_dcc_support_pixel_format( 139 enum surface_pixel_format format, 140 unsigned int *bytes_per_element) 141 { 142 /* DML: get_bytes_per_element */ 143 switch (format) { 144 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 145 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 146 *bytes_per_element = 2; 147 return true; 148 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 149 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 150 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 151 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 152 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 153 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 154 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 155 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 156 *bytes_per_element = 4; 157 return true; 158 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 159 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 160 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 161 *bytes_per_element = 8; 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 static void hubbub2_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height, 169 unsigned int bytes_per_element) 170 { 171 /* copied from DML. might want to refactor DML to leverage from DML */ 172 /* DML : get_blk256_size */ 173 if (bytes_per_element == 1) { 174 *blk256_width = 16; 175 *blk256_height = 16; 176 } else if (bytes_per_element == 2) { 177 *blk256_width = 16; 178 *blk256_height = 8; 179 } else if (bytes_per_element == 4) { 180 *blk256_width = 8; 181 *blk256_height = 8; 182 } else if (bytes_per_element == 8) { 183 *blk256_width = 8; 184 *blk256_height = 4; 185 } 186 } 187 188 static void hubbub2_det_request_size( 189 unsigned int height, 190 unsigned int width, 191 unsigned int bpe, 192 bool *req128_horz_wc, 193 bool *req128_vert_wc) 194 { 195 unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */ 196 197 unsigned int blk256_height = 0; 198 unsigned int blk256_width = 0; 199 unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc; 200 201 hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe); 202 203 swath_bytes_horz_wc = width * blk256_height * bpe; 204 swath_bytes_vert_wc = height * blk256_width * bpe; 205 206 *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ? 207 false : /* full 256B request */ 208 true; /* half 128b request */ 209 210 *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ? 211 false : /* full 256B request */ 212 true; /* half 128b request */ 213 } 214 215 bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub, 216 const struct dc_dcc_surface_param *input, 217 struct dc_surface_dcc_cap *output) 218 { 219 struct dc *dc = hubbub->ctx->dc; 220 /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */ 221 enum dcc_control dcc_control; 222 unsigned int bpe; 223 enum segment_order segment_order_horz, segment_order_vert; 224 bool req128_horz_wc, req128_vert_wc; 225 226 memset(output, 0, sizeof(*output)); 227 228 if (dc->debug.disable_dcc == DCC_DISABLE) 229 return false; 230 231 if (!hubbub->funcs->dcc_support_pixel_format(input->format, 232 &bpe)) 233 return false; 234 235 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe, 236 &segment_order_horz, &segment_order_vert)) 237 return false; 238 239 hubbub2_det_request_size(input->surface_size.height, input->surface_size.width, 240 bpe, &req128_horz_wc, &req128_vert_wc); 241 242 if (!req128_horz_wc && !req128_vert_wc) { 243 dcc_control = dcc_control__256_256_xxx; 244 } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) { 245 if (!req128_horz_wc) 246 dcc_control = dcc_control__256_256_xxx; 247 else if (segment_order_horz == segment_order__contiguous) 248 dcc_control = dcc_control__128_128_xxx; 249 else 250 dcc_control = dcc_control__256_64_64; 251 } else if (input->scan == SCAN_DIRECTION_VERTICAL) { 252 if (!req128_vert_wc) 253 dcc_control = dcc_control__256_256_xxx; 254 else if (segment_order_vert == segment_order__contiguous) 255 dcc_control = dcc_control__128_128_xxx; 256 else 257 dcc_control = dcc_control__256_64_64; 258 } else { 259 if ((req128_horz_wc && 260 segment_order_horz == segment_order__non_contiguous) || 261 (req128_vert_wc && 262 segment_order_vert == segment_order__non_contiguous)) 263 /* access_dir not known, must use most constraining */ 264 dcc_control = dcc_control__256_64_64; 265 else 266 /* reg128 is true for either horz and vert 267 * but segment_order is contiguous 268 */ 269 dcc_control = dcc_control__128_128_xxx; 270 } 271 272 /* Exception for 64KB_R_X */ 273 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X)) 274 dcc_control = dcc_control__128_128_xxx; 275 276 if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE && 277 dcc_control != dcc_control__256_256_xxx) 278 return false; 279 280 switch (dcc_control) { 281 case dcc_control__256_256_xxx: 282 output->grph.rgb.max_uncompressed_blk_size = 256; 283 output->grph.rgb.max_compressed_blk_size = 256; 284 output->grph.rgb.independent_64b_blks = false; 285 break; 286 case dcc_control__128_128_xxx: 287 output->grph.rgb.max_uncompressed_blk_size = 128; 288 output->grph.rgb.max_compressed_blk_size = 128; 289 output->grph.rgb.independent_64b_blks = false; 290 break; 291 case dcc_control__256_64_64: 292 output->grph.rgb.max_uncompressed_blk_size = 256; 293 output->grph.rgb.max_compressed_blk_size = 64; 294 output->grph.rgb.independent_64b_blks = true; 295 break; 296 } 297 output->capable = true; 298 output->const_color_support = true; 299 300 return true; 301 } 302 303 static enum dcn_hubbub_page_table_depth page_table_depth_to_hw(unsigned int page_table_depth) 304 { 305 enum dcn_hubbub_page_table_depth depth = 0; 306 307 switch (page_table_depth) { 308 case 1: 309 depth = DCN_PAGE_TABLE_DEPTH_1_LEVEL; 310 break; 311 case 2: 312 depth = DCN_PAGE_TABLE_DEPTH_2_LEVEL; 313 break; 314 case 3: 315 depth = DCN_PAGE_TABLE_DEPTH_3_LEVEL; 316 break; 317 case 4: 318 depth = DCN_PAGE_TABLE_DEPTH_4_LEVEL; 319 break; 320 default: 321 ASSERT(false); 322 break; 323 } 324 325 return depth; 326 } 327 328 static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigned int page_table_block_size) 329 { 330 enum dcn_hubbub_page_table_block_size block_size = 0; 331 332 switch (page_table_block_size) { 333 case 4096: 334 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB; 335 break; 336 case 65536: 337 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB; 338 break; 339 default: 340 ASSERT(false); 341 block_size = page_table_block_size; 342 break; 343 } 344 345 return block_size; 346 } 347 348 void hubbub2_init_vm_ctx(struct hubbub *hubbub, 349 struct dcn_hubbub_virt_addr_config *va_config, 350 int vmid) 351 { 352 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 353 struct dcn_vmid_page_table_config virt_config; 354 355 virt_config.page_table_start_addr = va_config->page_table_start_addr >> 12; 356 virt_config.page_table_end_addr = va_config->page_table_end_addr >> 12; 357 virt_config.depth = page_table_depth_to_hw(va_config->page_table_depth); 358 virt_config.block_size = page_table_block_size_to_hw(va_config->page_table_block_size); 359 virt_config.page_table_base_addr = va_config->page_table_base_addr; 360 361 dcn20_vmid_setup(&hubbub1->vmid[vmid], &virt_config); 362 } 363 364 int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, 365 struct dcn_hubbub_phys_addr_config *pa_config) 366 { 367 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 368 struct dcn_vmid_page_table_config phys_config; 369 370 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, 371 FB_BASE, pa_config->system_aperture.fb_base >> 24); 372 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, 373 FB_TOP, pa_config->system_aperture.fb_top >> 24); 374 REG_SET(DCN_VM_FB_OFFSET, 0, 375 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); 376 REG_SET(DCN_VM_AGP_BOT, 0, 377 AGP_BOT, pa_config->system_aperture.agp_bot >> 24); 378 REG_SET(DCN_VM_AGP_TOP, 0, 379 AGP_TOP, pa_config->system_aperture.agp_top >> 24); 380 REG_SET(DCN_VM_AGP_BASE, 0, 381 AGP_BASE, pa_config->system_aperture.agp_base >> 24); 382 383 if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { 384 phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; 385 phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12; 386 phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 387 phys_config.depth = 0; 388 phys_config.block_size = 0; 389 // Init VMID 0 based on PA config 390 dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config); 391 } 392 393 return NUM_VMID; 394 } 395 396 void hubbub2_update_dchub(struct hubbub *hubbub, 397 struct dchub_init_data *dh_data) 398 { 399 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 400 401 if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) { 402 ASSERT(false); 403 /*should not come here*/ 404 return; 405 } 406 /* TODO: port code from dal2 */ 407 switch (dh_data->fb_mode) { 408 case FRAME_BUFFER_MODE_ZFB_ONLY: 409 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/ 410 REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP, 411 SDPIF_FB_TOP, 0); 412 413 REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE, 414 SDPIF_FB_BASE, 0x0FFFF); 415 416 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, 417 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); 418 419 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, 420 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); 421 422 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, 423 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + 424 dh_data->zfb_size_in_byte - 1) >> 22); 425 break; 426 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL: 427 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ 428 429 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, 430 SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22); 431 432 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, 433 SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22); 434 435 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, 436 SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr + 437 dh_data->zfb_size_in_byte - 1) >> 22); 438 break; 439 case FRAME_BUFFER_MODE_LOCAL_ONLY: 440 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/ 441 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE, 442 SDPIF_AGP_BASE, 0); 443 444 REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT, 445 SDPIF_AGP_BOT, 0X03FFFF); 446 447 REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP, 448 SDPIF_AGP_TOP, 0); 449 break; 450 default: 451 break; 452 } 453 454 dh_data->dchub_initialzied = true; 455 dh_data->dchub_info_valid = false; 456 } 457 458 void hubbub2_wm_read_state(struct hubbub *hubbub, 459 struct dcn_hubbub_wm *wm) 460 { 461 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 462 463 struct dcn_hubbub_wm_set *s; 464 465 memset(wm, 0, sizeof(struct dcn_hubbub_wm)); 466 467 s = &wm->sets[0]; 468 s->wm_set = 0; 469 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A); 470 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A)) 471 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A); 472 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) { 473 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A); 474 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A); 475 } 476 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A); 477 478 s = &wm->sets[1]; 479 s->wm_set = 1; 480 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B); 481 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B)) 482 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B); 483 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) { 484 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B); 485 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B); 486 } 487 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B); 488 489 s = &wm->sets[2]; 490 s->wm_set = 2; 491 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C); 492 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C)) 493 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C); 494 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) { 495 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C); 496 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C); 497 } 498 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C); 499 500 s = &wm->sets[3]; 501 s->wm_set = 3; 502 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D); 503 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D)) 504 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D); 505 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) { 506 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D); 507 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D); 508 } 509 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); 510 } 511 512 void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub, 513 unsigned int dccg_ref_freq_inKhz, 514 unsigned int *dchub_ref_freq_inKhz) 515 { 516 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 517 uint32_t ref_div = 0; 518 uint32_t ref_en = 0; 519 520 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, 521 DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en); 522 523 if (ref_en) { 524 if (ref_div == 2) 525 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz / 2; 526 else 527 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz; 528 529 // DC hub reference frequency must be around 50Mhz, otherwise there may be 530 // overflow/underflow issues when doing HUBBUB programming 531 if (*dchub_ref_freq_inKhz < 40000 || *dchub_ref_freq_inKhz > 60000) 532 ASSERT_CRITICAL(false); 533 534 return; 535 } else { 536 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz; 537 538 // HUBBUB global timer must be enabled. 539 ASSERT_CRITICAL(false); 540 return; 541 } 542 } 543 544 static void hubbub2_program_watermarks( 545 struct hubbub *hubbub, 546 struct dcn_watermark_set *watermarks, 547 unsigned int refclk_mhz, 548 bool safe_to_lower) 549 { 550 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub); 551 /* 552 * Need to clamp to max of the register values (i.e. no wrap) 553 * for dcn1, all wm registers are 21-bit wide 554 */ 555 hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); 556 hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); 557 558 /* 559 * There's a special case when going from p-state support to p-state unsupported 560 * here we are going to LOWER watermarks to go to dummy p-state only, but this has 561 * to be done prepare_bandwidth, not optimize 562 */ 563 if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true && 564 hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false) 565 safe_to_lower = true; 566 567 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); 568 569 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, 570 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); 571 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180); 572 573 hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); 574 } 575 576 static const struct hubbub_funcs hubbub2_funcs = { 577 .update_dchub = hubbub2_update_dchub, 578 .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx, 579 .init_vm_ctx = hubbub2_init_vm_ctx, 580 .dcc_support_swizzle = hubbub2_dcc_support_swizzle, 581 .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, 582 .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap, 583 .wm_read_state = hubbub2_wm_read_state, 584 .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq, 585 .program_watermarks = hubbub2_program_watermarks, 586 }; 587 588 void hubbub2_construct(struct dcn20_hubbub *hubbub, 589 struct dc_context *ctx, 590 const struct dcn_hubbub_registers *hubbub_regs, 591 const struct dcn_hubbub_shift *hubbub_shift, 592 const struct dcn_hubbub_mask *hubbub_mask) 593 { 594 hubbub->base.ctx = ctx; 595 596 hubbub->base.funcs = &hubbub2_funcs; 597 598 hubbub->regs = hubbub_regs; 599 hubbub->shifts = hubbub_shift; 600 hubbub->masks = hubbub_mask; 601 602 hubbub->debug_test_index_pstate = 0xB; 603 } 604