1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn20_dsc.h" 28 #include "dsc/dscc_types.h" 29 30 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); 31 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 32 struct dsc_optc_config *dsc_optc_cfg); 33 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals); 34 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params); 35 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 36 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple); 37 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth); 38 39 /* Object I/F functions */ 40 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 41 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 42 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 43 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 44 struct dsc_optc_config *dsc_optc_cfg); 45 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); 46 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); 47 static void dsc2_disable(struct display_stream_compressor *dsc); 48 static void dsc2_disconnect(struct display_stream_compressor *dsc); 49 50 const struct dsc_funcs dcn20_dsc_funcs = { 51 .dsc_get_enc_caps = dsc2_get_enc_caps, 52 .dsc_read_state = dsc2_read_state, 53 .dsc_validate_stream = dsc2_validate_stream, 54 .dsc_set_config = dsc2_set_config, 55 .dsc_get_packed_pps = dsc2_get_packed_pps, 56 .dsc_enable = dsc2_enable, 57 .dsc_disable = dsc2_disable, 58 .dsc_disconnect = dsc2_disconnect, 59 }; 60 61 /* Macro definitios for REG_SET macros*/ 62 #define CTX \ 63 dsc20->base.ctx 64 65 #define REG(reg)\ 66 dsc20->dsc_regs->reg 67 68 #undef FN 69 #define FN(reg_name, field_name) \ 70 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name 71 #define DC_LOGGER \ 72 dsc->ctx->logger 73 74 enum dsc_bits_per_comp { 75 DSC_BPC_8 = 8, 76 DSC_BPC_10 = 10, 77 DSC_BPC_12 = 12, 78 DSC_BPC_UNKNOWN 79 }; 80 81 /* API functions (external or via structure->function_pointer) */ 82 83 void dsc2_construct(struct dcn20_dsc *dsc, 84 struct dc_context *ctx, 85 int inst, 86 const struct dcn20_dsc_registers *dsc_regs, 87 const struct dcn20_dsc_shift *dsc_shift, 88 const struct dcn20_dsc_mask *dsc_mask) 89 { 90 dsc->base.ctx = ctx; 91 dsc->base.inst = inst; 92 dsc->base.funcs = &dcn20_dsc_funcs; 93 94 dsc->dsc_regs = dsc_regs; 95 dsc->dsc_shift = dsc_shift; 96 dsc->dsc_mask = dsc_mask; 97 98 dsc->max_image_width = 5184; 99 } 100 101 102 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188 103 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200 104 105 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput 106 * can be doubled, tripled etc. by using additional DSC engines. 107 */ 108 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 109 { 110 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 111 112 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 113 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 114 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 115 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 116 117 dsc_enc_caps->lb_bit_depth = 13; 118 dsc_enc_caps->is_block_pred_supported = true; 119 120 dsc_enc_caps->color_formats.bits.RGB = 1; 121 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 122 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 123 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 124 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 125 126 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 127 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 128 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 129 130 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. 131 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. 132 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always 133 * be sufficient to process the input pixel rate fed into a single DSC engine. 134 */ 135 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; 136 137 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our 138 * throughput and number of slices, but also introduces a lower limit of 2 slices 139 */ 140 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) { 141 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0; 142 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 143 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 144 } 145 146 // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM. 147 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 148 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 149 } 150 151 152 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 153 * into a dcn_dsc_state struct. 154 */ 155 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 156 { 157 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 158 159 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 160 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 161 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); 162 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); 163 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); 164 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); 165 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); 166 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); 167 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en, 168 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source); 169 } 170 171 172 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 173 { 174 struct dsc_optc_config dsc_optc_cfg; 175 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 176 177 if (dsc_cfg->pic_width > dsc20->max_image_width) 178 return false; 179 180 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); 181 } 182 183 184 static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) 185 { 186 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); 187 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); 188 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", 189 config->dc_dsc_cfg.bits_per_pixel, 190 config->dc_dsc_cfg.bits_per_pixel / 16, 191 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); 192 DC_LOG_DSC("\tcolor_depth %d", config->color_depth); 193 } 194 195 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 196 struct dsc_optc_config *dsc_optc_cfg) 197 { 198 bool is_config_ok; 199 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 200 201 DC_LOG_DSC(" "); 202 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 203 dsc_config_log(dsc, dsc_cfg); 204 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); 205 ASSERT(is_config_ok); 206 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 207 dsc_log_pps(dsc, &dsc20->reg_vals.pps); 208 dsc_write_to_registers(dsc, &dsc20->reg_vals); 209 } 210 211 212 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) 213 { 214 bool is_config_ok; 215 struct dsc_reg_values dsc_reg_vals; 216 struct dsc_optc_config dsc_optc_cfg; 217 218 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals)); 219 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg)); 220 221 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); 222 dsc_config_log(dsc, dsc_cfg); 223 DC_LOG_DSC("DSC Picture Parameter Set (PPS):"); 224 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); 225 ASSERT(is_config_ok); 226 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); 227 dsc_log_pps(dsc, &dsc_reg_vals.pps); 228 229 return is_config_ok; 230 } 231 232 233 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) 234 { 235 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 236 int dsc_clock_en; 237 int dsc_fw_config; 238 int enabled_opp_pipe; 239 240 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 241 242 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 243 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 244 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 245 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 246 ASSERT(0); 247 } 248 249 REG_UPDATE(DSC_TOP_CONTROL, 250 DSC_CLOCK_EN, 1); 251 252 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 253 DSCRM_DSC_FORWARD_EN, 1, 254 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 255 } 256 257 258 static void dsc2_disable(struct display_stream_compressor *dsc) 259 { 260 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 261 int dsc_clock_en; 262 int dsc_fw_config; 263 int enabled_opp_pipe; 264 265 DC_LOG_DSC("disable DSC %d", dsc->inst); 266 267 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 268 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 269 if (!dsc_clock_en || !dsc_fw_config) { 270 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe); 271 ASSERT(0); 272 } 273 274 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 275 DSCRM_DSC_FORWARD_EN, 0); 276 277 REG_UPDATE(DSC_TOP_CONTROL, 278 DSC_CLOCK_EN, 0); 279 } 280 281 static void dsc2_disconnect(struct display_stream_compressor *dsc) 282 { 283 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 284 285 DC_LOG_DSC("disconnect DSC %d", dsc->inst); 286 287 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 288 DSCRM_DSC_FORWARD_EN, 0); 289 } 290 291 /* This module's internal functions */ 292 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) 293 { 294 int i; 295 int bits_per_pixel = pps->bits_per_pixel; 296 297 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); 298 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); 299 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); 300 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); 301 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); 302 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); 303 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); 304 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); 305 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); 306 DC_LOG_DSC("\tpic_height %d", pps->pic_height); 307 DC_LOG_DSC("\tpic_width %d", pps->pic_width); 308 DC_LOG_DSC("\tslice_height %d", pps->slice_height); 309 DC_LOG_DSC("\tslice_width %d", pps->slice_width); 310 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); 311 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); 312 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); 313 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); 314 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); 315 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); 316 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); 317 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); 318 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); 319 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); 320 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); 321 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); 322 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); 323 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */ 324 DC_LOG_DSC("\tnative_420 %d", pps->native_420); 325 DC_LOG_DSC("\tnative_422 %d", pps->native_422); 326 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); 327 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); 328 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); 329 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); 330 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); 331 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); 332 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); 333 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); 334 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); 335 336 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 337 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); 338 339 for (i = 0; i < NUM_BUF_RANGES; i++) { 340 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); 341 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); 342 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); 343 } 344 } 345 346 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 347 struct dsc_optc_config *dsc_optc_cfg) 348 { 349 struct dsc_parameters dsc_params; 350 351 /* Validate input parameters */ 352 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); 353 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); 354 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); 355 ASSERT(dsc_cfg->pic_width); 356 ASSERT(dsc_cfg->pic_height); 357 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && 358 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || 359 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && 360 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 361 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); 362 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 363 364 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || 365 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || 366 !dsc_cfg->pic_width || !dsc_cfg->pic_height || 367 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: 368 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || 369 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: 370 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 371 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || 372 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { 373 dm_output_to_console("%s: Invalid parameters\n", __func__); 374 return false; 375 } 376 377 dsc_init_reg_values(dsc_reg_vals); 378 379 /* Copy input config */ 380 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); 381 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; 382 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; 383 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; 384 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; 385 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; 386 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); 387 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; 388 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; 389 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; 390 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; 391 392 // TODO: in addition to validating slice height (pic height must be divisible by slice height), 393 // see what happens when the same condition doesn't apply for slice_width/pic_width. 394 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; 395 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; 396 397 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); 398 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { 399 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); 400 return false; 401 } 402 403 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; 404 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 405 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; 406 else 407 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; 408 409 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; 410 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); 411 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); 412 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); 413 414 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) { 415 dm_output_to_console("%s: DSC config failed\n", __func__); 416 return false; 417 } 418 419 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); 420 421 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; 422 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; 423 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || 424 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || 425 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; 426 427 return true; 428 } 429 430 431 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple) 432 { 433 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 434 435 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */ 436 437 switch (dc_pix_enc) { 438 case PIXEL_ENCODING_RGB: 439 dsc_pix_fmt = DSC_PIXFMT_RGB; 440 break; 441 case PIXEL_ENCODING_YCBCR422: 442 if (is_ycbcr422_simple) 443 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422; 444 else 445 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422; 446 break; 447 case PIXEL_ENCODING_YCBCR444: 448 dsc_pix_fmt = DSC_PIXFMT_YCBCR444; 449 break; 450 case PIXEL_ENCODING_YCBCR420: 451 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420; 452 break; 453 default: 454 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 455 break; 456 } 457 458 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN); 459 return dsc_pix_fmt; 460 } 461 462 463 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth) 464 { 465 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; 466 467 switch (dc_color_depth) { 468 case COLOR_DEPTH_888: 469 bpc = DSC_BPC_8; 470 break; 471 case COLOR_DEPTH_101010: 472 bpc = DSC_BPC_10; 473 break; 474 case COLOR_DEPTH_121212: 475 bpc = DSC_BPC_12; 476 break; 477 default: 478 bpc = DSC_BPC_UNKNOWN; 479 break; 480 } 481 482 return bpc; 483 } 484 485 486 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) 487 { 488 int i; 489 490 memset(reg_vals, 0, sizeof(struct dsc_reg_values)); 491 492 /* Non-PPS values */ 493 reg_vals->dsc_clock_enable = 1; 494 reg_vals->dsc_clock_gating_disable = 0; 495 reg_vals->underflow_recovery_en = 0; 496 reg_vals->underflow_occurred_int_en = 0; 497 reg_vals->underflow_occurred_status = 0; 498 reg_vals->ich_reset_at_eol = 0; 499 reg_vals->alternate_ich_encoding_en = 0; 500 reg_vals->rc_buffer_model_size = 0; 501 /*reg_vals->disable_ich = 0;*/ 502 reg_vals->dsc_dbg_en = 0; 503 504 for (i = 0; i < 4; i++) 505 reg_vals->rc_buffer_model_overflow_int_en[i] = 0; 506 507 /* PPS values */ 508 reg_vals->pps.dsc_version_minor = 2; 509 reg_vals->pps.dsc_version_major = 1; 510 reg_vals->pps.line_buf_depth = 9; 511 reg_vals->pps.bits_per_component = 8; 512 reg_vals->pps.block_pred_enable = 1; 513 reg_vals->pps.slice_chunk_size = 0; 514 reg_vals->pps.pic_width = 0; 515 reg_vals->pps.pic_height = 0; 516 reg_vals->pps.slice_width = 0; 517 reg_vals->pps.slice_height = 0; 518 reg_vals->pps.initial_xmit_delay = 170; 519 reg_vals->pps.initial_dec_delay = 0; 520 reg_vals->pps.initial_scale_value = 0; 521 reg_vals->pps.scale_increment_interval = 0; 522 reg_vals->pps.scale_decrement_interval = 0; 523 reg_vals->pps.nfl_bpg_offset = 0; 524 reg_vals->pps.slice_bpg_offset = 0; 525 reg_vals->pps.nsl_bpg_offset = 0; 526 reg_vals->pps.initial_offset = 6144; 527 reg_vals->pps.final_offset = 0; 528 reg_vals->pps.flatness_min_qp = 3; 529 reg_vals->pps.flatness_max_qp = 12; 530 reg_vals->pps.rc_model_size = 8192; 531 reg_vals->pps.rc_edge_factor = 6; 532 reg_vals->pps.rc_quant_incr_limit0 = 11; 533 reg_vals->pps.rc_quant_incr_limit1 = 11; 534 reg_vals->pps.rc_tgt_offset_low = 3; 535 reg_vals->pps.rc_tgt_offset_high = 3; 536 } 537 538 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params. 539 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn 540 * affects non-PPS register values. 541 */ 542 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) 543 { 544 int i; 545 546 reg_vals->pps = dsc_params->pps; 547 548 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs. 549 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 550 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; 551 552 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; 553 } 554 555 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 556 { 557 uint32_t temp_int; 558 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 559 560 REG_SET(DSC_DEBUG_CONTROL, 0, 561 DSC_DBG_EN, reg_vals->dsc_dbg_en); 562 563 // dsccif registers 564 REG_SET_5(DSCCIF_CONFIG0, 0, 565 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 566 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 567 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 568 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 569 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 570 571 REG_SET_2(DSCCIF_CONFIG1, 0, 572 PIC_WIDTH, reg_vals->pps.pic_width, 573 PIC_HEIGHT, reg_vals->pps.pic_height); 574 575 // dscc registers 576 REG_SET_4(DSCC_CONFIG0, 0, 577 ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol, 578 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 579 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 580 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 581 582 REG_SET(DSCC_CONFIG1, 0, 583 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 584 /*REG_SET_2(DSCC_CONFIG1, 0, 585 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 586 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 587 588 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, 589 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], 590 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], 591 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], 592 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); 593 594 REG_SET_3(DSCC_PPS_CONFIG0, 0, 595 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 596 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 597 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 598 599 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 600 temp_int = reg_vals->bpp_x32; 601 else 602 temp_int = reg_vals->bpp_x32 >> 1; 603 604 REG_SET_7(DSCC_PPS_CONFIG1, 0, 605 BITS_PER_PIXEL, temp_int, 606 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 607 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 608 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 609 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 610 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 611 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 612 613 REG_SET_2(DSCC_PPS_CONFIG2, 0, 614 PIC_WIDTH, reg_vals->pps.pic_width, 615 PIC_HEIGHT, reg_vals->pps.pic_height); 616 617 REG_SET_2(DSCC_PPS_CONFIG3, 0, 618 SLICE_WIDTH, reg_vals->pps.slice_width, 619 SLICE_HEIGHT, reg_vals->pps.slice_height); 620 621 REG_SET(DSCC_PPS_CONFIG4, 0, 622 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 623 624 REG_SET_2(DSCC_PPS_CONFIG5, 0, 625 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 626 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 627 628 REG_SET_3(DSCC_PPS_CONFIG6, 0, 629 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 630 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 631 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 632 633 REG_SET_2(DSCC_PPS_CONFIG7, 0, 634 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 635 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 636 637 REG_SET_2(DSCC_PPS_CONFIG8, 0, 638 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 639 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 640 641 REG_SET_2(DSCC_PPS_CONFIG9, 0, 642 INITIAL_OFFSET, reg_vals->pps.initial_offset, 643 FINAL_OFFSET, reg_vals->pps.final_offset); 644 645 REG_SET_3(DSCC_PPS_CONFIG10, 0, 646 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 647 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 648 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 649 650 REG_SET_5(DSCC_PPS_CONFIG11, 0, 651 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 652 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 653 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 654 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 655 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 656 657 REG_SET_4(DSCC_PPS_CONFIG12, 0, 658 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 659 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 660 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 661 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 662 663 REG_SET_4(DSCC_PPS_CONFIG13, 0, 664 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 665 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 666 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 667 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 668 669 REG_SET_4(DSCC_PPS_CONFIG14, 0, 670 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 671 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 672 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 673 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 674 675 REG_SET_5(DSCC_PPS_CONFIG15, 0, 676 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 677 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 678 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 679 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 680 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 681 682 REG_SET_6(DSCC_PPS_CONFIG16, 0, 683 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 684 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 685 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 686 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 687 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 688 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 689 690 REG_SET_6(DSCC_PPS_CONFIG17, 0, 691 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 692 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 693 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 694 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 695 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 696 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 697 698 REG_SET_6(DSCC_PPS_CONFIG18, 0, 699 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 700 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 701 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 702 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 703 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 704 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 705 706 REG_SET_6(DSCC_PPS_CONFIG19, 0, 707 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 708 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 709 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 710 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 711 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 712 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 713 714 REG_SET_6(DSCC_PPS_CONFIG20, 0, 715 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 716 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 717 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 718 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 719 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 720 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 721 722 REG_SET_6(DSCC_PPS_CONFIG21, 0, 723 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 724 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 725 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 726 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 727 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 728 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 729 730 REG_SET_6(DSCC_PPS_CONFIG22, 0, 731 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 732 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 733 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 734 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 735 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 736 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 737 738 } 739 740