1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn20_dsc.h" 28 #include "dsc/dscc_types.h" 29 30 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); 31 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 32 struct dsc_optc_config *dsc_optc_cfg); 33 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals); 34 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params); 35 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 36 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple); 37 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth); 38 39 /* Object I/F functions */ 40 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 41 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 42 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 43 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 44 struct dsc_optc_config *dsc_optc_cfg); 45 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); 46 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); 47 static void dsc2_disable(struct display_stream_compressor *dsc); 48 49 const struct dsc_funcs dcn20_dsc_funcs = { 50 .dsc_get_enc_caps = dsc2_get_enc_caps, 51 .dsc_read_state = dsc2_read_state, 52 .dsc_validate_stream = dsc2_validate_stream, 53 .dsc_set_config = dsc2_set_config, 54 .dsc_get_packed_pps = dsc2_get_packed_pps, 55 .dsc_enable = dsc2_enable, 56 .dsc_disable = dsc2_disable, 57 }; 58 59 /* Macro definitios for REG_SET macros*/ 60 #define CTX \ 61 dsc20->base.ctx 62 63 #define REG(reg)\ 64 dsc20->dsc_regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name 69 #define DC_LOGGER \ 70 dsc->ctx->logger 71 72 enum dsc_bits_per_comp { 73 DSC_BPC_8 = 8, 74 DSC_BPC_10 = 10, 75 DSC_BPC_12 = 12, 76 DSC_BPC_UNKNOWN 77 }; 78 79 /* API functions (external or via structure->function_pointer) */ 80 81 void dsc2_construct(struct dcn20_dsc *dsc, 82 struct dc_context *ctx, 83 int inst, 84 const struct dcn20_dsc_registers *dsc_regs, 85 const struct dcn20_dsc_shift *dsc_shift, 86 const struct dcn20_dsc_mask *dsc_mask) 87 { 88 dsc->base.ctx = ctx; 89 dsc->base.inst = inst; 90 dsc->base.funcs = &dcn20_dsc_funcs; 91 92 dsc->dsc_regs = dsc_regs; 93 dsc->dsc_shift = dsc_shift; 94 dsc->dsc_mask = dsc_mask; 95 96 dsc->max_image_width = 5184; 97 } 98 99 100 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188 101 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200 102 103 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput 104 * can be doubled, tripled etc. by using additional DSC engines. 105 */ 106 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 107 { 108 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 109 110 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 111 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 112 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 113 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 114 115 dsc_enc_caps->lb_bit_depth = 13; 116 dsc_enc_caps->is_block_pred_supported = true; 117 118 dsc_enc_caps->color_formats.bits.RGB = 1; 119 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 120 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 121 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 122 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 123 124 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 125 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 126 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 127 128 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. 129 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. 130 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always 131 * be sufficient to process the input pixel rate fed into a single DSC engine. 132 */ 133 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; 134 135 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our 136 * throughput and number of slices, but also introduces a lower limit of 2 slices 137 */ 138 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) { 139 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0; 140 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 141 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 142 } 143 144 // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM. 145 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 146 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 147 } 148 149 150 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 151 * into a dcn_dsc_state struct. 152 */ 153 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 154 { 155 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 156 157 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 158 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 159 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bytes_per_pixel); 160 } 161 162 163 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 164 { 165 struct dsc_optc_config dsc_optc_cfg; 166 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 167 168 if (dsc_cfg->pic_width > dsc20->max_image_width) 169 return false; 170 171 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); 172 } 173 174 175 static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) 176 { 177 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); 178 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); 179 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", 180 config->dc_dsc_cfg.bits_per_pixel, 181 config->dc_dsc_cfg.bits_per_pixel / 16, 182 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); 183 DC_LOG_DSC("\tcolor_depth %d", config->color_depth); 184 } 185 186 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 187 struct dsc_optc_config *dsc_optc_cfg) 188 { 189 bool is_config_ok; 190 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 191 192 DC_LOG_DSC(" "); 193 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 194 dsc_config_log(dsc, dsc_cfg); 195 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); 196 ASSERT(is_config_ok); 197 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 198 dsc_log_pps(dsc, &dsc20->reg_vals.pps); 199 dsc_write_to_registers(dsc, &dsc20->reg_vals); 200 } 201 202 203 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) 204 { 205 bool is_config_ok; 206 struct dsc_reg_values dsc_reg_vals; 207 struct dsc_optc_config dsc_optc_cfg; 208 209 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); 210 dsc_config_log(dsc, dsc_cfg); 211 DC_LOG_DSC("DSC Picture Parameter Set (PPS):"); 212 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); 213 ASSERT(is_config_ok); 214 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); 215 dsc_log_pps(dsc, &dsc_reg_vals.pps); 216 217 return is_config_ok; 218 } 219 220 221 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) 222 { 223 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 224 int dsc_clock_en; 225 int dsc_fw_config; 226 int enabled_opp_pipe; 227 228 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 229 230 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 231 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 232 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 233 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 234 ASSERT(0); 235 } 236 237 REG_UPDATE(DSC_TOP_CONTROL, 238 DSC_CLOCK_EN, 1); 239 240 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 241 DSCRM_DSC_FORWARD_EN, 1, 242 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 243 } 244 245 246 static void dsc2_disable(struct display_stream_compressor *dsc) 247 { 248 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 249 int dsc_clock_en; 250 int dsc_fw_config; 251 int enabled_opp_pipe; 252 253 DC_LOG_DSC("disable DSC %d", dsc->inst); 254 255 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 256 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 257 if (!dsc_clock_en || !dsc_fw_config) { 258 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe); 259 ASSERT(0); 260 } 261 262 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 263 DSCRM_DSC_FORWARD_EN, 0); 264 265 REG_UPDATE(DSC_TOP_CONTROL, 266 DSC_CLOCK_EN, 0); 267 } 268 269 270 /* This module's internal functions */ 271 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) 272 { 273 int i; 274 int bits_per_pixel = pps->bits_per_pixel; 275 276 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); 277 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); 278 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); 279 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); 280 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); 281 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); 282 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); 283 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); 284 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); 285 DC_LOG_DSC("\tpic_height %d", pps->pic_height); 286 DC_LOG_DSC("\tpic_width %d", pps->pic_width); 287 DC_LOG_DSC("\tslice_height %d", pps->slice_height); 288 DC_LOG_DSC("\tslice_width %d", pps->slice_width); 289 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); 290 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); 291 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); 292 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); 293 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); 294 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); 295 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); 296 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); 297 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); 298 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); 299 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); 300 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); 301 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); 302 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */ 303 DC_LOG_DSC("\tnative_420 %d", pps->native_420); 304 DC_LOG_DSC("\tnative_422 %d", pps->native_422); 305 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); 306 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); 307 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); 308 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); 309 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); 310 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); 311 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); 312 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); 313 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); 314 315 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 316 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); 317 318 for (i = 0; i < NUM_BUF_RANGES; i++) { 319 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); 320 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); 321 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); 322 } 323 } 324 325 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 326 struct dsc_optc_config *dsc_optc_cfg) 327 { 328 struct dsc_parameters dsc_params; 329 330 /* Validate input parameters */ 331 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); 332 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); 333 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); 334 ASSERT(dsc_cfg->pic_width); 335 ASSERT(dsc_cfg->pic_height); 336 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && 337 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || 338 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && 339 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 340 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); 341 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 342 343 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || 344 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || 345 !dsc_cfg->pic_width || !dsc_cfg->pic_height || 346 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: 347 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || 348 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: 349 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 350 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || 351 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { 352 dm_output_to_console("%s: Invalid parameters\n", __func__); 353 return false; 354 } 355 356 dsc_init_reg_values(dsc_reg_vals); 357 358 /* Copy input config */ 359 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); 360 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; 361 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; 362 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; 363 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; 364 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; 365 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); 366 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; 367 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; 368 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; 369 370 // TODO: in addition to validating slice height (pic height must be divisible by slice height), 371 // see what happens when the same condition doesn't apply for slice_width/pic_width. 372 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; 373 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; 374 375 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); 376 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { 377 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); 378 return false; 379 } 380 381 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; 382 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 383 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; 384 else 385 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; 386 387 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; 388 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); 389 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); 390 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); 391 392 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) { 393 dm_output_to_console("%s: DSC config failed\n", __func__); 394 return false; 395 } 396 397 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); 398 399 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; 400 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; 401 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || 402 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || 403 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; 404 405 return true; 406 } 407 408 409 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple) 410 { 411 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 412 413 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */ 414 415 switch (dc_pix_enc) { 416 case PIXEL_ENCODING_RGB: 417 dsc_pix_fmt = DSC_PIXFMT_RGB; 418 break; 419 case PIXEL_ENCODING_YCBCR422: 420 if (is_ycbcr422_simple) 421 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422; 422 else 423 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422; 424 break; 425 case PIXEL_ENCODING_YCBCR444: 426 dsc_pix_fmt = DSC_PIXFMT_YCBCR444; 427 break; 428 case PIXEL_ENCODING_YCBCR420: 429 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420; 430 break; 431 default: 432 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 433 break; 434 } 435 436 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN); 437 return dsc_pix_fmt; 438 } 439 440 441 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth) 442 { 443 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; 444 445 switch (dc_color_depth) { 446 case COLOR_DEPTH_888: 447 bpc = DSC_BPC_8; 448 break; 449 case COLOR_DEPTH_101010: 450 bpc = DSC_BPC_10; 451 break; 452 case COLOR_DEPTH_121212: 453 bpc = DSC_BPC_12; 454 break; 455 default: 456 bpc = DSC_BPC_UNKNOWN; 457 break; 458 } 459 460 return bpc; 461 } 462 463 464 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) 465 { 466 int i; 467 468 memset(reg_vals, 0, sizeof(struct dsc_reg_values)); 469 470 /* Non-PPS values */ 471 reg_vals->dsc_clock_enable = 1; 472 reg_vals->dsc_clock_gating_disable = 0; 473 reg_vals->underflow_recovery_en = 0; 474 reg_vals->underflow_occurred_int_en = 0; 475 reg_vals->underflow_occurred_status = 0; 476 reg_vals->ich_reset_at_eol = 0; 477 reg_vals->alternate_ich_encoding_en = 0; 478 reg_vals->rc_buffer_model_size = 0; 479 /*reg_vals->disable_ich = 0;*/ 480 reg_vals->dsc_dbg_en = 0; 481 482 for (i = 0; i < 4; i++) 483 reg_vals->rc_buffer_model_overflow_int_en[i] = 0; 484 485 /* PPS values */ 486 reg_vals->pps.dsc_version_minor = 2; 487 reg_vals->pps.dsc_version_major = 1; 488 reg_vals->pps.line_buf_depth = 9; 489 reg_vals->pps.bits_per_component = 8; 490 reg_vals->pps.block_pred_enable = 1; 491 reg_vals->pps.slice_chunk_size = 0; 492 reg_vals->pps.pic_width = 0; 493 reg_vals->pps.pic_height = 0; 494 reg_vals->pps.slice_width = 0; 495 reg_vals->pps.slice_height = 0; 496 reg_vals->pps.initial_xmit_delay = 170; 497 reg_vals->pps.initial_dec_delay = 0; 498 reg_vals->pps.initial_scale_value = 0; 499 reg_vals->pps.scale_increment_interval = 0; 500 reg_vals->pps.scale_decrement_interval = 0; 501 reg_vals->pps.nfl_bpg_offset = 0; 502 reg_vals->pps.slice_bpg_offset = 0; 503 reg_vals->pps.nsl_bpg_offset = 0; 504 reg_vals->pps.initial_offset = 6144; 505 reg_vals->pps.final_offset = 0; 506 reg_vals->pps.flatness_min_qp = 3; 507 reg_vals->pps.flatness_max_qp = 12; 508 reg_vals->pps.rc_model_size = 8192; 509 reg_vals->pps.rc_edge_factor = 6; 510 reg_vals->pps.rc_quant_incr_limit0 = 11; 511 reg_vals->pps.rc_quant_incr_limit1 = 11; 512 reg_vals->pps.rc_tgt_offset_low = 3; 513 reg_vals->pps.rc_tgt_offset_high = 3; 514 } 515 516 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params. 517 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn 518 * affects non-PPS register values. 519 */ 520 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) 521 { 522 int i; 523 524 reg_vals->pps = dsc_params->pps; 525 526 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs. 527 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 528 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; 529 530 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; 531 reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf; 532 } 533 534 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 535 { 536 uint32_t temp_int; 537 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 538 539 REG_SET(DSC_DEBUG_CONTROL, 0, 540 DSC_DBG_EN, reg_vals->dsc_dbg_en); 541 542 // dsccif registers 543 REG_SET_5(DSCCIF_CONFIG0, 0, 544 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 545 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 546 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 547 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 548 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 549 550 REG_SET_2(DSCCIF_CONFIG1, 0, 551 PIC_WIDTH, reg_vals->pps.pic_width, 552 PIC_HEIGHT, reg_vals->pps.pic_height); 553 554 // dscc registers 555 REG_SET_4(DSCC_CONFIG0, 0, 556 ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol, 557 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 558 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 559 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 560 561 REG_SET(DSCC_CONFIG1, 0, 562 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 563 /*REG_SET_2(DSCC_CONFIG1, 0, 564 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 565 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 566 567 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, 568 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], 569 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], 570 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], 571 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); 572 573 REG_SET_3(DSCC_PPS_CONFIG0, 0, 574 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 575 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 576 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 577 578 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 579 temp_int = reg_vals->bpp_x32; 580 else 581 temp_int = reg_vals->bpp_x32 >> 1; 582 583 REG_SET_7(DSCC_PPS_CONFIG1, 0, 584 BITS_PER_PIXEL, temp_int, 585 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 586 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 587 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 588 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 589 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 590 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 591 592 REG_SET_2(DSCC_PPS_CONFIG2, 0, 593 PIC_WIDTH, reg_vals->pps.pic_width, 594 PIC_HEIGHT, reg_vals->pps.pic_height); 595 596 REG_SET_2(DSCC_PPS_CONFIG3, 0, 597 SLICE_WIDTH, reg_vals->pps.slice_width, 598 SLICE_HEIGHT, reg_vals->pps.slice_height); 599 600 REG_SET(DSCC_PPS_CONFIG4, 0, 601 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 602 603 REG_SET_2(DSCC_PPS_CONFIG5, 0, 604 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 605 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 606 607 REG_SET_3(DSCC_PPS_CONFIG6, 0, 608 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 609 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 610 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 611 612 REG_SET_2(DSCC_PPS_CONFIG7, 0, 613 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 614 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 615 616 REG_SET_2(DSCC_PPS_CONFIG8, 0, 617 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 618 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 619 620 REG_SET_2(DSCC_PPS_CONFIG9, 0, 621 INITIAL_OFFSET, reg_vals->pps.initial_offset, 622 FINAL_OFFSET, reg_vals->pps.final_offset); 623 624 REG_SET_3(DSCC_PPS_CONFIG10, 0, 625 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 626 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 627 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 628 629 REG_SET_5(DSCC_PPS_CONFIG11, 0, 630 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 631 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 632 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 633 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 634 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 635 636 REG_SET_4(DSCC_PPS_CONFIG12, 0, 637 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 638 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 639 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 640 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 641 642 REG_SET_4(DSCC_PPS_CONFIG13, 0, 643 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 644 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 645 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 646 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 647 648 REG_SET_4(DSCC_PPS_CONFIG14, 0, 649 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 650 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 651 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 652 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 653 654 REG_SET_5(DSCC_PPS_CONFIG15, 0, 655 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 656 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 657 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 658 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 659 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 660 661 REG_SET_6(DSCC_PPS_CONFIG16, 0, 662 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 663 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 664 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 665 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 666 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 667 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 668 669 REG_SET_6(DSCC_PPS_CONFIG17, 0, 670 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 671 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 672 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 673 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 674 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 675 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 676 677 REG_SET_6(DSCC_PPS_CONFIG18, 0, 678 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 679 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 680 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 681 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 682 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 683 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 684 685 REG_SET_6(DSCC_PPS_CONFIG19, 0, 686 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 687 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 688 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 689 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 690 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 691 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 692 693 REG_SET_6(DSCC_PPS_CONFIG20, 0, 694 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 695 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 696 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 697 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 698 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 699 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 700 701 REG_SET_6(DSCC_PPS_CONFIG21, 0, 702 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 703 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 704 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 705 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 706 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 707 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 708 709 REG_SET_6(DSCC_PPS_CONFIG22, 0, 710 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 711 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 712 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 713 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 714 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 715 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 716 717 if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) { 718 /* It's safe to do this as long as debug bus is not being used in DAL Diag environment. 719 * 720 * This is because DSCC_PPS_CONFIG4.INITIAL_DEC_DELAY is a read-only register field (because it's a decoder 721 * value not required by DSC encoder). However, since decoding fails when this value is missing from PPS, it's 722 * required to communicate this value to the PPS header. When testing on FPGA, the values for PPS header are 723 * being read from Diag register dump. The register below is used in place of a scratch register to make 724 * 'initial_dec_delay' available. 725 */ 726 727 temp_int = reg_vals->pps.initial_dec_delay; 728 REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0, 729 DSCC_TEST_DEBUG_BUS0_ROTATE, temp_int & 0x1f, 730 DSCC_TEST_DEBUG_BUS1_ROTATE, temp_int >> 5 & 0x1f, 731 DSCC_TEST_DEBUG_BUS2_ROTATE, temp_int >> 10 & 0x1f, 732 DSCC_TEST_DEBUG_BUS3_ROTATE, temp_int >> 15 & 0x1); 733 } 734 } 735 736