1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <drm/display/drm_dsc_helper.h> 27 28 #include "reg_helper.h" 29 #include "dcn20_dsc.h" 30 #include "dsc/dscc_types.h" 31 #include "dsc/rc_calc.h" 32 33 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 34 35 /* Object I/F functions */ 36 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 37 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 38 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 39 struct dsc_optc_config *dsc_optc_cfg); 40 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); 41 static void dsc2_disable(struct display_stream_compressor *dsc); 42 static void dsc2_disconnect(struct display_stream_compressor *dsc); 43 44 static const struct dsc_funcs dcn20_dsc_funcs = { 45 .dsc_get_enc_caps = dsc2_get_enc_caps, 46 .dsc_read_state = dsc2_read_state, 47 .dsc_validate_stream = dsc2_validate_stream, 48 .dsc_set_config = dsc2_set_config, 49 .dsc_get_packed_pps = dsc2_get_packed_pps, 50 .dsc_enable = dsc2_enable, 51 .dsc_disable = dsc2_disable, 52 .dsc_disconnect = dsc2_disconnect, 53 }; 54 55 /* Macro definitios for REG_SET macros*/ 56 #define CTX \ 57 dsc20->base.ctx 58 59 #define REG(reg)\ 60 dsc20->dsc_regs->reg 61 62 #undef FN 63 #define FN(reg_name, field_name) \ 64 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name 65 #define DC_LOGGER \ 66 dsc->ctx->logger 67 68 enum dsc_bits_per_comp { 69 DSC_BPC_8 = 8, 70 DSC_BPC_10 = 10, 71 DSC_BPC_12 = 12, 72 DSC_BPC_UNKNOWN 73 }; 74 75 /* API functions (external or via structure->function_pointer) */ 76 77 void dsc2_construct(struct dcn20_dsc *dsc, 78 struct dc_context *ctx, 79 int inst, 80 const struct dcn20_dsc_registers *dsc_regs, 81 const struct dcn20_dsc_shift *dsc_shift, 82 const struct dcn20_dsc_mask *dsc_mask) 83 { 84 dsc->base.ctx = ctx; 85 dsc->base.inst = inst; 86 dsc->base.funcs = &dcn20_dsc_funcs; 87 88 dsc->dsc_regs = dsc_regs; 89 dsc->dsc_shift = dsc_shift; 90 dsc->dsc_mask = dsc_mask; 91 92 dsc->max_image_width = 5184; 93 } 94 95 96 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188 97 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200 98 99 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput 100 * can be doubled, tripled etc. by using additional DSC engines. 101 */ 102 void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 103 { 104 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 105 106 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 107 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 108 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 109 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 110 111 dsc_enc_caps->lb_bit_depth = 13; 112 dsc_enc_caps->is_block_pred_supported = true; 113 114 dsc_enc_caps->color_formats.bits.RGB = 1; 115 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 116 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 117 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 118 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 119 120 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 121 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 122 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 123 124 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. 125 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. 126 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always 127 * be sufficient to process the input pixel rate fed into a single DSC engine. 128 */ 129 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; 130 131 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our 132 * throughput and number of slices, but also introduces a lower limit of 2 slices 133 */ 134 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) { 135 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0; 136 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 137 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 138 } 139 140 // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM. 141 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 142 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 143 } 144 145 146 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 147 * into a dcn_dsc_state struct. 148 */ 149 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 150 { 151 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 152 153 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 154 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 155 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); 156 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); 157 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); 158 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); 159 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); 160 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); 161 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en, 162 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source); 163 } 164 165 166 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 167 { 168 struct dsc_optc_config dsc_optc_cfg; 169 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 170 171 if (dsc_cfg->pic_width > dsc20->max_image_width) 172 return false; 173 174 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); 175 } 176 177 178 void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) 179 { 180 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); 181 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); 182 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", 183 config->dc_dsc_cfg.bits_per_pixel, 184 config->dc_dsc_cfg.bits_per_pixel / 16, 185 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); 186 DC_LOG_DSC("\tcolor_depth %d", config->color_depth); 187 } 188 189 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 190 struct dsc_optc_config *dsc_optc_cfg) 191 { 192 bool is_config_ok; 193 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 194 195 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 196 dsc_config_log(dsc, dsc_cfg); 197 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); 198 ASSERT(is_config_ok); 199 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 200 dsc_log_pps(dsc, &dsc20->reg_vals.pps); 201 dsc_write_to_registers(dsc, &dsc20->reg_vals); 202 } 203 204 205 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) 206 { 207 bool is_config_ok; 208 struct dsc_reg_values dsc_reg_vals; 209 struct dsc_optc_config dsc_optc_cfg; 210 211 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals)); 212 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg)); 213 214 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); 215 dsc_config_log(dsc, dsc_cfg); 216 DC_LOG_DSC("DSC Picture Parameter Set (PPS):"); 217 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); 218 ASSERT(is_config_ok); 219 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); 220 dsc_log_pps(dsc, &dsc_reg_vals.pps); 221 222 return is_config_ok; 223 } 224 225 226 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) 227 { 228 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 229 int dsc_clock_en; 230 int dsc_fw_config; 231 int enabled_opp_pipe; 232 233 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 234 235 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 236 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 237 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 238 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 239 ASSERT(0); 240 } 241 242 REG_UPDATE(DSC_TOP_CONTROL, 243 DSC_CLOCK_EN, 1); 244 245 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 246 DSCRM_DSC_FORWARD_EN, 1, 247 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 248 } 249 250 251 static void dsc2_disable(struct display_stream_compressor *dsc) 252 { 253 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 254 int dsc_clock_en; 255 int dsc_fw_config; 256 int enabled_opp_pipe; 257 258 DC_LOG_DSC("disable DSC %d", dsc->inst); 259 260 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 261 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 262 if (!dsc_clock_en || !dsc_fw_config) { 263 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe); 264 ASSERT(0); 265 } 266 267 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 268 DSCRM_DSC_FORWARD_EN, 0); 269 270 REG_UPDATE(DSC_TOP_CONTROL, 271 DSC_CLOCK_EN, 0); 272 } 273 274 static void dsc2_disconnect(struct display_stream_compressor *dsc) 275 { 276 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 277 278 DC_LOG_DSC("disconnect DSC %d", dsc->inst); 279 280 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 281 DSCRM_DSC_FORWARD_EN, 0); 282 } 283 284 /* This module's internal functions */ 285 void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) 286 { 287 int i; 288 int bits_per_pixel = pps->bits_per_pixel; 289 290 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); 291 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); 292 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); 293 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); 294 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); 295 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); 296 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); 297 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); 298 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); 299 DC_LOG_DSC("\tpic_height %d", pps->pic_height); 300 DC_LOG_DSC("\tpic_width %d", pps->pic_width); 301 DC_LOG_DSC("\tslice_height %d", pps->slice_height); 302 DC_LOG_DSC("\tslice_width %d", pps->slice_width); 303 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); 304 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); 305 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); 306 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); 307 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); 308 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); 309 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); 310 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); 311 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); 312 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); 313 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); 314 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); 315 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); 316 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */ 317 DC_LOG_DSC("\tnative_420 %d", pps->native_420); 318 DC_LOG_DSC("\tnative_422 %d", pps->native_422); 319 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); 320 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); 321 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); 322 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); 323 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); 324 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); 325 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); 326 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); 327 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); 328 329 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 330 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); 331 332 for (i = 0; i < NUM_BUF_RANGES; i++) { 333 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); 334 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); 335 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); 336 } 337 } 338 339 void dsc_override_rc_params(struct rc_params *rc, const struct dc_dsc_rc_params_override *override) 340 { 341 uint8_t i; 342 343 rc->rc_model_size = override->rc_model_size; 344 for (i = 0; i < DC_DSC_RC_BUF_THRESH_SIZE; i++) 345 rc->rc_buf_thresh[i] = override->rc_buf_thresh[i]; 346 for (i = 0; i < DC_DSC_QP_SET_SIZE; i++) { 347 rc->qp_min[i] = override->rc_minqp[i]; 348 rc->qp_max[i] = override->rc_maxqp[i]; 349 rc->ofs[i] = override->rc_offset[i]; 350 } 351 352 rc->rc_tgt_offset_hi = override->rc_tgt_offset_hi; 353 rc->rc_tgt_offset_lo = override->rc_tgt_offset_lo; 354 rc->rc_edge_factor = override->rc_edge_factor; 355 rc->rc_quant_incr_limit0 = override->rc_quant_incr_limit0; 356 rc->rc_quant_incr_limit1 = override->rc_quant_incr_limit1; 357 358 rc->initial_fullness_offset = override->initial_fullness_offset; 359 rc->initial_xmit_delay = override->initial_delay; 360 361 rc->flatness_min_qp = override->flatness_min_qp; 362 rc->flatness_max_qp = override->flatness_max_qp; 363 rc->flatness_det_thresh = override->flatness_det_thresh; 364 } 365 366 bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 367 struct dsc_optc_config *dsc_optc_cfg) 368 { 369 struct dsc_parameters dsc_params; 370 struct rc_params rc; 371 372 /* Validate input parameters */ 373 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); 374 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); 375 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); 376 ASSERT(dsc_cfg->pic_width); 377 ASSERT(dsc_cfg->pic_height); 378 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && 379 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || 380 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && 381 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 382 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); 383 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 384 385 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || 386 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || 387 !dsc_cfg->pic_width || !dsc_cfg->pic_height || 388 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: 389 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || 390 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: 391 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 392 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || 393 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { 394 dm_output_to_console("%s: Invalid parameters\n", __func__); 395 return false; 396 } 397 398 dsc_init_reg_values(dsc_reg_vals); 399 400 /* Copy input config */ 401 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); 402 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; 403 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; 404 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; 405 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; 406 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; 407 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); 408 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; 409 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; 410 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; 411 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0; 412 413 // TODO: in addition to validating slice height (pic height must be divisible by slice height), 414 // see what happens when the same condition doesn't apply for slice_width/pic_width. 415 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; 416 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; 417 418 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); 419 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { 420 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); 421 return false; 422 } 423 424 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; 425 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 426 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; 427 else 428 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; 429 430 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; 431 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); 432 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); 433 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); 434 435 calc_rc_params(&rc, &dsc_reg_vals->pps); 436 437 if (dsc_cfg->dc_dsc_cfg.rc_params_ovrd) 438 dsc_override_rc_params(&rc, dsc_cfg->dc_dsc_cfg.rc_params_ovrd); 439 440 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &rc, &dsc_params)) { 441 dm_output_to_console("%s: DSC config failed\n", __func__); 442 return false; 443 } 444 445 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); 446 447 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; 448 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; 449 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || 450 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || 451 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; 452 453 return true; 454 } 455 456 457 enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple) 458 { 459 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 460 461 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */ 462 463 switch (dc_pix_enc) { 464 case PIXEL_ENCODING_RGB: 465 dsc_pix_fmt = DSC_PIXFMT_RGB; 466 break; 467 case PIXEL_ENCODING_YCBCR422: 468 if (is_ycbcr422_simple) 469 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422; 470 else 471 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422; 472 break; 473 case PIXEL_ENCODING_YCBCR444: 474 dsc_pix_fmt = DSC_PIXFMT_YCBCR444; 475 break; 476 case PIXEL_ENCODING_YCBCR420: 477 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420; 478 break; 479 default: 480 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 481 break; 482 } 483 484 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN); 485 return dsc_pix_fmt; 486 } 487 488 489 enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth) 490 { 491 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; 492 493 switch (dc_color_depth) { 494 case COLOR_DEPTH_888: 495 bpc = DSC_BPC_8; 496 break; 497 case COLOR_DEPTH_101010: 498 bpc = DSC_BPC_10; 499 break; 500 case COLOR_DEPTH_121212: 501 bpc = DSC_BPC_12; 502 break; 503 default: 504 bpc = DSC_BPC_UNKNOWN; 505 break; 506 } 507 508 return bpc; 509 } 510 511 512 void dsc_init_reg_values(struct dsc_reg_values *reg_vals) 513 { 514 int i; 515 516 memset(reg_vals, 0, sizeof(struct dsc_reg_values)); 517 518 /* Non-PPS values */ 519 reg_vals->dsc_clock_enable = 1; 520 reg_vals->dsc_clock_gating_disable = 0; 521 reg_vals->underflow_recovery_en = 0; 522 reg_vals->underflow_occurred_int_en = 0; 523 reg_vals->underflow_occurred_status = 0; 524 reg_vals->ich_reset_at_eol = 0; 525 reg_vals->alternate_ich_encoding_en = 0; 526 reg_vals->rc_buffer_model_size = 0; 527 /*reg_vals->disable_ich = 0;*/ 528 reg_vals->dsc_dbg_en = 0; 529 530 for (i = 0; i < 4; i++) 531 reg_vals->rc_buffer_model_overflow_int_en[i] = 0; 532 533 /* PPS values */ 534 reg_vals->pps.dsc_version_minor = 2; 535 reg_vals->pps.dsc_version_major = 1; 536 reg_vals->pps.line_buf_depth = 9; 537 reg_vals->pps.bits_per_component = 8; 538 reg_vals->pps.block_pred_enable = 1; 539 reg_vals->pps.slice_chunk_size = 0; 540 reg_vals->pps.pic_width = 0; 541 reg_vals->pps.pic_height = 0; 542 reg_vals->pps.slice_width = 0; 543 reg_vals->pps.slice_height = 0; 544 reg_vals->pps.initial_xmit_delay = 170; 545 reg_vals->pps.initial_dec_delay = 0; 546 reg_vals->pps.initial_scale_value = 0; 547 reg_vals->pps.scale_increment_interval = 0; 548 reg_vals->pps.scale_decrement_interval = 0; 549 reg_vals->pps.nfl_bpg_offset = 0; 550 reg_vals->pps.slice_bpg_offset = 0; 551 reg_vals->pps.nsl_bpg_offset = 0; 552 reg_vals->pps.initial_offset = 6144; 553 reg_vals->pps.final_offset = 0; 554 reg_vals->pps.flatness_min_qp = 3; 555 reg_vals->pps.flatness_max_qp = 12; 556 reg_vals->pps.rc_model_size = 8192; 557 reg_vals->pps.rc_edge_factor = 6; 558 reg_vals->pps.rc_quant_incr_limit0 = 11; 559 reg_vals->pps.rc_quant_incr_limit1 = 11; 560 reg_vals->pps.rc_tgt_offset_low = 3; 561 reg_vals->pps.rc_tgt_offset_high = 3; 562 } 563 564 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params. 565 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn 566 * affects non-PPS register values. 567 */ 568 void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) 569 { 570 int i; 571 572 reg_vals->pps = dsc_params->pps; 573 574 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs. 575 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 576 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; 577 578 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; 579 } 580 581 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 582 { 583 uint32_t temp_int; 584 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 585 586 REG_SET(DSC_DEBUG_CONTROL, 0, 587 DSC_DBG_EN, reg_vals->dsc_dbg_en); 588 589 // dsccif registers 590 REG_SET_5(DSCCIF_CONFIG0, 0, 591 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 592 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 593 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 594 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 595 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 596 597 REG_SET_2(DSCCIF_CONFIG1, 0, 598 PIC_WIDTH, reg_vals->pps.pic_width, 599 PIC_HEIGHT, reg_vals->pps.pic_height); 600 601 // dscc registers 602 if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) { 603 REG_SET_3(DSCC_CONFIG0, 0, 604 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 605 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 606 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 607 } else { 608 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, 609 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE, 610 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, 611 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, 612 reg_vals->num_slices_v - 1); 613 } 614 615 REG_SET(DSCC_CONFIG1, 0, 616 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 617 /*REG_SET_2(DSCC_CONFIG1, 0, 618 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 619 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 620 621 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, 622 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], 623 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], 624 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], 625 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); 626 627 REG_SET_3(DSCC_PPS_CONFIG0, 0, 628 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 629 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 630 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 631 632 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 633 temp_int = reg_vals->bpp_x32; 634 else 635 temp_int = reg_vals->bpp_x32 >> 1; 636 637 REG_SET_7(DSCC_PPS_CONFIG1, 0, 638 BITS_PER_PIXEL, temp_int, 639 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 640 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 641 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 642 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 643 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 644 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 645 646 REG_SET_2(DSCC_PPS_CONFIG2, 0, 647 PIC_WIDTH, reg_vals->pps.pic_width, 648 PIC_HEIGHT, reg_vals->pps.pic_height); 649 650 REG_SET_2(DSCC_PPS_CONFIG3, 0, 651 SLICE_WIDTH, reg_vals->pps.slice_width, 652 SLICE_HEIGHT, reg_vals->pps.slice_height); 653 654 REG_SET(DSCC_PPS_CONFIG4, 0, 655 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 656 657 REG_SET_2(DSCC_PPS_CONFIG5, 0, 658 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 659 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 660 661 REG_SET_3(DSCC_PPS_CONFIG6, 0, 662 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 663 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 664 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 665 666 REG_SET_2(DSCC_PPS_CONFIG7, 0, 667 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 668 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 669 670 REG_SET_2(DSCC_PPS_CONFIG8, 0, 671 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 672 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 673 674 REG_SET_2(DSCC_PPS_CONFIG9, 0, 675 INITIAL_OFFSET, reg_vals->pps.initial_offset, 676 FINAL_OFFSET, reg_vals->pps.final_offset); 677 678 REG_SET_3(DSCC_PPS_CONFIG10, 0, 679 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 680 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 681 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 682 683 REG_SET_5(DSCC_PPS_CONFIG11, 0, 684 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 685 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 686 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 687 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 688 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 689 690 REG_SET_4(DSCC_PPS_CONFIG12, 0, 691 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 692 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 693 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 694 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 695 696 REG_SET_4(DSCC_PPS_CONFIG13, 0, 697 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 698 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 699 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 700 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 701 702 REG_SET_4(DSCC_PPS_CONFIG14, 0, 703 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 704 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 705 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 706 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 707 708 REG_SET_5(DSCC_PPS_CONFIG15, 0, 709 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 710 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 711 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 712 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 713 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 714 715 REG_SET_6(DSCC_PPS_CONFIG16, 0, 716 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 717 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 718 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 719 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 720 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 721 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 722 723 REG_SET_6(DSCC_PPS_CONFIG17, 0, 724 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 725 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 726 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 727 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 728 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 729 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 730 731 REG_SET_6(DSCC_PPS_CONFIG18, 0, 732 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 733 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 734 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 735 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 736 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 737 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 738 739 REG_SET_6(DSCC_PPS_CONFIG19, 0, 740 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 741 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 742 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 743 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 744 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 745 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 746 747 REG_SET_6(DSCC_PPS_CONFIG20, 0, 748 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 749 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 750 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 751 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 752 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 753 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 754 755 REG_SET_6(DSCC_PPS_CONFIG21, 0, 756 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 757 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 758 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 759 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 760 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 761 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 762 763 REG_SET_6(DSCC_PPS_CONFIG22, 0, 764 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 765 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 766 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 767 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 768 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 769 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 770 771 } 772 773