1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 27 #include "reg_helper.h" 28 #include "dcn20_dsc.h" 29 #include "dsc/dscc_types.h" 30 31 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); 32 static bool dsc_prepare_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 33 struct dsc_optc_config *dsc_optc_cfg); 34 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals); 35 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params); 36 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 37 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple); 38 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth); 39 40 /* Object I/F functions */ 41 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 42 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 43 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 44 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 45 struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps); 46 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); 47 static void dsc2_disable(struct display_stream_compressor *dsc); 48 49 const struct dsc_funcs dcn20_dsc_funcs = { 50 .dsc_get_enc_caps = dsc2_get_enc_caps, 51 .dsc_read_state = dsc2_read_state, 52 .dsc_validate_stream = dsc2_validate_stream, 53 .dsc_set_config = dsc2_set_config, 54 .dsc_enable = dsc2_enable, 55 .dsc_disable = dsc2_disable, 56 }; 57 58 /* Macro definitios for REG_SET macros*/ 59 #define CTX \ 60 dsc20->base.ctx 61 62 #define REG(reg)\ 63 dsc20->dsc_regs->reg 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name 68 #define DC_LOGGER \ 69 dsc->ctx->logger 70 71 enum dsc_bits_per_comp { 72 DSC_BPC_8 = 8, 73 DSC_BPC_10 = 10, 74 DSC_BPC_12 = 12, 75 DSC_BPC_UNKNOWN 76 }; 77 78 /* API functions (external or via structure->function_pointer) */ 79 80 void dsc2_construct(struct dcn20_dsc *dsc, 81 struct dc_context *ctx, 82 int inst, 83 const struct dcn20_dsc_registers *dsc_regs, 84 const struct dcn20_dsc_shift *dsc_shift, 85 const struct dcn20_dsc_mask *dsc_mask) 86 { 87 dsc->base.ctx = ctx; 88 dsc->base.inst = inst; 89 dsc->base.funcs = &dcn20_dsc_funcs; 90 91 dsc->dsc_regs = dsc_regs; 92 dsc->dsc_shift = dsc_shift; 93 dsc->dsc_mask = dsc_mask; 94 95 dsc->max_image_width = 5184; 96 } 97 98 99 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188 100 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200 101 102 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput 103 * can be doubled, tripled etc. by using additional DSC engines. 104 */ 105 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 106 { 107 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 108 109 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 110 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 111 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 112 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 113 114 dsc_enc_caps->lb_bit_depth = 13; 115 dsc_enc_caps->is_block_pred_supported = true; 116 117 dsc_enc_caps->color_formats.bits.RGB = 1; 118 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 119 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 120 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; 121 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 122 123 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 124 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 125 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 126 127 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. 128 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. 129 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always 130 * be sufficient to process the input pixel rate fed into a single DSC engine. 131 */ 132 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; 133 134 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our 135 * throughput and number of slices, but also introduces a lower limit of 2 slices 136 */ 137 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) { 138 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0; 139 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 140 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 141 } 142 143 // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM. 144 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 145 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 146 } 147 148 149 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 150 * into a dcn_dsc_state struct. 151 */ 152 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 153 { 154 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 155 156 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 157 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 158 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bytes_per_pixel); 159 } 160 161 162 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 163 { 164 struct dsc_optc_config dsc_optc_cfg; 165 166 if (dsc_cfg->pic_width > TO_DCN20_DSC(dsc)->max_image_width) 167 return false; 168 169 return dsc_prepare_config(dsc, dsc_cfg, &dsc_optc_cfg); 170 } 171 172 173 static void dsc_config_log(struct display_stream_compressor *dsc, 174 const struct dsc_config *config) 175 { 176 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 177 DC_LOG_DSC("\n\tnum_slices_h %d\n\tnum_slices_v %d\n\tbits_per_pixel %d\n\tcolor_depth %d", 178 config->dc_dsc_cfg.num_slices_h, 179 config->dc_dsc_cfg.num_slices_v, 180 config->dc_dsc_cfg.bits_per_pixel, 181 config->color_depth); 182 } 183 184 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 185 struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps) 186 { 187 bool is_config_ok; 188 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 189 190 dsc_config_log(dsc, dsc_cfg); 191 is_config_ok = dsc_prepare_config(dsc, dsc_cfg, dsc_optc_cfg); 192 ASSERT(is_config_ok); 193 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc20->reg_vals.pps); 194 dsc_log_pps(dsc, &dsc20->reg_vals.pps); 195 dsc_write_to_registers(dsc, &dsc20->reg_vals); 196 } 197 198 199 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) 200 { 201 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 202 203 /* TODO Check if DSC alreay in use? */ 204 DC_LOG_DSC("enable DSC at opp pipe %d", opp_pipe); 205 206 REG_UPDATE(DSC_TOP_CONTROL, 207 DSC_CLOCK_EN, 1); 208 209 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 210 DSCRM_DSC_FORWARD_EN, 1, 211 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 212 } 213 214 215 static void dsc2_disable(struct display_stream_compressor *dsc) 216 { 217 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 218 219 DC_LOG_DSC("disable DSC"); 220 221 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 222 DSCRM_DSC_FORWARD_EN, 0); 223 224 REG_UPDATE(DSC_TOP_CONTROL, 225 DSC_CLOCK_EN, 0); 226 } 227 228 229 /* This module's internal functions */ 230 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) 231 { 232 int i; 233 int bits_per_pixel = pps->bits_per_pixel; 234 235 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 236 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); 237 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); 238 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); 239 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); 240 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); 241 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); 242 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); 243 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); 244 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); 245 DC_LOG_DSC("\tpic_height %d", pps->pic_height); 246 DC_LOG_DSC("\tpic_width %d", pps->pic_width); 247 DC_LOG_DSC("\tslice_height %d", pps->slice_height); 248 DC_LOG_DSC("\tslice_width %d", pps->slice_width); 249 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); 250 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); 251 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); 252 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); 253 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); 254 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); 255 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); 256 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); 257 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); 258 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); 259 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); 260 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); 261 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); 262 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */ 263 DC_LOG_DSC("\tnative_420 %d", pps->native_420); 264 DC_LOG_DSC("\tnative_422 %d", pps->native_422); 265 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); 266 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); 267 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); 268 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); 269 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); 270 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); 271 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); 272 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); 273 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); 274 275 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 276 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); 277 278 for (i = 0; i < NUM_BUF_RANGES; i++) { 279 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); 280 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); 281 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); 282 } 283 } 284 285 static bool dsc_prepare_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 286 struct dsc_optc_config *dsc_optc_cfg) 287 { 288 struct dsc_parameters dsc_params; 289 290 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 291 292 /* Validate input parameters */ 293 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); 294 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); 295 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); 296 ASSERT(dsc_cfg->pic_width); 297 ASSERT(dsc_cfg->pic_height); 298 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && 299 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || 300 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && 301 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 302 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); 303 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 304 305 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_v || 306 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || 307 !dsc_cfg->pic_width || !dsc_cfg->pic_height || 308 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: 309 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || 310 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: 311 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 312 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || 313 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { 314 dm_output_to_console("%s: Invalid parameters\n", __func__); 315 return false; 316 } 317 318 dsc_init_reg_values(&dsc20->reg_vals); 319 320 /* Copy input config */ 321 dsc20->reg_vals.pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); 322 dsc20->reg_vals.num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; 323 dsc20->reg_vals.num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; 324 dsc20->reg_vals.pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; 325 dsc20->reg_vals.pps.pic_width = dsc_cfg->pic_width; 326 dsc20->reg_vals.pps.pic_height = dsc_cfg->pic_height; 327 dsc20->reg_vals.pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); 328 dsc20->reg_vals.pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; 329 dsc20->reg_vals.pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; 330 dsc20->reg_vals.alternate_ich_encoding_en = dsc20->reg_vals.pps.dsc_version_minor == 1 ? 0 : 1; 331 332 // TODO: in addition to validating slice height (pic height must be divisible by slice height), 333 // see what happens when the same condition doesn't apply for slice_width/pic_width. 334 dsc20->reg_vals.pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; 335 dsc20->reg_vals.pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; 336 337 ASSERT(dsc20->reg_vals.pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); 338 if (!(dsc20->reg_vals.pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { 339 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); 340 return false; 341 } 342 343 dsc20->reg_vals.bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; 344 if (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 345 dsc20->reg_vals.pps.bits_per_pixel = dsc20->reg_vals.bpp_x32; 346 else 347 dsc20->reg_vals.pps.bits_per_pixel = dsc20->reg_vals.bpp_x32 >> 1; 348 349 dsc20->reg_vals.pps.convert_rgb = dsc20->reg_vals.pixel_format == DSC_PIXFMT_RGB ? 1 : 0; 350 dsc20->reg_vals.pps.native_422 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); 351 dsc20->reg_vals.pps.native_420 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); 352 dsc20->reg_vals.pps.simple_422 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); 353 354 if (dscc_compute_dsc_parameters(&dsc20->reg_vals.pps, &dsc_params)) { 355 dm_output_to_console("%s: DSC config failed\n", __func__); 356 return false; 357 } 358 359 dsc_update_from_dsc_parameters(&dsc20->reg_vals, &dsc_params); 360 361 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; 362 dsc_optc_cfg->slice_width = dsc20->reg_vals.pps.slice_width; 363 dsc_optc_cfg->is_pixel_format_444 = dsc20->reg_vals.pixel_format == DSC_PIXFMT_RGB || 364 dsc20->reg_vals.pixel_format == DSC_PIXFMT_YCBCR444 || 365 dsc20->reg_vals.pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; 366 367 return true; 368 } 369 370 371 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple) 372 { 373 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 374 375 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */ 376 377 switch (dc_pix_enc) { 378 case PIXEL_ENCODING_RGB: 379 dsc_pix_fmt = DSC_PIXFMT_RGB; 380 break; 381 case PIXEL_ENCODING_YCBCR422: 382 if (is_ycbcr422_simple) 383 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422; 384 else 385 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422; 386 break; 387 case PIXEL_ENCODING_YCBCR444: 388 dsc_pix_fmt = DSC_PIXFMT_YCBCR444; 389 break; 390 case PIXEL_ENCODING_YCBCR420: 391 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420; 392 break; 393 default: 394 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 395 break; 396 } 397 398 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN); 399 return dsc_pix_fmt; 400 } 401 402 403 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth) 404 { 405 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; 406 407 switch (dc_color_depth) { 408 case COLOR_DEPTH_888: 409 bpc = DSC_BPC_8; 410 break; 411 case COLOR_DEPTH_101010: 412 bpc = DSC_BPC_10; 413 break; 414 case COLOR_DEPTH_121212: 415 bpc = DSC_BPC_12; 416 break; 417 default: 418 bpc = DSC_BPC_UNKNOWN; 419 break; 420 } 421 422 return bpc; 423 } 424 425 426 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) 427 { 428 int i; 429 430 /* Non-PPS values */ 431 reg_vals->dsc_clock_enable = 1; 432 reg_vals->dsc_clock_gating_disable = 0; 433 reg_vals->underflow_recovery_en = 0; 434 reg_vals->underflow_occurred_int_en = 0; 435 reg_vals->underflow_occurred_status = 0; 436 reg_vals->ich_reset_at_eol = 0; 437 reg_vals->alternate_ich_encoding_en = 0; 438 reg_vals->rc_buffer_model_size = 0; 439 reg_vals->disable_ich = 0; 440 reg_vals->dsc_dbg_en = 0; 441 442 for (i = 0; i < 4; i++) 443 reg_vals->rc_buffer_model_overflow_int_en[i] = 0; 444 445 /* PPS values */ 446 reg_vals->pps.dsc_version_minor = 2; 447 reg_vals->pps.dsc_version_major = 1; 448 reg_vals->pps.line_buf_depth = 9; 449 reg_vals->pps.bits_per_component = 8; 450 reg_vals->pps.block_pred_enable = 1; 451 reg_vals->pps.slice_chunk_size = 0; 452 reg_vals->pps.pic_width = 0; 453 reg_vals->pps.pic_height = 0; 454 reg_vals->pps.slice_width = 0; 455 reg_vals->pps.slice_height = 0; 456 reg_vals->pps.initial_xmit_delay = 170; 457 reg_vals->pps.initial_dec_delay = 0; 458 reg_vals->pps.initial_scale_value = 0; 459 reg_vals->pps.scale_increment_interval = 0; 460 reg_vals->pps.scale_decrement_interval = 0; 461 reg_vals->pps.nfl_bpg_offset = 0; 462 reg_vals->pps.slice_bpg_offset = 0; 463 reg_vals->pps.nsl_bpg_offset = 0; 464 reg_vals->pps.initial_offset = 6144; 465 reg_vals->pps.final_offset = 0; 466 reg_vals->pps.flatness_min_qp = 3; 467 reg_vals->pps.flatness_max_qp = 12; 468 reg_vals->pps.rc_model_size = 8192; 469 reg_vals->pps.rc_edge_factor = 6; 470 reg_vals->pps.rc_quant_incr_limit0 = 11; 471 reg_vals->pps.rc_quant_incr_limit1 = 11; 472 reg_vals->pps.rc_tgt_offset_low = 3; 473 reg_vals->pps.rc_tgt_offset_high = 3; 474 } 475 476 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params. 477 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn 478 * affects non-PPS register values. 479 */ 480 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) 481 { 482 int i; 483 484 reg_vals->pps = dsc_params->pps; 485 486 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs. 487 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 488 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; 489 490 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; 491 reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf; 492 } 493 494 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 495 { 496 uint32_t temp_int; 497 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 498 499 REG_SET(DSC_DEBUG_CONTROL, 0, 500 DSC_DBG_EN, reg_vals->dsc_dbg_en); 501 502 // dsccif registers 503 REG_SET_5(DSCCIF_CONFIG0, 0, 504 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 505 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 506 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 507 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 508 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 509 510 REG_SET_2(DSCCIF_CONFIG1, 0, 511 PIC_WIDTH, reg_vals->pps.pic_width, 512 PIC_HEIGHT, reg_vals->pps.pic_height); 513 514 // dscc registers 515 REG_SET_4(DSCC_CONFIG0, 0, 516 ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol, 517 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 518 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 519 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 520 521 REG_SET_2(DSCC_CONFIG1, 0, 522 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 523 DSCC_DISABLE_ICH, reg_vals->disable_ich); 524 525 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, 526 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], 527 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], 528 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], 529 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); 530 531 REG_SET_3(DSCC_PPS_CONFIG0, 0, 532 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 533 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 534 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 535 536 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 537 temp_int = reg_vals->bpp_x32; 538 else 539 temp_int = reg_vals->bpp_x32 >> 1; 540 541 REG_SET_7(DSCC_PPS_CONFIG1, 0, 542 BITS_PER_PIXEL, temp_int, 543 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 544 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 545 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 546 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 547 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 548 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 549 550 REG_SET_2(DSCC_PPS_CONFIG2, 0, 551 PIC_WIDTH, reg_vals->pps.pic_width, 552 PIC_HEIGHT, reg_vals->pps.pic_height); 553 554 REG_SET_2(DSCC_PPS_CONFIG3, 0, 555 SLICE_WIDTH, reg_vals->pps.slice_width, 556 SLICE_HEIGHT, reg_vals->pps.slice_height); 557 558 REG_SET(DSCC_PPS_CONFIG4, 0, 559 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 560 561 REG_SET_2(DSCC_PPS_CONFIG5, 0, 562 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 563 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 564 565 REG_SET_3(DSCC_PPS_CONFIG6, 0, 566 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 567 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 568 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 569 570 REG_SET_2(DSCC_PPS_CONFIG7, 0, 571 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 572 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 573 574 REG_SET_2(DSCC_PPS_CONFIG8, 0, 575 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 576 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 577 578 REG_SET_2(DSCC_PPS_CONFIG9, 0, 579 INITIAL_OFFSET, reg_vals->pps.initial_offset, 580 FINAL_OFFSET, reg_vals->pps.final_offset); 581 582 REG_SET_3(DSCC_PPS_CONFIG10, 0, 583 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 584 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 585 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 586 587 REG_SET_5(DSCC_PPS_CONFIG11, 0, 588 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 589 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 590 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 591 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 592 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 593 594 REG_SET_4(DSCC_PPS_CONFIG12, 0, 595 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 596 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 597 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 598 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 599 600 REG_SET_4(DSCC_PPS_CONFIG13, 0, 601 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 602 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 603 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 604 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 605 606 REG_SET_4(DSCC_PPS_CONFIG14, 0, 607 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 608 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 609 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 610 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 611 612 REG_SET_5(DSCC_PPS_CONFIG15, 0, 613 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 614 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 615 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 616 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 617 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 618 619 REG_SET_6(DSCC_PPS_CONFIG16, 0, 620 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 621 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 622 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 623 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 624 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 625 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 626 627 REG_SET_6(DSCC_PPS_CONFIG17, 0, 628 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 629 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 630 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 631 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 632 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 633 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 634 635 REG_SET_6(DSCC_PPS_CONFIG18, 0, 636 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 637 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 638 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 639 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 640 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 641 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 642 643 REG_SET_6(DSCC_PPS_CONFIG19, 0, 644 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 645 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 646 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 647 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 648 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 649 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 650 651 REG_SET_6(DSCC_PPS_CONFIG20, 0, 652 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 653 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 654 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 655 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 656 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 657 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 658 659 REG_SET_6(DSCC_PPS_CONFIG21, 0, 660 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 661 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 662 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 663 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 664 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 665 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 666 667 REG_SET_6(DSCC_PPS_CONFIG22, 0, 668 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 669 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 670 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 671 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 672 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 673 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 674 675 if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) { 676 /* It's safe to do this as long as debug bus is not being used in DAL Diag environment. 677 * 678 * This is because DSCC_PPS_CONFIG4.INITIAL_DEC_DELAY is a read-only register field (because it's a decoder 679 * value not required by DSC encoder). However, since decoding fails when this value is missing from PPS, it's 680 * required to communicate this value to the PPS header. When testing on FPGA, the values for PPS header are 681 * being read from Diag register dump. The register below is used in place of a scratch register to make 682 * 'initial_dec_delay' available. 683 */ 684 685 temp_int = reg_vals->pps.initial_dec_delay; 686 REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0, 687 DSCC_TEST_DEBUG_BUS0_ROTATE, temp_int & 0x1f, 688 DSCC_TEST_DEBUG_BUS1_ROTATE, temp_int >> 5 & 0x1f, 689 DSCC_TEST_DEBUG_BUS2_ROTATE, temp_int >> 10 & 0x1f, 690 DSCC_TEST_DEBUG_BUS3_ROTATE, temp_int >> 15 & 0x1); 691 } 692 } 693 694 #endif 695