1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "core_types.h" 29 30 #include "reg_helper.h" 31 #include "dcn20_dpp.h" 32 #include "basics/conversion.h" 33 34 #define NUM_PHASES 64 35 #define HORZ_MAX_TAPS 8 36 #define VERT_MAX_TAPS 8 37 38 #define BLACK_OFFSET_RGB_Y 0x0 39 #define BLACK_OFFSET_CBCR 0x8000 40 41 #define REG(reg)\ 42 dpp->tf_regs->reg 43 44 #define CTX \ 45 dpp->base.ctx 46 47 #undef FN 48 #define FN(reg_name, field_name) \ 49 dpp->tf_shift->field_name, dpp->tf_mask->field_name 50 51 void dpp20_read_state(struct dpp *dpp_base, 52 struct dcn_dpp_state *s) 53 { 54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 55 56 REG_GET(DPP_CONTROL, 57 DPP_CLOCK_ENABLE, &s->is_enabled); 58 REG_GET(CM_DGAM_CONTROL, 59 CM_DGAM_LUT_MODE, &s->dgam_lut_mode); 60 // BGAM has no ROM, and definition is different, can't reuse same dump 61 //REG_GET(CM_BLNDGAM_CONTROL, 62 // CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode); 63 REG_GET(CM_GAMUT_REMAP_CONTROL, 64 CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode); 65 if (s->gamut_remap_mode) { 66 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); 67 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); 68 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); 69 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); 70 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); 71 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); 72 } 73 } 74 75 void dpp2_power_on_obuf( 76 struct dpp *dpp_base, 77 bool power_on) 78 { 79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 80 81 REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); 82 83 REG_UPDATE(OBUF_MEM_PWR_CTRL, 84 OBUF_MEM_PWR_FORCE, power_on == true ? 0:1); 85 86 REG_UPDATE(DSCL_MEM_PWR_CTRL, 87 LUT_MEM_PWR_FORCE, power_on == true ? 0:1); 88 } 89 90 void dpp2_dummy_program_input_lut( 91 struct dpp *dpp_base, 92 const struct dc_gamma *gamma) 93 {} 94 95 static void dpp2_cnv_setup ( 96 struct dpp *dpp_base, 97 enum surface_pixel_format format, 98 enum expansion_mode mode, 99 struct dc_csc_transform input_csc_color_matrix, 100 enum dc_color_space input_color_space, 101 struct cnv_alpha_2bit_lut *alpha_2bit_lut) 102 { 103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 104 uint32_t pixel_format = 0; 105 uint32_t alpha_en = 1; 106 enum dc_color_space color_space = COLOR_SPACE_SRGB; 107 enum dcn20_input_csc_select select = DCN2_ICSC_SELECT_BYPASS; 108 bool force_disable_cursor = false; 109 struct out_csc_color_matrix tbl_entry; 110 uint32_t is_2bit = 0; 111 int i = 0; 112 113 REG_SET_2(FORMAT_CONTROL, 0, 114 CNVC_BYPASS, 0, 115 FORMAT_EXPANSION_MODE, mode); 116 117 //hardcode default 118 //FORMAT_CONTROL. FORMAT_CNV16 default 0: U0.16/S.1.15; 1: U1.15/ S.1.14 119 //FORMAT_CONTROL. CNVC_BYPASS_MSB_ALIGN default 0: disabled 1: enabled 120 //FORMAT_CONTROL. CLAMP_POSITIVE default 0: disabled 1: enabled 121 //FORMAT_CONTROL. CLAMP_POSITIVE_C default 0: disabled 1: enabled 122 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); 123 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); 124 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); 125 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); 126 127 switch (format) { 128 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 129 pixel_format = 1; 130 break; 131 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 132 pixel_format = 3; 133 alpha_en = 0; 134 break; 135 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 136 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 137 pixel_format = 8; 138 break; 139 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 140 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 141 pixel_format = 10; 142 is_2bit = 1; 143 break; 144 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 145 force_disable_cursor = false; 146 pixel_format = 65; 147 color_space = COLOR_SPACE_YCBCR709; 148 select = DCN2_ICSC_SELECT_ICSC_A; 149 break; 150 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 151 force_disable_cursor = true; 152 pixel_format = 64; 153 color_space = COLOR_SPACE_YCBCR709; 154 select = DCN2_ICSC_SELECT_ICSC_A; 155 break; 156 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 157 force_disable_cursor = true; 158 pixel_format = 67; 159 color_space = COLOR_SPACE_YCBCR709; 160 select = DCN2_ICSC_SELECT_ICSC_A; 161 break; 162 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 163 force_disable_cursor = true; 164 pixel_format = 66; 165 color_space = COLOR_SPACE_YCBCR709; 166 select = DCN2_ICSC_SELECT_ICSC_A; 167 break; 168 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 169 pixel_format = 22; 170 break; 171 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 172 pixel_format = 24; 173 break; 174 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 175 pixel_format = 25; 176 break; 177 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: 178 pixel_format = 12; 179 color_space = COLOR_SPACE_YCBCR709; 180 select = DCN2_ICSC_SELECT_ICSC_A; 181 break; 182 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: 183 pixel_format = 112; 184 break; 185 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: 186 pixel_format = 113; 187 break; 188 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: 189 pixel_format = 114; 190 color_space = COLOR_SPACE_YCBCR709; 191 select = DCN2_ICSC_SELECT_ICSC_A; 192 is_2bit = 1; 193 break; 194 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: 195 pixel_format = 115; 196 color_space = COLOR_SPACE_YCBCR709; 197 select = DCN2_ICSC_SELECT_ICSC_A; 198 is_2bit = 1; 199 break; 200 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: 201 pixel_format = 118; 202 break; 203 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: 204 pixel_format = 119; 205 break; 206 default: 207 break; 208 } 209 210 if (is_2bit == 1 && alpha_2bit_lut != NULL) { 211 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); 212 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); 213 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); 214 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); 215 } 216 217 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, 218 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); 219 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 220 221 // if input adjustments exist, program icsc with those values 222 if (input_csc_color_matrix.enable_adjustment 223 == true) { 224 for (i = 0; i < 12; i++) 225 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 226 227 tbl_entry.color_space = input_color_space; 228 229 if (color_space >= COLOR_SPACE_YCBCR601) 230 select = DCN2_ICSC_SELECT_ICSC_A; 231 else 232 select = DCN2_ICSC_SELECT_BYPASS; 233 234 dpp2_program_input_csc(dpp_base, color_space, select, &tbl_entry); 235 } else 236 dpp2_program_input_csc(dpp_base, color_space, select, NULL); 237 238 if (force_disable_cursor) { 239 REG_UPDATE(CURSOR_CONTROL, 240 CURSOR_ENABLE, 0); 241 REG_UPDATE(CURSOR0_CONTROL, 242 CUR0_ENABLE, 0); 243 244 } 245 dpp2_power_on_obuf(dpp_base, true); 246 247 } 248 249 void dpp2_cnv_set_bias_scale( 250 struct dpp *dpp_base, 251 struct dc_bias_and_scale *bias_and_scale) 252 { 253 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 254 255 REG_UPDATE(FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, bias_and_scale->bias_red); 256 REG_UPDATE(FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, bias_and_scale->bias_green); 257 REG_UPDATE(FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, bias_and_scale->bias_blue); 258 REG_UPDATE(FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, bias_and_scale->scale_red); 259 REG_UPDATE(FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, bias_and_scale->scale_green); 260 REG_UPDATE(FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, bias_and_scale->scale_blue); 261 } 262 263 /*compute the maximum number of lines that we can fit in the line buffer*/ 264 void dscl2_calc_lb_num_partitions( 265 const struct scaler_data *scl_data, 266 enum lb_memory_config lb_config, 267 int *num_part_y, 268 int *num_part_c) 269 { 270 int memory_line_size_y, memory_line_size_c, memory_line_size_a, 271 lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a; 272 273 int line_size = scl_data->viewport.width < scl_data->recout.width ? 274 scl_data->viewport.width : scl_data->recout.width; 275 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? 276 scl_data->viewport_c.width : scl_data->recout.width; 277 278 if (line_size == 0) 279 line_size = 1; 280 281 if (line_size_c == 0) 282 line_size_c = 1; 283 284 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */ 285 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */ 286 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ 287 288 if (lb_config == LB_MEMORY_CONFIG_1) { 289 lb_memory_size = 970; 290 lb_memory_size_c = 970; 291 lb_memory_size_a = 970; 292 } else if (lb_config == LB_MEMORY_CONFIG_2) { 293 lb_memory_size = 1290; 294 lb_memory_size_c = 1290; 295 lb_memory_size_a = 1290; 296 } else if (lb_config == LB_MEMORY_CONFIG_3) { 297 /* 420 mode: using 3rd mem from Y, Cr and Cb */ 298 lb_memory_size = 970 + 1290 + 484 + 484 + 484; 299 lb_memory_size_c = 970 + 1290; 300 lb_memory_size_a = 970 + 1290 + 484; 301 } else { 302 lb_memory_size = 970 + 1290 + 484; 303 lb_memory_size_c = 970 + 1290 + 484; 304 lb_memory_size_a = 970 + 1290 + 484; 305 } 306 *num_part_y = lb_memory_size / memory_line_size_y; 307 *num_part_c = lb_memory_size_c / memory_line_size_c; 308 num_partitions_a = lb_memory_size_a / memory_line_size_a; 309 310 if (scl_data->lb_params.alpha_en 311 && (num_partitions_a < *num_part_y)) 312 *num_part_y = num_partitions_a; 313 314 if (*num_part_y > 64) 315 *num_part_y = 64; 316 if (*num_part_c > 64) 317 *num_part_c = 64; 318 } 319 320 void dpp2_cnv_set_alpha_keyer( 321 struct dpp *dpp_base, 322 struct cnv_color_keyer_params *color_keyer) 323 { 324 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 325 326 REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_EN, color_keyer->color_keyer_en); 327 328 REG_UPDATE(COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, color_keyer->color_keyer_mode); 329 330 REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, color_keyer->color_keyer_alpha_low); 331 REG_UPDATE(COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, color_keyer->color_keyer_alpha_high); 332 333 REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, color_keyer->color_keyer_red_low); 334 REG_UPDATE(COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, color_keyer->color_keyer_red_high); 335 336 REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, color_keyer->color_keyer_green_low); 337 REG_UPDATE(COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, color_keyer->color_keyer_green_high); 338 339 REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, color_keyer->color_keyer_blue_low); 340 REG_UPDATE(COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, color_keyer->color_keyer_blue_high); 341 } 342 343 void dpp2_set_cursor_attributes( 344 struct dpp *dpp_base, 345 struct dc_cursor_attributes *cursor_attributes) 346 { 347 enum dc_cursor_color_format color_format = cursor_attributes->color_format; 348 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); 349 int cur_rom_en = 0; 350 351 if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || 352 color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { 353 if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) { 354 cur_rom_en = 1; 355 } 356 } 357 358 REG_UPDATE_3(CURSOR0_CONTROL, 359 CUR0_MODE, color_format, 360 CUR0_EXPANSION_MODE, 0, 361 CUR0_ROM_EN, cur_rom_en); 362 363 if (color_format == CURSOR_MODE_MONO) { 364 /* todo: clarify what to program these to */ 365 REG_UPDATE(CURSOR0_COLOR0, 366 CUR0_COLOR0, 0x00000000); 367 REG_UPDATE(CURSOR0_COLOR1, 368 CUR0_COLOR1, 0xFFFFFFFF); 369 } 370 } 371 372 void oppn20_dummy_program_regamma_pwl( 373 struct dpp *dpp, 374 const struct pwl_params *params, 375 enum opp_regamma mode) 376 {} 377 378 static struct dpp_funcs dcn20_dpp_funcs = { 379 .dpp_read_state = dpp20_read_state, 380 .dpp_reset = dpp_reset, 381 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 382 .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps, 383 .dpp_set_gamut_remap = dpp2_cm_set_gamut_remap, 384 .dpp_set_csc_adjustment = NULL, 385 .dpp_set_csc_default = NULL, 386 .dpp_program_regamma_pwl = oppn20_dummy_program_regamma_pwl, 387 .dpp_set_degamma = dpp2_set_degamma, 388 .dpp_program_input_lut = dpp2_dummy_program_input_lut, 389 .dpp_full_bypass = dpp1_full_bypass, 390 .dpp_setup = dpp2_cnv_setup, 391 .dpp_program_degamma_pwl = dpp2_set_degamma_pwl, 392 .dpp_program_blnd_lut = dpp20_program_blnd_lut, 393 .dpp_program_shaper_lut = dpp20_program_shaper, 394 .dpp_program_3dlut = dpp20_program_3dlut, 395 .dpp_program_bias_and_scale = NULL, 396 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, 397 .set_cursor_attributes = dpp2_set_cursor_attributes, 398 .set_cursor_position = dpp1_set_cursor_position, 399 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, 400 .dpp_dppclk_control = dpp1_dppclk_control, 401 .dpp_set_hdr_multiplier = dpp2_set_hdr_multiplier, 402 }; 403 404 static struct dpp_caps dcn20_dpp_cap = { 405 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, 406 .dscl_calc_lb_num_partitions = dscl2_calc_lb_num_partitions, 407 }; 408 409 bool dpp2_construct( 410 struct dcn20_dpp *dpp, 411 struct dc_context *ctx, 412 uint32_t inst, 413 const struct dcn2_dpp_registers *tf_regs, 414 const struct dcn2_dpp_shift *tf_shift, 415 const struct dcn2_dpp_mask *tf_mask) 416 { 417 dpp->base.ctx = ctx; 418 419 dpp->base.inst = inst; 420 dpp->base.funcs = &dcn20_dpp_funcs; 421 dpp->base.caps = &dcn20_dpp_cap; 422 423 dpp->tf_regs = tf_regs; 424 dpp->tf_shift = tf_shift; 425 dpp->tf_mask = tf_mask; 426 427 dpp->lb_pixel_depth_supported = 428 LB_PIXEL_DEPTH_18BPP | 429 LB_PIXEL_DEPTH_24BPP | 430 LB_PIXEL_DEPTH_30BPP; 431 432 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; 433 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ 434 435 return true; 436 } 437 438