1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DCN20_DCCG_H__ 27 #define __DCN20_DCCG_H__ 28 29 #include "dccg.h" 30 31 #define DCCG_COMMON_REG_LIST_DCN_BASE() \ 32 SR(DPPCLK_DTO_CTRL),\ 33 DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ 34 DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ 35 DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ 36 DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ 37 SR(REFCLK_CNTL) 38 39 #define DCCG_REG_LIST_DCN2() \ 40 DCCG_COMMON_REG_LIST_DCN_BASE(),\ 41 DCCG_SRII(DTO_PARAM, DPPCLK, 4),\ 42 DCCG_SRII(DTO_PARAM, DPPCLK, 5) 43 44 #define DCCG_SF(reg_name, field_name, post_fix)\ 45 .field_name = reg_name ## __ ## field_name ## post_fix 46 47 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ 48 .field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix 49 50 #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ 51 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ 52 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ 53 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ 54 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ 55 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\ 56 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ 57 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\ 58 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ 59 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ 60 DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ 61 DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ 62 DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh) 63 64 #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \ 65 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\ 66 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\ 67 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\ 68 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\ 69 DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh) 70 71 #define DCCG_REG_FIELD_LIST(type) \ 72 type DPPCLK0_DTO_PHASE;\ 73 type DPPCLK0_DTO_MODULO;\ 74 type DPPCLK_DTO_ENABLE[6];\ 75 type DPPCLK_DTO_DB_EN[6];\ 76 type REFCLK_CLOCK_EN;\ 77 type REFCLK_SRC_SEL; 78 79 #define DCCG3_REG_FIELD_LIST(type) \ 80 type PHYASYMCLK_FORCE_EN;\ 81 type PHYASYMCLK_FORCE_SRC_SEL;\ 82 type PHYBSYMCLK_FORCE_EN;\ 83 type PHYBSYMCLK_FORCE_SRC_SEL;\ 84 type PHYCSYMCLK_FORCE_EN;\ 85 type PHYCSYMCLK_FORCE_SRC_SEL; 86 87 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 88 #define DCCG31_REG_FIELD_LIST(type) \ 89 type PHYDSYMCLK_FORCE_EN;\ 90 type PHYDSYMCLK_FORCE_SRC_SEL;\ 91 type PHYESYMCLK_FORCE_EN;\ 92 type PHYESYMCLK_FORCE_SRC_SEL;\ 93 type DPSTREAMCLK_PIPE0_EN;\ 94 type DPSTREAMCLK_PIPE1_EN;\ 95 type DPSTREAMCLK_PIPE2_EN;\ 96 type DPSTREAMCLK_PIPE3_EN;\ 97 type HDMISTREAMCLK0_SRC_SEL;\ 98 type HDMISTREAMCLK0_DTO_FORCE_DIS;\ 99 type SYMCLK32_SE0_SRC_SEL;\ 100 type SYMCLK32_SE1_SRC_SEL;\ 101 type SYMCLK32_SE2_SRC_SEL;\ 102 type SYMCLK32_SE3_SRC_SEL;\ 103 type SYMCLK32_SE0_EN;\ 104 type SYMCLK32_SE1_EN;\ 105 type SYMCLK32_SE2_EN;\ 106 type SYMCLK32_SE3_EN;\ 107 type SYMCLK32_LE0_SRC_SEL;\ 108 type SYMCLK32_LE1_SRC_SEL;\ 109 type SYMCLK32_LE0_EN;\ 110 type SYMCLK32_LE1_EN;\ 111 type DTBCLK_DTO_ENABLE[MAX_PIPES];\ 112 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\ 113 type PIPE_DTO_SRC_SEL[MAX_PIPES];\ 114 type DTBCLK_DTO_DIV[MAX_PIPES];\ 115 type DCCG_AUDIO_DTO_SEL;\ 116 type DCCG_AUDIO_DTO0_SOURCE_SEL;\ 117 type DENTIST_DISPCLK_CHG_MODE; 118 #endif 119 120 struct dccg_shift { 121 DCCG_REG_FIELD_LIST(uint8_t) 122 DCCG3_REG_FIELD_LIST(uint8_t) 123 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 124 DCCG31_REG_FIELD_LIST(uint8_t) 125 #endif 126 }; 127 128 struct dccg_mask { 129 DCCG_REG_FIELD_LIST(uint32_t) 130 DCCG3_REG_FIELD_LIST(uint32_t) 131 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 132 DCCG31_REG_FIELD_LIST(uint32_t) 133 #endif 134 }; 135 136 struct dccg_registers { 137 uint32_t DPPCLK_DTO_CTRL; 138 uint32_t DPPCLK_DTO_PARAM[6]; 139 uint32_t REFCLK_CNTL; 140 uint32_t HDMICHARCLK_CLOCK_CNTL[6]; 141 uint32_t PHYASYMCLK_CLOCK_CNTL; 142 uint32_t PHYBSYMCLK_CLOCK_CNTL; 143 uint32_t PHYCSYMCLK_CLOCK_CNTL; 144 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 145 uint32_t PHYDSYMCLK_CLOCK_CNTL; 146 uint32_t PHYESYMCLK_CLOCK_CNTL; 147 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; 148 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; 149 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; 150 uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; 151 uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; 152 uint32_t DCCG_AUDIO_DTO_SOURCE; 153 uint32_t DPSTREAMCLK_CNTL; 154 uint32_t HDMISTREAMCLK_CNTL; 155 uint32_t SYMCLK32_SE_CNTL; 156 uint32_t SYMCLK32_LE_CNTL; 157 uint32_t DENTIST_DISPCLK_CNTL; 158 #endif 159 }; 160 161 struct dcn_dccg { 162 struct dccg base; 163 const struct dccg_registers *regs; 164 const struct dccg_shift *dccg_shift; 165 const struct dccg_mask *dccg_mask; 166 }; 167 168 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); 169 170 void dccg2_get_dccg_ref_freq(struct dccg *dccg, 171 unsigned int xtalin_freq_inKhz, 172 unsigned int *dccg_ref_freq_inKhz); 173 174 void dccg2_init(struct dccg *dccg); 175 176 struct dccg *dccg2_create( 177 struct dc_context *ctx, 178 const struct dccg_registers *regs, 179 const struct dccg_shift *dccg_shift, 180 const struct dccg_mask *dccg_mask); 181 182 void dcn_dccg_destroy(struct dccg **dccg); 183 184 #endif //__DCN20_DCCG_H__ 185