1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DCN20_DCCG_H__
27 #define __DCN20_DCCG_H__
28 
29 #include "dccg.h"
30 
31 #define DCCG_COMMON_REG_LIST_DCN_BASE() \
32 	SR(DPPCLK_DTO_CTRL),\
33 	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
34 	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
35 	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
36 	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
37 	SR(REFCLK_CNTL),\
38 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
39 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
40 	SR(DISPCLK_FREQ_CHANGE_CNTL)
41 
42 #define DCCG_REG_LIST_DCN2() \
43 	DCCG_COMMON_REG_LIST_DCN_BASE(),\
44 	DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
45 	DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
46 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
47 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
48 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
49 	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
50 
51 #define DCCG_SF(reg_name, field_name, post_fix)\
52 	.field_name = reg_name ## __ ## field_name ## post_fix
53 
54 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
55 	.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
56 
57 #define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
58 	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
59 
60 #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
61 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
62 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
63 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
64 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
65 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
66 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
67 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
68 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
69 	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
70 	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
71 	DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
72 	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
73 	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
74 	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
75 	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
76 	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
77 	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
78 	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
79 	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
80 	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
81 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
82 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
83 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
84 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
85 
86 
87 
88 
89 #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
90 	DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
91 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
92 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
93 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
94 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
95 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
96 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
97 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
98 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
99 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
100 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
101 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\
102 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
103 
104 #define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \
105 	DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
106 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
107 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
108 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
109 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
110 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
111 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
112 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
113 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)
114 
115 
116 #define DCCG_REG_FIELD_LIST(type) \
117 	type DPPCLK0_DTO_PHASE;\
118 	type DPPCLK0_DTO_MODULO;\
119 	type DPPCLK_DTO_ENABLE[6];\
120 	type DPPCLK_DTO_DB_EN[6];\
121 	type REFCLK_CLOCK_EN;\
122 	type REFCLK_SRC_SEL;\
123 	type DISPCLK_STEP_DELAY;\
124 	type DISPCLK_STEP_SIZE;\
125 	type DISPCLK_FREQ_RAMP_DONE;\
126 	type DISPCLK_MAX_ERRDET_CYCLES;\
127 	type DCCG_FIFO_ERRDET_RESET;\
128 	type DCCG_FIFO_ERRDET_STATE;\
129 	type DCCG_FIFO_ERRDET_OVR_EN;\
130 	type DISPCLK_CHG_FWD_CORR_DISABLE;\
131 	type DISPCLK_FREQ_CHANGE_CNTL;\
132 	type OTG_ADD_PIXEL[MAX_PIPES];\
133 	type OTG_DROP_PIXEL[MAX_PIPES];
134 
135 #define DCCG3_REG_FIELD_LIST(type) \
136 	type PHYASYMCLK_FORCE_EN;\
137 	type PHYASYMCLK_FORCE_SRC_SEL;\
138 	type PHYBSYMCLK_FORCE_EN;\
139 	type PHYBSYMCLK_FORCE_SRC_SEL;\
140 	type PHYCSYMCLK_FORCE_EN;\
141 	type PHYCSYMCLK_FORCE_SRC_SEL;
142 
143 #define DCCG31_REG_FIELD_LIST(type) \
144 	type PHYDSYMCLK_FORCE_EN;\
145 	type PHYDSYMCLK_FORCE_SRC_SEL;\
146 	type PHYESYMCLK_FORCE_EN;\
147 	type PHYESYMCLK_FORCE_SRC_SEL;\
148 	type DPSTREAMCLK_PIPE0_EN;\
149 	type DPSTREAMCLK_PIPE1_EN;\
150 	type DPSTREAMCLK_PIPE2_EN;\
151 	type DPSTREAMCLK_PIPE3_EN;\
152 	type HDMISTREAMCLK0_SRC_SEL;\
153 	type HDMISTREAMCLK0_DTO_FORCE_DIS;\
154 	type SYMCLK32_SE0_SRC_SEL;\
155 	type SYMCLK32_SE1_SRC_SEL;\
156 	type SYMCLK32_SE2_SRC_SEL;\
157 	type SYMCLK32_SE3_SRC_SEL;\
158 	type SYMCLK32_SE0_EN;\
159 	type SYMCLK32_SE1_EN;\
160 	type SYMCLK32_SE2_EN;\
161 	type SYMCLK32_SE3_EN;\
162 	type SYMCLK32_LE0_SRC_SEL;\
163 	type SYMCLK32_LE1_SRC_SEL;\
164 	type SYMCLK32_LE0_EN;\
165 	type SYMCLK32_LE1_EN;\
166 	type DTBCLK_DTO_ENABLE[MAX_PIPES];\
167 	type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
168 	type PIPE_DTO_SRC_SEL[MAX_PIPES];\
169 	type DTBCLK_DTO_DIV[MAX_PIPES];\
170 	type DCCG_AUDIO_DTO_SEL;\
171 	type DCCG_AUDIO_DTO0_SOURCE_SEL;\
172 	type DENTIST_DISPCLK_CHG_MODE;\
173 	type DSCCLK0_DTO_PHASE;\
174 	type DSCCLK0_DTO_MODULO;\
175 	type DSCCLK1_DTO_PHASE;\
176 	type DSCCLK1_DTO_MODULO;\
177 	type DSCCLK2_DTO_PHASE;\
178 	type DSCCLK2_DTO_MODULO;\
179 	type DSCCLK0_DTO_ENABLE;\
180 	type DSCCLK1_DTO_ENABLE;\
181 	type DSCCLK2_DTO_ENABLE;\
182 	type SYMCLK32_ROOT_SE0_GATE_DISABLE;\
183 	type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
184 	type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
185 	type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
186 	type SYMCLK32_SE0_GATE_DISABLE;\
187 	type SYMCLK32_SE1_GATE_DISABLE;\
188 	type SYMCLK32_SE2_GATE_DISABLE;\
189 	type SYMCLK32_SE3_GATE_DISABLE;\
190 	type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
191 	type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
192 	type SYMCLK32_LE0_GATE_DISABLE;\
193 	type SYMCLK32_LE1_GATE_DISABLE;\
194 	type DPSTREAMCLK_ROOT_GATE_DISABLE;\
195 	type DPSTREAMCLK_GATE_DISABLE;\
196 	type HDMISTREAMCLK0_DTO_PHASE;\
197 	type HDMISTREAMCLK0_DTO_MODULO;\
198 	type HDMICHARCLK0_GATE_DISABLE;\
199 	type HDMICHARCLK0_ROOT_GATE_DISABLE; \
200 	type PHYASYMCLK_GATE_DISABLE; \
201 	type PHYBSYMCLK_GATE_DISABLE; \
202 	type PHYCSYMCLK_GATE_DISABLE; \
203 	type PHYDSYMCLK_GATE_DISABLE; \
204 	type PHYESYMCLK_GATE_DISABLE;
205 
206 struct dccg_shift {
207 	DCCG_REG_FIELD_LIST(uint8_t)
208 	DCCG3_REG_FIELD_LIST(uint8_t)
209 	DCCG31_REG_FIELD_LIST(uint8_t)
210 };
211 
212 struct dccg_mask {
213 	DCCG_REG_FIELD_LIST(uint32_t)
214 	DCCG3_REG_FIELD_LIST(uint32_t)
215 	DCCG31_REG_FIELD_LIST(uint32_t)
216 };
217 
218 struct dccg_registers {
219 	uint32_t DPPCLK_DTO_CTRL;
220 	uint32_t DPPCLK_DTO_PARAM[6];
221 	uint32_t REFCLK_CNTL;
222 	uint32_t DISPCLK_FREQ_CHANGE_CNTL;
223 	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
224 	uint32_t HDMICHARCLK_CLOCK_CNTL[6];
225 	uint32_t PHYASYMCLK_CLOCK_CNTL;
226 	uint32_t PHYBSYMCLK_CLOCK_CNTL;
227 	uint32_t PHYCSYMCLK_CLOCK_CNTL;
228 	uint32_t PHYDSYMCLK_CLOCK_CNTL;
229 	uint32_t PHYESYMCLK_CLOCK_CNTL;
230 	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
231 	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
232 	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
233 	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;
234 	uint32_t DCCG_AUDIO_DTO_SOURCE;
235 	uint32_t DPSTREAMCLK_CNTL;
236 	uint32_t HDMISTREAMCLK_CNTL;
237 	uint32_t SYMCLK32_SE_CNTL;
238 	uint32_t SYMCLK32_LE_CNTL;
239 	uint32_t DENTIST_DISPCLK_CNTL;
240 	uint32_t DSCCLK_DTO_CTRL;
241 	uint32_t DSCCLK0_DTO_PARAM;
242 	uint32_t DSCCLK1_DTO_PARAM;
243 	uint32_t DSCCLK2_DTO_PARAM;
244 	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
245 	uint32_t DPSTREAMCLK_GATE_DISABLE;
246 	uint32_t DCCG_GATE_DISABLE_CNTL2;
247 	uint32_t DCCG_GATE_DISABLE_CNTL3;
248 	uint32_t HDMISTREAMCLK0_DTO_PARAM;
249 	uint32_t DCCG_GATE_DISABLE_CNTL4;
250 
251 };
252 
253 struct dcn_dccg {
254 	struct dccg base;
255 	const struct dccg_registers *regs;
256 	const struct dccg_shift *dccg_shift;
257 	const struct dccg_mask *dccg_mask;
258 };
259 
260 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
261 
262 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
263 		unsigned int xtalin_freq_inKhz,
264 		unsigned int *dccg_ref_freq_inKhz);
265 
266 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
267 		bool en);
268 void dccg2_otg_add_pixel(struct dccg *dccg,
269 		uint32_t otg_inst);
270 void dccg2_otg_drop_pixel(struct dccg *dccg,
271 		uint32_t otg_inst);
272 
273 
274 void dccg2_init(struct dccg *dccg);
275 
276 struct dccg *dccg2_create(
277 	struct dc_context *ctx,
278 	const struct dccg_registers *regs,
279 	const struct dccg_shift *dccg_shift,
280 	const struct dccg_mask *dccg_mask);
281 
282 void dcn_dccg_destroy(struct dccg **dccg);
283 
284 #endif //__DCN20_DCCG_H__
285