1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "core_types.h" 28 #include "dcn20_dccg.h" 29 30 #define TO_DCN_DCCG(dccg)\ 31 container_of(dccg, struct dcn_dccg, base) 32 33 #define REG(reg) \ 34 (dccg_dcn->regs->reg) 35 36 #undef FN 37 #define FN(reg_name, field_name) \ 38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name 39 40 #define CTX \ 41 dccg_dcn->base.ctx 42 #define DC_LOGGER \ 43 dccg->ctx->logger 44 45 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) 46 { 47 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 48 49 if (dccg->ref_dppclk && req_dppclk) { 50 int ref_dppclk = dccg->ref_dppclk; 51 52 ASSERT(req_dppclk <= ref_dppclk); 53 /* need to clamp to 8 bits */ 54 if (ref_dppclk > 0xff) { 55 int divider = (ref_dppclk + 0xfe) / 0xff; 56 57 ref_dppclk /= divider; 58 req_dppclk = (req_dppclk + divider - 1) / divider; 59 if (req_dppclk > ref_dppclk) 60 req_dppclk = ref_dppclk; 61 } 62 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, 63 DPPCLK0_DTO_PHASE, req_dppclk, 64 DPPCLK0_DTO_MODULO, ref_dppclk); 65 REG_UPDATE(DPPCLK_DTO_CTRL, 66 DPPCLK_DTO_ENABLE[dpp_inst], 1); 67 } else { 68 REG_UPDATE(DPPCLK_DTO_CTRL, 69 DPPCLK_DTO_ENABLE[dpp_inst], 0); 70 } 71 } 72 73 void dccg2_get_dccg_ref_freq(struct dccg *dccg, 74 unsigned int xtalin_freq_inKhz, 75 unsigned int *dccg_ref_freq_inKhz) 76 { 77 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 78 uint32_t clk_en = 0; 79 uint32_t clk_sel = 0; 80 81 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); 82 83 if (clk_en != 0) { 84 // DCN20 has never been validated for non-xtalin as reference 85 // frequency. There's actually no way for DC to determine what 86 // frequency a non-xtalin source is. 87 ASSERT_CRITICAL(false); 88 } 89 90 *dccg_ref_freq_inKhz = xtalin_freq_inKhz; 91 92 return; 93 } 94 95 void dccg2_init(struct dccg *dccg) 96 { 97 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 98 99 // Fallthrough intentional to program all available dpp_dto's 100 switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) { 101 case 6: 102 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[5], 1); 103 case 5: 104 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[4], 1); 105 case 4: 106 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[3], 1); 107 case 3: 108 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[2], 1); 109 case 2: 110 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[1], 1); 111 case 1: 112 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[0], 1); 113 break; 114 default: 115 ASSERT(false); 116 break; 117 } 118 } 119 120 static const struct dccg_funcs dccg2_funcs = { 121 .update_dpp_dto = dccg2_update_dpp_dto, 122 .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, 123 .dccg_init = dccg2_init 124 }; 125 126 struct dccg *dccg2_create( 127 struct dc_context *ctx, 128 const struct dccg_registers *regs, 129 const struct dccg_shift *dccg_shift, 130 const struct dccg_mask *dccg_mask) 131 { 132 struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); 133 struct dccg *base; 134 135 if (dccg_dcn == NULL) { 136 BREAK_TO_DEBUGGER(); 137 return NULL; 138 } 139 140 base = &dccg_dcn->base; 141 base->ctx = ctx; 142 base->funcs = &dccg2_funcs; 143 144 dccg_dcn->regs = regs; 145 dccg_dcn->dccg_shift = dccg_shift; 146 dccg_dcn->dccg_mask = dccg_mask; 147 148 return &dccg_dcn->base; 149 } 150 151 void dcn_dccg_destroy(struct dccg **dccg) 152 { 153 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg); 154 155 kfree(dccg_dcn); 156 *dccg = NULL; 157 } 158