1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "reg_helper.h" 29 #include "core_types.h" 30 #include "dcn20_dccg.h" 31 32 #define TO_DCN_DCCG(dccg)\ 33 container_of(dccg, struct dcn_dccg, base) 34 35 #define REG(reg) \ 36 (dccg_dcn->regs->reg) 37 38 #undef FN 39 #define FN(reg_name, field_name) \ 40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name 41 42 #define CTX \ 43 dccg_dcn->base.ctx 44 #define DC_LOGGER \ 45 dccg->ctx->logger 46 47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) 48 { 49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 50 51 if (dccg->ref_dppclk && req_dppclk) { 52 int ref_dppclk = dccg->ref_dppclk; 53 int modulo, phase; 54 55 // phase / modulo = dpp pipe clk / dpp global clk 56 modulo = 0xff; // use FF at the end 57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; 58 59 if (phase > 0xff) { 60 ASSERT(false); 61 phase = 0xff; 62 } 63 64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, 65 DPPCLK0_DTO_PHASE, phase, 66 DPPCLK0_DTO_MODULO, modulo); 67 REG_UPDATE(DPPCLK_DTO_CTRL, 68 DPPCLK_DTO_ENABLE[dpp_inst], 1); 69 } else { 70 REG_UPDATE(DPPCLK_DTO_CTRL, 71 DPPCLK_DTO_ENABLE[dpp_inst], 0); 72 } 73 74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; 75 } 76 77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, 78 unsigned int xtalin_freq_inKhz, 79 unsigned int *dccg_ref_freq_inKhz) 80 { 81 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 82 uint32_t clk_en = 0; 83 uint32_t clk_sel = 0; 84 85 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); 86 87 if (clk_en != 0) { 88 // DCN20 has never been validated for non-xtalin as reference 89 // frequency. There's actually no way for DC to determine what 90 // frequency a non-xtalin source is. 91 ASSERT_CRITICAL(false); 92 } 93 94 *dccg_ref_freq_inKhz = xtalin_freq_inKhz; 95 96 return; 97 } 98 99 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, 100 bool en) 101 { 102 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 103 104 REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, 105 DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0); 106 } 107 108 void dccg2_otg_add_pixel(struct dccg *dccg, 109 uint32_t otg_inst) 110 { 111 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 112 113 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], 114 OTG_ADD_PIXEL[otg_inst], 0, 115 OTG_DROP_PIXEL[otg_inst], 0); 116 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 117 OTG_ADD_PIXEL[otg_inst], 1); 118 } 119 120 void dccg2_otg_drop_pixel(struct dccg *dccg, 121 uint32_t otg_inst) 122 { 123 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 124 125 REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst], 126 OTG_ADD_PIXEL[otg_inst], 0, 127 OTG_DROP_PIXEL[otg_inst], 0); 128 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 129 OTG_DROP_PIXEL[otg_inst], 1); 130 } 131 132 void dccg2_init(struct dccg *dccg) 133 { 134 } 135 136 static const struct dccg_funcs dccg2_funcs = { 137 .update_dpp_dto = dccg2_update_dpp_dto, 138 .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, 139 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, 140 .otg_add_pixel = dccg2_otg_add_pixel, 141 .otg_drop_pixel = dccg2_otg_drop_pixel, 142 .dccg_init = dccg2_init 143 }; 144 145 struct dccg *dccg2_create( 146 struct dc_context *ctx, 147 const struct dccg_registers *regs, 148 const struct dccg_shift *dccg_shift, 149 const struct dccg_mask *dccg_mask) 150 { 151 struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_ATOMIC); 152 struct dccg *base; 153 154 if (dccg_dcn == NULL) { 155 BREAK_TO_DEBUGGER(); 156 return NULL; 157 } 158 159 base = &dccg_dcn->base; 160 base->ctx = ctx; 161 base->funcs = &dccg2_funcs; 162 163 dccg_dcn->regs = regs; 164 dccg_dcn->dccg_shift = dccg_shift; 165 dccg_dcn->dccg_mask = dccg_mask; 166 167 return &dccg_dcn->base; 168 } 169 170 void dcn_dccg_destroy(struct dccg **dccg) 171 { 172 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg); 173 174 kfree(dccg_dcn); 175 *dccg = NULL; 176 } 177