1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dm_services.h" 29 #include "dc_bios_types.h" 30 #include "dcn10_stream_encoder.h" 31 #include "reg_helper.h" 32 #include "hw_shared.h" 33 #include "inc/link_dpcd.h" 34 #include "dpcd_defs.h" 35 #include "dcn30/dcn30_afmt.h" 36 37 #define DC_LOGGER \ 38 enc1->base.ctx->logger 39 40 41 #define REG(reg)\ 42 (enc1->regs->reg) 43 44 #undef FN 45 #define FN(reg_name, field_name) \ 46 enc1->se_shift->field_name, enc1->se_mask->field_name 47 48 #define VBI_LINE_0 0 49 #define DP_BLANK_MAX_RETRY 20 50 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 51 52 53 enum { 54 DP_MST_UPDATE_MAX_RETRY = 50 55 }; 56 57 #define CTX \ 58 enc1->base.ctx 59 60 void enc1_update_generic_info_packet( 61 struct dcn10_stream_encoder *enc1, 62 uint32_t packet_index, 63 const struct dc_info_packet *info_packet) 64 { 65 uint32_t regval; 66 /* TODOFPGA Figure out a proper number for max_retries polling for lock 67 * use 50 for now. 68 */ 69 uint32_t max_retries = 50; 70 71 /*we need turn on clock before programming AFMT block*/ 72 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 73 74 if (packet_index >= 8) 75 ASSERT(0); 76 77 /* poll dig_update_lock is not locked -> asic internal signal 78 * assume otg master lock will unlock it 79 */ 80 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 81 0, 10, max_retries);*/ 82 83 /* check if HW reading GSP memory */ 84 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 85 0, 10, max_retries); 86 87 /* HW does is not reading GSP memory not reading too long -> 88 * something wrong. clear GPS memory access and notify? 89 * hw SW is writing to GSP memory 90 */ 91 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 92 93 /* choose which generic packet to use */ 94 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 95 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 96 AFMT_GENERIC_INDEX, packet_index); 97 98 /* write generic packet header 99 * (4th byte is for GENERIC0 only) 100 */ 101 REG_SET_4(AFMT_GENERIC_HDR, 0, 102 AFMT_GENERIC_HB0, info_packet->hb0, 103 AFMT_GENERIC_HB1, info_packet->hb1, 104 AFMT_GENERIC_HB2, info_packet->hb2, 105 AFMT_GENERIC_HB3, info_packet->hb3); 106 107 /* write generic packet contents 108 * (we never use last 4 bytes) 109 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 110 */ 111 { 112 const uint32_t *content = 113 (const uint32_t *) &info_packet->sb[0]; 114 115 REG_WRITE(AFMT_GENERIC_0, *content++); 116 REG_WRITE(AFMT_GENERIC_1, *content++); 117 REG_WRITE(AFMT_GENERIC_2, *content++); 118 REG_WRITE(AFMT_GENERIC_3, *content++); 119 REG_WRITE(AFMT_GENERIC_4, *content++); 120 REG_WRITE(AFMT_GENERIC_5, *content++); 121 REG_WRITE(AFMT_GENERIC_6, *content++); 122 REG_WRITE(AFMT_GENERIC_7, *content); 123 } 124 125 switch (packet_index) { 126 case 0: 127 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 128 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1); 129 break; 130 case 1: 131 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 132 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1); 133 break; 134 case 2: 135 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 136 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1); 137 break; 138 case 3: 139 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 140 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1); 141 break; 142 case 4: 143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 144 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); 145 break; 146 case 5: 147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 148 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1); 149 break; 150 case 6: 151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 152 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1); 153 break; 154 case 7: 155 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 156 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1); 157 break; 158 default: 159 break; 160 } 161 } 162 163 static void enc1_update_hdmi_info_packet( 164 struct dcn10_stream_encoder *enc1, 165 uint32_t packet_index, 166 const struct dc_info_packet *info_packet) 167 { 168 uint32_t cont, send, line; 169 170 if (info_packet->valid) { 171 enc1_update_generic_info_packet( 172 enc1, 173 packet_index, 174 info_packet); 175 176 /* enable transmission of packet(s) - 177 * packet transmission begins on the next frame 178 */ 179 cont = 1; 180 /* send packet(s) every frame */ 181 send = 1; 182 /* select line number to send packets on */ 183 line = 2; 184 } else { 185 cont = 0; 186 send = 0; 187 line = 0; 188 } 189 190 /* choose which generic packet control to use */ 191 switch (packet_index) { 192 case 0: 193 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 194 HDMI_GENERIC0_CONT, cont, 195 HDMI_GENERIC0_SEND, send, 196 HDMI_GENERIC0_LINE, line); 197 break; 198 case 1: 199 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 200 HDMI_GENERIC1_CONT, cont, 201 HDMI_GENERIC1_SEND, send, 202 HDMI_GENERIC1_LINE, line); 203 break; 204 case 2: 205 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 206 HDMI_GENERIC0_CONT, cont, 207 HDMI_GENERIC0_SEND, send, 208 HDMI_GENERIC0_LINE, line); 209 break; 210 case 3: 211 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 212 HDMI_GENERIC1_CONT, cont, 213 HDMI_GENERIC1_SEND, send, 214 HDMI_GENERIC1_LINE, line); 215 break; 216 case 4: 217 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 218 HDMI_GENERIC0_CONT, cont, 219 HDMI_GENERIC0_SEND, send, 220 HDMI_GENERIC0_LINE, line); 221 break; 222 case 5: 223 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 224 HDMI_GENERIC1_CONT, cont, 225 HDMI_GENERIC1_SEND, send, 226 HDMI_GENERIC1_LINE, line); 227 break; 228 case 6: 229 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 230 HDMI_GENERIC0_CONT, cont, 231 HDMI_GENERIC0_SEND, send, 232 HDMI_GENERIC0_LINE, line); 233 break; 234 case 7: 235 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 236 HDMI_GENERIC1_CONT, cont, 237 HDMI_GENERIC1_SEND, send, 238 HDMI_GENERIC1_LINE, line); 239 break; 240 default: 241 /* invalid HW packet index */ 242 DC_LOG_WARNING( 243 "Invalid HW packet index: %s()\n", 244 __func__); 245 return; 246 } 247 } 248 249 /* setup stream encoder in dp mode */ 250 void enc1_stream_encoder_dp_set_stream_attribute( 251 struct stream_encoder *enc, 252 struct dc_crtc_timing *crtc_timing, 253 enum dc_color_space output_color_space, 254 bool use_vsc_sdp_for_colorimetry, 255 uint32_t enable_sdp_splitting) 256 { 257 uint32_t h_active_start; 258 uint32_t v_active_start; 259 uint32_t misc0 = 0; 260 uint32_t misc1 = 0; 261 uint32_t h_blank; 262 uint32_t h_back_porch; 263 uint8_t synchronous_clock = 0; /* asynchronous mode */ 264 uint8_t colorimetry_bpc; 265 uint8_t dynamic_range_rgb = 0; /*full range*/ 266 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 267 uint8_t dp_pixel_encoding = 0; 268 uint8_t dp_component_depth = 0; 269 270 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 271 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; 272 273 if (hw_crtc_timing.flags.INTERLACE) { 274 /*the input timing is in VESA spec format with Interlace flag =1*/ 275 hw_crtc_timing.v_total /= 2; 276 hw_crtc_timing.v_border_top /= 2; 277 hw_crtc_timing.v_addressable /= 2; 278 hw_crtc_timing.v_border_bottom /= 2; 279 hw_crtc_timing.v_front_porch /= 2; 280 hw_crtc_timing.v_sync_width /= 2; 281 } 282 283 284 /* set pixel encoding */ 285 switch (hw_crtc_timing.pixel_encoding) { 286 case PIXEL_ENCODING_YCBCR422: 287 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422; 288 break; 289 case PIXEL_ENCODING_YCBCR444: 290 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444; 291 292 if (hw_crtc_timing.flags.Y_ONLY) 293 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) 294 /* HW testing only, no use case yet. 295 * Color depth of Y-only could be 296 * 8, 10, 12, 16 bits 297 */ 298 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY; 299 300 /* Note: DP_MSA_MISC1 bit 7 is the indicator 301 * of Y-only mode. 302 * This bit is set in HW if register 303 * DP_PIXEL_ENCODING is programmed to 0x4 304 */ 305 break; 306 case PIXEL_ENCODING_YCBCR420: 307 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; 308 break; 309 default: 310 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; 311 break; 312 } 313 314 misc1 = REG_READ(DP_MSA_MISC); 315 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used. 316 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the 317 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7, 318 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care"). 319 */ 320 if (use_vsc_sdp_for_colorimetry) 321 misc1 = misc1 | 0x40; 322 else 323 misc1 = misc1 & ~0x40; 324 325 /* set color depth */ 326 switch (hw_crtc_timing.display_color_depth) { 327 case COLOR_DEPTH_666: 328 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 329 break; 330 case COLOR_DEPTH_888: 331 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC; 332 break; 333 case COLOR_DEPTH_101010: 334 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC; 335 break; 336 case COLOR_DEPTH_121212: 337 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC; 338 break; 339 case COLOR_DEPTH_161616: 340 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC; 341 break; 342 default: 343 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 344 break; 345 } 346 347 /* Set DP pixel encoding and component depth */ 348 REG_UPDATE_2(DP_PIXEL_FORMAT, 349 DP_PIXEL_ENCODING, dp_pixel_encoding, 350 DP_COMPONENT_DEPTH, dp_component_depth); 351 352 /* set dynamic range and YCbCr range */ 353 354 switch (hw_crtc_timing.display_color_depth) { 355 case COLOR_DEPTH_666: 356 colorimetry_bpc = 0; 357 break; 358 case COLOR_DEPTH_888: 359 colorimetry_bpc = 1; 360 break; 361 case COLOR_DEPTH_101010: 362 colorimetry_bpc = 2; 363 break; 364 case COLOR_DEPTH_121212: 365 colorimetry_bpc = 3; 366 break; 367 default: 368 colorimetry_bpc = 0; 369 break; 370 } 371 372 misc0 = misc0 | synchronous_clock; 373 misc0 = colorimetry_bpc << 5; 374 375 switch (output_color_space) { 376 case COLOR_SPACE_SRGB: 377 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 378 dynamic_range_rgb = 0; /*full range*/ 379 break; 380 case COLOR_SPACE_SRGB_LIMITED: 381 misc0 = misc0 | 0x8; /* bit3=1 */ 382 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 383 dynamic_range_rgb = 1; /*limited range*/ 384 break; 385 case COLOR_SPACE_YCBCR601: 386 case COLOR_SPACE_YCBCR601_LIMITED: 387 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 388 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 389 dynamic_range_ycbcr = 0; /*bt601*/ 390 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 391 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 392 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 393 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 394 break; 395 case COLOR_SPACE_YCBCR709: 396 case COLOR_SPACE_YCBCR709_LIMITED: 397 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 398 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 399 dynamic_range_ycbcr = 1; /*bt709*/ 400 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 401 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 402 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 403 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 404 break; 405 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 406 dynamic_range_rgb = 1; /*limited range*/ 407 break; 408 case COLOR_SPACE_2020_RGB_FULLRANGE: 409 case COLOR_SPACE_2020_YCBCR: 410 case COLOR_SPACE_XR_RGB: 411 case COLOR_SPACE_MSREF_SCRGB: 412 case COLOR_SPACE_ADOBERGB: 413 case COLOR_SPACE_DCIP3: 414 case COLOR_SPACE_XV_YCC_709: 415 case COLOR_SPACE_XV_YCC_601: 416 case COLOR_SPACE_DISPLAYNATIVE: 417 case COLOR_SPACE_DOLBYVISION: 418 case COLOR_SPACE_APPCTRL: 419 case COLOR_SPACE_CUSTOMPOINTS: 420 case COLOR_SPACE_UNKNOWN: 421 case COLOR_SPACE_YCBCR709_BLACK: 422 /* do nothing */ 423 break; 424 } 425 426 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 427 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 428 429 /* dcn new register 430 * dc_crtc_timing is vesa dmt struct. data from edid 431 */ 432 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 433 DP_MSA_HTOTAL, hw_crtc_timing.h_total, 434 DP_MSA_VTOTAL, hw_crtc_timing.v_total); 435 436 /* calculate from vesa timing parameters 437 * h_active_start related to leading edge of sync 438 */ 439 440 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - 441 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; 442 443 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - 444 hw_crtc_timing.h_sync_width; 445 446 /* start at beginning of left border */ 447 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; 448 449 450 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - 451 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - 452 hw_crtc_timing.v_front_porch; 453 454 455 /* start at beginning of left border */ 456 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 457 DP_MSA_HSTART, h_active_start, 458 DP_MSA_VSTART, v_active_start); 459 460 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 461 DP_MSA_HSYNCWIDTH, 462 hw_crtc_timing.h_sync_width, 463 DP_MSA_HSYNCPOLARITY, 464 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, 465 DP_MSA_VSYNCWIDTH, 466 hw_crtc_timing.v_sync_width, 467 DP_MSA_VSYNCPOLARITY, 468 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); 469 470 /* HWDITH include border or overscan */ 471 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 472 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + 473 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, 474 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + 475 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); 476 } 477 478 void enc1_stream_encoder_set_stream_attribute_helper( 479 struct dcn10_stream_encoder *enc1, 480 struct dc_crtc_timing *crtc_timing) 481 { 482 switch (crtc_timing->pixel_encoding) { 483 case PIXEL_ENCODING_YCBCR422: 484 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 485 break; 486 default: 487 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 488 break; 489 } 490 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 491 } 492 493 /* setup stream encoder in hdmi mode */ 494 void enc1_stream_encoder_hdmi_set_stream_attribute( 495 struct stream_encoder *enc, 496 struct dc_crtc_timing *crtc_timing, 497 int actual_pix_clk_khz, 498 bool enable_audio) 499 { 500 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 501 struct bp_encoder_control cntl = {0}; 502 503 cntl.action = ENCODER_CONTROL_SETUP; 504 cntl.engine_id = enc1->base.id; 505 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 506 cntl.enable_dp_audio = enable_audio; 507 cntl.pixel_clock = actual_pix_clk_khz; 508 cntl.lanes_number = LANE_COUNT_FOUR; 509 510 if (enc1->base.bp->funcs->encoder_control( 511 enc1->base.bp, &cntl) != BP_RESULT_OK) 512 return; 513 514 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 515 516 /* setup HDMI engine */ 517 REG_UPDATE_6(HDMI_CONTROL, 518 HDMI_PACKET_GEN_VERSION, 1, 519 HDMI_KEEPOUT_MODE, 1, 520 HDMI_DEEP_COLOR_ENABLE, 0, 521 HDMI_DATA_SCRAMBLE_EN, 0, 522 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, 523 HDMI_CLOCK_CHANNEL_RATE, 0); 524 525 526 switch (crtc_timing->display_color_depth) { 527 case COLOR_DEPTH_888: 528 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 529 DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n"); 530 break; 531 case COLOR_DEPTH_101010: 532 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 533 REG_UPDATE_2(HDMI_CONTROL, 534 HDMI_DEEP_COLOR_DEPTH, 1, 535 HDMI_DEEP_COLOR_ENABLE, 0); 536 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \ 537 "disabled for YCBCR422 pixel encoding\n"); 538 } else { 539 REG_UPDATE_2(HDMI_CONTROL, 540 HDMI_DEEP_COLOR_DEPTH, 1, 541 HDMI_DEEP_COLOR_ENABLE, 1); 542 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \ 543 "enabled for YCBCR422 non-pixel encoding\n"); 544 } 545 break; 546 case COLOR_DEPTH_121212: 547 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 548 REG_UPDATE_2(HDMI_CONTROL, 549 HDMI_DEEP_COLOR_DEPTH, 2, 550 HDMI_DEEP_COLOR_ENABLE, 0); 551 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \ 552 "disabled for YCBCR422 pixel encoding\n"); 553 } else { 554 REG_UPDATE_2(HDMI_CONTROL, 555 HDMI_DEEP_COLOR_DEPTH, 2, 556 HDMI_DEEP_COLOR_ENABLE, 1); 557 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \ 558 "enabled for non-pixel YCBCR422 encoding\n"); 559 } 560 break; 561 case COLOR_DEPTH_161616: 562 REG_UPDATE_2(HDMI_CONTROL, 563 HDMI_DEEP_COLOR_DEPTH, 3, 564 HDMI_DEEP_COLOR_ENABLE, 1); 565 DC_LOG_DEBUG("HDMI source deep color depth enabled in" \ 566 "reserved mode\n"); 567 break; 568 default: 569 break; 570 } 571 572 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 573 /* enable HDMI data scrambler 574 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 575 * Clock channel frequency is 1/4 of character rate. 576 */ 577 REG_UPDATE_2(HDMI_CONTROL, 578 HDMI_DATA_SCRAMBLE_EN, 1, 579 HDMI_CLOCK_CHANNEL_RATE, 1); 580 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 581 582 /* TODO: New feature for DCE11, still need to implement */ 583 584 /* enable HDMI data scrambler 585 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 586 * Clock channel frequency is the same 587 * as character rate 588 */ 589 REG_UPDATE_2(HDMI_CONTROL, 590 HDMI_DATA_SCRAMBLE_EN, 1, 591 HDMI_CLOCK_CHANNEL_RATE, 0); 592 } 593 594 595 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 596 HDMI_GC_CONT, 1, 597 HDMI_GC_SEND, 1, 598 HDMI_NULL_SEND, 1); 599 600 /* following belongs to audio */ 601 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 602 603 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 604 605 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 606 VBI_LINE_0 + 2); 607 608 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 609 } 610 611 /* setup stream encoder in dvi mode */ 612 void enc1_stream_encoder_dvi_set_stream_attribute( 613 struct stream_encoder *enc, 614 struct dc_crtc_timing *crtc_timing, 615 bool is_dual_link) 616 { 617 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 618 struct bp_encoder_control cntl = {0}; 619 620 cntl.action = ENCODER_CONTROL_SETUP; 621 cntl.engine_id = enc1->base.id; 622 cntl.signal = is_dual_link ? 623 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 624 cntl.enable_dp_audio = false; 625 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 626 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 627 628 if (enc1->base.bp->funcs->encoder_control( 629 enc1->base.bp, &cntl) != BP_RESULT_OK) 630 return; 631 632 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 633 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 634 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 635 } 636 637 void enc1_stream_encoder_set_throttled_vcp_size( 638 struct stream_encoder *enc, 639 struct fixed31_32 avg_time_slots_per_mtp) 640 { 641 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 642 uint32_t x = dc_fixpt_floor( 643 avg_time_slots_per_mtp); 644 uint32_t y = dc_fixpt_ceil( 645 dc_fixpt_shl( 646 dc_fixpt_sub_int( 647 avg_time_slots_per_mtp, 648 x), 649 26)); 650 651 // If y rounds up to integer, carry it over to x. 652 if (y >> 26) { 653 x += 1; 654 y = 0; 655 } 656 657 REG_SET_2(DP_MSE_RATE_CNTL, 0, 658 DP_MSE_RATE_X, x, 659 DP_MSE_RATE_Y, y); 660 661 /* wait for update to be completed on the link */ 662 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 663 /* is reset to 0 (not pending) */ 664 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 665 0, 666 10, DP_MST_UPDATE_MAX_RETRY); 667 } 668 669 static void enc1_stream_encoder_update_hdmi_info_packets( 670 struct stream_encoder *enc, 671 const struct encoder_info_frame *info_frame) 672 { 673 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 674 675 /* for bring up, disable dp double TODO */ 676 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 677 678 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi); 679 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); 680 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); 681 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd); 682 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); 683 } 684 685 static void enc1_stream_encoder_stop_hdmi_info_packets( 686 struct stream_encoder *enc) 687 { 688 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 689 690 /* stop generic packets 0 & 1 on HDMI */ 691 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 692 HDMI_GENERIC1_CONT, 0, 693 HDMI_GENERIC1_LINE, 0, 694 HDMI_GENERIC1_SEND, 0, 695 HDMI_GENERIC0_CONT, 0, 696 HDMI_GENERIC0_LINE, 0, 697 HDMI_GENERIC0_SEND, 0); 698 699 /* stop generic packets 2 & 3 on HDMI */ 700 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 701 HDMI_GENERIC0_CONT, 0, 702 HDMI_GENERIC0_LINE, 0, 703 HDMI_GENERIC0_SEND, 0, 704 HDMI_GENERIC1_CONT, 0, 705 HDMI_GENERIC1_LINE, 0, 706 HDMI_GENERIC1_SEND, 0); 707 708 /* stop generic packets 2 & 3 on HDMI */ 709 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 710 HDMI_GENERIC0_CONT, 0, 711 HDMI_GENERIC0_LINE, 0, 712 HDMI_GENERIC0_SEND, 0, 713 HDMI_GENERIC1_CONT, 0, 714 HDMI_GENERIC1_LINE, 0, 715 HDMI_GENERIC1_SEND, 0); 716 717 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 718 HDMI_GENERIC0_CONT, 0, 719 HDMI_GENERIC0_LINE, 0, 720 HDMI_GENERIC0_SEND, 0, 721 HDMI_GENERIC1_CONT, 0, 722 HDMI_GENERIC1_LINE, 0, 723 HDMI_GENERIC1_SEND, 0); 724 } 725 726 void enc1_stream_encoder_update_dp_info_packets( 727 struct stream_encoder *enc, 728 const struct encoder_info_frame *info_frame) 729 { 730 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 731 uint32_t value = 0; 732 733 if (info_frame->vsc.valid) 734 enc1_update_generic_info_packet( 735 enc1, 736 0, /* packetIndex */ 737 &info_frame->vsc); 738 739 /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW. 740 * Note that the enablement of GSP1 is not done below, 741 * it's done in FW. 742 */ 743 if (info_frame->vsc.valid) 744 enc1_update_generic_info_packet( 745 enc1, 746 1, /* packetIndex */ 747 &info_frame->vsc); 748 749 if (info_frame->spd.valid) 750 enc1_update_generic_info_packet( 751 enc1, 752 2, /* packetIndex */ 753 &info_frame->spd); 754 755 if (info_frame->hdrsmd.valid) 756 enc1_update_generic_info_packet( 757 enc1, 758 3, /* packetIndex */ 759 &info_frame->hdrsmd); 760 761 /* packetIndex 4 is used for send immediate sdp message, and please 762 * use other packetIndex (such as 5,6) for other info packet 763 */ 764 765 /* enable/disable transmission of packet(s). 766 * If enabled, packet transmission begins on the next frame 767 */ 768 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 769 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 770 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 771 772 /* This bit is the master enable bit. 773 * When enabling secondary stream engine, 774 * this master bit must also be set. 775 * This register shared with audio info frame. 776 * Therefore we need to enable master bit 777 * if at least on of the fields is not 0 778 */ 779 value = REG_READ(DP_SEC_CNTL); 780 if (value) 781 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 782 } 783 784 void enc1_stream_encoder_send_immediate_sdp_message( 785 struct stream_encoder *enc, 786 const uint8_t *custom_sdp_message, 787 unsigned int sdp_message_size) 788 { 789 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 790 uint32_t value = 0; 791 792 /* TODOFPGA Figure out a proper number for max_retries polling for lock 793 * use 50 for now. 794 */ 795 uint32_t max_retries = 50; 796 797 /* check if GSP4 is transmitted */ 798 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, 799 0, 10, max_retries); 800 801 /* disable GSP4 transmitting */ 802 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0); 803 804 /* transmit GSP4 at the earliest time in a frame */ 805 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1); 806 807 /*we need turn on clock before programming AFMT block*/ 808 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 809 810 /* check if HW reading GSP memory */ 811 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 812 0, 10, max_retries); 813 814 /* HW does is not reading GSP memory not reading too long -> 815 * something wrong. clear GPS memory access and notify? 816 * hw SW is writing to GSP memory 817 */ 818 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 819 820 /* use generic packet 4 for immediate sdp message */ 821 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 822 AFMT_GENERIC_INDEX, 4); 823 824 /* write generic packet header 825 * (4th byte is for GENERIC0 only) 826 */ 827 REG_SET_4(AFMT_GENERIC_HDR, 0, 828 AFMT_GENERIC_HB0, custom_sdp_message[0], 829 AFMT_GENERIC_HB1, custom_sdp_message[1], 830 AFMT_GENERIC_HB2, custom_sdp_message[2], 831 AFMT_GENERIC_HB3, custom_sdp_message[3]); 832 833 /* write generic packet contents 834 * (we never use last 4 bytes) 835 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 836 */ 837 { 838 const uint32_t *content = 839 (const uint32_t *) &custom_sdp_message[4]; 840 841 REG_WRITE(AFMT_GENERIC_0, *content++); 842 REG_WRITE(AFMT_GENERIC_1, *content++); 843 REG_WRITE(AFMT_GENERIC_2, *content++); 844 REG_WRITE(AFMT_GENERIC_3, *content++); 845 REG_WRITE(AFMT_GENERIC_4, *content++); 846 REG_WRITE(AFMT_GENERIC_5, *content++); 847 REG_WRITE(AFMT_GENERIC_6, *content++); 848 REG_WRITE(AFMT_GENERIC_7, *content); 849 } 850 851 /* check whether GENERIC4 registers double buffer update in immediate mode 852 * is pending 853 */ 854 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, 855 0, 10, max_retries); 856 857 /* atomically update double-buffered GENERIC4 registers in immediate mode 858 * (update immediately) 859 */ 860 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 861 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); 862 863 /* enable GSP4 transmitting */ 864 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1); 865 866 /* This bit is the master enable bit. 867 * When enabling secondary stream engine, 868 * this master bit must also be set. 869 * This register shared with audio info frame. 870 * Therefore we need to enable master bit 871 * if at least on of the fields is not 0 872 */ 873 value = REG_READ(DP_SEC_CNTL); 874 if (value) 875 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 876 } 877 878 void enc1_stream_encoder_stop_dp_info_packets( 879 struct stream_encoder *enc) 880 { 881 /* stop generic packets on DP */ 882 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 883 uint32_t value = 0; 884 885 REG_SET_10(DP_SEC_CNTL, 0, 886 DP_SEC_GSP0_ENABLE, 0, 887 DP_SEC_GSP1_ENABLE, 0, 888 DP_SEC_GSP2_ENABLE, 0, 889 DP_SEC_GSP3_ENABLE, 0, 890 DP_SEC_GSP4_ENABLE, 0, 891 DP_SEC_GSP5_ENABLE, 0, 892 DP_SEC_GSP6_ENABLE, 0, 893 DP_SEC_GSP7_ENABLE, 0, 894 DP_SEC_MPG_ENABLE, 0, 895 DP_SEC_STREAM_ENABLE, 0); 896 897 /* this register shared with audio info frame. 898 * therefore we need to keep master enabled 899 * if at least one of the fields is not 0 */ 900 value = REG_READ(DP_SEC_CNTL); 901 if (value) 902 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 903 904 } 905 906 void enc1_stream_encoder_dp_blank( 907 struct dc_link *link, 908 struct stream_encoder *enc) 909 { 910 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 911 uint32_t reg1 = 0; 912 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 913 914 /* Note: For CZ, we are changing driver default to disable 915 * stream deferred to next VBLANK. If results are positive, we 916 * will make the same change to all DCE versions. There are a 917 * handful of panels that cannot handle disable stream at 918 * HBLANK and will result in a white line flash across the 919 * screen on stream disable. 920 */ 921 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 922 if ((reg1 & 0x1) == 0) 923 /*stream not enabled*/ 924 return; 925 /* Specify the video stream disable point 926 * (2 = start of the next vertical blank) 927 */ 928 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 929 /* Larger delay to wait until VBLANK - use max retry of 930 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode + 931 * a little more because we may not trust delay accuracy. 932 */ 933 max_retries = DP_BLANK_MAX_RETRY * 501; 934 935 /* disable DP stream */ 936 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 937 938 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM); 939 940 /* the encoder stops sending the video stream 941 * at the start of the vertical blanking. 942 * Poll for DP_VID_STREAM_STATUS == 0 943 */ 944 945 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 946 0, 947 10, max_retries); 948 949 /* Tell the DP encoder to ignore timing from CRTC, must be done after 950 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 951 * complete, stream status will be stuck in video stream enabled state, 952 * i.e. DP_VID_STREAM_STATUS stuck at 1. 953 */ 954 955 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 956 957 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET); 958 } 959 960 /* output video stream to link encoder */ 961 void enc1_stream_encoder_dp_unblank( 962 struct dc_link *link, 963 struct stream_encoder *enc, 964 const struct encoder_unblank_param *param) 965 { 966 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 967 968 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 969 uint32_t n_vid = 0x8000; 970 uint32_t m_vid; 971 uint32_t n_multiply = 0; 972 uint64_t m_vid_l = n_vid; 973 974 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ 975 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 976 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/ 977 n_multiply = 1; 978 } 979 /* M / N = Fstream / Flink 980 * m_vid / n_vid = pixel rate / link rate 981 */ 982 983 m_vid_l *= param->timing.pix_clk_100hz / 10; 984 m_vid_l = div_u64(m_vid_l, 985 param->link_settings.link_rate 986 * LINK_RATE_REF_FREQ_IN_KHZ); 987 988 m_vid = (uint32_t) m_vid_l; 989 990 /* enable auto measurement */ 991 992 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 993 994 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 995 * therefore program initial value for Mvid and Nvid 996 */ 997 998 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 999 1000 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 1001 1002 REG_UPDATE_2(DP_VID_TIMING, 1003 DP_VID_M_N_GEN_EN, 1, 1004 DP_VID_N_MUL, n_multiply); 1005 } 1006 1007 /* set DIG_START to 0x1 to resync FIFO */ 1008 1009 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 1010 1011 /* switch DP encoder to CRTC data */ 1012 1013 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 1014 1015 /* wait 100us for DIG/DP logic to prime 1016 * (i.e. a few video lines) 1017 */ 1018 udelay(100); 1019 1020 /* the hardware would start sending video at the start of the next DP 1021 * frame (i.e. rising edge of the vblank). 1022 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 1023 * register has no effect on enable transition! HW always guarantees 1024 * VID_STREAM enable at start of next frame, and this is not 1025 * programmable 1026 */ 1027 1028 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 1029 1030 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); 1031 } 1032 1033 void enc1_stream_encoder_set_avmute( 1034 struct stream_encoder *enc, 1035 bool enable) 1036 { 1037 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1038 unsigned int value = enable ? 1 : 0; 1039 1040 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1041 } 1042 1043 void enc1_reset_hdmi_stream_attribute( 1044 struct stream_encoder *enc) 1045 { 1046 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1047 1048 REG_UPDATE_5(HDMI_CONTROL, 1049 HDMI_PACKET_GEN_VERSION, 1, 1050 HDMI_KEEPOUT_MODE, 1, 1051 HDMI_DEEP_COLOR_ENABLE, 0, 1052 HDMI_DATA_SCRAMBLE_EN, 0, 1053 HDMI_CLOCK_CHANNEL_RATE, 0); 1054 } 1055 1056 1057 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1058 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1059 1060 #include "include/audio_types.h" 1061 1062 1063 /* 25.2MHz/1.001*/ 1064 /* 25.2MHz/1.001*/ 1065 /* 25.2MHz*/ 1066 /* 27MHz */ 1067 /* 27MHz*1.001*/ 1068 /* 27MHz*1.001*/ 1069 /* 54MHz*/ 1070 /* 54MHz*1.001*/ 1071 /* 74.25MHz/1.001*/ 1072 /* 74.25MHz*/ 1073 /* 148.5MHz/1.001*/ 1074 /* 148.5MHz*/ 1075 1076 static const struct audio_clock_info audio_clock_info_table[16] = { 1077 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1078 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1079 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1080 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1081 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1082 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1083 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1084 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1085 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1086 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1087 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1088 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1089 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1090 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1091 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1092 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1093 }; 1094 1095 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1096 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1097 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1098 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1099 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1100 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1101 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1102 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1103 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1104 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1105 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1106 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1107 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1108 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1109 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1110 }; 1111 1112 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1113 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1114 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1115 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1116 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1117 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1118 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1119 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1120 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1121 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1122 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1123 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1124 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1125 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1126 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1127 1128 1129 }; 1130 1131 static union audio_cea_channels speakers_to_channels( 1132 struct audio_speaker_flags speaker_flags) 1133 { 1134 union audio_cea_channels cea_channels = {0}; 1135 1136 /* these are one to one */ 1137 cea_channels.channels.FL = speaker_flags.FL_FR; 1138 cea_channels.channels.FR = speaker_flags.FL_FR; 1139 cea_channels.channels.LFE = speaker_flags.LFE; 1140 cea_channels.channels.FC = speaker_flags.FC; 1141 1142 /* if Rear Left and Right exist move RC speaker to channel 7 1143 * otherwise to channel 5 1144 */ 1145 if (speaker_flags.RL_RR) { 1146 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1147 cea_channels.channels.RR = speaker_flags.RL_RR; 1148 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1149 } else { 1150 cea_channels.channels.RL_RC = speaker_flags.RC; 1151 } 1152 1153 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1154 if (speaker_flags.FLC_FRC) { 1155 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1156 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1157 } else { 1158 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1159 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1160 } 1161 1162 return cea_channels; 1163 } 1164 1165 void get_audio_clock_info( 1166 enum dc_color_depth color_depth, 1167 uint32_t crtc_pixel_clock_100Hz, 1168 uint32_t actual_pixel_clock_100Hz, 1169 struct audio_clock_info *audio_clock_info) 1170 { 1171 const struct audio_clock_info *clock_info; 1172 uint32_t index; 1173 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; 1174 uint32_t audio_array_size; 1175 1176 switch (color_depth) { 1177 case COLOR_DEPTH_161616: 1178 clock_info = audio_clock_info_table_48bpc; 1179 audio_array_size = ARRAY_SIZE( 1180 audio_clock_info_table_48bpc); 1181 break; 1182 case COLOR_DEPTH_121212: 1183 clock_info = audio_clock_info_table_36bpc; 1184 audio_array_size = ARRAY_SIZE( 1185 audio_clock_info_table_36bpc); 1186 break; 1187 default: 1188 clock_info = audio_clock_info_table; 1189 audio_array_size = ARRAY_SIZE( 1190 audio_clock_info_table); 1191 break; 1192 } 1193 1194 if (clock_info != NULL) { 1195 /* search for exact pixel clock in table */ 1196 for (index = 0; index < audio_array_size; index++) { 1197 if (clock_info[index].pixel_clock_in_10khz > 1198 crtc_pixel_clock_in_10khz) 1199 break; /* not match */ 1200 else if (clock_info[index].pixel_clock_in_10khz == 1201 crtc_pixel_clock_in_10khz) { 1202 /* match found */ 1203 *audio_clock_info = clock_info[index]; 1204 return; 1205 } 1206 } 1207 } 1208 1209 /* not found */ 1210 if (actual_pixel_clock_100Hz == 0) 1211 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; 1212 1213 /* See HDMI spec the table entry under 1214 * pixel clock of "Other". */ 1215 audio_clock_info->pixel_clock_in_10khz = 1216 actual_pixel_clock_100Hz / 100; 1217 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; 1218 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; 1219 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; 1220 1221 audio_clock_info->n_32khz = 4096; 1222 audio_clock_info->n_44khz = 6272; 1223 audio_clock_info->n_48khz = 6144; 1224 } 1225 1226 static void enc1_se_audio_setup( 1227 struct stream_encoder *enc, 1228 unsigned int az_inst, 1229 struct audio_info *audio_info) 1230 { 1231 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1232 1233 uint32_t channels = 0; 1234 1235 ASSERT(audio_info); 1236 if (audio_info == NULL) 1237 /* This should not happen.it does so we don't get BSOD*/ 1238 return; 1239 1240 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1241 1242 /* setup the audio stream source select (audio -> dig mapping) */ 1243 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1244 1245 /* Channel allocation */ 1246 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1247 } 1248 1249 static void enc1_se_setup_hdmi_audio( 1250 struct stream_encoder *enc, 1251 const struct audio_crtc_info *crtc_info) 1252 { 1253 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1254 1255 struct audio_clock_info audio_clock_info = {0}; 1256 1257 /* HDMI_AUDIO_PACKET_CONTROL */ 1258 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, 1259 HDMI_AUDIO_DELAY_EN, 1); 1260 1261 /* AFMT_AUDIO_PACKET_CONTROL */ 1262 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1263 1264 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1265 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1266 AFMT_AUDIO_LAYOUT_OVRD, 0, 1267 AFMT_60958_OSF_OVRD, 0); 1268 1269 /* HDMI_ACR_PACKET_CONTROL */ 1270 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1271 HDMI_ACR_AUTO_SEND, 1, 1272 HDMI_ACR_SOURCE, 0, 1273 HDMI_ACR_AUDIO_PRIORITY, 0); 1274 1275 /* Program audio clock sample/regeneration parameters */ 1276 get_audio_clock_info(crtc_info->color_depth, 1277 crtc_info->requested_pixel_clock_100Hz, 1278 crtc_info->calculated_pixel_clock_100Hz, 1279 &audio_clock_info); 1280 DC_LOG_HW_AUDIO( 1281 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 1282 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 1283 crtc_info->requested_pixel_clock_100Hz, \ 1284 crtc_info->calculated_pixel_clock_100Hz); 1285 1286 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1287 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1288 1289 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1290 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1291 1292 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1293 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1294 1295 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1296 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1297 1298 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1299 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1300 1301 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1302 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1303 1304 /* Video driver cannot know in advance which sample rate will 1305 * be used by HD Audio driver 1306 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1307 * programmed below in interruppt callback 1308 */ 1309 1310 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1311 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 1312 */ 1313 REG_UPDATE_2(AFMT_60958_0, 1314 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1315 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1316 1317 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1318 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1319 1320 /* AFMT_60958_2 now keep this settings until 1321 * Programming guide comes out 1322 */ 1323 REG_UPDATE_6(AFMT_60958_2, 1324 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1325 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1326 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1327 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1328 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1329 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1330 } 1331 1332 static void enc1_se_setup_dp_audio( 1333 struct stream_encoder *enc) 1334 { 1335 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1336 1337 /* --- DP Audio packet configurations --- */ 1338 1339 /* ATP Configuration */ 1340 REG_SET(DP_SEC_AUD_N, 0, 1341 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1342 1343 /* Async/auto-calc timestamp mode */ 1344 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1345 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1346 1347 /* --- The following are the registers 1348 * copied from the SetupHDMI --- 1349 */ 1350 1351 /* AFMT_AUDIO_PACKET_CONTROL */ 1352 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1353 1354 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1355 /* Program the ATP and AIP next */ 1356 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1357 AFMT_AUDIO_LAYOUT_OVRD, 0, 1358 AFMT_60958_OSF_OVRD, 0); 1359 1360 /* AFMT_INFOFRAME_CONTROL0 */ 1361 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1362 1363 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1364 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1365 } 1366 1367 void enc1_se_enable_audio_clock( 1368 struct stream_encoder *enc, 1369 bool enable) 1370 { 1371 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1372 1373 if (REG(AFMT_CNTL) == 0) 1374 return; /* DCE8/10 does not have this register */ 1375 1376 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1377 1378 /* wait for AFMT clock to turn on, 1379 * expectation: this should complete in 1-2 reads 1380 * 1381 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1382 * 1383 * TODO: wait for clock_on does not work well. May need HW 1384 * program sequence. But audio seems work normally even without wait 1385 * for clock_on status change 1386 */ 1387 } 1388 1389 void enc1_se_enable_dp_audio( 1390 struct stream_encoder *enc) 1391 { 1392 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1393 1394 /* Enable Audio packets */ 1395 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1396 1397 /* Program the ATP and AIP next */ 1398 REG_UPDATE_2(DP_SEC_CNTL, 1399 DP_SEC_ATP_ENABLE, 1, 1400 DP_SEC_AIP_ENABLE, 1); 1401 1402 /* Program STREAM_ENABLE after all the other enables. */ 1403 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1404 } 1405 1406 static void enc1_se_disable_dp_audio( 1407 struct stream_encoder *enc) 1408 { 1409 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1410 uint32_t value = 0; 1411 1412 /* Disable Audio packets */ 1413 REG_UPDATE_5(DP_SEC_CNTL, 1414 DP_SEC_ASP_ENABLE, 0, 1415 DP_SEC_ATP_ENABLE, 0, 1416 DP_SEC_AIP_ENABLE, 0, 1417 DP_SEC_ACM_ENABLE, 0, 1418 DP_SEC_STREAM_ENABLE, 0); 1419 1420 /* This register shared with encoder info frame. Therefore we need to 1421 * keep master enabled if at least on of the fields is not 0 1422 */ 1423 value = REG_READ(DP_SEC_CNTL); 1424 if (value != 0) 1425 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1426 1427 } 1428 1429 void enc1_se_audio_mute_control( 1430 struct stream_encoder *enc, 1431 bool mute) 1432 { 1433 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1434 1435 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1436 } 1437 1438 void enc1_se_dp_audio_setup( 1439 struct stream_encoder *enc, 1440 unsigned int az_inst, 1441 struct audio_info *info) 1442 { 1443 enc1_se_audio_setup(enc, az_inst, info); 1444 } 1445 1446 void enc1_se_dp_audio_enable( 1447 struct stream_encoder *enc) 1448 { 1449 enc1_se_enable_audio_clock(enc, true); 1450 enc1_se_setup_dp_audio(enc); 1451 enc1_se_enable_dp_audio(enc); 1452 } 1453 1454 void enc1_se_dp_audio_disable( 1455 struct stream_encoder *enc) 1456 { 1457 enc1_se_disable_dp_audio(enc); 1458 enc1_se_enable_audio_clock(enc, false); 1459 } 1460 1461 void enc1_se_hdmi_audio_setup( 1462 struct stream_encoder *enc, 1463 unsigned int az_inst, 1464 struct audio_info *info, 1465 struct audio_crtc_info *audio_crtc_info) 1466 { 1467 enc1_se_enable_audio_clock(enc, true); 1468 enc1_se_setup_hdmi_audio(enc, audio_crtc_info); 1469 enc1_se_audio_setup(enc, az_inst, info); 1470 } 1471 1472 void enc1_se_hdmi_audio_disable( 1473 struct stream_encoder *enc) 1474 { 1475 #if defined(CONFIG_DRM_AMD_DC_DCN) 1476 if (enc->afmt && enc->afmt->funcs->afmt_powerdown) 1477 enc->afmt->funcs->afmt_powerdown(enc->afmt); 1478 #endif 1479 enc1_se_enable_audio_clock(enc, false); 1480 } 1481 1482 1483 void enc1_setup_stereo_sync( 1484 struct stream_encoder *enc, 1485 int tg_inst, bool enable) 1486 { 1487 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1488 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1489 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1490 } 1491 1492 void enc1_dig_connect_to_otg( 1493 struct stream_encoder *enc, 1494 int tg_inst) 1495 { 1496 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1497 1498 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); 1499 } 1500 1501 unsigned int enc1_dig_source_otg( 1502 struct stream_encoder *enc) 1503 { 1504 uint32_t tg_inst = 0; 1505 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1506 1507 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); 1508 1509 return tg_inst; 1510 } 1511 1512 bool enc1_stream_encoder_dp_get_pixel_format( 1513 struct stream_encoder *enc, 1514 enum dc_pixel_encoding *encoding, 1515 enum dc_color_depth *depth) 1516 { 1517 uint32_t hw_encoding = 0; 1518 uint32_t hw_depth = 0; 1519 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1520 1521 if (enc == NULL || 1522 encoding == NULL || 1523 depth == NULL) 1524 return false; 1525 1526 REG_GET_2(DP_PIXEL_FORMAT, 1527 DP_PIXEL_ENCODING, &hw_encoding, 1528 DP_COMPONENT_DEPTH, &hw_depth); 1529 1530 switch (hw_depth) { 1531 case DP_COMPONENT_PIXEL_DEPTH_6BPC: 1532 *depth = COLOR_DEPTH_666; 1533 break; 1534 case DP_COMPONENT_PIXEL_DEPTH_8BPC: 1535 *depth = COLOR_DEPTH_888; 1536 break; 1537 case DP_COMPONENT_PIXEL_DEPTH_10BPC: 1538 *depth = COLOR_DEPTH_101010; 1539 break; 1540 case DP_COMPONENT_PIXEL_DEPTH_12BPC: 1541 *depth = COLOR_DEPTH_121212; 1542 break; 1543 case DP_COMPONENT_PIXEL_DEPTH_16BPC: 1544 *depth = COLOR_DEPTH_161616; 1545 break; 1546 default: 1547 *depth = COLOR_DEPTH_UNDEFINED; 1548 break; 1549 } 1550 1551 switch (hw_encoding) { 1552 case DP_PIXEL_ENCODING_TYPE_RGB444: 1553 *encoding = PIXEL_ENCODING_RGB; 1554 break; 1555 case DP_PIXEL_ENCODING_TYPE_YCBCR422: 1556 *encoding = PIXEL_ENCODING_YCBCR422; 1557 break; 1558 case DP_PIXEL_ENCODING_TYPE_YCBCR444: 1559 case DP_PIXEL_ENCODING_TYPE_Y_ONLY: 1560 *encoding = PIXEL_ENCODING_YCBCR444; 1561 break; 1562 case DP_PIXEL_ENCODING_TYPE_YCBCR420: 1563 *encoding = PIXEL_ENCODING_YCBCR420; 1564 break; 1565 default: 1566 *encoding = PIXEL_ENCODING_UNDEFINED; 1567 break; 1568 } 1569 return true; 1570 } 1571 1572 static const struct stream_encoder_funcs dcn10_str_enc_funcs = { 1573 .dp_set_stream_attribute = 1574 enc1_stream_encoder_dp_set_stream_attribute, 1575 .hdmi_set_stream_attribute = 1576 enc1_stream_encoder_hdmi_set_stream_attribute, 1577 .dvi_set_stream_attribute = 1578 enc1_stream_encoder_dvi_set_stream_attribute, 1579 .set_throttled_vcp_size = 1580 enc1_stream_encoder_set_throttled_vcp_size, 1581 .update_hdmi_info_packets = 1582 enc1_stream_encoder_update_hdmi_info_packets, 1583 .stop_hdmi_info_packets = 1584 enc1_stream_encoder_stop_hdmi_info_packets, 1585 .update_dp_info_packets = 1586 enc1_stream_encoder_update_dp_info_packets, 1587 .send_immediate_sdp_message = 1588 enc1_stream_encoder_send_immediate_sdp_message, 1589 .stop_dp_info_packets = 1590 enc1_stream_encoder_stop_dp_info_packets, 1591 .dp_blank = 1592 enc1_stream_encoder_dp_blank, 1593 .dp_unblank = 1594 enc1_stream_encoder_dp_unblank, 1595 .audio_mute_control = enc1_se_audio_mute_control, 1596 1597 .dp_audio_setup = enc1_se_dp_audio_setup, 1598 .dp_audio_enable = enc1_se_dp_audio_enable, 1599 .dp_audio_disable = enc1_se_dp_audio_disable, 1600 1601 .hdmi_audio_setup = enc1_se_hdmi_audio_setup, 1602 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 1603 .setup_stereo_sync = enc1_setup_stereo_sync, 1604 .set_avmute = enc1_stream_encoder_set_avmute, 1605 .dig_connect_to_otg = enc1_dig_connect_to_otg, 1606 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, 1607 .dig_source_otg = enc1_dig_source_otg, 1608 1609 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, 1610 }; 1611 1612 void dcn10_stream_encoder_construct( 1613 struct dcn10_stream_encoder *enc1, 1614 struct dc_context *ctx, 1615 struct dc_bios *bp, 1616 enum engine_id eng_id, 1617 const struct dcn10_stream_enc_registers *regs, 1618 const struct dcn10_stream_encoder_shift *se_shift, 1619 const struct dcn10_stream_encoder_mask *se_mask) 1620 { 1621 enc1->base.funcs = &dcn10_str_enc_funcs; 1622 enc1->base.ctx = ctx; 1623 enc1->base.id = eng_id; 1624 enc1->base.bp = bp; 1625 enc1->regs = regs; 1626 enc1->se_shift = se_shift; 1627 enc1->se_mask = se_mask; 1628 enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA; 1629 } 1630 1631