1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 28 #include "dc_bios_types.h" 29 #include "dcn10_stream_encoder.h" 30 #include "reg_helper.h" 31 #include "hw_shared.h" 32 33 #define DC_LOGGER \ 34 enc1->base.ctx->logger 35 36 37 #define REG(reg)\ 38 (enc1->regs->reg) 39 40 #undef FN 41 #define FN(reg_name, field_name) \ 42 enc1->se_shift->field_name, enc1->se_mask->field_name 43 44 #define VBI_LINE_0 0 45 #define DP_BLANK_MAX_RETRY 20 46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 47 48 49 enum { 50 DP_MST_UPDATE_MAX_RETRY = 50 51 }; 52 53 #define CTX \ 54 enc1->base.ctx 55 56 void enc1_update_generic_info_packet( 57 struct dcn10_stream_encoder *enc1, 58 uint32_t packet_index, 59 const struct dc_info_packet *info_packet) 60 { 61 uint32_t regval; 62 /* TODOFPGA Figure out a proper number for max_retries polling for lock 63 * use 50 for now. 64 */ 65 uint32_t max_retries = 50; 66 67 /*we need turn on clock before programming AFMT block*/ 68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 69 70 if (packet_index >= 8) 71 ASSERT(0); 72 73 /* poll dig_update_lock is not locked -> asic internal signal 74 * assume otg master lock will unlock it 75 */ 76 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 77 0, 10, max_retries);*/ 78 79 /* check if HW reading GSP memory */ 80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 81 0, 10, max_retries); 82 83 /* HW does is not reading GSP memory not reading too long -> 84 * something wrong. clear GPS memory access and notify? 85 * hw SW is writing to GSP memory 86 */ 87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 88 89 /* choose which generic packet to use */ 90 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 91 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 92 AFMT_GENERIC_INDEX, packet_index); 93 94 /* write generic packet header 95 * (4th byte is for GENERIC0 only) 96 */ 97 REG_SET_4(AFMT_GENERIC_HDR, 0, 98 AFMT_GENERIC_HB0, info_packet->hb0, 99 AFMT_GENERIC_HB1, info_packet->hb1, 100 AFMT_GENERIC_HB2, info_packet->hb2, 101 AFMT_GENERIC_HB3, info_packet->hb3); 102 103 /* write generic packet contents 104 * (we never use last 4 bytes) 105 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 106 */ 107 { 108 const uint32_t *content = 109 (const uint32_t *) &info_packet->sb[0]; 110 111 REG_WRITE(AFMT_GENERIC_0, *content++); 112 REG_WRITE(AFMT_GENERIC_1, *content++); 113 REG_WRITE(AFMT_GENERIC_2, *content++); 114 REG_WRITE(AFMT_GENERIC_3, *content++); 115 REG_WRITE(AFMT_GENERIC_4, *content++); 116 REG_WRITE(AFMT_GENERIC_5, *content++); 117 REG_WRITE(AFMT_GENERIC_6, *content++); 118 REG_WRITE(AFMT_GENERIC_7, *content); 119 } 120 121 switch (packet_index) { 122 case 0: 123 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 124 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1); 125 break; 126 case 1: 127 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 128 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1); 129 break; 130 case 2: 131 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 132 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1); 133 break; 134 case 3: 135 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 136 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1); 137 break; 138 case 4: 139 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 140 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); 141 break; 142 case 5: 143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 144 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1); 145 break; 146 case 6: 147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 148 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1); 149 break; 150 case 7: 151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 152 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1); 153 break; 154 default: 155 break; 156 } 157 } 158 159 static void enc1_update_hdmi_info_packet( 160 struct dcn10_stream_encoder *enc1, 161 uint32_t packet_index, 162 const struct dc_info_packet *info_packet) 163 { 164 uint32_t cont, send, line; 165 166 if (info_packet->valid) { 167 enc1_update_generic_info_packet( 168 enc1, 169 packet_index, 170 info_packet); 171 172 /* enable transmission of packet(s) - 173 * packet transmission begins on the next frame 174 */ 175 cont = 1; 176 /* send packet(s) every frame */ 177 send = 1; 178 /* select line number to send packets on */ 179 line = 2; 180 } else { 181 cont = 0; 182 send = 0; 183 line = 0; 184 } 185 186 /* choose which generic packet control to use */ 187 switch (packet_index) { 188 case 0: 189 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 190 HDMI_GENERIC0_CONT, cont, 191 HDMI_GENERIC0_SEND, send, 192 HDMI_GENERIC0_LINE, line); 193 break; 194 case 1: 195 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 196 HDMI_GENERIC1_CONT, cont, 197 HDMI_GENERIC1_SEND, send, 198 HDMI_GENERIC1_LINE, line); 199 break; 200 case 2: 201 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 202 HDMI_GENERIC0_CONT, cont, 203 HDMI_GENERIC0_SEND, send, 204 HDMI_GENERIC0_LINE, line); 205 break; 206 case 3: 207 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 208 HDMI_GENERIC1_CONT, cont, 209 HDMI_GENERIC1_SEND, send, 210 HDMI_GENERIC1_LINE, line); 211 break; 212 case 4: 213 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 214 HDMI_GENERIC0_CONT, cont, 215 HDMI_GENERIC0_SEND, send, 216 HDMI_GENERIC0_LINE, line); 217 break; 218 case 5: 219 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 220 HDMI_GENERIC1_CONT, cont, 221 HDMI_GENERIC1_SEND, send, 222 HDMI_GENERIC1_LINE, line); 223 break; 224 case 6: 225 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 226 HDMI_GENERIC0_CONT, cont, 227 HDMI_GENERIC0_SEND, send, 228 HDMI_GENERIC0_LINE, line); 229 break; 230 case 7: 231 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 232 HDMI_GENERIC1_CONT, cont, 233 HDMI_GENERIC1_SEND, send, 234 HDMI_GENERIC1_LINE, line); 235 break; 236 default: 237 /* invalid HW packet index */ 238 DC_LOG_WARNING( 239 "Invalid HW packet index: %s()\n", 240 __func__); 241 return; 242 } 243 } 244 245 /* setup stream encoder in dp mode */ 246 void enc1_stream_encoder_dp_set_stream_attribute( 247 struct stream_encoder *enc, 248 struct dc_crtc_timing *crtc_timing, 249 enum dc_color_space output_color_space, 250 bool use_vsc_sdp_for_colorimetry, 251 uint32_t enable_sdp_splitting) 252 { 253 uint32_t h_active_start; 254 uint32_t v_active_start; 255 uint32_t misc0 = 0; 256 uint32_t misc1 = 0; 257 uint32_t h_blank; 258 uint32_t h_back_porch; 259 uint8_t synchronous_clock = 0; /* asynchronous mode */ 260 uint8_t colorimetry_bpc; 261 uint8_t dynamic_range_rgb = 0; /*full range*/ 262 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 263 uint8_t dp_pixel_encoding = 0; 264 uint8_t dp_component_depth = 0; 265 266 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 267 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; 268 269 if (hw_crtc_timing.flags.INTERLACE) { 270 /*the input timing is in VESA spec format with Interlace flag =1*/ 271 hw_crtc_timing.v_total /= 2; 272 hw_crtc_timing.v_border_top /= 2; 273 hw_crtc_timing.v_addressable /= 2; 274 hw_crtc_timing.v_border_bottom /= 2; 275 hw_crtc_timing.v_front_porch /= 2; 276 hw_crtc_timing.v_sync_width /= 2; 277 } 278 279 280 /* set pixel encoding */ 281 switch (hw_crtc_timing.pixel_encoding) { 282 case PIXEL_ENCODING_YCBCR422: 283 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422; 284 break; 285 case PIXEL_ENCODING_YCBCR444: 286 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444; 287 288 if (hw_crtc_timing.flags.Y_ONLY) 289 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) 290 /* HW testing only, no use case yet. 291 * Color depth of Y-only could be 292 * 8, 10, 12, 16 bits 293 */ 294 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY; 295 296 /* Note: DP_MSA_MISC1 bit 7 is the indicator 297 * of Y-only mode. 298 * This bit is set in HW if register 299 * DP_PIXEL_ENCODING is programmed to 0x4 300 */ 301 break; 302 case PIXEL_ENCODING_YCBCR420: 303 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; 304 break; 305 default: 306 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; 307 break; 308 } 309 310 misc1 = REG_READ(DP_MSA_MISC); 311 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used. 312 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the 313 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7, 314 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care"). 315 */ 316 if (use_vsc_sdp_for_colorimetry) 317 misc1 = misc1 | 0x40; 318 else 319 misc1 = misc1 & ~0x40; 320 321 /* set color depth */ 322 switch (hw_crtc_timing.display_color_depth) { 323 case COLOR_DEPTH_666: 324 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 325 break; 326 case COLOR_DEPTH_888: 327 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC; 328 break; 329 case COLOR_DEPTH_101010: 330 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC; 331 break; 332 case COLOR_DEPTH_121212: 333 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC; 334 break; 335 case COLOR_DEPTH_161616: 336 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC; 337 break; 338 default: 339 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 340 break; 341 } 342 343 /* Set DP pixel encoding and component depth */ 344 REG_UPDATE_2(DP_PIXEL_FORMAT, 345 DP_PIXEL_ENCODING, dp_pixel_encoding, 346 DP_COMPONENT_DEPTH, dp_component_depth); 347 348 /* set dynamic range and YCbCr range */ 349 350 switch (hw_crtc_timing.display_color_depth) { 351 case COLOR_DEPTH_666: 352 colorimetry_bpc = 0; 353 break; 354 case COLOR_DEPTH_888: 355 colorimetry_bpc = 1; 356 break; 357 case COLOR_DEPTH_101010: 358 colorimetry_bpc = 2; 359 break; 360 case COLOR_DEPTH_121212: 361 colorimetry_bpc = 3; 362 break; 363 default: 364 colorimetry_bpc = 0; 365 break; 366 } 367 368 misc0 = misc0 | synchronous_clock; 369 misc0 = colorimetry_bpc << 5; 370 371 switch (output_color_space) { 372 case COLOR_SPACE_SRGB: 373 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 374 dynamic_range_rgb = 0; /*full range*/ 375 break; 376 case COLOR_SPACE_SRGB_LIMITED: 377 misc0 = misc0 | 0x8; /* bit3=1 */ 378 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 379 dynamic_range_rgb = 1; /*limited range*/ 380 break; 381 case COLOR_SPACE_YCBCR601: 382 case COLOR_SPACE_YCBCR601_LIMITED: 383 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 384 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 385 dynamic_range_ycbcr = 0; /*bt601*/ 386 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 387 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 388 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 389 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 390 break; 391 case COLOR_SPACE_YCBCR709: 392 case COLOR_SPACE_YCBCR709_LIMITED: 393 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 394 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 395 dynamic_range_ycbcr = 1; /*bt709*/ 396 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 397 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 398 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 399 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 400 break; 401 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 402 dynamic_range_rgb = 1; /*limited range*/ 403 break; 404 case COLOR_SPACE_2020_RGB_FULLRANGE: 405 case COLOR_SPACE_2020_YCBCR: 406 case COLOR_SPACE_XR_RGB: 407 case COLOR_SPACE_MSREF_SCRGB: 408 case COLOR_SPACE_ADOBERGB: 409 case COLOR_SPACE_DCIP3: 410 case COLOR_SPACE_XV_YCC_709: 411 case COLOR_SPACE_XV_YCC_601: 412 case COLOR_SPACE_DISPLAYNATIVE: 413 case COLOR_SPACE_DOLBYVISION: 414 case COLOR_SPACE_APPCTRL: 415 case COLOR_SPACE_CUSTOMPOINTS: 416 case COLOR_SPACE_UNKNOWN: 417 case COLOR_SPACE_YCBCR709_BLACK: 418 /* do nothing */ 419 break; 420 } 421 422 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 423 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 424 425 /* dcn new register 426 * dc_crtc_timing is vesa dmt struct. data from edid 427 */ 428 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 429 DP_MSA_HTOTAL, hw_crtc_timing.h_total, 430 DP_MSA_VTOTAL, hw_crtc_timing.v_total); 431 432 /* calculate from vesa timing parameters 433 * h_active_start related to leading edge of sync 434 */ 435 436 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - 437 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; 438 439 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - 440 hw_crtc_timing.h_sync_width; 441 442 /* start at beginning of left border */ 443 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; 444 445 446 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - 447 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - 448 hw_crtc_timing.v_front_porch; 449 450 451 /* start at beginning of left border */ 452 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 453 DP_MSA_HSTART, h_active_start, 454 DP_MSA_VSTART, v_active_start); 455 456 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 457 DP_MSA_HSYNCWIDTH, 458 hw_crtc_timing.h_sync_width, 459 DP_MSA_HSYNCPOLARITY, 460 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, 461 DP_MSA_VSYNCWIDTH, 462 hw_crtc_timing.v_sync_width, 463 DP_MSA_VSYNCPOLARITY, 464 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); 465 466 /* HWDITH include border or overscan */ 467 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 468 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + 469 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, 470 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + 471 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); 472 } 473 474 void enc1_stream_encoder_set_stream_attribute_helper( 475 struct dcn10_stream_encoder *enc1, 476 struct dc_crtc_timing *crtc_timing) 477 { 478 switch (crtc_timing->pixel_encoding) { 479 case PIXEL_ENCODING_YCBCR422: 480 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 481 break; 482 default: 483 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 484 break; 485 } 486 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 487 } 488 489 /* setup stream encoder in hdmi mode */ 490 void enc1_stream_encoder_hdmi_set_stream_attribute( 491 struct stream_encoder *enc, 492 struct dc_crtc_timing *crtc_timing, 493 int actual_pix_clk_khz, 494 bool enable_audio) 495 { 496 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 497 struct bp_encoder_control cntl = {0}; 498 499 cntl.action = ENCODER_CONTROL_SETUP; 500 cntl.engine_id = enc1->base.id; 501 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 502 cntl.enable_dp_audio = enable_audio; 503 cntl.pixel_clock = actual_pix_clk_khz; 504 cntl.lanes_number = LANE_COUNT_FOUR; 505 506 if (enc1->base.bp->funcs->encoder_control( 507 enc1->base.bp, &cntl) != BP_RESULT_OK) 508 return; 509 510 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 511 512 /* setup HDMI engine */ 513 REG_UPDATE_6(HDMI_CONTROL, 514 HDMI_PACKET_GEN_VERSION, 1, 515 HDMI_KEEPOUT_MODE, 1, 516 HDMI_DEEP_COLOR_ENABLE, 0, 517 HDMI_DATA_SCRAMBLE_EN, 0, 518 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, 519 HDMI_CLOCK_CHANNEL_RATE, 0); 520 521 522 switch (crtc_timing->display_color_depth) { 523 case COLOR_DEPTH_888: 524 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 525 break; 526 case COLOR_DEPTH_101010: 527 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 528 REG_UPDATE_2(HDMI_CONTROL, 529 HDMI_DEEP_COLOR_DEPTH, 1, 530 HDMI_DEEP_COLOR_ENABLE, 0); 531 } else { 532 REG_UPDATE_2(HDMI_CONTROL, 533 HDMI_DEEP_COLOR_DEPTH, 1, 534 HDMI_DEEP_COLOR_ENABLE, 1); 535 } 536 break; 537 case COLOR_DEPTH_121212: 538 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 539 REG_UPDATE_2(HDMI_CONTROL, 540 HDMI_DEEP_COLOR_DEPTH, 2, 541 HDMI_DEEP_COLOR_ENABLE, 0); 542 } else { 543 REG_UPDATE_2(HDMI_CONTROL, 544 HDMI_DEEP_COLOR_DEPTH, 2, 545 HDMI_DEEP_COLOR_ENABLE, 1); 546 } 547 break; 548 case COLOR_DEPTH_161616: 549 REG_UPDATE_2(HDMI_CONTROL, 550 HDMI_DEEP_COLOR_DEPTH, 3, 551 HDMI_DEEP_COLOR_ENABLE, 1); 552 break; 553 default: 554 break; 555 } 556 557 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 558 /* enable HDMI data scrambler 559 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 560 * Clock channel frequency is 1/4 of character rate. 561 */ 562 REG_UPDATE_2(HDMI_CONTROL, 563 HDMI_DATA_SCRAMBLE_EN, 1, 564 HDMI_CLOCK_CHANNEL_RATE, 1); 565 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 566 567 /* TODO: New feature for DCE11, still need to implement */ 568 569 /* enable HDMI data scrambler 570 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 571 * Clock channel frequency is the same 572 * as character rate 573 */ 574 REG_UPDATE_2(HDMI_CONTROL, 575 HDMI_DATA_SCRAMBLE_EN, 1, 576 HDMI_CLOCK_CHANNEL_RATE, 0); 577 } 578 579 580 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 581 HDMI_GC_CONT, 1, 582 HDMI_GC_SEND, 1, 583 HDMI_NULL_SEND, 1); 584 585 /* following belongs to audio */ 586 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 587 588 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 589 590 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 591 VBI_LINE_0 + 2); 592 593 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 594 } 595 596 /* setup stream encoder in dvi mode */ 597 void enc1_stream_encoder_dvi_set_stream_attribute( 598 struct stream_encoder *enc, 599 struct dc_crtc_timing *crtc_timing, 600 bool is_dual_link) 601 { 602 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 603 struct bp_encoder_control cntl = {0}; 604 605 cntl.action = ENCODER_CONTROL_SETUP; 606 cntl.engine_id = enc1->base.id; 607 cntl.signal = is_dual_link ? 608 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 609 cntl.enable_dp_audio = false; 610 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 611 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 612 613 if (enc1->base.bp->funcs->encoder_control( 614 enc1->base.bp, &cntl) != BP_RESULT_OK) 615 return; 616 617 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 618 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 619 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 620 } 621 622 void enc1_stream_encoder_set_throttled_vcp_size( 623 struct stream_encoder *enc, 624 struct fixed31_32 avg_time_slots_per_mtp) 625 { 626 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 627 uint32_t x = dc_fixpt_floor( 628 avg_time_slots_per_mtp); 629 uint32_t y = dc_fixpt_ceil( 630 dc_fixpt_shl( 631 dc_fixpt_sub_int( 632 avg_time_slots_per_mtp, 633 x), 634 26)); 635 636 REG_SET_2(DP_MSE_RATE_CNTL, 0, 637 DP_MSE_RATE_X, x, 638 DP_MSE_RATE_Y, y); 639 640 /* wait for update to be completed on the link */ 641 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 642 /* is reset to 0 (not pending) */ 643 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 644 0, 645 10, DP_MST_UPDATE_MAX_RETRY); 646 } 647 648 static void enc1_stream_encoder_update_hdmi_info_packets( 649 struct stream_encoder *enc, 650 const struct encoder_info_frame *info_frame) 651 { 652 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 653 654 /* for bring up, disable dp double TODO */ 655 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 656 657 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi); 658 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); 659 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); 660 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd); 661 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); 662 } 663 664 static void enc1_stream_encoder_stop_hdmi_info_packets( 665 struct stream_encoder *enc) 666 { 667 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 668 669 /* stop generic packets 0 & 1 on HDMI */ 670 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 671 HDMI_GENERIC1_CONT, 0, 672 HDMI_GENERIC1_LINE, 0, 673 HDMI_GENERIC1_SEND, 0, 674 HDMI_GENERIC0_CONT, 0, 675 HDMI_GENERIC0_LINE, 0, 676 HDMI_GENERIC0_SEND, 0); 677 678 /* stop generic packets 2 & 3 on HDMI */ 679 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 680 HDMI_GENERIC0_CONT, 0, 681 HDMI_GENERIC0_LINE, 0, 682 HDMI_GENERIC0_SEND, 0, 683 HDMI_GENERIC1_CONT, 0, 684 HDMI_GENERIC1_LINE, 0, 685 HDMI_GENERIC1_SEND, 0); 686 687 /* stop generic packets 2 & 3 on HDMI */ 688 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 689 HDMI_GENERIC0_CONT, 0, 690 HDMI_GENERIC0_LINE, 0, 691 HDMI_GENERIC0_SEND, 0, 692 HDMI_GENERIC1_CONT, 0, 693 HDMI_GENERIC1_LINE, 0, 694 HDMI_GENERIC1_SEND, 0); 695 696 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 697 HDMI_GENERIC0_CONT, 0, 698 HDMI_GENERIC0_LINE, 0, 699 HDMI_GENERIC0_SEND, 0, 700 HDMI_GENERIC1_CONT, 0, 701 HDMI_GENERIC1_LINE, 0, 702 HDMI_GENERIC1_SEND, 0); 703 } 704 705 void enc1_stream_encoder_update_dp_info_packets( 706 struct stream_encoder *enc, 707 const struct encoder_info_frame *info_frame) 708 { 709 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 710 uint32_t value = 0; 711 712 if (info_frame->vsc.valid) 713 enc1_update_generic_info_packet( 714 enc1, 715 0, /* packetIndex */ 716 &info_frame->vsc); 717 718 if (info_frame->spd.valid) 719 enc1_update_generic_info_packet( 720 enc1, 721 2, /* packetIndex */ 722 &info_frame->spd); 723 724 if (info_frame->hdrsmd.valid) 725 enc1_update_generic_info_packet( 726 enc1, 727 3, /* packetIndex */ 728 &info_frame->hdrsmd); 729 730 /* packetIndex 4 is used for send immediate sdp message, and please 731 * use other packetIndex (such as 5,6) for other info packet 732 */ 733 734 /* enable/disable transmission of packet(s). 735 * If enabled, packet transmission begins on the next frame 736 */ 737 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 738 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 739 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 740 741 /* This bit is the master enable bit. 742 * When enabling secondary stream engine, 743 * this master bit must also be set. 744 * This register shared with audio info frame. 745 * Therefore we need to enable master bit 746 * if at least on of the fields is not 0 747 */ 748 value = REG_READ(DP_SEC_CNTL); 749 if (value) 750 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 751 } 752 753 void enc1_stream_encoder_send_immediate_sdp_message( 754 struct stream_encoder *enc, 755 const uint8_t *custom_sdp_message, 756 unsigned int sdp_message_size) 757 { 758 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 759 uint32_t value = 0; 760 761 /* TODOFPGA Figure out a proper number for max_retries polling for lock 762 * use 50 for now. 763 */ 764 uint32_t max_retries = 50; 765 766 /* check if GSP4 is transmitted */ 767 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, 768 0, 10, max_retries); 769 770 /* disable GSP4 transmitting */ 771 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0); 772 773 /* transmit GSP4 at the earliest time in a frame */ 774 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1); 775 776 /*we need turn on clock before programming AFMT block*/ 777 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 778 779 /* check if HW reading GSP memory */ 780 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 781 0, 10, max_retries); 782 783 /* HW does is not reading GSP memory not reading too long -> 784 * something wrong. clear GPS memory access and notify? 785 * hw SW is writing to GSP memory 786 */ 787 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 788 789 /* use generic packet 4 for immediate sdp message */ 790 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 791 AFMT_GENERIC_INDEX, 4); 792 793 /* write generic packet header 794 * (4th byte is for GENERIC0 only) 795 */ 796 REG_SET_4(AFMT_GENERIC_HDR, 0, 797 AFMT_GENERIC_HB0, custom_sdp_message[0], 798 AFMT_GENERIC_HB1, custom_sdp_message[1], 799 AFMT_GENERIC_HB2, custom_sdp_message[2], 800 AFMT_GENERIC_HB3, custom_sdp_message[3]); 801 802 /* write generic packet contents 803 * (we never use last 4 bytes) 804 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 805 */ 806 { 807 const uint32_t *content = 808 (const uint32_t *) &custom_sdp_message[4]; 809 810 REG_WRITE(AFMT_GENERIC_0, *content++); 811 REG_WRITE(AFMT_GENERIC_1, *content++); 812 REG_WRITE(AFMT_GENERIC_2, *content++); 813 REG_WRITE(AFMT_GENERIC_3, *content++); 814 REG_WRITE(AFMT_GENERIC_4, *content++); 815 REG_WRITE(AFMT_GENERIC_5, *content++); 816 REG_WRITE(AFMT_GENERIC_6, *content++); 817 REG_WRITE(AFMT_GENERIC_7, *content); 818 } 819 820 /* check whether GENERIC4 registers double buffer update in immediate mode 821 * is pending 822 */ 823 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, 824 0, 10, max_retries); 825 826 /* atomically update double-buffered GENERIC4 registers in immediate mode 827 * (update immediately) 828 */ 829 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 830 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1); 831 832 /* enable GSP4 transmitting */ 833 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1); 834 835 /* This bit is the master enable bit. 836 * When enabling secondary stream engine, 837 * this master bit must also be set. 838 * This register shared with audio info frame. 839 * Therefore we need to enable master bit 840 * if at least on of the fields is not 0 841 */ 842 value = REG_READ(DP_SEC_CNTL); 843 if (value) 844 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 845 } 846 847 void enc1_stream_encoder_stop_dp_info_packets( 848 struct stream_encoder *enc) 849 { 850 /* stop generic packets on DP */ 851 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 852 uint32_t value = 0; 853 854 REG_SET_10(DP_SEC_CNTL, 0, 855 DP_SEC_GSP0_ENABLE, 0, 856 DP_SEC_GSP1_ENABLE, 0, 857 DP_SEC_GSP2_ENABLE, 0, 858 DP_SEC_GSP3_ENABLE, 0, 859 DP_SEC_GSP4_ENABLE, 0, 860 DP_SEC_GSP5_ENABLE, 0, 861 DP_SEC_GSP6_ENABLE, 0, 862 DP_SEC_GSP7_ENABLE, 0, 863 DP_SEC_MPG_ENABLE, 0, 864 DP_SEC_STREAM_ENABLE, 0); 865 866 /* this register shared with audio info frame. 867 * therefore we need to keep master enabled 868 * if at least one of the fields is not 0 */ 869 value = REG_READ(DP_SEC_CNTL); 870 if (value) 871 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 872 873 } 874 875 void enc1_stream_encoder_dp_blank( 876 struct stream_encoder *enc) 877 { 878 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 879 uint32_t reg1 = 0; 880 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 881 882 /* Note: For CZ, we are changing driver default to disable 883 * stream deferred to next VBLANK. If results are positive, we 884 * will make the same change to all DCE versions. There are a 885 * handful of panels that cannot handle disable stream at 886 * HBLANK and will result in a white line flash across the 887 * screen on stream disable. 888 */ 889 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 890 if ((reg1 & 0x1) == 0) 891 /*stream not enabled*/ 892 return; 893 /* Specify the video stream disable point 894 * (2 = start of the next vertical blank) 895 */ 896 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 897 /* Larger delay to wait until VBLANK - use max retry of 898 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode + 899 * a little more because we may not trust delay accuracy. 900 */ 901 max_retries = DP_BLANK_MAX_RETRY * 501; 902 903 /* disable DP stream */ 904 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 905 906 /* the encoder stops sending the video stream 907 * at the start of the vertical blanking. 908 * Poll for DP_VID_STREAM_STATUS == 0 909 */ 910 911 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 912 0, 913 10, max_retries); 914 915 /* Tell the DP encoder to ignore timing from CRTC, must be done after 916 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 917 * complete, stream status will be stuck in video stream enabled state, 918 * i.e. DP_VID_STREAM_STATUS stuck at 1. 919 */ 920 921 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 922 } 923 924 /* output video stream to link encoder */ 925 void enc1_stream_encoder_dp_unblank( 926 struct stream_encoder *enc, 927 const struct encoder_unblank_param *param) 928 { 929 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 930 931 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 932 uint32_t n_vid = 0x8000; 933 uint32_t m_vid; 934 uint32_t n_multiply = 0; 935 uint64_t m_vid_l = n_vid; 936 937 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ 938 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 939 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/ 940 n_multiply = 1; 941 } 942 /* M / N = Fstream / Flink 943 * m_vid / n_vid = pixel rate / link rate 944 */ 945 946 m_vid_l *= param->timing.pix_clk_100hz / 10; 947 m_vid_l = div_u64(m_vid_l, 948 param->link_settings.link_rate 949 * LINK_RATE_REF_FREQ_IN_KHZ); 950 951 m_vid = (uint32_t) m_vid_l; 952 953 /* enable auto measurement */ 954 955 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 956 957 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 958 * therefore program initial value for Mvid and Nvid 959 */ 960 961 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 962 963 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 964 965 REG_UPDATE_2(DP_VID_TIMING, 966 DP_VID_M_N_GEN_EN, 1, 967 DP_VID_N_MUL, n_multiply); 968 } 969 970 /* set DIG_START to 0x1 to resync FIFO */ 971 972 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 973 974 /* switch DP encoder to CRTC data */ 975 976 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 977 978 /* wait 100us for DIG/DP logic to prime 979 * (i.e. a few video lines) 980 */ 981 udelay(100); 982 983 /* the hardware would start sending video at the start of the next DP 984 * frame (i.e. rising edge of the vblank). 985 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 986 * register has no effect on enable transition! HW always guarantees 987 * VID_STREAM enable at start of next frame, and this is not 988 * programmable 989 */ 990 991 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 992 } 993 994 void enc1_stream_encoder_set_avmute( 995 struct stream_encoder *enc, 996 bool enable) 997 { 998 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 999 unsigned int value = enable ? 1 : 0; 1000 1001 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1002 } 1003 1004 void enc1_reset_hdmi_stream_attribute( 1005 struct stream_encoder *enc) 1006 { 1007 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1008 1009 REG_UPDATE_5(HDMI_CONTROL, 1010 HDMI_PACKET_GEN_VERSION, 1, 1011 HDMI_KEEPOUT_MODE, 1, 1012 HDMI_DEEP_COLOR_ENABLE, 0, 1013 HDMI_DATA_SCRAMBLE_EN, 0, 1014 HDMI_CLOCK_CHANNEL_RATE, 0); 1015 } 1016 1017 1018 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1019 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1020 1021 #include "include/audio_types.h" 1022 1023 1024 /* 25.2MHz/1.001*/ 1025 /* 25.2MHz/1.001*/ 1026 /* 25.2MHz*/ 1027 /* 27MHz */ 1028 /* 27MHz*1.001*/ 1029 /* 27MHz*1.001*/ 1030 /* 54MHz*/ 1031 /* 54MHz*1.001*/ 1032 /* 74.25MHz/1.001*/ 1033 /* 74.25MHz*/ 1034 /* 148.5MHz/1.001*/ 1035 /* 148.5MHz*/ 1036 1037 static const struct audio_clock_info audio_clock_info_table[16] = { 1038 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1039 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1040 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1041 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1042 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1043 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1044 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1045 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1046 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1047 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1048 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1049 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1050 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1051 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1052 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1053 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1054 }; 1055 1056 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1057 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1058 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1059 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1060 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1061 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1062 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1063 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1064 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1065 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1066 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1067 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1068 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1069 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1070 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1071 }; 1072 1073 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1074 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1075 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1076 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1077 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1078 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1079 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1080 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1081 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1082 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1083 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1084 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1085 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1086 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1087 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1088 1089 1090 }; 1091 1092 static union audio_cea_channels speakers_to_channels( 1093 struct audio_speaker_flags speaker_flags) 1094 { 1095 union audio_cea_channels cea_channels = {0}; 1096 1097 /* these are one to one */ 1098 cea_channels.channels.FL = speaker_flags.FL_FR; 1099 cea_channels.channels.FR = speaker_flags.FL_FR; 1100 cea_channels.channels.LFE = speaker_flags.LFE; 1101 cea_channels.channels.FC = speaker_flags.FC; 1102 1103 /* if Rear Left and Right exist move RC speaker to channel 7 1104 * otherwise to channel 5 1105 */ 1106 if (speaker_flags.RL_RR) { 1107 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1108 cea_channels.channels.RR = speaker_flags.RL_RR; 1109 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1110 } else { 1111 cea_channels.channels.RL_RC = speaker_flags.RC; 1112 } 1113 1114 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1115 if (speaker_flags.FLC_FRC) { 1116 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1117 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1118 } else { 1119 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1120 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1121 } 1122 1123 return cea_channels; 1124 } 1125 1126 void get_audio_clock_info( 1127 enum dc_color_depth color_depth, 1128 uint32_t crtc_pixel_clock_100Hz, 1129 uint32_t actual_pixel_clock_100Hz, 1130 struct audio_clock_info *audio_clock_info) 1131 { 1132 const struct audio_clock_info *clock_info; 1133 uint32_t index; 1134 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; 1135 uint32_t audio_array_size; 1136 1137 switch (color_depth) { 1138 case COLOR_DEPTH_161616: 1139 clock_info = audio_clock_info_table_48bpc; 1140 audio_array_size = ARRAY_SIZE( 1141 audio_clock_info_table_48bpc); 1142 break; 1143 case COLOR_DEPTH_121212: 1144 clock_info = audio_clock_info_table_36bpc; 1145 audio_array_size = ARRAY_SIZE( 1146 audio_clock_info_table_36bpc); 1147 break; 1148 default: 1149 clock_info = audio_clock_info_table; 1150 audio_array_size = ARRAY_SIZE( 1151 audio_clock_info_table); 1152 break; 1153 } 1154 1155 if (clock_info != NULL) { 1156 /* search for exact pixel clock in table */ 1157 for (index = 0; index < audio_array_size; index++) { 1158 if (clock_info[index].pixel_clock_in_10khz > 1159 crtc_pixel_clock_in_10khz) 1160 break; /* not match */ 1161 else if (clock_info[index].pixel_clock_in_10khz == 1162 crtc_pixel_clock_in_10khz) { 1163 /* match found */ 1164 *audio_clock_info = clock_info[index]; 1165 return; 1166 } 1167 } 1168 } 1169 1170 /* not found */ 1171 if (actual_pixel_clock_100Hz == 0) 1172 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; 1173 1174 /* See HDMI spec the table entry under 1175 * pixel clock of "Other". */ 1176 audio_clock_info->pixel_clock_in_10khz = 1177 actual_pixel_clock_100Hz / 100; 1178 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; 1179 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; 1180 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; 1181 1182 audio_clock_info->n_32khz = 4096; 1183 audio_clock_info->n_44khz = 6272; 1184 audio_clock_info->n_48khz = 6144; 1185 } 1186 1187 static void enc1_se_audio_setup( 1188 struct stream_encoder *enc, 1189 unsigned int az_inst, 1190 struct audio_info *audio_info) 1191 { 1192 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1193 1194 uint32_t channels = 0; 1195 1196 ASSERT(audio_info); 1197 if (audio_info == NULL) 1198 /* This should not happen.it does so we don't get BSOD*/ 1199 return; 1200 1201 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1202 1203 /* setup the audio stream source select (audio -> dig mapping) */ 1204 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1205 1206 /* Channel allocation */ 1207 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1208 } 1209 1210 static void enc1_se_setup_hdmi_audio( 1211 struct stream_encoder *enc, 1212 const struct audio_crtc_info *crtc_info) 1213 { 1214 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1215 1216 struct audio_clock_info audio_clock_info = {0}; 1217 1218 /* HDMI_AUDIO_PACKET_CONTROL */ 1219 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, 1220 HDMI_AUDIO_DELAY_EN, 1); 1221 1222 /* AFMT_AUDIO_PACKET_CONTROL */ 1223 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1224 1225 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1226 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1227 AFMT_AUDIO_LAYOUT_OVRD, 0, 1228 AFMT_60958_OSF_OVRD, 0); 1229 1230 /* HDMI_ACR_PACKET_CONTROL */ 1231 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1232 HDMI_ACR_AUTO_SEND, 1, 1233 HDMI_ACR_SOURCE, 0, 1234 HDMI_ACR_AUDIO_PRIORITY, 0); 1235 1236 /* Program audio clock sample/regeneration parameters */ 1237 get_audio_clock_info(crtc_info->color_depth, 1238 crtc_info->requested_pixel_clock_100Hz, 1239 crtc_info->calculated_pixel_clock_100Hz, 1240 &audio_clock_info); 1241 DC_LOG_HW_AUDIO( 1242 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 1243 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 1244 crtc_info->requested_pixel_clock_100Hz, \ 1245 crtc_info->calculated_pixel_clock_100Hz); 1246 1247 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1248 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1249 1250 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1251 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1252 1253 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1254 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1255 1256 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1257 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1258 1259 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1260 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1261 1262 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1263 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1264 1265 /* Video driver cannot know in advance which sample rate will 1266 * be used by HD Audio driver 1267 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1268 * programmed below in interruppt callback 1269 */ 1270 1271 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1272 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 1273 */ 1274 REG_UPDATE_2(AFMT_60958_0, 1275 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1276 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1277 1278 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1279 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1280 1281 /* AFMT_60958_2 now keep this settings until 1282 * Programming guide comes out 1283 */ 1284 REG_UPDATE_6(AFMT_60958_2, 1285 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1286 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1287 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1288 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1289 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1290 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1291 } 1292 1293 static void enc1_se_setup_dp_audio( 1294 struct stream_encoder *enc) 1295 { 1296 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1297 1298 /* --- DP Audio packet configurations --- */ 1299 1300 /* ATP Configuration */ 1301 REG_SET(DP_SEC_AUD_N, 0, 1302 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1303 1304 /* Async/auto-calc timestamp mode */ 1305 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1306 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1307 1308 /* --- The following are the registers 1309 * copied from the SetupHDMI --- 1310 */ 1311 1312 /* AFMT_AUDIO_PACKET_CONTROL */ 1313 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1314 1315 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1316 /* Program the ATP and AIP next */ 1317 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1318 AFMT_AUDIO_LAYOUT_OVRD, 0, 1319 AFMT_60958_OSF_OVRD, 0); 1320 1321 /* AFMT_INFOFRAME_CONTROL0 */ 1322 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1323 1324 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1325 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1326 } 1327 1328 void enc1_se_enable_audio_clock( 1329 struct stream_encoder *enc, 1330 bool enable) 1331 { 1332 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1333 1334 if (REG(AFMT_CNTL) == 0) 1335 return; /* DCE8/10 does not have this register */ 1336 1337 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1338 1339 /* wait for AFMT clock to turn on, 1340 * expectation: this should complete in 1-2 reads 1341 * 1342 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1343 * 1344 * TODO: wait for clock_on does not work well. May need HW 1345 * program sequence. But audio seems work normally even without wait 1346 * for clock_on status change 1347 */ 1348 } 1349 1350 void enc1_se_enable_dp_audio( 1351 struct stream_encoder *enc) 1352 { 1353 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1354 1355 /* Enable Audio packets */ 1356 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1357 1358 /* Program the ATP and AIP next */ 1359 REG_UPDATE_2(DP_SEC_CNTL, 1360 DP_SEC_ATP_ENABLE, 1, 1361 DP_SEC_AIP_ENABLE, 1); 1362 1363 /* Program STREAM_ENABLE after all the other enables. */ 1364 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1365 } 1366 1367 static void enc1_se_disable_dp_audio( 1368 struct stream_encoder *enc) 1369 { 1370 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1371 uint32_t value = 0; 1372 1373 /* Disable Audio packets */ 1374 REG_UPDATE_5(DP_SEC_CNTL, 1375 DP_SEC_ASP_ENABLE, 0, 1376 DP_SEC_ATP_ENABLE, 0, 1377 DP_SEC_AIP_ENABLE, 0, 1378 DP_SEC_ACM_ENABLE, 0, 1379 DP_SEC_STREAM_ENABLE, 0); 1380 1381 /* This register shared with encoder info frame. Therefore we need to 1382 * keep master enabled if at least on of the fields is not 0 1383 */ 1384 value = REG_READ(DP_SEC_CNTL); 1385 if (value != 0) 1386 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1387 1388 } 1389 1390 void enc1_se_audio_mute_control( 1391 struct stream_encoder *enc, 1392 bool mute) 1393 { 1394 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1395 1396 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1397 } 1398 1399 void enc1_se_dp_audio_setup( 1400 struct stream_encoder *enc, 1401 unsigned int az_inst, 1402 struct audio_info *info) 1403 { 1404 enc1_se_audio_setup(enc, az_inst, info); 1405 } 1406 1407 void enc1_se_dp_audio_enable( 1408 struct stream_encoder *enc) 1409 { 1410 enc1_se_enable_audio_clock(enc, true); 1411 enc1_se_setup_dp_audio(enc); 1412 enc1_se_enable_dp_audio(enc); 1413 } 1414 1415 void enc1_se_dp_audio_disable( 1416 struct stream_encoder *enc) 1417 { 1418 enc1_se_disable_dp_audio(enc); 1419 enc1_se_enable_audio_clock(enc, false); 1420 } 1421 1422 void enc1_se_hdmi_audio_setup( 1423 struct stream_encoder *enc, 1424 unsigned int az_inst, 1425 struct audio_info *info, 1426 struct audio_crtc_info *audio_crtc_info) 1427 { 1428 enc1_se_enable_audio_clock(enc, true); 1429 enc1_se_setup_hdmi_audio(enc, audio_crtc_info); 1430 enc1_se_audio_setup(enc, az_inst, info); 1431 } 1432 1433 void enc1_se_hdmi_audio_disable( 1434 struct stream_encoder *enc) 1435 { 1436 enc1_se_enable_audio_clock(enc, false); 1437 } 1438 1439 1440 void enc1_setup_stereo_sync( 1441 struct stream_encoder *enc, 1442 int tg_inst, bool enable) 1443 { 1444 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1445 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1446 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1447 } 1448 1449 void enc1_dig_connect_to_otg( 1450 struct stream_encoder *enc, 1451 int tg_inst) 1452 { 1453 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1454 1455 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); 1456 } 1457 1458 unsigned int enc1_dig_source_otg( 1459 struct stream_encoder *enc) 1460 { 1461 uint32_t tg_inst = 0; 1462 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1463 1464 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); 1465 1466 return tg_inst; 1467 } 1468 1469 bool enc1_stream_encoder_dp_get_pixel_format( 1470 struct stream_encoder *enc, 1471 enum dc_pixel_encoding *encoding, 1472 enum dc_color_depth *depth) 1473 { 1474 uint32_t hw_encoding = 0; 1475 uint32_t hw_depth = 0; 1476 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1477 1478 if (enc == NULL || 1479 encoding == NULL || 1480 depth == NULL) 1481 return false; 1482 1483 REG_GET_2(DP_PIXEL_FORMAT, 1484 DP_PIXEL_ENCODING, &hw_encoding, 1485 DP_COMPONENT_DEPTH, &hw_depth); 1486 1487 switch (hw_depth) { 1488 case DP_COMPONENT_PIXEL_DEPTH_6BPC: 1489 *depth = COLOR_DEPTH_666; 1490 break; 1491 case DP_COMPONENT_PIXEL_DEPTH_8BPC: 1492 *depth = COLOR_DEPTH_888; 1493 break; 1494 case DP_COMPONENT_PIXEL_DEPTH_10BPC: 1495 *depth = COLOR_DEPTH_101010; 1496 break; 1497 case DP_COMPONENT_PIXEL_DEPTH_12BPC: 1498 *depth = COLOR_DEPTH_121212; 1499 break; 1500 case DP_COMPONENT_PIXEL_DEPTH_16BPC: 1501 *depth = COLOR_DEPTH_161616; 1502 break; 1503 default: 1504 *depth = COLOR_DEPTH_UNDEFINED; 1505 break; 1506 } 1507 1508 switch (hw_encoding) { 1509 case DP_PIXEL_ENCODING_TYPE_RGB444: 1510 *encoding = PIXEL_ENCODING_RGB; 1511 break; 1512 case DP_PIXEL_ENCODING_TYPE_YCBCR422: 1513 *encoding = PIXEL_ENCODING_YCBCR422; 1514 break; 1515 case DP_PIXEL_ENCODING_TYPE_YCBCR444: 1516 case DP_PIXEL_ENCODING_TYPE_Y_ONLY: 1517 *encoding = PIXEL_ENCODING_YCBCR444; 1518 break; 1519 case DP_PIXEL_ENCODING_TYPE_YCBCR420: 1520 *encoding = PIXEL_ENCODING_YCBCR420; 1521 break; 1522 default: 1523 *encoding = PIXEL_ENCODING_UNDEFINED; 1524 break; 1525 } 1526 return true; 1527 } 1528 1529 static const struct stream_encoder_funcs dcn10_str_enc_funcs = { 1530 .dp_set_stream_attribute = 1531 enc1_stream_encoder_dp_set_stream_attribute, 1532 .hdmi_set_stream_attribute = 1533 enc1_stream_encoder_hdmi_set_stream_attribute, 1534 .dvi_set_stream_attribute = 1535 enc1_stream_encoder_dvi_set_stream_attribute, 1536 .set_throttled_vcp_size = 1537 enc1_stream_encoder_set_throttled_vcp_size, 1538 .update_hdmi_info_packets = 1539 enc1_stream_encoder_update_hdmi_info_packets, 1540 .stop_hdmi_info_packets = 1541 enc1_stream_encoder_stop_hdmi_info_packets, 1542 .update_dp_info_packets = 1543 enc1_stream_encoder_update_dp_info_packets, 1544 .send_immediate_sdp_message = 1545 enc1_stream_encoder_send_immediate_sdp_message, 1546 .stop_dp_info_packets = 1547 enc1_stream_encoder_stop_dp_info_packets, 1548 .dp_blank = 1549 enc1_stream_encoder_dp_blank, 1550 .dp_unblank = 1551 enc1_stream_encoder_dp_unblank, 1552 .audio_mute_control = enc1_se_audio_mute_control, 1553 1554 .dp_audio_setup = enc1_se_dp_audio_setup, 1555 .dp_audio_enable = enc1_se_dp_audio_enable, 1556 .dp_audio_disable = enc1_se_dp_audio_disable, 1557 1558 .hdmi_audio_setup = enc1_se_hdmi_audio_setup, 1559 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 1560 .setup_stereo_sync = enc1_setup_stereo_sync, 1561 .set_avmute = enc1_stream_encoder_set_avmute, 1562 .dig_connect_to_otg = enc1_dig_connect_to_otg, 1563 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, 1564 .dig_source_otg = enc1_dig_source_otg, 1565 1566 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, 1567 }; 1568 1569 void dcn10_stream_encoder_construct( 1570 struct dcn10_stream_encoder *enc1, 1571 struct dc_context *ctx, 1572 struct dc_bios *bp, 1573 enum engine_id eng_id, 1574 const struct dcn10_stream_enc_registers *regs, 1575 const struct dcn10_stream_encoder_shift *se_shift, 1576 const struct dcn10_stream_encoder_mask *se_mask) 1577 { 1578 enc1->base.funcs = &dcn10_str_enc_funcs; 1579 enc1->base.ctx = ctx; 1580 enc1->base.id = eng_id; 1581 enc1->base.bp = bp; 1582 enc1->regs = regs; 1583 enc1->se_shift = se_shift; 1584 enc1->se_mask = se_mask; 1585 enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA; 1586 } 1587 1588