10c41891cSEric Bernstein /* 20c41891cSEric Bernstein * Copyright 2012-15 Advanced Micro Devices, Inc. 30c41891cSEric Bernstein * 40c41891cSEric Bernstein * Permission is hereby granted, free of charge, to any person obtaining a 50c41891cSEric Bernstein * copy of this software and associated documentation files (the "Software"), 60c41891cSEric Bernstein * to deal in the Software without restriction, including without limitation 70c41891cSEric Bernstein * the rights to use, copy, modify, merge, publish, distribute, sublicense, 80c41891cSEric Bernstein * and/or sell copies of the Software, and to permit persons to whom the 90c41891cSEric Bernstein * Software is furnished to do so, subject to the following conditions: 100c41891cSEric Bernstein * 110c41891cSEric Bernstein * The above copyright notice and this permission notice shall be included in 120c41891cSEric Bernstein * all copies or substantial portions of the Software. 130c41891cSEric Bernstein * 140c41891cSEric Bernstein * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 150c41891cSEric Bernstein * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 160c41891cSEric Bernstein * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 170c41891cSEric Bernstein * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 180c41891cSEric Bernstein * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 190c41891cSEric Bernstein * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 200c41891cSEric Bernstein * OTHER DEALINGS IN THE SOFTWARE. 210c41891cSEric Bernstein * 220c41891cSEric Bernstein * Authors: AMD 230c41891cSEric Bernstein * 240c41891cSEric Bernstein */ 250c41891cSEric Bernstein 260c41891cSEric Bernstein 270c41891cSEric Bernstein #include "dc_bios_types.h" 280c41891cSEric Bernstein #include "dcn10_stream_encoder.h" 290c41891cSEric Bernstein #include "reg_helper.h" 30c5011872SEric Bernstein #include "hw_shared.h" 31c5011872SEric Bernstein 320c41891cSEric Bernstein #define DC_LOGGER \ 330c41891cSEric Bernstein enc1->base.ctx->logger 340c41891cSEric Bernstein 350c41891cSEric Bernstein 360c41891cSEric Bernstein #define REG(reg)\ 370c41891cSEric Bernstein (enc1->regs->reg) 380c41891cSEric Bernstein 390c41891cSEric Bernstein #undef FN 400c41891cSEric Bernstein #define FN(reg_name, field_name) \ 410c41891cSEric Bernstein enc1->se_shift->field_name, enc1->se_mask->field_name 420c41891cSEric Bernstein 430c41891cSEric Bernstein #define VBI_LINE_0 0 440c41891cSEric Bernstein #define DP_BLANK_MAX_RETRY 20 450c41891cSEric Bernstein #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 460c41891cSEric Bernstein 470c41891cSEric Bernstein 480c41891cSEric Bernstein enum { 490c41891cSEric Bernstein DP_MST_UPDATE_MAX_RETRY = 50 500c41891cSEric Bernstein }; 510c41891cSEric Bernstein 520c41891cSEric Bernstein #define CTX \ 530c41891cSEric Bernstein enc1->base.ctx 540c41891cSEric Bernstein 55c5011872SEric Bernstein void enc1_update_generic_info_packet( 560c41891cSEric Bernstein struct dcn10_stream_encoder *enc1, 570c41891cSEric Bernstein uint32_t packet_index, 580c41891cSEric Bernstein const struct dc_info_packet *info_packet) 590c41891cSEric Bernstein { 600c41891cSEric Bernstein uint32_t regval; 610c41891cSEric Bernstein /* TODOFPGA Figure out a proper number for max_retries polling for lock 620c41891cSEric Bernstein * use 50 for now. 630c41891cSEric Bernstein */ 640c41891cSEric Bernstein uint32_t max_retries = 50; 650c41891cSEric Bernstein 660c41891cSEric Bernstein /*we need turn on clock before programming AFMT block*/ 670c41891cSEric Bernstein REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 680c41891cSEric Bernstein 690c41891cSEric Bernstein if (packet_index >= 8) 700c41891cSEric Bernstein ASSERT(0); 710c41891cSEric Bernstein 720c41891cSEric Bernstein /* poll dig_update_lock is not locked -> asic internal signal 730c41891cSEric Bernstein * assume otg master lock will unlock it 740c41891cSEric Bernstein */ 750c41891cSEric Bernstein /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 760c41891cSEric Bernstein 0, 10, max_retries);*/ 770c41891cSEric Bernstein 780c41891cSEric Bernstein /* check if HW reading GSP memory */ 790c41891cSEric Bernstein REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 800c41891cSEric Bernstein 0, 10, max_retries); 810c41891cSEric Bernstein 820c41891cSEric Bernstein /* HW does is not reading GSP memory not reading too long -> 830c41891cSEric Bernstein * something wrong. clear GPS memory access and notify? 840c41891cSEric Bernstein * hw SW is writing to GSP memory 850c41891cSEric Bernstein */ 860c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 870c41891cSEric Bernstein 880c41891cSEric Bernstein /* choose which generic packet to use */ 890c41891cSEric Bernstein regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 900c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 910c41891cSEric Bernstein AFMT_GENERIC_INDEX, packet_index); 920c41891cSEric Bernstein 930c41891cSEric Bernstein /* write generic packet header 940c41891cSEric Bernstein * (4th byte is for GENERIC0 only) 950c41891cSEric Bernstein */ 960c41891cSEric Bernstein REG_SET_4(AFMT_GENERIC_HDR, 0, 970c41891cSEric Bernstein AFMT_GENERIC_HB0, info_packet->hb0, 980c41891cSEric Bernstein AFMT_GENERIC_HB1, info_packet->hb1, 990c41891cSEric Bernstein AFMT_GENERIC_HB2, info_packet->hb2, 1000c41891cSEric Bernstein AFMT_GENERIC_HB3, info_packet->hb3); 1010c41891cSEric Bernstein 1020c41891cSEric Bernstein /* write generic packet contents 1030c41891cSEric Bernstein * (we never use last 4 bytes) 1040c41891cSEric Bernstein * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 1050c41891cSEric Bernstein */ 1060c41891cSEric Bernstein { 1070c41891cSEric Bernstein const uint32_t *content = 1080c41891cSEric Bernstein (const uint32_t *) &info_packet->sb[0]; 1090c41891cSEric Bernstein 1100c41891cSEric Bernstein REG_WRITE(AFMT_GENERIC_0, *content++); 1110c41891cSEric Bernstein REG_WRITE(AFMT_GENERIC_1, *content++); 1120c41891cSEric Bernstein REG_WRITE(AFMT_GENERIC_2, *content++); 1130c41891cSEric Bernstein REG_WRITE(AFMT_GENERIC_3, *content++); 1140c41891cSEric Bernstein REG_WRITE(AFMT_GENERIC_4, *content++); 1150c41891cSEric Bernstein REG_WRITE(AFMT_GENERIC_5, *content++); 1160c41891cSEric Bernstein REG_WRITE(AFMT_GENERIC_6, *content++); 1170c41891cSEric Bernstein REG_WRITE(AFMT_GENERIC_7, *content); 1180c41891cSEric Bernstein } 1190c41891cSEric Bernstein 1200c41891cSEric Bernstein switch (packet_index) { 1210c41891cSEric Bernstein case 0: 1220c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 1230c41891cSEric Bernstein AFMT_GENERIC0_FRAME_UPDATE, 1); 1240c41891cSEric Bernstein break; 1250c41891cSEric Bernstein case 1: 1260c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 1270c41891cSEric Bernstein AFMT_GENERIC1_FRAME_UPDATE, 1); 1280c41891cSEric Bernstein break; 1290c41891cSEric Bernstein case 2: 1300c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 1310c41891cSEric Bernstein AFMT_GENERIC2_FRAME_UPDATE, 1); 1320c41891cSEric Bernstein break; 1330c41891cSEric Bernstein case 3: 1340c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 1350c41891cSEric Bernstein AFMT_GENERIC3_FRAME_UPDATE, 1); 1360c41891cSEric Bernstein break; 1370c41891cSEric Bernstein case 4: 1380c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 1390c41891cSEric Bernstein AFMT_GENERIC4_FRAME_UPDATE, 1); 1400c41891cSEric Bernstein break; 1410c41891cSEric Bernstein case 5: 1420c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 1430c41891cSEric Bernstein AFMT_GENERIC5_FRAME_UPDATE, 1); 1440c41891cSEric Bernstein break; 1450c41891cSEric Bernstein case 6: 1460c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 1470c41891cSEric Bernstein AFMT_GENERIC6_FRAME_UPDATE, 1); 1480c41891cSEric Bernstein break; 1490c41891cSEric Bernstein case 7: 1500c41891cSEric Bernstein REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 1510c41891cSEric Bernstein AFMT_GENERIC7_FRAME_UPDATE, 1); 1520c41891cSEric Bernstein break; 1530c41891cSEric Bernstein default: 1540c41891cSEric Bernstein break; 1550c41891cSEric Bernstein } 1560c41891cSEric Bernstein } 1570c41891cSEric Bernstein 1580c41891cSEric Bernstein static void enc1_update_hdmi_info_packet( 1590c41891cSEric Bernstein struct dcn10_stream_encoder *enc1, 1600c41891cSEric Bernstein uint32_t packet_index, 1610c41891cSEric Bernstein const struct dc_info_packet *info_packet) 1620c41891cSEric Bernstein { 1630c41891cSEric Bernstein uint32_t cont, send, line; 1640c41891cSEric Bernstein 1650c41891cSEric Bernstein if (info_packet->valid) { 1660c41891cSEric Bernstein enc1_update_generic_info_packet( 1670c41891cSEric Bernstein enc1, 1680c41891cSEric Bernstein packet_index, 1690c41891cSEric Bernstein info_packet); 1700c41891cSEric Bernstein 1710c41891cSEric Bernstein /* enable transmission of packet(s) - 1720c41891cSEric Bernstein * packet transmission begins on the next frame 1730c41891cSEric Bernstein */ 1740c41891cSEric Bernstein cont = 1; 1750c41891cSEric Bernstein /* send packet(s) every frame */ 1760c41891cSEric Bernstein send = 1; 1770c41891cSEric Bernstein /* select line number to send packets on */ 1780c41891cSEric Bernstein line = 2; 1790c41891cSEric Bernstein } else { 1800c41891cSEric Bernstein cont = 0; 1810c41891cSEric Bernstein send = 0; 1820c41891cSEric Bernstein line = 0; 1830c41891cSEric Bernstein } 1840c41891cSEric Bernstein 1850c41891cSEric Bernstein /* choose which generic packet control to use */ 1860c41891cSEric Bernstein switch (packet_index) { 1870c41891cSEric Bernstein case 0: 1880c41891cSEric Bernstein REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 1890c41891cSEric Bernstein HDMI_GENERIC0_CONT, cont, 1900c41891cSEric Bernstein HDMI_GENERIC0_SEND, send, 1910c41891cSEric Bernstein HDMI_GENERIC0_LINE, line); 1920c41891cSEric Bernstein break; 1930c41891cSEric Bernstein case 1: 1940c41891cSEric Bernstein REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 1950c41891cSEric Bernstein HDMI_GENERIC1_CONT, cont, 1960c41891cSEric Bernstein HDMI_GENERIC1_SEND, send, 1970c41891cSEric Bernstein HDMI_GENERIC1_LINE, line); 1980c41891cSEric Bernstein break; 1990c41891cSEric Bernstein case 2: 2000c41891cSEric Bernstein REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 2010c41891cSEric Bernstein HDMI_GENERIC0_CONT, cont, 2020c41891cSEric Bernstein HDMI_GENERIC0_SEND, send, 2030c41891cSEric Bernstein HDMI_GENERIC0_LINE, line); 2040c41891cSEric Bernstein break; 2050c41891cSEric Bernstein case 3: 2060c41891cSEric Bernstein REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 2070c41891cSEric Bernstein HDMI_GENERIC1_CONT, cont, 2080c41891cSEric Bernstein HDMI_GENERIC1_SEND, send, 2090c41891cSEric Bernstein HDMI_GENERIC1_LINE, line); 2100c41891cSEric Bernstein break; 2110c41891cSEric Bernstein case 4: 2120c41891cSEric Bernstein REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 2130c41891cSEric Bernstein HDMI_GENERIC0_CONT, cont, 2140c41891cSEric Bernstein HDMI_GENERIC0_SEND, send, 2150c41891cSEric Bernstein HDMI_GENERIC0_LINE, line); 2160c41891cSEric Bernstein break; 2170c41891cSEric Bernstein case 5: 2180c41891cSEric Bernstein REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 2190c41891cSEric Bernstein HDMI_GENERIC1_CONT, cont, 2200c41891cSEric Bernstein HDMI_GENERIC1_SEND, send, 2210c41891cSEric Bernstein HDMI_GENERIC1_LINE, line); 2220c41891cSEric Bernstein break; 2230c41891cSEric Bernstein case 6: 2240c41891cSEric Bernstein REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 2250c41891cSEric Bernstein HDMI_GENERIC0_CONT, cont, 2260c41891cSEric Bernstein HDMI_GENERIC0_SEND, send, 2270c41891cSEric Bernstein HDMI_GENERIC0_LINE, line); 2280c41891cSEric Bernstein break; 2290c41891cSEric Bernstein case 7: 2300c41891cSEric Bernstein REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 2310c41891cSEric Bernstein HDMI_GENERIC1_CONT, cont, 2320c41891cSEric Bernstein HDMI_GENERIC1_SEND, send, 2330c41891cSEric Bernstein HDMI_GENERIC1_LINE, line); 2340c41891cSEric Bernstein break; 2350c41891cSEric Bernstein default: 2360c41891cSEric Bernstein /* invalid HW packet index */ 2370c41891cSEric Bernstein DC_LOG_WARNING( 2380c41891cSEric Bernstein "Invalid HW packet index: %s()\n", 2390c41891cSEric Bernstein __func__); 2400c41891cSEric Bernstein return; 2410c41891cSEric Bernstein } 2420c41891cSEric Bernstein } 2430c41891cSEric Bernstein 2440c41891cSEric Bernstein /* setup stream encoder in dp mode */ 245c5011872SEric Bernstein void enc1_stream_encoder_dp_set_stream_attribute( 2460c41891cSEric Bernstein struct stream_encoder *enc, 2470c41891cSEric Bernstein struct dc_crtc_timing *crtc_timing, 2480c41891cSEric Bernstein enum dc_color_space output_color_space) 2490c41891cSEric Bernstein { 2500c41891cSEric Bernstein uint32_t h_active_start; 2510c41891cSEric Bernstein uint32_t v_active_start; 2520c41891cSEric Bernstein uint32_t misc0 = 0; 2530c41891cSEric Bernstein uint32_t misc1 = 0; 2540c41891cSEric Bernstein uint32_t h_blank; 2550c41891cSEric Bernstein uint32_t h_back_porch; 2560c41891cSEric Bernstein uint8_t synchronous_clock = 0; /* asynchronous mode */ 2570c41891cSEric Bernstein uint8_t colorimetry_bpc; 2580c41891cSEric Bernstein uint8_t dynamic_range_rgb = 0; /*full range*/ 2590c41891cSEric Bernstein uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 26012036586SEric Bernstein uint8_t dp_pixel_encoding = 0; 26112036586SEric Bernstein uint8_t dp_component_depth = 0; 2620c41891cSEric Bernstein 2630c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 2640c41891cSEric Bernstein 2650c41891cSEric Bernstein /* set pixel encoding */ 2660c41891cSEric Bernstein switch (crtc_timing->pixel_encoding) { 2670c41891cSEric Bernstein case PIXEL_ENCODING_YCBCR422: 26812036586SEric Bernstein dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422; 2690c41891cSEric Bernstein break; 2700c41891cSEric Bernstein case PIXEL_ENCODING_YCBCR444: 27112036586SEric Bernstein dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444; 2720c41891cSEric Bernstein 2730c41891cSEric Bernstein if (crtc_timing->flags.Y_ONLY) 2740c41891cSEric Bernstein if (crtc_timing->display_color_depth != COLOR_DEPTH_666) 2750c41891cSEric Bernstein /* HW testing only, no use case yet. 2760c41891cSEric Bernstein * Color depth of Y-only could be 2770c41891cSEric Bernstein * 8, 10, 12, 16 bits 2780c41891cSEric Bernstein */ 27912036586SEric Bernstein dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY; 28012036586SEric Bernstein 2810c41891cSEric Bernstein /* Note: DP_MSA_MISC1 bit 7 is the indicator 2820c41891cSEric Bernstein * of Y-only mode. 2830c41891cSEric Bernstein * This bit is set in HW if register 2840c41891cSEric Bernstein * DP_PIXEL_ENCODING is programmed to 0x4 2850c41891cSEric Bernstein */ 2860c41891cSEric Bernstein break; 2870c41891cSEric Bernstein case PIXEL_ENCODING_YCBCR420: 28812036586SEric Bernstein dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; 2890c41891cSEric Bernstein REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 2900c41891cSEric Bernstein break; 2910c41891cSEric Bernstein default: 29212036586SEric Bernstein dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; 2930c41891cSEric Bernstein break; 2940c41891cSEric Bernstein } 2950c41891cSEric Bernstein 2960c41891cSEric Bernstein misc1 = REG_READ(DP_MSA_MISC); 2970b126112SEric Bernstein /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used. 2980b126112SEric Bernstein * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the 2990b126112SEric Bernstein * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7, 300b7355232SKrunoslav Kovac * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care"). 3010b126112SEric Bernstein */ 3020b126112SEric Bernstein if ((crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) || 3030b126112SEric Bernstein (output_color_space == COLOR_SPACE_2020_YCBCR) || 3040b126112SEric Bernstein (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) || 3050b126112SEric Bernstein (output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)) 3060b126112SEric Bernstein misc1 = misc1 | 0x40; 3070b126112SEric Bernstein else 3080b126112SEric Bernstein misc1 = misc1 & ~0x40; 3090c41891cSEric Bernstein 3100c41891cSEric Bernstein /* set color depth */ 3110c41891cSEric Bernstein switch (crtc_timing->display_color_depth) { 3120c41891cSEric Bernstein case COLOR_DEPTH_666: 31312036586SEric Bernstein dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 3140c41891cSEric Bernstein break; 3150c41891cSEric Bernstein case COLOR_DEPTH_888: 31612036586SEric Bernstein dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC; 3170c41891cSEric Bernstein break; 3180c41891cSEric Bernstein case COLOR_DEPTH_101010: 31912036586SEric Bernstein dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC; 3200c41891cSEric Bernstein break; 3210c41891cSEric Bernstein case COLOR_DEPTH_121212: 32212036586SEric Bernstein dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC; 3230c41891cSEric Bernstein break; 32401884c02SEric Bernstein case COLOR_DEPTH_161616: 32512036586SEric Bernstein dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC; 32601884c02SEric Bernstein break; 3270c41891cSEric Bernstein default: 32812036586SEric Bernstein dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 3290c41891cSEric Bernstein break; 3300c41891cSEric Bernstein } 3310c41891cSEric Bernstein 33212036586SEric Bernstein /* Set DP pixel encoding and component depth */ 33312036586SEric Bernstein REG_UPDATE_2(DP_PIXEL_FORMAT, 33412036586SEric Bernstein DP_PIXEL_ENCODING, dp_pixel_encoding, 33512036586SEric Bernstein DP_COMPONENT_DEPTH, dp_component_depth); 33612036586SEric Bernstein 3370c41891cSEric Bernstein /* set dynamic range and YCbCr range */ 3380c41891cSEric Bernstein 3390c41891cSEric Bernstein switch (crtc_timing->display_color_depth) { 3400c41891cSEric Bernstein case COLOR_DEPTH_666: 3410c41891cSEric Bernstein colorimetry_bpc = 0; 3420c41891cSEric Bernstein break; 3430c41891cSEric Bernstein case COLOR_DEPTH_888: 3440c41891cSEric Bernstein colorimetry_bpc = 1; 3450c41891cSEric Bernstein break; 3460c41891cSEric Bernstein case COLOR_DEPTH_101010: 3470c41891cSEric Bernstein colorimetry_bpc = 2; 3480c41891cSEric Bernstein break; 3490c41891cSEric Bernstein case COLOR_DEPTH_121212: 3500c41891cSEric Bernstein colorimetry_bpc = 3; 3510c41891cSEric Bernstein break; 3520c41891cSEric Bernstein default: 3530c41891cSEric Bernstein colorimetry_bpc = 0; 3540c41891cSEric Bernstein break; 3550c41891cSEric Bernstein } 3560c41891cSEric Bernstein 3570c41891cSEric Bernstein misc0 = misc0 | synchronous_clock; 3580c41891cSEric Bernstein misc0 = colorimetry_bpc << 5; 3590c41891cSEric Bernstein 3600c41891cSEric Bernstein switch (output_color_space) { 3610c41891cSEric Bernstein case COLOR_SPACE_SRGB: 3620c41891cSEric Bernstein misc1 = misc1 & ~0x80; /* bit7 = 0*/ 3630c41891cSEric Bernstein dynamic_range_rgb = 0; /*full range*/ 3640c41891cSEric Bernstein break; 3650c41891cSEric Bernstein case COLOR_SPACE_SRGB_LIMITED: 3660c41891cSEric Bernstein misc0 = misc0 | 0x8; /* bit3=1 */ 3670c41891cSEric Bernstein misc1 = misc1 & ~0x80; /* bit7 = 0*/ 3680c41891cSEric Bernstein dynamic_range_rgb = 1; /*limited range*/ 3690c41891cSEric Bernstein break; 3700c41891cSEric Bernstein case COLOR_SPACE_YCBCR601: 3710c41891cSEric Bernstein case COLOR_SPACE_YCBCR601_LIMITED: 3720c41891cSEric Bernstein misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 3730c41891cSEric Bernstein misc1 = misc1 & ~0x80; /* bit7 = 0*/ 3740c41891cSEric Bernstein dynamic_range_ycbcr = 0; /*bt601*/ 3750c41891cSEric Bernstein if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 3760c41891cSEric Bernstein misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 3770c41891cSEric Bernstein else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 3780c41891cSEric Bernstein misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 3790c41891cSEric Bernstein break; 3800c41891cSEric Bernstein case COLOR_SPACE_YCBCR709: 3810c41891cSEric Bernstein case COLOR_SPACE_YCBCR709_LIMITED: 3820c41891cSEric Bernstein misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 3830c41891cSEric Bernstein misc1 = misc1 & ~0x80; /* bit7 = 0*/ 3840c41891cSEric Bernstein dynamic_range_ycbcr = 1; /*bt709*/ 3850c41891cSEric Bernstein if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 3860c41891cSEric Bernstein misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 3870c41891cSEric Bernstein else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 3880c41891cSEric Bernstein misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 3890c41891cSEric Bernstein break; 3900c41891cSEric Bernstein case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 3910c41891cSEric Bernstein dynamic_range_rgb = 1; /*limited range*/ 3920c41891cSEric Bernstein break; 3930c41891cSEric Bernstein case COLOR_SPACE_2020_RGB_FULLRANGE: 3940c41891cSEric Bernstein case COLOR_SPACE_2020_YCBCR: 3950c41891cSEric Bernstein case COLOR_SPACE_XR_RGB: 3960c41891cSEric Bernstein case COLOR_SPACE_MSREF_SCRGB: 3970c41891cSEric Bernstein case COLOR_SPACE_ADOBERGB: 3980c41891cSEric Bernstein case COLOR_SPACE_DCIP3: 3990c41891cSEric Bernstein case COLOR_SPACE_XV_YCC_709: 4000c41891cSEric Bernstein case COLOR_SPACE_XV_YCC_601: 4010c41891cSEric Bernstein case COLOR_SPACE_DISPLAYNATIVE: 4020c41891cSEric Bernstein case COLOR_SPACE_DOLBYVISION: 4030c41891cSEric Bernstein case COLOR_SPACE_APPCTRL: 4040c41891cSEric Bernstein case COLOR_SPACE_CUSTOMPOINTS: 4050c41891cSEric Bernstein case COLOR_SPACE_UNKNOWN: 4060c41891cSEric Bernstein /* do nothing */ 4070c41891cSEric Bernstein break; 4080c41891cSEric Bernstein } 4090c41891cSEric Bernstein 4100c41891cSEric Bernstein REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 4110c41891cSEric Bernstein REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 4120c41891cSEric Bernstein 4130c41891cSEric Bernstein /* dcn new register 4140c41891cSEric Bernstein * dc_crtc_timing is vesa dmt struct. data from edid 4150c41891cSEric Bernstein */ 4160c41891cSEric Bernstein REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 4170c41891cSEric Bernstein DP_MSA_HTOTAL, crtc_timing->h_total, 4180c41891cSEric Bernstein DP_MSA_VTOTAL, crtc_timing->v_total); 4190c41891cSEric Bernstein 4200c41891cSEric Bernstein /* calculate from vesa timing parameters 4210c41891cSEric Bernstein * h_active_start related to leading edge of sync 4220c41891cSEric Bernstein */ 4230c41891cSEric Bernstein 4240c41891cSEric Bernstein h_blank = crtc_timing->h_total - crtc_timing->h_border_left - 4250c41891cSEric Bernstein crtc_timing->h_addressable - crtc_timing->h_border_right; 4260c41891cSEric Bernstein 4270c41891cSEric Bernstein h_back_porch = h_blank - crtc_timing->h_front_porch - 4280c41891cSEric Bernstein crtc_timing->h_sync_width; 4290c41891cSEric Bernstein 4300c41891cSEric Bernstein /* start at beginning of left border */ 4310c41891cSEric Bernstein h_active_start = crtc_timing->h_sync_width + h_back_porch; 4320c41891cSEric Bernstein 4330c41891cSEric Bernstein 4340c41891cSEric Bernstein v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - 4350c41891cSEric Bernstein crtc_timing->v_addressable - crtc_timing->v_border_bottom - 4360c41891cSEric Bernstein crtc_timing->v_front_porch; 4370c41891cSEric Bernstein 4380c41891cSEric Bernstein 4390c41891cSEric Bernstein /* start at beginning of left border */ 4400c41891cSEric Bernstein REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 4410c41891cSEric Bernstein DP_MSA_HSTART, h_active_start, 4420c41891cSEric Bernstein DP_MSA_VSTART, v_active_start); 4430c41891cSEric Bernstein 4440c41891cSEric Bernstein REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 4450c41891cSEric Bernstein DP_MSA_HSYNCWIDTH, 4460c41891cSEric Bernstein crtc_timing->h_sync_width, 4470c41891cSEric Bernstein DP_MSA_HSYNCPOLARITY, 4480c41891cSEric Bernstein !crtc_timing->flags.HSYNC_POSITIVE_POLARITY, 4490c41891cSEric Bernstein DP_MSA_VSYNCWIDTH, 4500c41891cSEric Bernstein crtc_timing->v_sync_width, 4510c41891cSEric Bernstein DP_MSA_VSYNCPOLARITY, 4520c41891cSEric Bernstein !crtc_timing->flags.VSYNC_POSITIVE_POLARITY); 4530c41891cSEric Bernstein 4540c41891cSEric Bernstein /* HWDITH include border or overscan */ 4550c41891cSEric Bernstein REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 4560c41891cSEric Bernstein DP_MSA_HWIDTH, crtc_timing->h_border_left + 4570c41891cSEric Bernstein crtc_timing->h_addressable + crtc_timing->h_border_right, 4580c41891cSEric Bernstein DP_MSA_VHEIGHT, crtc_timing->v_border_top + 4590c41891cSEric Bernstein crtc_timing->v_addressable + crtc_timing->v_border_bottom); 4600c41891cSEric Bernstein } 4610c41891cSEric Bernstein 4620c41891cSEric Bernstein static void enc1_stream_encoder_set_stream_attribute_helper( 4630c41891cSEric Bernstein struct dcn10_stream_encoder *enc1, 4640c41891cSEric Bernstein struct dc_crtc_timing *crtc_timing) 4650c41891cSEric Bernstein { 4660c41891cSEric Bernstein switch (crtc_timing->pixel_encoding) { 4670c41891cSEric Bernstein case PIXEL_ENCODING_YCBCR422: 4680c41891cSEric Bernstein REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 4690c41891cSEric Bernstein break; 4700c41891cSEric Bernstein default: 4710c41891cSEric Bernstein REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 4720c41891cSEric Bernstein break; 4730c41891cSEric Bernstein } 4740c41891cSEric Bernstein REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 4750c41891cSEric Bernstein } 4760c41891cSEric Bernstein 4770c41891cSEric Bernstein /* setup stream encoder in hdmi mode */ 478c5011872SEric Bernstein void enc1_stream_encoder_hdmi_set_stream_attribute( 4790c41891cSEric Bernstein struct stream_encoder *enc, 4800c41891cSEric Bernstein struct dc_crtc_timing *crtc_timing, 4810c41891cSEric Bernstein int actual_pix_clk_khz, 4820c41891cSEric Bernstein bool enable_audio) 4830c41891cSEric Bernstein { 4840c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 4850c41891cSEric Bernstein struct bp_encoder_control cntl = {0}; 4860c41891cSEric Bernstein 4870c41891cSEric Bernstein cntl.action = ENCODER_CONTROL_SETUP; 4880c41891cSEric Bernstein cntl.engine_id = enc1->base.id; 4890c41891cSEric Bernstein cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 4900c41891cSEric Bernstein cntl.enable_dp_audio = enable_audio; 4910c41891cSEric Bernstein cntl.pixel_clock = actual_pix_clk_khz; 4920c41891cSEric Bernstein cntl.lanes_number = LANE_COUNT_FOUR; 4930c41891cSEric Bernstein 4940c41891cSEric Bernstein if (enc1->base.bp->funcs->encoder_control( 4950c41891cSEric Bernstein enc1->base.bp, &cntl) != BP_RESULT_OK) 4960c41891cSEric Bernstein return; 4970c41891cSEric Bernstein 4980c41891cSEric Bernstein enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 4990c41891cSEric Bernstein 5000c41891cSEric Bernstein /* setup HDMI engine */ 5010c41891cSEric Bernstein REG_UPDATE_5(HDMI_CONTROL, 5020c41891cSEric Bernstein HDMI_PACKET_GEN_VERSION, 1, 5030c41891cSEric Bernstein HDMI_KEEPOUT_MODE, 1, 5040c41891cSEric Bernstein HDMI_DEEP_COLOR_ENABLE, 0, 5050c41891cSEric Bernstein HDMI_DATA_SCRAMBLE_EN, 0, 5060c41891cSEric Bernstein HDMI_CLOCK_CHANNEL_RATE, 0); 5070c41891cSEric Bernstein 5080c41891cSEric Bernstein 5090c41891cSEric Bernstein switch (crtc_timing->display_color_depth) { 5100c41891cSEric Bernstein case COLOR_DEPTH_888: 5110c41891cSEric Bernstein REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 5120c41891cSEric Bernstein break; 5130c41891cSEric Bernstein case COLOR_DEPTH_101010: 5140c41891cSEric Bernstein if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 5150c41891cSEric Bernstein REG_UPDATE_2(HDMI_CONTROL, 5160c41891cSEric Bernstein HDMI_DEEP_COLOR_DEPTH, 1, 5170c41891cSEric Bernstein HDMI_DEEP_COLOR_ENABLE, 0); 5180c41891cSEric Bernstein } else { 5190c41891cSEric Bernstein REG_UPDATE_2(HDMI_CONTROL, 5200c41891cSEric Bernstein HDMI_DEEP_COLOR_DEPTH, 1, 5210c41891cSEric Bernstein HDMI_DEEP_COLOR_ENABLE, 1); 5220c41891cSEric Bernstein } 5230c41891cSEric Bernstein break; 5240c41891cSEric Bernstein case COLOR_DEPTH_121212: 5250c41891cSEric Bernstein if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 5260c41891cSEric Bernstein REG_UPDATE_2(HDMI_CONTROL, 5270c41891cSEric Bernstein HDMI_DEEP_COLOR_DEPTH, 2, 5280c41891cSEric Bernstein HDMI_DEEP_COLOR_ENABLE, 0); 5290c41891cSEric Bernstein } else { 5300c41891cSEric Bernstein REG_UPDATE_2(HDMI_CONTROL, 5310c41891cSEric Bernstein HDMI_DEEP_COLOR_DEPTH, 2, 5320c41891cSEric Bernstein HDMI_DEEP_COLOR_ENABLE, 1); 5330c41891cSEric Bernstein } 5340c41891cSEric Bernstein break; 5350c41891cSEric Bernstein case COLOR_DEPTH_161616: 5360c41891cSEric Bernstein REG_UPDATE_2(HDMI_CONTROL, 5370c41891cSEric Bernstein HDMI_DEEP_COLOR_DEPTH, 3, 5380c41891cSEric Bernstein HDMI_DEEP_COLOR_ENABLE, 1); 5390c41891cSEric Bernstein break; 5400c41891cSEric Bernstein default: 5410c41891cSEric Bernstein break; 5420c41891cSEric Bernstein } 5430c41891cSEric Bernstein 5440c41891cSEric Bernstein if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 5450c41891cSEric Bernstein /* enable HDMI data scrambler 5460c41891cSEric Bernstein * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 5470c41891cSEric Bernstein * Clock channel frequency is 1/4 of character rate. 5480c41891cSEric Bernstein */ 5490c41891cSEric Bernstein REG_UPDATE_2(HDMI_CONTROL, 5500c41891cSEric Bernstein HDMI_DATA_SCRAMBLE_EN, 1, 5510c41891cSEric Bernstein HDMI_CLOCK_CHANNEL_RATE, 1); 5520c41891cSEric Bernstein } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 5530c41891cSEric Bernstein 5540c41891cSEric Bernstein /* TODO: New feature for DCE11, still need to implement */ 5550c41891cSEric Bernstein 5560c41891cSEric Bernstein /* enable HDMI data scrambler 5570c41891cSEric Bernstein * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 5580c41891cSEric Bernstein * Clock channel frequency is the same 5590c41891cSEric Bernstein * as character rate 5600c41891cSEric Bernstein */ 5610c41891cSEric Bernstein REG_UPDATE_2(HDMI_CONTROL, 5620c41891cSEric Bernstein HDMI_DATA_SCRAMBLE_EN, 1, 5630c41891cSEric Bernstein HDMI_CLOCK_CHANNEL_RATE, 0); 5640c41891cSEric Bernstein } 5650c41891cSEric Bernstein 5660c41891cSEric Bernstein 5670c41891cSEric Bernstein REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 5680c41891cSEric Bernstein HDMI_GC_CONT, 1, 5690c41891cSEric Bernstein HDMI_GC_SEND, 1, 5700c41891cSEric Bernstein HDMI_NULL_SEND, 1); 5710c41891cSEric Bernstein 5720c41891cSEric Bernstein /* following belongs to audio */ 5730c41891cSEric Bernstein REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 5740c41891cSEric Bernstein 5750c41891cSEric Bernstein REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 5760c41891cSEric Bernstein 5770c41891cSEric Bernstein REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 5780c41891cSEric Bernstein VBI_LINE_0 + 2); 5790c41891cSEric Bernstein 5800c41891cSEric Bernstein REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 5810c41891cSEric Bernstein } 5820c41891cSEric Bernstein 5830c41891cSEric Bernstein /* setup stream encoder in dvi mode */ 584c5011872SEric Bernstein void enc1_stream_encoder_dvi_set_stream_attribute( 5850c41891cSEric Bernstein struct stream_encoder *enc, 5860c41891cSEric Bernstein struct dc_crtc_timing *crtc_timing, 5870c41891cSEric Bernstein bool is_dual_link) 5880c41891cSEric Bernstein { 5890c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 5900c41891cSEric Bernstein struct bp_encoder_control cntl = {0}; 5910c41891cSEric Bernstein 5920c41891cSEric Bernstein cntl.action = ENCODER_CONTROL_SETUP; 5930c41891cSEric Bernstein cntl.engine_id = enc1->base.id; 5940c41891cSEric Bernstein cntl.signal = is_dual_link ? 5950c41891cSEric Bernstein SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 5960c41891cSEric Bernstein cntl.enable_dp_audio = false; 597380604e2SKen Chalmers cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 5980c41891cSEric Bernstein cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 5990c41891cSEric Bernstein 6000c41891cSEric Bernstein if (enc1->base.bp->funcs->encoder_control( 6010c41891cSEric Bernstein enc1->base.bp, &cntl) != BP_RESULT_OK) 6020c41891cSEric Bernstein return; 6030c41891cSEric Bernstein 6040c41891cSEric Bernstein ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 6050c41891cSEric Bernstein ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 6060c41891cSEric Bernstein enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 6070c41891cSEric Bernstein } 6080c41891cSEric Bernstein 609c5011872SEric Bernstein void enc1_stream_encoder_set_mst_bandwidth( 6100c41891cSEric Bernstein struct stream_encoder *enc, 6110c41891cSEric Bernstein struct fixed31_32 avg_time_slots_per_mtp) 6120c41891cSEric Bernstein { 6130c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 614eb0e5154SDmytro Laktyushkin uint32_t x = dc_fixpt_floor( 6150c41891cSEric Bernstein avg_time_slots_per_mtp); 616eb0e5154SDmytro Laktyushkin uint32_t y = dc_fixpt_ceil( 617eb0e5154SDmytro Laktyushkin dc_fixpt_shl( 618eb0e5154SDmytro Laktyushkin dc_fixpt_sub_int( 6190c41891cSEric Bernstein avg_time_slots_per_mtp, 6200c41891cSEric Bernstein x), 6210c41891cSEric Bernstein 26)); 6220c41891cSEric Bernstein 6230c41891cSEric Bernstein REG_SET_2(DP_MSE_RATE_CNTL, 0, 6240c41891cSEric Bernstein DP_MSE_RATE_X, x, 6250c41891cSEric Bernstein DP_MSE_RATE_Y, y); 6260c41891cSEric Bernstein 6270c41891cSEric Bernstein /* wait for update to be completed on the link */ 6280c41891cSEric Bernstein /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 6290c41891cSEric Bernstein /* is reset to 0 (not pending) */ 6300c41891cSEric Bernstein REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 6310c41891cSEric Bernstein 0, 6320c41891cSEric Bernstein 10, DP_MST_UPDATE_MAX_RETRY); 6330c41891cSEric Bernstein } 6340c41891cSEric Bernstein 6350c41891cSEric Bernstein static void enc1_stream_encoder_update_hdmi_info_packets( 6360c41891cSEric Bernstein struct stream_encoder *enc, 6370c41891cSEric Bernstein const struct encoder_info_frame *info_frame) 6380c41891cSEric Bernstein { 6390c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 6400c41891cSEric Bernstein 6410c41891cSEric Bernstein /* for bring up, disable dp double TODO */ 6420c41891cSEric Bernstein REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 6430c41891cSEric Bernstein 6440c41891cSEric Bernstein enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi); 6450c41891cSEric Bernstein enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); 6460c41891cSEric Bernstein enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); 6470c41891cSEric Bernstein enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd); 6480c41891cSEric Bernstein enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); 6490c41891cSEric Bernstein } 6500c41891cSEric Bernstein 6510c41891cSEric Bernstein static void enc1_stream_encoder_stop_hdmi_info_packets( 6520c41891cSEric Bernstein struct stream_encoder *enc) 6530c41891cSEric Bernstein { 6540c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 6550c41891cSEric Bernstein 6560c41891cSEric Bernstein /* stop generic packets 0 & 1 on HDMI */ 6570c41891cSEric Bernstein REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 6580c41891cSEric Bernstein HDMI_GENERIC1_CONT, 0, 6590c41891cSEric Bernstein HDMI_GENERIC1_LINE, 0, 6600c41891cSEric Bernstein HDMI_GENERIC1_SEND, 0, 6610c41891cSEric Bernstein HDMI_GENERIC0_CONT, 0, 6620c41891cSEric Bernstein HDMI_GENERIC0_LINE, 0, 6630c41891cSEric Bernstein HDMI_GENERIC0_SEND, 0); 6640c41891cSEric Bernstein 6650c41891cSEric Bernstein /* stop generic packets 2 & 3 on HDMI */ 6660c41891cSEric Bernstein REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 6670c41891cSEric Bernstein HDMI_GENERIC0_CONT, 0, 6680c41891cSEric Bernstein HDMI_GENERIC0_LINE, 0, 6690c41891cSEric Bernstein HDMI_GENERIC0_SEND, 0, 6700c41891cSEric Bernstein HDMI_GENERIC1_CONT, 0, 6710c41891cSEric Bernstein HDMI_GENERIC1_LINE, 0, 6720c41891cSEric Bernstein HDMI_GENERIC1_SEND, 0); 6730c41891cSEric Bernstein 6740c41891cSEric Bernstein /* stop generic packets 2 & 3 on HDMI */ 6750c41891cSEric Bernstein REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 6760c41891cSEric Bernstein HDMI_GENERIC0_CONT, 0, 6770c41891cSEric Bernstein HDMI_GENERIC0_LINE, 0, 6780c41891cSEric Bernstein HDMI_GENERIC0_SEND, 0, 6790c41891cSEric Bernstein HDMI_GENERIC1_CONT, 0, 6800c41891cSEric Bernstein HDMI_GENERIC1_LINE, 0, 6810c41891cSEric Bernstein HDMI_GENERIC1_SEND, 0); 6820c41891cSEric Bernstein 6830c41891cSEric Bernstein REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 6840c41891cSEric Bernstein HDMI_GENERIC0_CONT, 0, 6850c41891cSEric Bernstein HDMI_GENERIC0_LINE, 0, 6860c41891cSEric Bernstein HDMI_GENERIC0_SEND, 0, 6870c41891cSEric Bernstein HDMI_GENERIC1_CONT, 0, 6880c41891cSEric Bernstein HDMI_GENERIC1_LINE, 0, 6890c41891cSEric Bernstein HDMI_GENERIC1_SEND, 0); 6900c41891cSEric Bernstein } 6910c41891cSEric Bernstein 692c5011872SEric Bernstein void enc1_stream_encoder_update_dp_info_packets( 6930c41891cSEric Bernstein struct stream_encoder *enc, 6940c41891cSEric Bernstein const struct encoder_info_frame *info_frame) 6950c41891cSEric Bernstein { 6960c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 697388277b1SAnthony Koo uint32_t value = 0; 6980c41891cSEric Bernstein 6990c41891cSEric Bernstein if (info_frame->vsc.valid) 7000c41891cSEric Bernstein enc1_update_generic_info_packet( 7010c41891cSEric Bernstein enc1, 7020c41891cSEric Bernstein 0, /* packetIndex */ 7030c41891cSEric Bernstein &info_frame->vsc); 7040c41891cSEric Bernstein 7050c41891cSEric Bernstein if (info_frame->spd.valid) 7060c41891cSEric Bernstein enc1_update_generic_info_packet( 7070c41891cSEric Bernstein enc1, 7080c41891cSEric Bernstein 2, /* packetIndex */ 7090c41891cSEric Bernstein &info_frame->spd); 7100c41891cSEric Bernstein 7110c41891cSEric Bernstein if (info_frame->hdrsmd.valid) 7120c41891cSEric Bernstein enc1_update_generic_info_packet( 7130c41891cSEric Bernstein enc1, 7140c41891cSEric Bernstein 3, /* packetIndex */ 7150c41891cSEric Bernstein &info_frame->hdrsmd); 7160c41891cSEric Bernstein 7170c41891cSEric Bernstein /* enable/disable transmission of packet(s). 7180c41891cSEric Bernstein * If enabled, packet transmission begins on the next frame 7190c41891cSEric Bernstein */ 7200c41891cSEric Bernstein REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 7210c41891cSEric Bernstein REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 7220c41891cSEric Bernstein REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 7230c41891cSEric Bernstein 724388277b1SAnthony Koo 7250c41891cSEric Bernstein /* This bit is the master enable bit. 7260c41891cSEric Bernstein * When enabling secondary stream engine, 7270c41891cSEric Bernstein * this master bit must also be set. 7280c41891cSEric Bernstein * This register shared with audio info frame. 7290c41891cSEric Bernstein * Therefore we need to enable master bit 7300c41891cSEric Bernstein * if at least on of the fields is not 0 7310c41891cSEric Bernstein */ 732388277b1SAnthony Koo value = REG_READ(DP_SEC_CNTL); 7330c41891cSEric Bernstein if (value) 7340c41891cSEric Bernstein REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 7350c41891cSEric Bernstein } 7360c41891cSEric Bernstein 737c5011872SEric Bernstein void enc1_stream_encoder_stop_dp_info_packets( 7380c41891cSEric Bernstein struct stream_encoder *enc) 7390c41891cSEric Bernstein { 7400c41891cSEric Bernstein /* stop generic packets on DP */ 7410c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 742388277b1SAnthony Koo uint32_t value = 0; 7430c41891cSEric Bernstein 7440c41891cSEric Bernstein REG_SET_10(DP_SEC_CNTL, 0, 7450c41891cSEric Bernstein DP_SEC_GSP0_ENABLE, 0, 7460c41891cSEric Bernstein DP_SEC_GSP1_ENABLE, 0, 7470c41891cSEric Bernstein DP_SEC_GSP2_ENABLE, 0, 7480c41891cSEric Bernstein DP_SEC_GSP3_ENABLE, 0, 7490c41891cSEric Bernstein DP_SEC_GSP4_ENABLE, 0, 7500c41891cSEric Bernstein DP_SEC_GSP5_ENABLE, 0, 7510c41891cSEric Bernstein DP_SEC_GSP6_ENABLE, 0, 7520c41891cSEric Bernstein DP_SEC_GSP7_ENABLE, 0, 7530c41891cSEric Bernstein DP_SEC_MPG_ENABLE, 0, 7540c41891cSEric Bernstein DP_SEC_STREAM_ENABLE, 0); 7550c41891cSEric Bernstein 7560c41891cSEric Bernstein /* this register shared with audio info frame. 7570c41891cSEric Bernstein * therefore we need to keep master enabled 7580c41891cSEric Bernstein * if at least one of the fields is not 0 */ 759388277b1SAnthony Koo value = REG_READ(DP_SEC_CNTL); 7600c41891cSEric Bernstein if (value) 7610c41891cSEric Bernstein REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 7620c41891cSEric Bernstein 7630c41891cSEric Bernstein } 7640c41891cSEric Bernstein 765c5011872SEric Bernstein void enc1_stream_encoder_dp_blank( 7660c41891cSEric Bernstein struct stream_encoder *enc) 7670c41891cSEric Bernstein { 7680c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 7690c41891cSEric Bernstein uint32_t reg1 = 0; 7700c41891cSEric Bernstein uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 7710c41891cSEric Bernstein 7720c41891cSEric Bernstein /* Note: For CZ, we are changing driver default to disable 7730c41891cSEric Bernstein * stream deferred to next VBLANK. If results are positive, we 7740c41891cSEric Bernstein * will make the same change to all DCE versions. There are a 7750c41891cSEric Bernstein * handful of panels that cannot handle disable stream at 7760c41891cSEric Bernstein * HBLANK and will result in a white line flash across the 7770c41891cSEric Bernstein * screen on stream disable. 7780c41891cSEric Bernstein */ 7790c41891cSEric Bernstein REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 7800c41891cSEric Bernstein if ((reg1 & 0x1) == 0) 7810c41891cSEric Bernstein /*stream not enabled*/ 7820c41891cSEric Bernstein return; 7830c41891cSEric Bernstein /* Specify the video stream disable point 7840c41891cSEric Bernstein * (2 = start of the next vertical blank) 7850c41891cSEric Bernstein */ 7860c41891cSEric Bernstein REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 7870c41891cSEric Bernstein /* Larger delay to wait until VBLANK - use max retry of 7880c41891cSEric Bernstein * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 7890c41891cSEric Bernstein * a little more because we may not trust delay accuracy. 7900c41891cSEric Bernstein */ 7910c41891cSEric Bernstein max_retries = DP_BLANK_MAX_RETRY * 150; 7920c41891cSEric Bernstein 7930c41891cSEric Bernstein /* disable DP stream */ 7940c41891cSEric Bernstein REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 7950c41891cSEric Bernstein 7960c41891cSEric Bernstein /* the encoder stops sending the video stream 7970c41891cSEric Bernstein * at the start of the vertical blanking. 7980c41891cSEric Bernstein * Poll for DP_VID_STREAM_STATUS == 0 7990c41891cSEric Bernstein */ 8000c41891cSEric Bernstein 8010c41891cSEric Bernstein REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 8020c41891cSEric Bernstein 0, 8030c41891cSEric Bernstein 10, max_retries); 8040c41891cSEric Bernstein 8050c41891cSEric Bernstein /* Tell the DP encoder to ignore timing from CRTC, must be done after 8060c41891cSEric Bernstein * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 8070c41891cSEric Bernstein * complete, stream status will be stuck in video stream enabled state, 8080c41891cSEric Bernstein * i.e. DP_VID_STREAM_STATUS stuck at 1. 8090c41891cSEric Bernstein */ 8100c41891cSEric Bernstein 8110c41891cSEric Bernstein REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 8120c41891cSEric Bernstein } 8130c41891cSEric Bernstein 8140c41891cSEric Bernstein /* output video stream to link encoder */ 815c5011872SEric Bernstein void enc1_stream_encoder_dp_unblank( 8160c41891cSEric Bernstein struct stream_encoder *enc, 8170c41891cSEric Bernstein const struct encoder_unblank_param *param) 8180c41891cSEric Bernstein { 8190c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 8200c41891cSEric Bernstein 8210c41891cSEric Bernstein if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 8220c41891cSEric Bernstein uint32_t n_vid = 0x8000; 8230c41891cSEric Bernstein uint32_t m_vid; 8240c41891cSEric Bernstein 8250c41891cSEric Bernstein /* M / N = Fstream / Flink 8260c41891cSEric Bernstein * m_vid / n_vid = pixel rate / link rate 8270c41891cSEric Bernstein */ 8280c41891cSEric Bernstein 8290c41891cSEric Bernstein uint64_t m_vid_l = n_vid; 8300c41891cSEric Bernstein 8310c41891cSEric Bernstein m_vid_l *= param->pixel_clk_khz; 8320c41891cSEric Bernstein m_vid_l = div_u64(m_vid_l, 8330c41891cSEric Bernstein param->link_settings.link_rate 8340c41891cSEric Bernstein * LINK_RATE_REF_FREQ_IN_KHZ); 8350c41891cSEric Bernstein 8360c41891cSEric Bernstein m_vid = (uint32_t) m_vid_l; 8370c41891cSEric Bernstein 8380c41891cSEric Bernstein /* enable auto measurement */ 8390c41891cSEric Bernstein 8400c41891cSEric Bernstein REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 8410c41891cSEric Bernstein 8420c41891cSEric Bernstein /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 8430c41891cSEric Bernstein * therefore program initial value for Mvid and Nvid 8440c41891cSEric Bernstein */ 8450c41891cSEric Bernstein 8460c41891cSEric Bernstein REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 8470c41891cSEric Bernstein 8480c41891cSEric Bernstein REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 8490c41891cSEric Bernstein 8500c41891cSEric Bernstein REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 8510c41891cSEric Bernstein } 8520c41891cSEric Bernstein 8530c41891cSEric Bernstein /* set DIG_START to 0x1 to resync FIFO */ 8540c41891cSEric Bernstein 8550c41891cSEric Bernstein REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 8560c41891cSEric Bernstein 8570c41891cSEric Bernstein /* switch DP encoder to CRTC data */ 8580c41891cSEric Bernstein 8590c41891cSEric Bernstein REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 8600c41891cSEric Bernstein 8610c41891cSEric Bernstein /* wait 100us for DIG/DP logic to prime 8620c41891cSEric Bernstein * (i.e. a few video lines) 8630c41891cSEric Bernstein */ 8640c41891cSEric Bernstein udelay(100); 8650c41891cSEric Bernstein 8660c41891cSEric Bernstein /* the hardware would start sending video at the start of the next DP 8670c41891cSEric Bernstein * frame (i.e. rising edge of the vblank). 8680c41891cSEric Bernstein * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 8690c41891cSEric Bernstein * register has no effect on enable transition! HW always guarantees 8700c41891cSEric Bernstein * VID_STREAM enable at start of next frame, and this is not 8710c41891cSEric Bernstein * programmable 8720c41891cSEric Bernstein */ 8730c41891cSEric Bernstein 8740c41891cSEric Bernstein REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 8750c41891cSEric Bernstein } 8760c41891cSEric Bernstein 877c5011872SEric Bernstein void enc1_stream_encoder_set_avmute( 8780c41891cSEric Bernstein struct stream_encoder *enc, 8790c41891cSEric Bernstein bool enable) 8800c41891cSEric Bernstein { 8810c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 8820c41891cSEric Bernstein unsigned int value = enable ? 1 : 0; 8830c41891cSEric Bernstein 8840c41891cSEric Bernstein REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 8850c41891cSEric Bernstein } 8860c41891cSEric Bernstein 8870c41891cSEric Bernstein 8880c41891cSEric Bernstein #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 8890c41891cSEric Bernstein #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 8900c41891cSEric Bernstein 8910c41891cSEric Bernstein #include "include/audio_types.h" 8920c41891cSEric Bernstein 8930c41891cSEric Bernstein /** 8940c41891cSEric Bernstein * speakersToChannels 8950c41891cSEric Bernstein * 8960c41891cSEric Bernstein * @brief 8970c41891cSEric Bernstein * translate speakers to channels 8980c41891cSEric Bernstein * 8990c41891cSEric Bernstein * FL - Front Left 9000c41891cSEric Bernstein * FR - Front Right 9010c41891cSEric Bernstein * RL - Rear Left 9020c41891cSEric Bernstein * RR - Rear Right 9030c41891cSEric Bernstein * RC - Rear Center 9040c41891cSEric Bernstein * FC - Front Center 9050c41891cSEric Bernstein * FLC - Front Left Center 9060c41891cSEric Bernstein * FRC - Front Right Center 9070c41891cSEric Bernstein * RLC - Rear Left Center 9080c41891cSEric Bernstein * RRC - Rear Right Center 9090c41891cSEric Bernstein * LFE - Low Freq Effect 9100c41891cSEric Bernstein * 9110c41891cSEric Bernstein * FC 9120c41891cSEric Bernstein * FLC FRC 9130c41891cSEric Bernstein * FL FR 9140c41891cSEric Bernstein * 9150c41891cSEric Bernstein * LFE 9160c41891cSEric Bernstein * () 9170c41891cSEric Bernstein * 9180c41891cSEric Bernstein * 9190c41891cSEric Bernstein * RL RR 9200c41891cSEric Bernstein * RLC RRC 9210c41891cSEric Bernstein * RC 9220c41891cSEric Bernstein * 9230c41891cSEric Bernstein * ch 8 7 6 5 4 3 2 1 9240c41891cSEric Bernstein * 0b00000011 - - - - - - FR FL 9250c41891cSEric Bernstein * 0b00000111 - - - - - LFE FR FL 9260c41891cSEric Bernstein * 0b00001011 - - - - FC - FR FL 9270c41891cSEric Bernstein * 0b00001111 - - - - FC LFE FR FL 9280c41891cSEric Bernstein * 0b00010011 - - - RC - - FR FL 9290c41891cSEric Bernstein * 0b00010111 - - - RC - LFE FR FL 9300c41891cSEric Bernstein * 0b00011011 - - - RC FC - FR FL 9310c41891cSEric Bernstein * 0b00011111 - - - RC FC LFE FR FL 9320c41891cSEric Bernstein * 0b00110011 - - RR RL - - FR FL 9330c41891cSEric Bernstein * 0b00110111 - - RR RL - LFE FR FL 9340c41891cSEric Bernstein * 0b00111011 - - RR RL FC - FR FL 9350c41891cSEric Bernstein * 0b00111111 - - RR RL FC LFE FR FL 9360c41891cSEric Bernstein * 0b01110011 - RC RR RL - - FR FL 9370c41891cSEric Bernstein * 0b01110111 - RC RR RL - LFE FR FL 9380c41891cSEric Bernstein * 0b01111011 - RC RR RL FC - FR FL 9390c41891cSEric Bernstein * 0b01111111 - RC RR RL FC LFE FR FL 9400c41891cSEric Bernstein * 0b11110011 RRC RLC RR RL - - FR FL 9410c41891cSEric Bernstein * 0b11110111 RRC RLC RR RL - LFE FR FL 9420c41891cSEric Bernstein * 0b11111011 RRC RLC RR RL FC - FR FL 9430c41891cSEric Bernstein * 0b11111111 RRC RLC RR RL FC LFE FR FL 9440c41891cSEric Bernstein * 0b11000011 FRC FLC - - - - FR FL 9450c41891cSEric Bernstein * 0b11000111 FRC FLC - - - LFE FR FL 9460c41891cSEric Bernstein * 0b11001011 FRC FLC - - FC - FR FL 9470c41891cSEric Bernstein * 0b11001111 FRC FLC - - FC LFE FR FL 9480c41891cSEric Bernstein * 0b11010011 FRC FLC - RC - - FR FL 9490c41891cSEric Bernstein * 0b11010111 FRC FLC - RC - LFE FR FL 9500c41891cSEric Bernstein * 0b11011011 FRC FLC - RC FC - FR FL 9510c41891cSEric Bernstein * 0b11011111 FRC FLC - RC FC LFE FR FL 9520c41891cSEric Bernstein * 0b11110011 FRC FLC RR RL - - FR FL 9530c41891cSEric Bernstein * 0b11110111 FRC FLC RR RL - LFE FR FL 9540c41891cSEric Bernstein * 0b11111011 FRC FLC RR RL FC - FR FL 9550c41891cSEric Bernstein * 0b11111111 FRC FLC RR RL FC LFE FR FL 9560c41891cSEric Bernstein * 9570c41891cSEric Bernstein * @param 9580c41891cSEric Bernstein * speakers - speaker information as it comes from CEA audio block 9590c41891cSEric Bernstein */ 9600c41891cSEric Bernstein /* translate speakers to channels */ 9610c41891cSEric Bernstein 9620c41891cSEric Bernstein union audio_cea_channels { 9630c41891cSEric Bernstein uint8_t all; 9640c41891cSEric Bernstein struct audio_cea_channels_bits { 9650c41891cSEric Bernstein uint32_t FL:1; 9660c41891cSEric Bernstein uint32_t FR:1; 9670c41891cSEric Bernstein uint32_t LFE:1; 9680c41891cSEric Bernstein uint32_t FC:1; 9690c41891cSEric Bernstein uint32_t RL_RC:1; 9700c41891cSEric Bernstein uint32_t RR:1; 9710c41891cSEric Bernstein uint32_t RC_RLC_FLC:1; 9720c41891cSEric Bernstein uint32_t RRC_FRC:1; 9730c41891cSEric Bernstein } channels; 9740c41891cSEric Bernstein }; 9750c41891cSEric Bernstein 9760c41891cSEric Bernstein struct audio_clock_info { 9770c41891cSEric Bernstein /* pixel clock frequency*/ 9780c41891cSEric Bernstein uint32_t pixel_clock_in_10khz; 9790c41891cSEric Bernstein /* N - 32KHz audio */ 9800c41891cSEric Bernstein uint32_t n_32khz; 9810c41891cSEric Bernstein /* CTS - 32KHz audio*/ 9820c41891cSEric Bernstein uint32_t cts_32khz; 9830c41891cSEric Bernstein uint32_t n_44khz; 9840c41891cSEric Bernstein uint32_t cts_44khz; 9850c41891cSEric Bernstein uint32_t n_48khz; 9860c41891cSEric Bernstein uint32_t cts_48khz; 9870c41891cSEric Bernstein }; 9880c41891cSEric Bernstein 9890c41891cSEric Bernstein /* 25.2MHz/1.001*/ 9900c41891cSEric Bernstein /* 25.2MHz/1.001*/ 9910c41891cSEric Bernstein /* 25.2MHz*/ 9920c41891cSEric Bernstein /* 27MHz */ 9930c41891cSEric Bernstein /* 27MHz*1.001*/ 9940c41891cSEric Bernstein /* 27MHz*1.001*/ 9950c41891cSEric Bernstein /* 54MHz*/ 9960c41891cSEric Bernstein /* 54MHz*1.001*/ 9970c41891cSEric Bernstein /* 74.25MHz/1.001*/ 9980c41891cSEric Bernstein /* 74.25MHz*/ 9990c41891cSEric Bernstein /* 148.5MHz/1.001*/ 10000c41891cSEric Bernstein /* 148.5MHz*/ 10010c41891cSEric Bernstein 10020c41891cSEric Bernstein static const struct audio_clock_info audio_clock_info_table[16] = { 10030c41891cSEric Bernstein {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 10040c41891cSEric Bernstein {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 10050c41891cSEric Bernstein {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 10060c41891cSEric Bernstein {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 10070c41891cSEric Bernstein {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 10080c41891cSEric Bernstein {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 10090c41891cSEric Bernstein {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 10100c41891cSEric Bernstein {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 10110c41891cSEric Bernstein {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 10120c41891cSEric Bernstein {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 10130c41891cSEric Bernstein {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 10140c41891cSEric Bernstein {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 10150c41891cSEric Bernstein {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 10160c41891cSEric Bernstein {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 10170c41891cSEric Bernstein {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 10180c41891cSEric Bernstein {59400, 3072, 445500, 9408, 990000, 6144, 594000} 10190c41891cSEric Bernstein }; 10200c41891cSEric Bernstein 10210c41891cSEric Bernstein static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 10220c41891cSEric Bernstein {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 10230c41891cSEric Bernstein {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 10240c41891cSEric Bernstein {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 10250c41891cSEric Bernstein {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 10260c41891cSEric Bernstein {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 10270c41891cSEric Bernstein {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 10280c41891cSEric Bernstein {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 10290c41891cSEric Bernstein {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 10300c41891cSEric Bernstein {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 10310c41891cSEric Bernstein {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 10320c41891cSEric Bernstein {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 10330c41891cSEric Bernstein {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 10340c41891cSEric Bernstein {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 10350c41891cSEric Bernstein {29700, 4096, 445500, 4704, 371250, 5120, 371250} 10360c41891cSEric Bernstein }; 10370c41891cSEric Bernstein 10380c41891cSEric Bernstein static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 10390c41891cSEric Bernstein {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 10400c41891cSEric Bernstein {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 10410c41891cSEric Bernstein {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 10420c41891cSEric Bernstein {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 10430c41891cSEric Bernstein {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 10440c41891cSEric Bernstein {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 10450c41891cSEric Bernstein {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 10460c41891cSEric Bernstein {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 10470c41891cSEric Bernstein {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 10480c41891cSEric Bernstein {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 10490c41891cSEric Bernstein {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 10500c41891cSEric Bernstein {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 10510c41891cSEric Bernstein {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 10520c41891cSEric Bernstein {29700, 3072, 445500, 4704, 495000, 5120, 495000} 10530c41891cSEric Bernstein 10540c41891cSEric Bernstein 10550c41891cSEric Bernstein }; 10560c41891cSEric Bernstein 10570c41891cSEric Bernstein static union audio_cea_channels speakers_to_channels( 10580c41891cSEric Bernstein struct audio_speaker_flags speaker_flags) 10590c41891cSEric Bernstein { 10600c41891cSEric Bernstein union audio_cea_channels cea_channels = {0}; 10610c41891cSEric Bernstein 10620c41891cSEric Bernstein /* these are one to one */ 10630c41891cSEric Bernstein cea_channels.channels.FL = speaker_flags.FL_FR; 10640c41891cSEric Bernstein cea_channels.channels.FR = speaker_flags.FL_FR; 10650c41891cSEric Bernstein cea_channels.channels.LFE = speaker_flags.LFE; 10660c41891cSEric Bernstein cea_channels.channels.FC = speaker_flags.FC; 10670c41891cSEric Bernstein 10680c41891cSEric Bernstein /* if Rear Left and Right exist move RC speaker to channel 7 10690c41891cSEric Bernstein * otherwise to channel 5 10700c41891cSEric Bernstein */ 10710c41891cSEric Bernstein if (speaker_flags.RL_RR) { 10720c41891cSEric Bernstein cea_channels.channels.RL_RC = speaker_flags.RL_RR; 10730c41891cSEric Bernstein cea_channels.channels.RR = speaker_flags.RL_RR; 10740c41891cSEric Bernstein cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 10750c41891cSEric Bernstein } else { 10760c41891cSEric Bernstein cea_channels.channels.RL_RC = speaker_flags.RC; 10770c41891cSEric Bernstein } 10780c41891cSEric Bernstein 10790c41891cSEric Bernstein /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 10800c41891cSEric Bernstein if (speaker_flags.FLC_FRC) { 10810c41891cSEric Bernstein cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 10820c41891cSEric Bernstein cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 10830c41891cSEric Bernstein } else { 10840c41891cSEric Bernstein cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 10850c41891cSEric Bernstein cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 10860c41891cSEric Bernstein } 10870c41891cSEric Bernstein 10880c41891cSEric Bernstein return cea_channels; 10890c41891cSEric Bernstein } 10900c41891cSEric Bernstein 10910c41891cSEric Bernstein static void get_audio_clock_info( 10920c41891cSEric Bernstein enum dc_color_depth color_depth, 10930c41891cSEric Bernstein uint32_t crtc_pixel_clock_in_khz, 10940c41891cSEric Bernstein uint32_t actual_pixel_clock_in_khz, 10950c41891cSEric Bernstein struct audio_clock_info *audio_clock_info) 10960c41891cSEric Bernstein { 10970c41891cSEric Bernstein const struct audio_clock_info *clock_info; 10980c41891cSEric Bernstein uint32_t index; 10990c41891cSEric Bernstein uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; 11000c41891cSEric Bernstein uint32_t audio_array_size; 11010c41891cSEric Bernstein 11020c41891cSEric Bernstein switch (color_depth) { 11030c41891cSEric Bernstein case COLOR_DEPTH_161616: 11040c41891cSEric Bernstein clock_info = audio_clock_info_table_48bpc; 11050c41891cSEric Bernstein audio_array_size = ARRAY_SIZE( 11060c41891cSEric Bernstein audio_clock_info_table_48bpc); 11070c41891cSEric Bernstein break; 11080c41891cSEric Bernstein case COLOR_DEPTH_121212: 11090c41891cSEric Bernstein clock_info = audio_clock_info_table_36bpc; 11100c41891cSEric Bernstein audio_array_size = ARRAY_SIZE( 11110c41891cSEric Bernstein audio_clock_info_table_36bpc); 11120c41891cSEric Bernstein break; 11130c41891cSEric Bernstein default: 11140c41891cSEric Bernstein clock_info = audio_clock_info_table; 11150c41891cSEric Bernstein audio_array_size = ARRAY_SIZE( 11160c41891cSEric Bernstein audio_clock_info_table); 11170c41891cSEric Bernstein break; 11180c41891cSEric Bernstein } 11190c41891cSEric Bernstein 11200c41891cSEric Bernstein if (clock_info != NULL) { 11210c41891cSEric Bernstein /* search for exact pixel clock in table */ 11220c41891cSEric Bernstein for (index = 0; index < audio_array_size; index++) { 11230c41891cSEric Bernstein if (clock_info[index].pixel_clock_in_10khz > 11240c41891cSEric Bernstein crtc_pixel_clock_in_10khz) 11250c41891cSEric Bernstein break; /* not match */ 11260c41891cSEric Bernstein else if (clock_info[index].pixel_clock_in_10khz == 11270c41891cSEric Bernstein crtc_pixel_clock_in_10khz) { 11280c41891cSEric Bernstein /* match found */ 11290c41891cSEric Bernstein *audio_clock_info = clock_info[index]; 11300c41891cSEric Bernstein return; 11310c41891cSEric Bernstein } 11320c41891cSEric Bernstein } 11330c41891cSEric Bernstein } 11340c41891cSEric Bernstein 11350c41891cSEric Bernstein /* not found */ 11360c41891cSEric Bernstein if (actual_pixel_clock_in_khz == 0) 11370c41891cSEric Bernstein actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; 11380c41891cSEric Bernstein 11390c41891cSEric Bernstein /* See HDMI spec the table entry under 11400c41891cSEric Bernstein * pixel clock of "Other". */ 11410c41891cSEric Bernstein audio_clock_info->pixel_clock_in_10khz = 11420c41891cSEric Bernstein actual_pixel_clock_in_khz / 10; 11430c41891cSEric Bernstein audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; 11440c41891cSEric Bernstein audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; 11450c41891cSEric Bernstein audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; 11460c41891cSEric Bernstein 11470c41891cSEric Bernstein audio_clock_info->n_32khz = 4096; 11480c41891cSEric Bernstein audio_clock_info->n_44khz = 6272; 11490c41891cSEric Bernstein audio_clock_info->n_48khz = 6144; 11500c41891cSEric Bernstein } 11510c41891cSEric Bernstein 11520c41891cSEric Bernstein static void enc1_se_audio_setup( 11530c41891cSEric Bernstein struct stream_encoder *enc, 11540c41891cSEric Bernstein unsigned int az_inst, 11550c41891cSEric Bernstein struct audio_info *audio_info) 11560c41891cSEric Bernstein { 11570c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 11580c41891cSEric Bernstein 11590c41891cSEric Bernstein uint32_t speakers = 0; 11600c41891cSEric Bernstein uint32_t channels = 0; 11610c41891cSEric Bernstein 11620c41891cSEric Bernstein ASSERT(audio_info); 11630c41891cSEric Bernstein if (audio_info == NULL) 11640c41891cSEric Bernstein /* This should not happen.it does so we don't get BSOD*/ 11650c41891cSEric Bernstein return; 11660c41891cSEric Bernstein 11670c41891cSEric Bernstein speakers = audio_info->flags.info.ALLSPEAKERS; 11680c41891cSEric Bernstein channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 11690c41891cSEric Bernstein 11700c41891cSEric Bernstein /* setup the audio stream source select (audio -> dig mapping) */ 11710c41891cSEric Bernstein REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 11720c41891cSEric Bernstein 11730c41891cSEric Bernstein /* Channel allocation */ 11740c41891cSEric Bernstein REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 11750c41891cSEric Bernstein } 11760c41891cSEric Bernstein 11770c41891cSEric Bernstein static void enc1_se_setup_hdmi_audio( 11780c41891cSEric Bernstein struct stream_encoder *enc, 11790c41891cSEric Bernstein const struct audio_crtc_info *crtc_info) 11800c41891cSEric Bernstein { 11810c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 11820c41891cSEric Bernstein 11830c41891cSEric Bernstein struct audio_clock_info audio_clock_info = {0}; 11840c41891cSEric Bernstein 11850c41891cSEric Bernstein /* HDMI_AUDIO_PACKET_CONTROL */ 1186b4f84bdfSEric Bernstein REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, 11870c41891cSEric Bernstein HDMI_AUDIO_DELAY_EN, 1); 11880c41891cSEric Bernstein 11890c41891cSEric Bernstein /* AFMT_AUDIO_PACKET_CONTROL */ 11900c41891cSEric Bernstein REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 11910c41891cSEric Bernstein 11920c41891cSEric Bernstein /* AFMT_AUDIO_PACKET_CONTROL2 */ 11930c41891cSEric Bernstein REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 11940c41891cSEric Bernstein AFMT_AUDIO_LAYOUT_OVRD, 0, 11950c41891cSEric Bernstein AFMT_60958_OSF_OVRD, 0); 11960c41891cSEric Bernstein 11970c41891cSEric Bernstein /* HDMI_ACR_PACKET_CONTROL */ 11980c41891cSEric Bernstein REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 11990c41891cSEric Bernstein HDMI_ACR_AUTO_SEND, 1, 12000c41891cSEric Bernstein HDMI_ACR_SOURCE, 0, 12010c41891cSEric Bernstein HDMI_ACR_AUDIO_PRIORITY, 0); 12020c41891cSEric Bernstein 12030c41891cSEric Bernstein /* Program audio clock sample/regeneration parameters */ 12040c41891cSEric Bernstein get_audio_clock_info(crtc_info->color_depth, 12050c41891cSEric Bernstein crtc_info->requested_pixel_clock, 12060c41891cSEric Bernstein crtc_info->calculated_pixel_clock, 12070c41891cSEric Bernstein &audio_clock_info); 12080c41891cSEric Bernstein DC_LOG_HW_AUDIO( 12090c41891cSEric Bernstein "\n%s:Input::requested_pixel_clock = %d" \ 12100c41891cSEric Bernstein "calculated_pixel_clock = %d \n", __func__, \ 12110c41891cSEric Bernstein crtc_info->requested_pixel_clock, \ 12120c41891cSEric Bernstein crtc_info->calculated_pixel_clock); 12130c41891cSEric Bernstein 12140c41891cSEric Bernstein /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 12150c41891cSEric Bernstein REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 12160c41891cSEric Bernstein 12170c41891cSEric Bernstein /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 12180c41891cSEric Bernstein REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 12190c41891cSEric Bernstein 12200c41891cSEric Bernstein /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 12210c41891cSEric Bernstein REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 12220c41891cSEric Bernstein 12230c41891cSEric Bernstein /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 12240c41891cSEric Bernstein REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 12250c41891cSEric Bernstein 12260c41891cSEric Bernstein /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 12270c41891cSEric Bernstein REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 12280c41891cSEric Bernstein 12290c41891cSEric Bernstein /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 12300c41891cSEric Bernstein REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 12310c41891cSEric Bernstein 12320c41891cSEric Bernstein /* Video driver cannot know in advance which sample rate will 12330c41891cSEric Bernstein * be used by HD Audio driver 12340c41891cSEric Bernstein * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 12350c41891cSEric Bernstein * programmed below in interruppt callback 12360c41891cSEric Bernstein */ 12370c41891cSEric Bernstein 12380c41891cSEric Bernstein /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 12390c41891cSEric Bernstein * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 12400c41891cSEric Bernstein */ 12410c41891cSEric Bernstein REG_UPDATE_2(AFMT_60958_0, 12420c41891cSEric Bernstein AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 12430c41891cSEric Bernstein AFMT_60958_CS_CLOCK_ACCURACY, 0); 12440c41891cSEric Bernstein 12450c41891cSEric Bernstein /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 12460c41891cSEric Bernstein REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 12470c41891cSEric Bernstein 12480c41891cSEric Bernstein /* AFMT_60958_2 now keep this settings until 12490c41891cSEric Bernstein * Programming guide comes out 12500c41891cSEric Bernstein */ 12510c41891cSEric Bernstein REG_UPDATE_6(AFMT_60958_2, 12520c41891cSEric Bernstein AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 12530c41891cSEric Bernstein AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 12540c41891cSEric Bernstein AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 12550c41891cSEric Bernstein AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 12560c41891cSEric Bernstein AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 12570c41891cSEric Bernstein AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 12580c41891cSEric Bernstein } 12590c41891cSEric Bernstein 12600c41891cSEric Bernstein static void enc1_se_setup_dp_audio( 12610c41891cSEric Bernstein struct stream_encoder *enc) 12620c41891cSEric Bernstein { 12630c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 12640c41891cSEric Bernstein 12650c41891cSEric Bernstein /* --- DP Audio packet configurations --- */ 12660c41891cSEric Bernstein 12670c41891cSEric Bernstein /* ATP Configuration */ 12680c41891cSEric Bernstein REG_SET(DP_SEC_AUD_N, 0, 12690c41891cSEric Bernstein DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 12700c41891cSEric Bernstein 12710c41891cSEric Bernstein /* Async/auto-calc timestamp mode */ 12720c41891cSEric Bernstein REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 12730c41891cSEric Bernstein DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 12740c41891cSEric Bernstein 12750c41891cSEric Bernstein /* --- The following are the registers 12760c41891cSEric Bernstein * copied from the SetupHDMI --- 12770c41891cSEric Bernstein */ 12780c41891cSEric Bernstein 12790c41891cSEric Bernstein /* AFMT_AUDIO_PACKET_CONTROL */ 12800c41891cSEric Bernstein REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 12810c41891cSEric Bernstein 12820c41891cSEric Bernstein /* AFMT_AUDIO_PACKET_CONTROL2 */ 12830c41891cSEric Bernstein /* Program the ATP and AIP next */ 12840c41891cSEric Bernstein REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 12850c41891cSEric Bernstein AFMT_AUDIO_LAYOUT_OVRD, 0, 12860c41891cSEric Bernstein AFMT_60958_OSF_OVRD, 0); 12870c41891cSEric Bernstein 12880c41891cSEric Bernstein /* AFMT_INFOFRAME_CONTROL0 */ 12890c41891cSEric Bernstein REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 12900c41891cSEric Bernstein 12910c41891cSEric Bernstein /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 12920c41891cSEric Bernstein REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 12930c41891cSEric Bernstein } 12940c41891cSEric Bernstein 12950c41891cSEric Bernstein static void enc1_se_enable_audio_clock( 12960c41891cSEric Bernstein struct stream_encoder *enc, 12970c41891cSEric Bernstein bool enable) 12980c41891cSEric Bernstein { 12990c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 13000c41891cSEric Bernstein 13010c41891cSEric Bernstein if (REG(AFMT_CNTL) == 0) 13020c41891cSEric Bernstein return; /* DCE8/10 does not have this register */ 13030c41891cSEric Bernstein 13040c41891cSEric Bernstein REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 13050c41891cSEric Bernstein 13060c41891cSEric Bernstein /* wait for AFMT clock to turn on, 13070c41891cSEric Bernstein * expectation: this should complete in 1-2 reads 13080c41891cSEric Bernstein * 13090c41891cSEric Bernstein * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 13100c41891cSEric Bernstein * 13110c41891cSEric Bernstein * TODO: wait for clock_on does not work well. May need HW 13120c41891cSEric Bernstein * program sequence. But audio seems work normally even without wait 13130c41891cSEric Bernstein * for clock_on status change 13140c41891cSEric Bernstein */ 13150c41891cSEric Bernstein } 13160c41891cSEric Bernstein 13170c41891cSEric Bernstein static void enc1_se_enable_dp_audio( 13180c41891cSEric Bernstein struct stream_encoder *enc) 13190c41891cSEric Bernstein { 13200c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 13210c41891cSEric Bernstein 13220c41891cSEric Bernstein /* Enable Audio packets */ 13230c41891cSEric Bernstein REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 13240c41891cSEric Bernstein 13250c41891cSEric Bernstein /* Program the ATP and AIP next */ 13260c41891cSEric Bernstein REG_UPDATE_2(DP_SEC_CNTL, 13270c41891cSEric Bernstein DP_SEC_ATP_ENABLE, 1, 13280c41891cSEric Bernstein DP_SEC_AIP_ENABLE, 1); 13290c41891cSEric Bernstein 13300c41891cSEric Bernstein /* Program STREAM_ENABLE after all the other enables. */ 13310c41891cSEric Bernstein REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 13320c41891cSEric Bernstein } 13330c41891cSEric Bernstein 13340c41891cSEric Bernstein static void enc1_se_disable_dp_audio( 13350c41891cSEric Bernstein struct stream_encoder *enc) 13360c41891cSEric Bernstein { 13370c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1338388277b1SAnthony Koo uint32_t value = 0; 13390c41891cSEric Bernstein 13400c41891cSEric Bernstein /* Disable Audio packets */ 13410c41891cSEric Bernstein REG_UPDATE_5(DP_SEC_CNTL, 13420c41891cSEric Bernstein DP_SEC_ASP_ENABLE, 0, 13430c41891cSEric Bernstein DP_SEC_ATP_ENABLE, 0, 13440c41891cSEric Bernstein DP_SEC_AIP_ENABLE, 0, 13450c41891cSEric Bernstein DP_SEC_ACM_ENABLE, 0, 13460c41891cSEric Bernstein DP_SEC_STREAM_ENABLE, 0); 13470c41891cSEric Bernstein 13480c41891cSEric Bernstein /* This register shared with encoder info frame. Therefore we need to 13490c41891cSEric Bernstein * keep master enabled if at least on of the fields is not 0 13500c41891cSEric Bernstein */ 1351388277b1SAnthony Koo value = REG_READ(DP_SEC_CNTL); 13520c41891cSEric Bernstein if (value != 0) 13530c41891cSEric Bernstein REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 13540c41891cSEric Bernstein 13550c41891cSEric Bernstein } 13560c41891cSEric Bernstein 13570c41891cSEric Bernstein void enc1_se_audio_mute_control( 13580c41891cSEric Bernstein struct stream_encoder *enc, 13590c41891cSEric Bernstein bool mute) 13600c41891cSEric Bernstein { 13610c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 13620c41891cSEric Bernstein 13630c41891cSEric Bernstein REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 13640c41891cSEric Bernstein } 13650c41891cSEric Bernstein 13660c41891cSEric Bernstein void enc1_se_dp_audio_setup( 13670c41891cSEric Bernstein struct stream_encoder *enc, 13680c41891cSEric Bernstein unsigned int az_inst, 13690c41891cSEric Bernstein struct audio_info *info) 13700c41891cSEric Bernstein { 13710c41891cSEric Bernstein enc1_se_audio_setup(enc, az_inst, info); 13720c41891cSEric Bernstein } 13730c41891cSEric Bernstein 13740c41891cSEric Bernstein void enc1_se_dp_audio_enable( 13750c41891cSEric Bernstein struct stream_encoder *enc) 13760c41891cSEric Bernstein { 13770c41891cSEric Bernstein enc1_se_enable_audio_clock(enc, true); 13780c41891cSEric Bernstein enc1_se_setup_dp_audio(enc); 13790c41891cSEric Bernstein enc1_se_enable_dp_audio(enc); 13800c41891cSEric Bernstein } 13810c41891cSEric Bernstein 13820c41891cSEric Bernstein void enc1_se_dp_audio_disable( 13830c41891cSEric Bernstein struct stream_encoder *enc) 13840c41891cSEric Bernstein { 13850c41891cSEric Bernstein enc1_se_disable_dp_audio(enc); 13860c41891cSEric Bernstein enc1_se_enable_audio_clock(enc, false); 13870c41891cSEric Bernstein } 13880c41891cSEric Bernstein 13890c41891cSEric Bernstein void enc1_se_hdmi_audio_setup( 13900c41891cSEric Bernstein struct stream_encoder *enc, 13910c41891cSEric Bernstein unsigned int az_inst, 13920c41891cSEric Bernstein struct audio_info *info, 13930c41891cSEric Bernstein struct audio_crtc_info *audio_crtc_info) 13940c41891cSEric Bernstein { 13950c41891cSEric Bernstein enc1_se_enable_audio_clock(enc, true); 13960c41891cSEric Bernstein enc1_se_setup_hdmi_audio(enc, audio_crtc_info); 13970c41891cSEric Bernstein enc1_se_audio_setup(enc, az_inst, info); 13980c41891cSEric Bernstein } 13990c41891cSEric Bernstein 14000c41891cSEric Bernstein void enc1_se_hdmi_audio_disable( 14010c41891cSEric Bernstein struct stream_encoder *enc) 14020c41891cSEric Bernstein { 14030c41891cSEric Bernstein enc1_se_enable_audio_clock(enc, false); 14040c41891cSEric Bernstein } 14050c41891cSEric Bernstein 14060c41891cSEric Bernstein 1407c5011872SEric Bernstein void enc1_setup_stereo_sync( 14080c41891cSEric Bernstein struct stream_encoder *enc, 14090c41891cSEric Bernstein int tg_inst, bool enable) 14100c41891cSEric Bernstein { 14110c41891cSEric Bernstein struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 14120c41891cSEric Bernstein REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 14130c41891cSEric Bernstein REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 14140c41891cSEric Bernstein } 14150c41891cSEric Bernstein 14160c41891cSEric Bernstein 14170c41891cSEric Bernstein static const struct stream_encoder_funcs dcn10_str_enc_funcs = { 14180c41891cSEric Bernstein .dp_set_stream_attribute = 14190c41891cSEric Bernstein enc1_stream_encoder_dp_set_stream_attribute, 14200c41891cSEric Bernstein .hdmi_set_stream_attribute = 14210c41891cSEric Bernstein enc1_stream_encoder_hdmi_set_stream_attribute, 14220c41891cSEric Bernstein .dvi_set_stream_attribute = 14230c41891cSEric Bernstein enc1_stream_encoder_dvi_set_stream_attribute, 14240c41891cSEric Bernstein .set_mst_bandwidth = 14250c41891cSEric Bernstein enc1_stream_encoder_set_mst_bandwidth, 14260c41891cSEric Bernstein .update_hdmi_info_packets = 14270c41891cSEric Bernstein enc1_stream_encoder_update_hdmi_info_packets, 14280c41891cSEric Bernstein .stop_hdmi_info_packets = 14290c41891cSEric Bernstein enc1_stream_encoder_stop_hdmi_info_packets, 14300c41891cSEric Bernstein .update_dp_info_packets = 14310c41891cSEric Bernstein enc1_stream_encoder_update_dp_info_packets, 14320c41891cSEric Bernstein .stop_dp_info_packets = 14330c41891cSEric Bernstein enc1_stream_encoder_stop_dp_info_packets, 14340c41891cSEric Bernstein .dp_blank = 14350c41891cSEric Bernstein enc1_stream_encoder_dp_blank, 14360c41891cSEric Bernstein .dp_unblank = 14370c41891cSEric Bernstein enc1_stream_encoder_dp_unblank, 14380c41891cSEric Bernstein .audio_mute_control = enc1_se_audio_mute_control, 14390c41891cSEric Bernstein 14400c41891cSEric Bernstein .dp_audio_setup = enc1_se_dp_audio_setup, 14410c41891cSEric Bernstein .dp_audio_enable = enc1_se_dp_audio_enable, 14420c41891cSEric Bernstein .dp_audio_disable = enc1_se_dp_audio_disable, 14430c41891cSEric Bernstein 14440c41891cSEric Bernstein .hdmi_audio_setup = enc1_se_hdmi_audio_setup, 14450c41891cSEric Bernstein .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 14460c41891cSEric Bernstein .setup_stereo_sync = enc1_setup_stereo_sync, 14470c41891cSEric Bernstein .set_avmute = enc1_stream_encoder_set_avmute, 14480c41891cSEric Bernstein }; 14490c41891cSEric Bernstein 14500c41891cSEric Bernstein void dcn10_stream_encoder_construct( 14510c41891cSEric Bernstein struct dcn10_stream_encoder *enc1, 14520c41891cSEric Bernstein struct dc_context *ctx, 14530c41891cSEric Bernstein struct dc_bios *bp, 14540c41891cSEric Bernstein enum engine_id eng_id, 14550c41891cSEric Bernstein const struct dcn10_stream_enc_registers *regs, 14560c41891cSEric Bernstein const struct dcn10_stream_encoder_shift *se_shift, 14570c41891cSEric Bernstein const struct dcn10_stream_encoder_mask *se_mask) 14580c41891cSEric Bernstein { 14590c41891cSEric Bernstein enc1->base.funcs = &dcn10_str_enc_funcs; 14600c41891cSEric Bernstein enc1->base.ctx = ctx; 14610c41891cSEric Bernstein enc1->base.id = eng_id; 14620c41891cSEric Bernstein enc1->base.bp = bp; 14630c41891cSEric Bernstein enc1->regs = regs; 14640c41891cSEric Bernstein enc1->se_shift = se_shift; 14650c41891cSEric Bernstein enc1->se_mask = se_mask; 14660c41891cSEric Bernstein } 14670c41891cSEric Bernstein 1468