1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "dcn10_init.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dcn10_resource.h" 34 #include "dcn10_ipp.h" 35 #include "dcn10_mpc.h" 36 #include "irq/dcn10/irq_service_dcn10.h" 37 #include "dcn10_dpp.h" 38 #include "dcn10_optc.h" 39 #include "dcn10_hw_sequencer.h" 40 #include "dce110/dce110_hw_sequencer.h" 41 #include "dcn10_opp.h" 42 #include "dcn10_link_encoder.h" 43 #include "dcn10_stream_encoder.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 #include "dce/dce_panel_cntl.h" 53 54 #include "soc15_hw_ip.h" 55 #include "vega10_ip_offset.h" 56 57 #include "dcn/dcn_1_0_offset.h" 58 #include "dcn/dcn_1_0_sh_mask.h" 59 60 #include "nbio/nbio_7_0_offset.h" 61 62 #include "mmhub/mmhub_9_1_offset.h" 63 #include "mmhub/mmhub_9_1_sh_mask.h" 64 65 #include "reg_helper.h" 66 #include "dce/dce_abm.h" 67 #include "dce/dce_dmcu.h" 68 #include "dce/dce_aux.h" 69 #include "dce/dce_i2c.h" 70 71 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 73 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 75 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 77 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 79 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 81 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 83 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 85 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #endif 87 88 89 enum dcn10_clk_src_array_id { 90 DCN10_CLK_SRC_PLL0, 91 DCN10_CLK_SRC_PLL1, 92 DCN10_CLK_SRC_PLL2, 93 DCN10_CLK_SRC_PLL3, 94 DCN10_CLK_SRC_TOTAL, 95 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 96 }; 97 98 /* begin ********************* 99 * macros to expend register list macro defined in HW object header file */ 100 101 /* DCN */ 102 #define BASE_INNER(seg) \ 103 DCE_BASE__INST0_SEG ## seg 104 105 #define BASE(seg) \ 106 BASE_INNER(seg) 107 108 #define SR(reg_name)\ 109 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 110 mm ## reg_name 111 112 #define SRI(reg_name, block, id)\ 113 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 114 mm ## block ## id ## _ ## reg_name 115 116 117 #define SRII(reg_name, block, id)\ 118 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 119 mm ## block ## id ## _ ## reg_name 120 121 #define VUPDATE_SRII(reg_name, block, id)\ 122 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \ 123 mm ## reg_name ## 0 ## _ ## block ## id 124 125 /* set field/register/bitfield name */ 126 #define SFRB(field_name, reg_name, bitfield, post_fix)\ 127 .field_name = reg_name ## __ ## bitfield ## post_fix 128 129 /* NBIO */ 130 #define NBIO_BASE_INNER(seg) \ 131 NBIF_BASE__INST0_SEG ## seg 132 133 #define NBIO_BASE(seg) \ 134 NBIO_BASE_INNER(seg) 135 136 #define NBIO_SR(reg_name)\ 137 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 138 mm ## reg_name 139 140 /* MMHUB */ 141 #define MMHUB_BASE_INNER(seg) \ 142 MMHUB_BASE__INST0_SEG ## seg 143 144 #define MMHUB_BASE(seg) \ 145 MMHUB_BASE_INNER(seg) 146 147 #define MMHUB_SR(reg_name)\ 148 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 149 mm ## reg_name 150 151 /* macros to expend register list macro defined in HW object header file 152 * end *********************/ 153 154 155 static const struct dce_dmcu_registers dmcu_regs = { 156 DMCU_DCN10_REG_LIST() 157 }; 158 159 static const struct dce_dmcu_shift dmcu_shift = { 160 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 161 }; 162 163 static const struct dce_dmcu_mask dmcu_mask = { 164 DMCU_MASK_SH_LIST_DCN10(_MASK) 165 }; 166 167 static const struct dce_abm_registers abm_regs = { 168 ABM_DCN10_REG_LIST(0) 169 }; 170 171 static const struct dce_abm_shift abm_shift = { 172 ABM_MASK_SH_LIST_DCN10(__SHIFT) 173 }; 174 175 static const struct dce_abm_mask abm_mask = { 176 ABM_MASK_SH_LIST_DCN10(_MASK) 177 }; 178 179 #define stream_enc_regs(id)\ 180 [id] = {\ 181 SE_DCN_REG_LIST(id)\ 182 } 183 184 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 185 stream_enc_regs(0), 186 stream_enc_regs(1), 187 stream_enc_regs(2), 188 stream_enc_regs(3), 189 }; 190 191 static const struct dcn10_stream_encoder_shift se_shift = { 192 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 193 }; 194 195 static const struct dcn10_stream_encoder_mask se_mask = { 196 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 197 }; 198 199 #define audio_regs(id)\ 200 [id] = {\ 201 AUD_COMMON_REG_LIST(id)\ 202 } 203 204 static const struct dce_audio_registers audio_regs[] = { 205 audio_regs(0), 206 audio_regs(1), 207 audio_regs(2), 208 audio_regs(3), 209 }; 210 211 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 212 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 213 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 214 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 215 216 static const struct dce_audio_shift audio_shift = { 217 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 218 }; 219 220 static const struct dce_audio_mask audio_mask = { 221 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 222 }; 223 224 #define aux_regs(id)\ 225 [id] = {\ 226 AUX_REG_LIST(id)\ 227 } 228 229 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 230 aux_regs(0), 231 aux_regs(1), 232 aux_regs(2), 233 aux_regs(3) 234 }; 235 236 #define hpd_regs(id)\ 237 [id] = {\ 238 HPD_REG_LIST(id)\ 239 } 240 241 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 242 hpd_regs(0), 243 hpd_regs(1), 244 hpd_regs(2), 245 hpd_regs(3) 246 }; 247 248 #define link_regs(id)\ 249 [id] = {\ 250 LE_DCN10_REG_LIST(id), \ 251 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 252 } 253 254 static const struct dcn10_link_enc_registers link_enc_regs[] = { 255 link_regs(0), 256 link_regs(1), 257 link_regs(2), 258 link_regs(3) 259 }; 260 261 static const struct dcn10_link_enc_shift le_shift = { 262 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 263 }; 264 265 static const struct dcn10_link_enc_mask le_mask = { 266 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 267 }; 268 269 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 270 { DCN_PANEL_CNTL_REG_LIST() } 271 }; 272 273 static const struct dce_panel_cntl_shift panel_cntl_shift = { 274 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 275 }; 276 277 static const struct dce_panel_cntl_mask panel_cntl_mask = { 278 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 279 }; 280 281 static const struct dce110_aux_registers_shift aux_shift = { 282 DCN10_AUX_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dce110_aux_registers_mask aux_mask = { 286 DCN10_AUX_MASK_SH_LIST(_MASK) 287 }; 288 289 #define ipp_regs(id)\ 290 [id] = {\ 291 IPP_REG_LIST_DCN10(id),\ 292 } 293 294 static const struct dcn10_ipp_registers ipp_regs[] = { 295 ipp_regs(0), 296 ipp_regs(1), 297 ipp_regs(2), 298 ipp_regs(3), 299 }; 300 301 static const struct dcn10_ipp_shift ipp_shift = { 302 IPP_MASK_SH_LIST_DCN10(__SHIFT) 303 }; 304 305 static const struct dcn10_ipp_mask ipp_mask = { 306 IPP_MASK_SH_LIST_DCN10(_MASK), 307 }; 308 309 #define opp_regs(id)\ 310 [id] = {\ 311 OPP_REG_LIST_DCN10(id),\ 312 } 313 314 static const struct dcn10_opp_registers opp_regs[] = { 315 opp_regs(0), 316 opp_regs(1), 317 opp_regs(2), 318 opp_regs(3), 319 }; 320 321 static const struct dcn10_opp_shift opp_shift = { 322 OPP_MASK_SH_LIST_DCN10(__SHIFT) 323 }; 324 325 static const struct dcn10_opp_mask opp_mask = { 326 OPP_MASK_SH_LIST_DCN10(_MASK), 327 }; 328 329 #define aux_engine_regs(id)\ 330 [id] = {\ 331 AUX_COMMON_REG_LIST(id), \ 332 .AUX_RESET_MASK = 0 \ 333 } 334 335 static const struct dce110_aux_registers aux_engine_regs[] = { 336 aux_engine_regs(0), 337 aux_engine_regs(1), 338 aux_engine_regs(2), 339 aux_engine_regs(3), 340 aux_engine_regs(4), 341 aux_engine_regs(5) 342 }; 343 344 #define tf_regs(id)\ 345 [id] = {\ 346 TF_REG_LIST_DCN10(id),\ 347 } 348 349 static const struct dcn_dpp_registers tf_regs[] = { 350 tf_regs(0), 351 tf_regs(1), 352 tf_regs(2), 353 tf_regs(3), 354 }; 355 356 static const struct dcn_dpp_shift tf_shift = { 357 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 358 TF_DEBUG_REG_LIST_SH_DCN10 359 360 }; 361 362 static const struct dcn_dpp_mask tf_mask = { 363 TF_REG_LIST_SH_MASK_DCN10(_MASK), 364 TF_DEBUG_REG_LIST_MASK_DCN10 365 }; 366 367 static const struct dcn_mpc_registers mpc_regs = { 368 MPC_COMMON_REG_LIST_DCN1_0(0), 369 MPC_COMMON_REG_LIST_DCN1_0(1), 370 MPC_COMMON_REG_LIST_DCN1_0(2), 371 MPC_COMMON_REG_LIST_DCN1_0(3), 372 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 373 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 374 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 375 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 376 }; 377 378 static const struct dcn_mpc_shift mpc_shift = { 379 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\ 380 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT) 381 }; 382 383 static const struct dcn_mpc_mask mpc_mask = { 384 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\ 385 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK) 386 }; 387 388 #define tg_regs(id)\ 389 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 390 391 static const struct dcn_optc_registers tg_regs[] = { 392 tg_regs(0), 393 tg_regs(1), 394 tg_regs(2), 395 tg_regs(3), 396 }; 397 398 static const struct dcn_optc_shift tg_shift = { 399 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 400 }; 401 402 static const struct dcn_optc_mask tg_mask = { 403 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 404 }; 405 406 static const struct bios_registers bios_regs = { 407 NBIO_SR(BIOS_SCRATCH_3), 408 NBIO_SR(BIOS_SCRATCH_6) 409 }; 410 411 #define hubp_regs(id)\ 412 [id] = {\ 413 HUBP_REG_LIST_DCN10(id)\ 414 } 415 416 static const struct dcn_mi_registers hubp_regs[] = { 417 hubp_regs(0), 418 hubp_regs(1), 419 hubp_regs(2), 420 hubp_regs(3), 421 }; 422 423 static const struct dcn_mi_shift hubp_shift = { 424 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 425 }; 426 427 static const struct dcn_mi_mask hubp_mask = { 428 HUBP_MASK_SH_LIST_DCN10(_MASK) 429 }; 430 431 static const struct dcn_hubbub_registers hubbub_reg = { 432 HUBBUB_REG_LIST_DCN10(0) 433 }; 434 435 static const struct dcn_hubbub_shift hubbub_shift = { 436 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 437 }; 438 439 static const struct dcn_hubbub_mask hubbub_mask = { 440 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 441 }; 442 443 static int map_transmitter_id_to_phy_instance( 444 enum transmitter transmitter) 445 { 446 switch (transmitter) { 447 case TRANSMITTER_UNIPHY_A: 448 return 0; 449 break; 450 case TRANSMITTER_UNIPHY_B: 451 return 1; 452 break; 453 case TRANSMITTER_UNIPHY_C: 454 return 2; 455 break; 456 case TRANSMITTER_UNIPHY_D: 457 return 3; 458 break; 459 default: 460 ASSERT(0); 461 return 0; 462 } 463 } 464 465 #define clk_src_regs(index, pllid)\ 466 [index] = {\ 467 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 468 } 469 470 static const struct dce110_clk_src_regs clk_src_regs[] = { 471 clk_src_regs(0, A), 472 clk_src_regs(1, B), 473 clk_src_regs(2, C), 474 clk_src_regs(3, D) 475 }; 476 477 static const struct dce110_clk_src_shift cs_shift = { 478 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 479 }; 480 481 static const struct dce110_clk_src_mask cs_mask = { 482 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 483 }; 484 485 static const struct resource_caps res_cap = { 486 .num_timing_generator = 4, 487 .num_opp = 4, 488 .num_video_plane = 4, 489 .num_audio = 4, 490 .num_stream_encoder = 4, 491 .num_pll = 4, 492 .num_ddc = 4, 493 }; 494 495 static const struct resource_caps rv2_res_cap = { 496 .num_timing_generator = 3, 497 .num_opp = 3, 498 .num_video_plane = 3, 499 .num_audio = 3, 500 .num_stream_encoder = 3, 501 .num_pll = 3, 502 .num_ddc = 4, 503 }; 504 505 static const struct dc_plane_cap plane_cap = { 506 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 507 .per_pixel_alpha = true, 508 509 .pixel_format_support = { 510 .argb8888 = true, 511 .nv12 = true, 512 .fp16 = true, 513 .p010 = true 514 }, 515 516 .max_upscale_factor = { 517 .argb8888 = 16000, 518 .nv12 = 16000, 519 .fp16 = 1 520 }, 521 522 .max_downscale_factor = { 523 .argb8888 = 250, 524 .nv12 = 250, 525 .fp16 = 1 526 } 527 }; 528 529 static const struct dc_debug_options debug_defaults_drv = { 530 .sanity_checks = true, 531 .disable_dmcu = false, 532 .force_abm_enable = false, 533 .timing_trace = false, 534 .clock_trace = true, 535 536 /* raven smu dones't allow 0 disp clk, 537 * smu min disp clk limit is 50Mhz 538 * keep min disp clk 100Mhz avoid smu hang 539 */ 540 .min_disp_clk_khz = 100000, 541 542 .disable_pplib_clock_request = false, 543 .disable_pplib_wm_range = false, 544 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 545 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 546 .force_single_disp_pipe_split = true, 547 .disable_dcc = DCC_ENABLE, 548 .voltage_align_fclk = true, 549 .disable_stereo_support = true, 550 .vsr_support = true, 551 .performance_trace = false, 552 .az_endpoint_mute_only = true, 553 .recovery_enabled = false, /*enable this by default after testing.*/ 554 .max_downscale_src_width = 3840, 555 .underflow_assert_delay_us = 0xFFFFFFFF, 556 }; 557 558 static const struct dc_debug_options debug_defaults_diags = { 559 .disable_dmcu = false, 560 .force_abm_enable = false, 561 .timing_trace = true, 562 .clock_trace = true, 563 .disable_stutter = true, 564 .disable_pplib_clock_request = true, 565 .disable_pplib_wm_range = true, 566 .underflow_assert_delay_us = 0xFFFFFFFF, 567 }; 568 569 static void dcn10_dpp_destroy(struct dpp **dpp) 570 { 571 kfree(TO_DCN10_DPP(*dpp)); 572 *dpp = NULL; 573 } 574 575 static struct dpp *dcn10_dpp_create( 576 struct dc_context *ctx, 577 uint32_t inst) 578 { 579 struct dcn10_dpp *dpp = 580 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 581 582 if (!dpp) 583 return NULL; 584 585 dpp1_construct(dpp, ctx, inst, 586 &tf_regs[inst], &tf_shift, &tf_mask); 587 return &dpp->base; 588 } 589 590 static struct input_pixel_processor *dcn10_ipp_create( 591 struct dc_context *ctx, uint32_t inst) 592 { 593 struct dcn10_ipp *ipp = 594 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 595 596 if (!ipp) { 597 BREAK_TO_DEBUGGER(); 598 return NULL; 599 } 600 601 dcn10_ipp_construct(ipp, ctx, inst, 602 &ipp_regs[inst], &ipp_shift, &ipp_mask); 603 return &ipp->base; 604 } 605 606 607 static struct output_pixel_processor *dcn10_opp_create( 608 struct dc_context *ctx, uint32_t inst) 609 { 610 struct dcn10_opp *opp = 611 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 612 613 if (!opp) { 614 BREAK_TO_DEBUGGER(); 615 return NULL; 616 } 617 618 dcn10_opp_construct(opp, ctx, inst, 619 &opp_regs[inst], &opp_shift, &opp_mask); 620 return &opp->base; 621 } 622 623 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx, 624 uint32_t inst) 625 { 626 struct aux_engine_dce110 *aux_engine = 627 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 628 629 if (!aux_engine) 630 return NULL; 631 632 dce110_aux_engine_construct(aux_engine, ctx, inst, 633 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 634 &aux_engine_regs[inst], 635 &aux_mask, 636 &aux_shift, 637 ctx->dc->caps.extended_aux_timeout_support); 638 639 return &aux_engine->base; 640 } 641 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 642 643 static const struct dce_i2c_registers i2c_hw_regs[] = { 644 i2c_inst_regs(1), 645 i2c_inst_regs(2), 646 i2c_inst_regs(3), 647 i2c_inst_regs(4), 648 i2c_inst_regs(5), 649 i2c_inst_regs(6), 650 }; 651 652 static const struct dce_i2c_shift i2c_shifts = { 653 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 654 }; 655 656 static const struct dce_i2c_mask i2c_masks = { 657 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 658 }; 659 660 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx, 661 uint32_t inst) 662 { 663 struct dce_i2c_hw *dce_i2c_hw = 664 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 665 666 if (!dce_i2c_hw) 667 return NULL; 668 669 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 670 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 671 672 return dce_i2c_hw; 673 } 674 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 675 { 676 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 677 GFP_KERNEL); 678 679 if (!mpc10) 680 return NULL; 681 682 dcn10_mpc_construct(mpc10, ctx, 683 &mpc_regs, 684 &mpc_shift, 685 &mpc_mask, 686 4); 687 688 return &mpc10->base; 689 } 690 691 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 692 { 693 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 694 GFP_KERNEL); 695 696 if (!dcn10_hubbub) 697 return NULL; 698 699 hubbub1_construct(&dcn10_hubbub->base, ctx, 700 &hubbub_reg, 701 &hubbub_shift, 702 &hubbub_mask); 703 704 return &dcn10_hubbub->base; 705 } 706 707 static struct timing_generator *dcn10_timing_generator_create( 708 struct dc_context *ctx, 709 uint32_t instance) 710 { 711 struct optc *tgn10 = 712 kzalloc(sizeof(struct optc), GFP_KERNEL); 713 714 if (!tgn10) 715 return NULL; 716 717 tgn10->base.inst = instance; 718 tgn10->base.ctx = ctx; 719 720 tgn10->tg_regs = &tg_regs[instance]; 721 tgn10->tg_shift = &tg_shift; 722 tgn10->tg_mask = &tg_mask; 723 724 dcn10_timing_generator_init(tgn10); 725 726 return &tgn10->base; 727 } 728 729 static const struct encoder_feature_support link_enc_feature = { 730 .max_hdmi_deep_color = COLOR_DEPTH_121212, 731 .max_hdmi_pixel_clock = 600000, 732 .hdmi_ycbcr420_supported = true, 733 .dp_ycbcr420_supported = true, 734 .flags.bits.IS_HBR2_CAPABLE = true, 735 .flags.bits.IS_HBR3_CAPABLE = true, 736 .flags.bits.IS_TPS3_CAPABLE = true, 737 .flags.bits.IS_TPS4_CAPABLE = true 738 }; 739 740 static struct link_encoder *dcn10_link_encoder_create( 741 struct dc_context *ctx, 742 const struct encoder_init_data *enc_init_data) 743 { 744 struct dcn10_link_encoder *enc10 = 745 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 746 int link_regs_id; 747 748 if (!enc10) 749 return NULL; 750 751 link_regs_id = 752 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 753 754 dcn10_link_encoder_construct(enc10, 755 enc_init_data, 756 &link_enc_feature, 757 &link_enc_regs[link_regs_id], 758 &link_enc_aux_regs[enc_init_data->channel - 1], 759 &link_enc_hpd_regs[enc_init_data->hpd_source], 760 &le_shift, 761 &le_mask); 762 763 return &enc10->base; 764 } 765 766 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data) 767 { 768 struct dce_panel_cntl *panel_cntl = 769 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 770 771 if (!panel_cntl) 772 return NULL; 773 774 dce_panel_cntl_construct(panel_cntl, 775 init_data, 776 &panel_cntl_regs[init_data->inst], 777 &panel_cntl_shift, 778 &panel_cntl_mask); 779 780 return &panel_cntl->base; 781 } 782 783 static struct clock_source *dcn10_clock_source_create( 784 struct dc_context *ctx, 785 struct dc_bios *bios, 786 enum clock_source_id id, 787 const struct dce110_clk_src_regs *regs, 788 bool dp_clk_src) 789 { 790 struct dce110_clk_src *clk_src = 791 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 792 793 if (!clk_src) 794 return NULL; 795 796 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 797 regs, &cs_shift, &cs_mask)) { 798 clk_src->base.dp_clk_src = dp_clk_src; 799 return &clk_src->base; 800 } 801 802 kfree(clk_src); 803 BREAK_TO_DEBUGGER(); 804 return NULL; 805 } 806 807 static void read_dce_straps( 808 struct dc_context *ctx, 809 struct resource_straps *straps) 810 { 811 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 812 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 813 } 814 815 static struct audio *create_audio( 816 struct dc_context *ctx, unsigned int inst) 817 { 818 return dce_audio_create(ctx, inst, 819 &audio_regs[inst], &audio_shift, &audio_mask); 820 } 821 822 static struct stream_encoder *dcn10_stream_encoder_create( 823 enum engine_id eng_id, 824 struct dc_context *ctx) 825 { 826 struct dcn10_stream_encoder *enc1 = 827 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 828 829 if (!enc1) 830 return NULL; 831 832 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 833 &stream_enc_regs[eng_id], 834 &se_shift, &se_mask); 835 return &enc1->base; 836 } 837 838 static const struct dce_hwseq_registers hwseq_reg = { 839 HWSEQ_DCN1_REG_LIST() 840 }; 841 842 static const struct dce_hwseq_shift hwseq_shift = { 843 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 844 }; 845 846 static const struct dce_hwseq_mask hwseq_mask = { 847 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 848 }; 849 850 static struct dce_hwseq *dcn10_hwseq_create( 851 struct dc_context *ctx) 852 { 853 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 854 855 if (hws) { 856 hws->ctx = ctx; 857 hws->regs = &hwseq_reg; 858 hws->shifts = &hwseq_shift; 859 hws->masks = &hwseq_mask; 860 hws->wa.DEGVIDCN10_253 = true; 861 hws->wa.false_optc_underflow = true; 862 hws->wa.DEGVIDCN10_254 = true; 863 864 if ((ctx->asic_id.chip_family == FAMILY_RV) && 865 ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev)) 866 switch (ctx->asic_id.pci_revision_id) { 867 case PRID_POLLOCK_94: 868 case PRID_POLLOCK_95: 869 case PRID_POLLOCK_E9: 870 case PRID_POLLOCK_EA: 871 case PRID_POLLOCK_EB: 872 hws->wa.wait_hubpret_read_start_during_mpo_transition = true; 873 break; 874 default: 875 hws->wa.wait_hubpret_read_start_during_mpo_transition = false; 876 break; 877 } 878 } 879 return hws; 880 } 881 882 static const struct resource_create_funcs res_create_funcs = { 883 .read_dce_straps = read_dce_straps, 884 .create_audio = create_audio, 885 .create_stream_encoder = dcn10_stream_encoder_create, 886 .create_hwseq = dcn10_hwseq_create, 887 }; 888 889 static const struct resource_create_funcs res_create_maximus_funcs = { 890 .read_dce_straps = NULL, 891 .create_audio = NULL, 892 .create_stream_encoder = NULL, 893 .create_hwseq = dcn10_hwseq_create, 894 }; 895 896 static void dcn10_clock_source_destroy(struct clock_source **clk_src) 897 { 898 kfree(TO_DCE110_CLK_SRC(*clk_src)); 899 *clk_src = NULL; 900 } 901 902 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 903 { 904 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 905 906 if (!pp_smu) 907 return pp_smu; 908 909 dm_pp_get_funcs(ctx, pp_smu); 910 return pp_smu; 911 } 912 913 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) 914 { 915 unsigned int i; 916 917 for (i = 0; i < pool->base.stream_enc_count; i++) { 918 if (pool->base.stream_enc[i] != NULL) { 919 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 920 pool->base.stream_enc[i] = NULL; 921 } 922 } 923 924 if (pool->base.mpc != NULL) { 925 kfree(TO_DCN10_MPC(pool->base.mpc)); 926 pool->base.mpc = NULL; 927 } 928 929 kfree(pool->base.hubbub); 930 pool->base.hubbub = NULL; 931 932 for (i = 0; i < pool->base.pipe_count; i++) { 933 if (pool->base.opps[i] != NULL) 934 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 935 936 if (pool->base.dpps[i] != NULL) 937 dcn10_dpp_destroy(&pool->base.dpps[i]); 938 939 if (pool->base.ipps[i] != NULL) 940 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 941 942 if (pool->base.hubps[i] != NULL) { 943 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 944 pool->base.hubps[i] = NULL; 945 } 946 947 if (pool->base.irqs != NULL) { 948 dal_irq_service_destroy(&pool->base.irqs); 949 } 950 951 if (pool->base.timing_generators[i] != NULL) { 952 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 953 pool->base.timing_generators[i] = NULL; 954 } 955 } 956 957 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 958 if (pool->base.engines[i] != NULL) 959 dce110_engine_destroy(&pool->base.engines[i]); 960 kfree(pool->base.hw_i2cs[i]); 961 pool->base.hw_i2cs[i] = NULL; 962 kfree(pool->base.sw_i2cs[i]); 963 pool->base.sw_i2cs[i] = NULL; 964 } 965 966 for (i = 0; i < pool->base.audio_count; i++) { 967 if (pool->base.audios[i]) 968 dce_aud_destroy(&pool->base.audios[i]); 969 } 970 971 for (i = 0; i < pool->base.clk_src_count; i++) { 972 if (pool->base.clock_sources[i] != NULL) { 973 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 974 pool->base.clock_sources[i] = NULL; 975 } 976 } 977 978 if (pool->base.dp_clock_source != NULL) { 979 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 980 pool->base.dp_clock_source = NULL; 981 } 982 983 if (pool->base.abm != NULL) 984 dce_abm_destroy(&pool->base.abm); 985 986 if (pool->base.dmcu != NULL) 987 dce_dmcu_destroy(&pool->base.dmcu); 988 989 kfree(pool->base.pp_smu); 990 } 991 992 static struct hubp *dcn10_hubp_create( 993 struct dc_context *ctx, 994 uint32_t inst) 995 { 996 struct dcn10_hubp *hubp1 = 997 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 998 999 if (!hubp1) 1000 return NULL; 1001 1002 dcn10_hubp_construct(hubp1, ctx, inst, 1003 &hubp_regs[inst], &hubp_shift, &hubp_mask); 1004 return &hubp1->base; 1005 } 1006 1007 static void get_pixel_clock_parameters( 1008 const struct pipe_ctx *pipe_ctx, 1009 struct pixel_clk_params *pixel_clk_params) 1010 { 1011 const struct dc_stream_state *stream = pipe_ctx->stream; 1012 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1013 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1014 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1015 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1016 /* TODO: un-hardcode*/ 1017 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1018 LINK_RATE_REF_FREQ_IN_KHZ; 1019 pixel_clk_params->flags.ENABLE_SS = 0; 1020 pixel_clk_params->color_depth = 1021 stream->timing.display_color_depth; 1022 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1023 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1024 1025 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1026 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1027 1028 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1029 pixel_clk_params->requested_pix_clk_100hz /= 2; 1030 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1031 pixel_clk_params->requested_pix_clk_100hz *= 2; 1032 1033 } 1034 1035 static void build_clamping_params(struct dc_stream_state *stream) 1036 { 1037 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1038 stream->clamping.c_depth = stream->timing.display_color_depth; 1039 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1040 } 1041 1042 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1043 { 1044 1045 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1046 1047 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1048 pipe_ctx->clock_source, 1049 &pipe_ctx->stream_res.pix_clk_params, 1050 &pipe_ctx->pll_settings); 1051 1052 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1053 1054 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1055 &pipe_ctx->stream->bit_depth_params); 1056 build_clamping_params(pipe_ctx->stream); 1057 } 1058 1059 static enum dc_status build_mapped_resource( 1060 const struct dc *dc, 1061 struct dc_state *context, 1062 struct dc_stream_state *stream) 1063 { 1064 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1065 1066 if (!pipe_ctx) 1067 return DC_ERROR_UNEXPECTED; 1068 1069 build_pipe_hw_param(pipe_ctx); 1070 return DC_OK; 1071 } 1072 1073 static enum dc_status dcn10_add_stream_to_ctx( 1074 struct dc *dc, 1075 struct dc_state *new_ctx, 1076 struct dc_stream_state *dc_stream) 1077 { 1078 enum dc_status result = DC_ERROR_UNEXPECTED; 1079 1080 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1081 1082 if (result == DC_OK) 1083 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1084 1085 1086 if (result == DC_OK) 1087 result = build_mapped_resource(dc, new_ctx, dc_stream); 1088 1089 return result; 1090 } 1091 1092 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1093 struct dc_state *context, 1094 const struct resource_pool *pool, 1095 struct dc_stream_state *stream) 1096 { 1097 struct resource_context *res_ctx = &context->res_ctx; 1098 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1099 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 1100 1101 if (!head_pipe) { 1102 ASSERT(0); 1103 return NULL; 1104 } 1105 1106 if (!idle_pipe) 1107 return NULL; 1108 1109 idle_pipe->stream = head_pipe->stream; 1110 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1111 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1112 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1113 1114 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1115 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1116 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1117 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1118 1119 return idle_pipe; 1120 } 1121 1122 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1123 const struct dc_dcc_surface_param *input, 1124 struct dc_surface_dcc_cap *output) 1125 { 1126 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1127 dc->res_pool->hubbub, 1128 input, 1129 output); 1130 } 1131 1132 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1133 { 1134 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1135 1136 dcn10_resource_destruct(dcn10_pool); 1137 kfree(dcn10_pool); 1138 *pool = NULL; 1139 } 1140 1141 static bool dcn10_validate_bandwidth( 1142 struct dc *dc, 1143 struct dc_state *context, 1144 bool fast_validate) 1145 { 1146 bool voltage_supported; 1147 1148 DC_FP_START(); 1149 voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate); 1150 DC_FP_END(); 1151 1152 return voltage_supported; 1153 } 1154 1155 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1156 { 1157 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1158 && caps->max_video_width != 0 1159 && plane_state->src_rect.width > caps->max_video_width) 1160 return DC_FAIL_SURFACE_VALIDATE; 1161 1162 return DC_OK; 1163 } 1164 1165 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1166 { 1167 int i, j; 1168 bool video_down_scaled = false; 1169 bool video_large = false; 1170 bool desktop_large = false; 1171 bool dcc_disabled = false; 1172 bool mpo_enabled = false; 1173 1174 for (i = 0; i < context->stream_count; i++) { 1175 if (context->stream_status[i].plane_count == 0) 1176 continue; 1177 1178 if (context->stream_status[i].plane_count > 2) 1179 return DC_FAIL_UNSUPPORTED_1; 1180 1181 if (context->stream_status[i].plane_count > 1) 1182 mpo_enabled = true; 1183 1184 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1185 struct dc_plane_state *plane = 1186 context->stream_status[i].plane_states[j]; 1187 1188 1189 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1190 1191 if (plane->src_rect.width > plane->dst_rect.width || 1192 plane->src_rect.height > plane->dst_rect.height) 1193 video_down_scaled = true; 1194 1195 if (plane->src_rect.width >= 3840) 1196 video_large = true; 1197 1198 } else { 1199 if (plane->src_rect.width >= 3840) 1200 desktop_large = true; 1201 if (!plane->dcc.enable) 1202 dcc_disabled = true; 1203 } 1204 } 1205 } 1206 1207 /* Disable MPO in multi-display configurations. */ 1208 if (context->stream_count > 1 && mpo_enabled) 1209 return DC_FAIL_UNSUPPORTED_1; 1210 1211 /* 1212 * Workaround: On DCN10 there is UMC issue that causes underflow when 1213 * playing 4k video on 4k desktop with video downscaled and single channel 1214 * memory 1215 */ 1216 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1217 dc->dcn_soc->number_of_channels == 1) 1218 return DC_FAIL_SURFACE_VALIDATE; 1219 1220 return DC_OK; 1221 } 1222 1223 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1224 { 1225 enum surface_pixel_format surf_pix_format = plane_state->format; 1226 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1227 1228 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1229 1230 if (bpp == 64) 1231 swizzle = DC_SW_64KB_D; 1232 else 1233 swizzle = DC_SW_64KB_S; 1234 1235 plane_state->tiling_info.gfx9.swizzle = swizzle; 1236 return DC_OK; 1237 } 1238 1239 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 1240 struct resource_context *res_ctx, 1241 const struct resource_pool *pool, 1242 struct dc_stream_state *stream) 1243 { 1244 int i; 1245 int j = -1; 1246 struct dc_link *link = stream->link; 1247 1248 for (i = 0; i < pool->stream_enc_count; i++) { 1249 if (!res_ctx->is_stream_enc_acquired[i] && 1250 pool->stream_enc[i]) { 1251 /* Store first available for MST second display 1252 * in daisy chain use case 1253 */ 1254 j = i; 1255 if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id == 1256 link->link_enc->preferred_engine) 1257 return pool->stream_enc[i]; 1258 } 1259 } 1260 1261 /* 1262 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1263 */ 1264 1265 if (j >= 0) 1266 return pool->stream_enc[j]; 1267 1268 return NULL; 1269 } 1270 1271 static const struct dc_cap_funcs cap_funcs = { 1272 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1273 }; 1274 1275 static const struct resource_funcs dcn10_res_pool_funcs = { 1276 .destroy = dcn10_destroy_resource_pool, 1277 .link_enc_create = dcn10_link_encoder_create, 1278 .panel_cntl_create = dcn10_panel_cntl_create, 1279 .validate_bandwidth = dcn10_validate_bandwidth, 1280 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1281 .validate_plane = dcn10_validate_plane, 1282 .validate_global = dcn10_validate_global, 1283 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1284 .patch_unknown_plane_state = dcn10_patch_unknown_plane_state, 1285 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 1286 }; 1287 1288 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1289 { 1290 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1291 /* RV1 support max 4 pipes */ 1292 value = value & 0xf; 1293 return value; 1294 } 1295 1296 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) 1297 { 1298 int i; 1299 1300 if (clks->num_levels == 0) 1301 return false; 1302 1303 for (i = 0; i < clks->num_levels; i++) 1304 /* Ensure that the result is sane */ 1305 if (clks->data[i].clocks_in_khz == 0) 1306 return false; 1307 1308 return true; 1309 } 1310 1311 static bool dcn10_resource_construct( 1312 uint8_t num_virtual_links, 1313 struct dc *dc, 1314 struct dcn10_resource_pool *pool) 1315 { 1316 int i; 1317 int j; 1318 struct dc_context *ctx = dc->ctx; 1319 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1320 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; 1321 int min_fclk_khz, min_dcfclk_khz, socclk_khz; 1322 bool res; 1323 1324 ctx->dc_bios->regs = &bios_regs; 1325 1326 if (ctx->dce_version == DCN_VERSION_1_01) 1327 pool->base.res_cap = &rv2_res_cap; 1328 else 1329 pool->base.res_cap = &res_cap; 1330 pool->base.funcs = &dcn10_res_pool_funcs; 1331 1332 /* 1333 * TODO fill in from actual raven resource when we create 1334 * more than virtual encoder 1335 */ 1336 1337 /************************************************* 1338 * Resource + asic cap harcoding * 1339 *************************************************/ 1340 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1341 1342 /* max pipe num for ASIC before check pipe fuses */ 1343 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1344 1345 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1346 pool->base.pipe_count = 3; 1347 dc->caps.max_video_width = 3840; 1348 dc->caps.max_downscale_ratio = 200; 1349 dc->caps.i2c_speed_in_khz = 100; 1350 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 1351 dc->caps.max_cursor_size = 256; 1352 dc->caps.min_horizontal_blanking_period = 80; 1353 dc->caps.max_slave_planes = 1; 1354 dc->caps.max_slave_yuv_planes = 1; 1355 dc->caps.max_slave_rgb_planes = 0; 1356 dc->caps.is_apu = true; 1357 dc->caps.post_blend_color_processing = false; 1358 dc->caps.extended_aux_timeout_support = false; 1359 1360 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1361 dc->caps.force_dp_tps4_for_cp2520 = true; 1362 1363 /* Color pipeline capabilities */ 1364 dc->caps.color.dpp.dcn_arch = 1; 1365 dc->caps.color.dpp.input_lut_shared = 1; 1366 dc->caps.color.dpp.icsc = 1; 1367 dc->caps.color.dpp.dgam_ram = 1; 1368 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1369 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1370 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 1371 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 1372 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 1373 dc->caps.color.dpp.post_csc = 0; 1374 dc->caps.color.dpp.gamma_corr = 0; 1375 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 1376 1377 dc->caps.color.dpp.hw_3d_lut = 0; 1378 dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1 1379 dc->caps.color.dpp.ogam_rom_caps.srgb = 1; 1380 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1; 1381 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1382 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1383 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1384 dc->caps.color.dpp.ocsc = 1; 1385 1386 /* no post-blend color operations */ 1387 dc->caps.color.mpc.gamut_remap = 0; 1388 dc->caps.color.mpc.num_3dluts = 0; 1389 dc->caps.color.mpc.shared_3d_lut = 0; 1390 dc->caps.color.mpc.ogam_ram = 0; 1391 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1392 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1393 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1394 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1395 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1396 dc->caps.color.mpc.ocsc = 0; 1397 1398 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1399 dc->debug = debug_defaults_drv; 1400 else 1401 dc->debug = debug_defaults_diags; 1402 1403 /************************************************* 1404 * Create resources * 1405 *************************************************/ 1406 1407 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1408 dcn10_clock_source_create(ctx, ctx->dc_bios, 1409 CLOCK_SOURCE_COMBO_PHY_PLL0, 1410 &clk_src_regs[0], false); 1411 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1412 dcn10_clock_source_create(ctx, ctx->dc_bios, 1413 CLOCK_SOURCE_COMBO_PHY_PLL1, 1414 &clk_src_regs[1], false); 1415 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1416 dcn10_clock_source_create(ctx, ctx->dc_bios, 1417 CLOCK_SOURCE_COMBO_PHY_PLL2, 1418 &clk_src_regs[2], false); 1419 1420 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1421 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1422 dcn10_clock_source_create(ctx, ctx->dc_bios, 1423 CLOCK_SOURCE_COMBO_PHY_PLL3, 1424 &clk_src_regs[3], false); 1425 } 1426 1427 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1428 1429 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1430 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1431 1432 pool->base.dp_clock_source = 1433 dcn10_clock_source_create(ctx, ctx->dc_bios, 1434 CLOCK_SOURCE_ID_DP_DTO, 1435 /* todo: not reuse phy_pll registers */ 1436 &clk_src_regs[0], true); 1437 1438 for (i = 0; i < pool->base.clk_src_count; i++) { 1439 if (pool->base.clock_sources[i] == NULL) { 1440 dm_error("DC: failed to create clock sources!\n"); 1441 BREAK_TO_DEBUGGER(); 1442 goto fail; 1443 } 1444 } 1445 1446 pool->base.dmcu = dcn10_dmcu_create(ctx, 1447 &dmcu_regs, 1448 &dmcu_shift, 1449 &dmcu_mask); 1450 if (pool->base.dmcu == NULL) { 1451 dm_error("DC: failed to create dmcu!\n"); 1452 BREAK_TO_DEBUGGER(); 1453 goto fail; 1454 } 1455 1456 pool->base.abm = dce_abm_create(ctx, 1457 &abm_regs, 1458 &abm_shift, 1459 &abm_mask); 1460 if (pool->base.abm == NULL) { 1461 dm_error("DC: failed to create abm!\n"); 1462 BREAK_TO_DEBUGGER(); 1463 goto fail; 1464 } 1465 1466 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1467 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1468 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1469 1470 DC_FP_START(); 1471 dcn10_resource_construct_fp(dc); 1472 DC_FP_END(); 1473 1474 if (!dc->config.is_vmin_only_asic) 1475 if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev)) 1476 switch (dc->ctx->asic_id.pci_revision_id) { 1477 case PRID_DALI_DE: 1478 case PRID_DALI_DF: 1479 case PRID_DALI_E3: 1480 case PRID_DALI_E4: 1481 case PRID_POLLOCK_94: 1482 case PRID_POLLOCK_95: 1483 case PRID_POLLOCK_E9: 1484 case PRID_POLLOCK_EA: 1485 case PRID_POLLOCK_EB: 1486 dc->config.is_vmin_only_asic = true; 1487 break; 1488 default: 1489 break; 1490 } 1491 1492 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1493 1494 /* 1495 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * 1496 * implemented. So AZ D3 should work.For issue 197007. * 1497 */ 1498 if (pool->base.pp_smu != NULL 1499 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) 1500 dc->debug.az_endpoint_mute_only = false; 1501 1502 1503 if (!dc->debug.disable_pplib_clock_request) { 1504 /* 1505 * TODO: This is not the proper way to obtain 1506 * fabric_and_dram_bandwidth, should be min(fclk, memclk). 1507 */ 1508 res = dm_pp_get_clock_levels_by_type_with_voltage( 1509 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); 1510 1511 DC_FP_START(); 1512 1513 if (res) 1514 res = verify_clock_values(&fclks); 1515 1516 if (res) 1517 dcn_bw_update_from_pplib_fclks(dc, &fclks); 1518 else 1519 BREAK_TO_DEBUGGER(); 1520 1521 DC_FP_END(); 1522 1523 res = dm_pp_get_clock_levels_by_type_with_voltage( 1524 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); 1525 1526 DC_FP_START(); 1527 1528 if (res) 1529 res = verify_clock_values(&dcfclks); 1530 1531 if (res) 1532 dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks); 1533 else 1534 BREAK_TO_DEBUGGER(); 1535 1536 DC_FP_END(); 1537 } 1538 1539 dcn_bw_sync_calcs_and_dml(dc); 1540 if (!dc->debug.disable_pplib_wm_range) { 1541 dc->res_pool = &pool->base; 1542 DC_FP_START(); 1543 dcn_get_soc_clks( 1544 dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz); 1545 DC_FP_END(); 1546 dcn_bw_notify_pplib_of_wm_ranges( 1547 dc, min_fclk_khz, min_dcfclk_khz, socclk_khz); 1548 } 1549 1550 { 1551 struct irq_service_init_data init_data; 1552 init_data.ctx = dc->ctx; 1553 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1554 if (!pool->base.irqs) 1555 goto fail; 1556 } 1557 1558 /* index to valid pipe resource */ 1559 j = 0; 1560 /* mem input -> ipp -> dpp -> opp -> TG */ 1561 for (i = 0; i < pool->base.pipe_count; i++) { 1562 /* if pipe is disabled, skip instance of HW pipe, 1563 * i.e, skip ASIC register instance 1564 */ 1565 if ((pipe_fuses & (1 << i)) != 0) 1566 continue; 1567 1568 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1569 if (pool->base.hubps[j] == NULL) { 1570 BREAK_TO_DEBUGGER(); 1571 dm_error( 1572 "DC: failed to create memory input!\n"); 1573 goto fail; 1574 } 1575 1576 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1577 if (pool->base.ipps[j] == NULL) { 1578 BREAK_TO_DEBUGGER(); 1579 dm_error( 1580 "DC: failed to create input pixel processor!\n"); 1581 goto fail; 1582 } 1583 1584 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1585 if (pool->base.dpps[j] == NULL) { 1586 BREAK_TO_DEBUGGER(); 1587 dm_error( 1588 "DC: failed to create dpp!\n"); 1589 goto fail; 1590 } 1591 1592 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1593 if (pool->base.opps[j] == NULL) { 1594 BREAK_TO_DEBUGGER(); 1595 dm_error( 1596 "DC: failed to create output pixel processor!\n"); 1597 goto fail; 1598 } 1599 1600 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1601 ctx, i); 1602 if (pool->base.timing_generators[j] == NULL) { 1603 BREAK_TO_DEBUGGER(); 1604 dm_error("DC: failed to create tg!\n"); 1605 goto fail; 1606 } 1607 /* check next valid pipe */ 1608 j++; 1609 } 1610 1611 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1612 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1613 if (pool->base.engines[i] == NULL) { 1614 BREAK_TO_DEBUGGER(); 1615 dm_error( 1616 "DC:failed to create aux engine!!\n"); 1617 goto fail; 1618 } 1619 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1620 if (pool->base.hw_i2cs[i] == NULL) { 1621 BREAK_TO_DEBUGGER(); 1622 dm_error( 1623 "DC:failed to create hw i2c!!\n"); 1624 goto fail; 1625 } 1626 pool->base.sw_i2cs[i] = NULL; 1627 } 1628 1629 /* valid pipe num */ 1630 pool->base.pipe_count = j; 1631 pool->base.timing_generator_count = j; 1632 1633 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1634 * the value may be changed 1635 */ 1636 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1637 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1638 1639 pool->base.mpc = dcn10_mpc_create(ctx); 1640 if (pool->base.mpc == NULL) { 1641 BREAK_TO_DEBUGGER(); 1642 dm_error("DC: failed to create mpc!\n"); 1643 goto fail; 1644 } 1645 1646 pool->base.hubbub = dcn10_hubbub_create(ctx); 1647 if (pool->base.hubbub == NULL) { 1648 BREAK_TO_DEBUGGER(); 1649 dm_error("DC: failed to create hubbub!\n"); 1650 goto fail; 1651 } 1652 1653 if (!resource_construct(num_virtual_links, dc, &pool->base, 1654 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1655 &res_create_funcs : &res_create_maximus_funcs))) 1656 goto fail; 1657 1658 dcn10_hw_sequencer_construct(dc); 1659 dc->caps.max_planes = pool->base.pipe_count; 1660 1661 for (i = 0; i < dc->caps.max_planes; ++i) 1662 dc->caps.planes[i] = plane_cap; 1663 1664 dc->cap_funcs = cap_funcs; 1665 1666 return true; 1667 1668 fail: 1669 1670 dcn10_resource_destruct(pool); 1671 1672 return false; 1673 } 1674 1675 struct resource_pool *dcn10_create_resource_pool( 1676 const struct dc_init_data *init_data, 1677 struct dc *dc) 1678 { 1679 struct dcn10_resource_pool *pool = 1680 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1681 1682 if (!pool) 1683 return NULL; 1684 1685 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool)) 1686 return &pool->base; 1687 1688 kfree(pool); 1689 BREAK_TO_DEBUGGER(); 1690 return NULL; 1691 } 1692