1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn10_resource.h" 32 33 #include "dcn10_ipp.h" 34 #include "dcn10_mpc.h" 35 #include "irq/dcn10/irq_service_dcn10.h" 36 #include "dcn10_dpp.h" 37 #include "dcn10_optc.h" 38 #include "dcn10_hw_sequencer.h" 39 #include "dce110/dce110_hw_sequencer.h" 40 #include "dcn10_opp.h" 41 #include "dcn10_link_encoder.h" 42 #include "dcn10_stream_encoder.h" 43 #include "dcn10_clk_mgr.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs_luma = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 157 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 158 #endif 159 }; 160 161 /* begin ********************* 162 * macros to expend register list macro defined in HW object header file */ 163 164 /* DCN */ 165 #define BASE_INNER(seg) \ 166 DCE_BASE__INST0_SEG ## seg 167 168 #define BASE(seg) \ 169 BASE_INNER(seg) 170 171 #define SR(reg_name)\ 172 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 173 mm ## reg_name 174 175 #define SRI(reg_name, block, id)\ 176 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 mm ## block ## id ## _ ## reg_name 178 179 180 #define SRII(reg_name, block, id)\ 181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 mm ## block ## id ## _ ## reg_name 183 184 /* NBIO */ 185 #define NBIO_BASE_INNER(seg) \ 186 NBIF_BASE__INST0_SEG ## seg 187 188 #define NBIO_BASE(seg) \ 189 NBIO_BASE_INNER(seg) 190 191 #define NBIO_SR(reg_name)\ 192 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 193 mm ## reg_name 194 195 /* MMHUB */ 196 #define MMHUB_BASE_INNER(seg) \ 197 MMHUB_BASE__INST0_SEG ## seg 198 199 #define MMHUB_BASE(seg) \ 200 MMHUB_BASE_INNER(seg) 201 202 #define MMHUB_SR(reg_name)\ 203 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 204 mm ## reg_name 205 /* macros to expend register list macro defined in HW object header file 206 * end *********************/ 207 208 209 static const struct dce_dmcu_registers dmcu_regs = { 210 DMCU_DCN10_REG_LIST() 211 }; 212 213 static const struct dce_dmcu_shift dmcu_shift = { 214 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 215 }; 216 217 static const struct dce_dmcu_mask dmcu_mask = { 218 DMCU_MASK_SH_LIST_DCN10(_MASK) 219 }; 220 221 static const struct dce_abm_registers abm_regs = { 222 ABM_DCN10_REG_LIST(0) 223 }; 224 225 static const struct dce_abm_shift abm_shift = { 226 ABM_MASK_SH_LIST_DCN10(__SHIFT) 227 }; 228 229 static const struct dce_abm_mask abm_mask = { 230 ABM_MASK_SH_LIST_DCN10(_MASK) 231 }; 232 233 #define stream_enc_regs(id)\ 234 [id] = {\ 235 SE_DCN_REG_LIST(id)\ 236 } 237 238 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 239 stream_enc_regs(0), 240 stream_enc_regs(1), 241 stream_enc_regs(2), 242 stream_enc_regs(3), 243 }; 244 245 static const struct dcn10_stream_encoder_shift se_shift = { 246 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 247 }; 248 249 static const struct dcn10_stream_encoder_mask se_mask = { 250 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 251 }; 252 253 #define audio_regs(id)\ 254 [id] = {\ 255 AUD_COMMON_REG_LIST(id)\ 256 } 257 258 static const struct dce_audio_registers audio_regs[] = { 259 audio_regs(0), 260 audio_regs(1), 261 audio_regs(2), 262 audio_regs(3), 263 }; 264 265 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 266 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 267 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 268 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 269 270 static const struct dce_audio_shift audio_shift = { 271 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dce_aduio_mask audio_mask = { 275 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 276 }; 277 278 #define aux_regs(id)\ 279 [id] = {\ 280 AUX_REG_LIST(id)\ 281 } 282 283 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 284 aux_regs(0), 285 aux_regs(1), 286 aux_regs(2), 287 aux_regs(3) 288 }; 289 290 #define hpd_regs(id)\ 291 [id] = {\ 292 HPD_REG_LIST(id)\ 293 } 294 295 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 296 hpd_regs(0), 297 hpd_regs(1), 298 hpd_regs(2), 299 hpd_regs(3) 300 }; 301 302 #define link_regs(id)\ 303 [id] = {\ 304 LE_DCN10_REG_LIST(id), \ 305 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 306 } 307 308 static const struct dcn10_link_enc_registers link_enc_regs[] = { 309 link_regs(0), 310 link_regs(1), 311 link_regs(2), 312 link_regs(3) 313 }; 314 315 static const struct dcn10_link_enc_shift le_shift = { 316 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 317 }; 318 319 static const struct dcn10_link_enc_mask le_mask = { 320 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 321 }; 322 323 #define ipp_regs(id)\ 324 [id] = {\ 325 IPP_REG_LIST_DCN10(id),\ 326 } 327 328 static const struct dcn10_ipp_registers ipp_regs[] = { 329 ipp_regs(0), 330 ipp_regs(1), 331 ipp_regs(2), 332 ipp_regs(3), 333 }; 334 335 static const struct dcn10_ipp_shift ipp_shift = { 336 IPP_MASK_SH_LIST_DCN10(__SHIFT) 337 }; 338 339 static const struct dcn10_ipp_mask ipp_mask = { 340 IPP_MASK_SH_LIST_DCN10(_MASK), 341 }; 342 343 #define opp_regs(id)\ 344 [id] = {\ 345 OPP_REG_LIST_DCN10(id),\ 346 } 347 348 static const struct dcn10_opp_registers opp_regs[] = { 349 opp_regs(0), 350 opp_regs(1), 351 opp_regs(2), 352 opp_regs(3), 353 }; 354 355 static const struct dcn10_opp_shift opp_shift = { 356 OPP_MASK_SH_LIST_DCN10(__SHIFT) 357 }; 358 359 static const struct dcn10_opp_mask opp_mask = { 360 OPP_MASK_SH_LIST_DCN10(_MASK), 361 }; 362 363 #define aux_engine_regs(id)\ 364 [id] = {\ 365 AUX_COMMON_REG_LIST(id), \ 366 .AUX_RESET_MASK = 0 \ 367 } 368 369 static const struct dce110_aux_registers aux_engine_regs[] = { 370 aux_engine_regs(0), 371 aux_engine_regs(1), 372 aux_engine_regs(2), 373 aux_engine_regs(3), 374 aux_engine_regs(4), 375 aux_engine_regs(5) 376 }; 377 378 #define tf_regs(id)\ 379 [id] = {\ 380 TF_REG_LIST_DCN10(id),\ 381 } 382 383 static const struct dcn_dpp_registers tf_regs[] = { 384 tf_regs(0), 385 tf_regs(1), 386 tf_regs(2), 387 tf_regs(3), 388 }; 389 390 static const struct dcn_dpp_shift tf_shift = { 391 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 392 TF_DEBUG_REG_LIST_SH_DCN10 393 394 }; 395 396 static const struct dcn_dpp_mask tf_mask = { 397 TF_REG_LIST_SH_MASK_DCN10(_MASK), 398 TF_DEBUG_REG_LIST_MASK_DCN10 399 }; 400 401 static const struct dcn_mpc_registers mpc_regs = { 402 MPC_COMMON_REG_LIST_DCN1_0(0), 403 MPC_COMMON_REG_LIST_DCN1_0(1), 404 MPC_COMMON_REG_LIST_DCN1_0(2), 405 MPC_COMMON_REG_LIST_DCN1_0(3), 406 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 407 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 408 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 409 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 410 }; 411 412 static const struct dcn_mpc_shift mpc_shift = { 413 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 414 }; 415 416 static const struct dcn_mpc_mask mpc_mask = { 417 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 418 }; 419 420 #define tg_regs(id)\ 421 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 422 423 static const struct dcn_optc_registers tg_regs[] = { 424 tg_regs(0), 425 tg_regs(1), 426 tg_regs(2), 427 tg_regs(3), 428 }; 429 430 static const struct dcn_optc_shift tg_shift = { 431 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 432 }; 433 434 static const struct dcn_optc_mask tg_mask = { 435 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 436 }; 437 438 static const struct bios_registers bios_regs = { 439 NBIO_SR(BIOS_SCRATCH_3), 440 NBIO_SR(BIOS_SCRATCH_6) 441 }; 442 443 #define hubp_regs(id)\ 444 [id] = {\ 445 HUBP_REG_LIST_DCN10(id)\ 446 } 447 448 449 static const struct dcn_mi_registers hubp_regs[] = { 450 hubp_regs(0), 451 hubp_regs(1), 452 hubp_regs(2), 453 hubp_regs(3), 454 }; 455 456 static const struct dcn_mi_shift hubp_shift = { 457 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 458 }; 459 460 static const struct dcn_mi_mask hubp_mask = { 461 HUBP_MASK_SH_LIST_DCN10(_MASK) 462 }; 463 464 465 static const struct dcn_hubbub_registers hubbub_reg = { 466 HUBBUB_REG_LIST_DCN10(0) 467 }; 468 469 static const struct dcn_hubbub_shift hubbub_shift = { 470 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 471 }; 472 473 static const struct dcn_hubbub_mask hubbub_mask = { 474 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 475 }; 476 477 #define clk_src_regs(index, pllid)\ 478 [index] = {\ 479 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 480 } 481 482 static const struct dce110_clk_src_regs clk_src_regs[] = { 483 clk_src_regs(0, A), 484 clk_src_regs(1, B), 485 clk_src_regs(2, C), 486 clk_src_regs(3, D) 487 }; 488 489 static const struct dce110_clk_src_shift cs_shift = { 490 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 491 }; 492 493 static const struct dce110_clk_src_mask cs_mask = { 494 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 495 }; 496 497 static const struct resource_caps res_cap = { 498 .num_timing_generator = 4, 499 .num_opp = 4, 500 .num_video_plane = 4, 501 .num_audio = 4, 502 .num_stream_encoder = 4, 503 .num_pll = 4, 504 .num_ddc = 4, 505 }; 506 507 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 508 static const struct resource_caps rv2_res_cap = { 509 .num_timing_generator = 3, 510 .num_opp = 3, 511 .num_video_plane = 3, 512 .num_audio = 3, 513 .num_stream_encoder = 3, 514 .num_pll = 3, 515 .num_ddc = 3, 516 }; 517 #endif 518 519 static const struct dc_debug_options debug_defaults_drv = { 520 .sanity_checks = true, 521 .disable_dmcu = true, 522 .force_abm_enable = false, 523 .timing_trace = false, 524 .clock_trace = true, 525 526 /* raven smu dones't allow 0 disp clk, 527 * smu min disp clk limit is 50Mhz 528 * keep min disp clk 100Mhz avoid smu hang 529 */ 530 .min_disp_clk_khz = 100000, 531 532 .disable_pplib_clock_request = false, 533 .disable_pplib_wm_range = false, 534 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 535 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 536 .force_single_disp_pipe_split = true, 537 .disable_dcc = DCC_ENABLE, 538 .voltage_align_fclk = true, 539 .disable_stereo_support = true, 540 .vsr_support = true, 541 .performance_trace = false, 542 .az_endpoint_mute_only = true, 543 .recovery_enabled = false, /*enable this by default after testing.*/ 544 .max_downscale_src_width = 3840, 545 }; 546 547 static const struct dc_debug_options debug_defaults_diags = { 548 .disable_dmcu = true, 549 .force_abm_enable = false, 550 .timing_trace = true, 551 .clock_trace = true, 552 .disable_stutter = true, 553 .disable_pplib_clock_request = true, 554 .disable_pplib_wm_range = true 555 }; 556 557 static void dcn10_dpp_destroy(struct dpp **dpp) 558 { 559 kfree(TO_DCN10_DPP(*dpp)); 560 *dpp = NULL; 561 } 562 563 static struct dpp *dcn10_dpp_create( 564 struct dc_context *ctx, 565 uint32_t inst) 566 { 567 struct dcn10_dpp *dpp = 568 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 569 570 if (!dpp) 571 return NULL; 572 573 dpp1_construct(dpp, ctx, inst, 574 &tf_regs[inst], &tf_shift, &tf_mask); 575 return &dpp->base; 576 } 577 578 static struct input_pixel_processor *dcn10_ipp_create( 579 struct dc_context *ctx, uint32_t inst) 580 { 581 struct dcn10_ipp *ipp = 582 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 583 584 if (!ipp) { 585 BREAK_TO_DEBUGGER(); 586 return NULL; 587 } 588 589 dcn10_ipp_construct(ipp, ctx, inst, 590 &ipp_regs[inst], &ipp_shift, &ipp_mask); 591 return &ipp->base; 592 } 593 594 595 static struct output_pixel_processor *dcn10_opp_create( 596 struct dc_context *ctx, uint32_t inst) 597 { 598 struct dcn10_opp *opp = 599 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 600 601 if (!opp) { 602 BREAK_TO_DEBUGGER(); 603 return NULL; 604 } 605 606 dcn10_opp_construct(opp, ctx, inst, 607 &opp_regs[inst], &opp_shift, &opp_mask); 608 return &opp->base; 609 } 610 611 struct dce_aux *dcn10_aux_engine_create( 612 struct dc_context *ctx, 613 uint32_t inst) 614 { 615 struct aux_engine_dce110 *aux_engine = 616 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 617 618 if (!aux_engine) 619 return NULL; 620 621 dce110_aux_engine_construct(aux_engine, ctx, inst, 622 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 623 &aux_engine_regs[inst]); 624 625 return &aux_engine->base; 626 } 627 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 628 629 static const struct dce_i2c_registers i2c_hw_regs[] = { 630 i2c_inst_regs(1), 631 i2c_inst_regs(2), 632 i2c_inst_regs(3), 633 i2c_inst_regs(4), 634 i2c_inst_regs(5), 635 i2c_inst_regs(6), 636 }; 637 638 static const struct dce_i2c_shift i2c_shifts = { 639 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 640 }; 641 642 static const struct dce_i2c_mask i2c_masks = { 643 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 644 }; 645 646 struct dce_i2c_hw *dcn10_i2c_hw_create( 647 struct dc_context *ctx, 648 uint32_t inst) 649 { 650 struct dce_i2c_hw *dce_i2c_hw = 651 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 652 653 if (!dce_i2c_hw) 654 return NULL; 655 656 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 657 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 658 659 return dce_i2c_hw; 660 } 661 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 662 { 663 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 664 GFP_KERNEL); 665 666 if (!mpc10) 667 return NULL; 668 669 dcn10_mpc_construct(mpc10, ctx, 670 &mpc_regs, 671 &mpc_shift, 672 &mpc_mask, 673 4); 674 675 return &mpc10->base; 676 } 677 678 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 679 { 680 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 681 GFP_KERNEL); 682 683 if (!dcn10_hubbub) 684 return NULL; 685 686 hubbub1_construct(&dcn10_hubbub->base, ctx, 687 &hubbub_reg, 688 &hubbub_shift, 689 &hubbub_mask); 690 691 return &dcn10_hubbub->base; 692 } 693 694 static struct timing_generator *dcn10_timing_generator_create( 695 struct dc_context *ctx, 696 uint32_t instance) 697 { 698 struct optc *tgn10 = 699 kzalloc(sizeof(struct optc), GFP_KERNEL); 700 701 if (!tgn10) 702 return NULL; 703 704 tgn10->base.inst = instance; 705 tgn10->base.ctx = ctx; 706 707 tgn10->tg_regs = &tg_regs[instance]; 708 tgn10->tg_shift = &tg_shift; 709 tgn10->tg_mask = &tg_mask; 710 711 dcn10_timing_generator_init(tgn10); 712 713 return &tgn10->base; 714 } 715 716 static const struct encoder_feature_support link_enc_feature = { 717 .max_hdmi_deep_color = COLOR_DEPTH_121212, 718 .max_hdmi_pixel_clock = 600000, 719 .hdmi_ycbcr420_supported = true, 720 .dp_ycbcr420_supported = false, 721 .flags.bits.IS_HBR2_CAPABLE = true, 722 .flags.bits.IS_HBR3_CAPABLE = true, 723 .flags.bits.IS_TPS3_CAPABLE = true, 724 .flags.bits.IS_TPS4_CAPABLE = true 725 }; 726 727 struct link_encoder *dcn10_link_encoder_create( 728 const struct encoder_init_data *enc_init_data) 729 { 730 struct dcn10_link_encoder *enc10 = 731 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 732 733 if (!enc10) 734 return NULL; 735 736 dcn10_link_encoder_construct(enc10, 737 enc_init_data, 738 &link_enc_feature, 739 &link_enc_regs[enc_init_data->transmitter], 740 &link_enc_aux_regs[enc_init_data->channel - 1], 741 &link_enc_hpd_regs[enc_init_data->hpd_source], 742 &le_shift, 743 &le_mask); 744 745 return &enc10->base; 746 } 747 748 struct clock_source *dcn10_clock_source_create( 749 struct dc_context *ctx, 750 struct dc_bios *bios, 751 enum clock_source_id id, 752 const struct dce110_clk_src_regs *regs, 753 bool dp_clk_src) 754 { 755 struct dce110_clk_src *clk_src = 756 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 757 758 if (!clk_src) 759 return NULL; 760 761 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 762 regs, &cs_shift, &cs_mask)) { 763 clk_src->base.dp_clk_src = dp_clk_src; 764 return &clk_src->base; 765 } 766 767 BREAK_TO_DEBUGGER(); 768 return NULL; 769 } 770 771 static void read_dce_straps( 772 struct dc_context *ctx, 773 struct resource_straps *straps) 774 { 775 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 776 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 777 } 778 779 static struct audio *create_audio( 780 struct dc_context *ctx, unsigned int inst) 781 { 782 return dce_audio_create(ctx, inst, 783 &audio_regs[inst], &audio_shift, &audio_mask); 784 } 785 786 static struct stream_encoder *dcn10_stream_encoder_create( 787 enum engine_id eng_id, 788 struct dc_context *ctx) 789 { 790 struct dcn10_stream_encoder *enc1 = 791 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 792 793 if (!enc1) 794 return NULL; 795 796 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 797 &stream_enc_regs[eng_id], 798 &se_shift, &se_mask); 799 return &enc1->base; 800 } 801 802 static const struct dce_hwseq_registers hwseq_reg = { 803 HWSEQ_DCN1_REG_LIST() 804 }; 805 806 static const struct dce_hwseq_shift hwseq_shift = { 807 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 808 }; 809 810 static const struct dce_hwseq_mask hwseq_mask = { 811 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 812 }; 813 814 static struct dce_hwseq *dcn10_hwseq_create( 815 struct dc_context *ctx) 816 { 817 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 818 819 if (hws) { 820 hws->ctx = ctx; 821 hws->regs = &hwseq_reg; 822 hws->shifts = &hwseq_shift; 823 hws->masks = &hwseq_mask; 824 hws->wa.DEGVIDCN10_253 = true; 825 hws->wa.false_optc_underflow = true; 826 hws->wa.DEGVIDCN10_254 = true; 827 } 828 return hws; 829 } 830 831 static const struct resource_create_funcs res_create_funcs = { 832 .read_dce_straps = read_dce_straps, 833 .create_audio = create_audio, 834 .create_stream_encoder = dcn10_stream_encoder_create, 835 .create_hwseq = dcn10_hwseq_create, 836 }; 837 838 static const struct resource_create_funcs res_create_maximus_funcs = { 839 .read_dce_straps = NULL, 840 .create_audio = NULL, 841 .create_stream_encoder = NULL, 842 .create_hwseq = dcn10_hwseq_create, 843 }; 844 845 void dcn10_clock_source_destroy(struct clock_source **clk_src) 846 { 847 kfree(TO_DCE110_CLK_SRC(*clk_src)); 848 *clk_src = NULL; 849 } 850 851 static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) 852 { 853 struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 854 855 if (!pp_smu) 856 return pp_smu; 857 858 dm_pp_get_funcs_rv(ctx, pp_smu); 859 return pp_smu; 860 } 861 862 static void destruct(struct dcn10_resource_pool *pool) 863 { 864 unsigned int i; 865 866 for (i = 0; i < pool->base.stream_enc_count; i++) { 867 if (pool->base.stream_enc[i] != NULL) { 868 /* TODO: free dcn version of stream encoder once implemented 869 * rather than using virtual stream encoder 870 */ 871 kfree(pool->base.stream_enc[i]); 872 pool->base.stream_enc[i] = NULL; 873 } 874 } 875 876 if (pool->base.mpc != NULL) { 877 kfree(TO_DCN10_MPC(pool->base.mpc)); 878 pool->base.mpc = NULL; 879 } 880 881 if (pool->base.hubbub != NULL) { 882 kfree(pool->base.hubbub); 883 pool->base.hubbub = NULL; 884 } 885 886 for (i = 0; i < pool->base.pipe_count; i++) { 887 if (pool->base.opps[i] != NULL) 888 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 889 890 if (pool->base.dpps[i] != NULL) 891 dcn10_dpp_destroy(&pool->base.dpps[i]); 892 893 if (pool->base.ipps[i] != NULL) 894 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 895 896 if (pool->base.hubps[i] != NULL) { 897 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 898 pool->base.hubps[i] = NULL; 899 } 900 901 if (pool->base.irqs != NULL) { 902 dal_irq_service_destroy(&pool->base.irqs); 903 } 904 905 if (pool->base.timing_generators[i] != NULL) { 906 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 907 pool->base.timing_generators[i] = NULL; 908 } 909 } 910 911 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 912 if (pool->base.engines[i] != NULL) 913 dce110_engine_destroy(&pool->base.engines[i]); 914 if (pool->base.hw_i2cs[i] != NULL) { 915 kfree(pool->base.hw_i2cs[i]); 916 pool->base.hw_i2cs[i] = NULL; 917 } 918 if (pool->base.sw_i2cs[i] != NULL) { 919 kfree(pool->base.sw_i2cs[i]); 920 pool->base.sw_i2cs[i] = NULL; 921 } 922 } 923 924 for (i = 0; i < pool->base.stream_enc_count; i++) 925 kfree(pool->base.stream_enc[i]); 926 927 for (i = 0; i < pool->base.audio_count; i++) { 928 if (pool->base.audios[i]) 929 dce_aud_destroy(&pool->base.audios[i]); 930 } 931 932 for (i = 0; i < pool->base.clk_src_count; i++) { 933 if (pool->base.clock_sources[i] != NULL) { 934 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 935 pool->base.clock_sources[i] = NULL; 936 } 937 } 938 939 if (pool->base.dp_clock_source != NULL) { 940 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 941 pool->base.dp_clock_source = NULL; 942 } 943 944 if (pool->base.abm != NULL) 945 dce_abm_destroy(&pool->base.abm); 946 947 if (pool->base.dmcu != NULL) 948 dce_dmcu_destroy(&pool->base.dmcu); 949 950 if (pool->base.clk_mgr != NULL) 951 dce_clk_mgr_destroy(&pool->base.clk_mgr); 952 953 kfree(pool->base.pp_smu); 954 } 955 956 static struct hubp *dcn10_hubp_create( 957 struct dc_context *ctx, 958 uint32_t inst) 959 { 960 struct dcn10_hubp *hubp1 = 961 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 962 963 if (!hubp1) 964 return NULL; 965 966 dcn10_hubp_construct(hubp1, ctx, inst, 967 &hubp_regs[inst], &hubp_shift, &hubp_mask); 968 return &hubp1->base; 969 } 970 971 static void get_pixel_clock_parameters( 972 const struct pipe_ctx *pipe_ctx, 973 struct pixel_clk_params *pixel_clk_params) 974 { 975 const struct dc_stream_state *stream = pipe_ctx->stream; 976 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 977 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 978 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 979 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 980 /* TODO: un-hardcode*/ 981 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 982 LINK_RATE_REF_FREQ_IN_KHZ; 983 pixel_clk_params->flags.ENABLE_SS = 0; 984 pixel_clk_params->color_depth = 985 stream->timing.display_color_depth; 986 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 987 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 988 989 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 990 pixel_clk_params->color_depth = COLOR_DEPTH_888; 991 992 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 993 pixel_clk_params->requested_pix_clk_100hz /= 2; 994 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 995 pixel_clk_params->requested_pix_clk_100hz *= 2; 996 997 } 998 999 static void build_clamping_params(struct dc_stream_state *stream) 1000 { 1001 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1002 stream->clamping.c_depth = stream->timing.display_color_depth; 1003 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1004 } 1005 1006 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1007 { 1008 1009 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1010 1011 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1012 pipe_ctx->clock_source, 1013 &pipe_ctx->stream_res.pix_clk_params, 1014 &pipe_ctx->pll_settings); 1015 1016 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1017 1018 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1019 &pipe_ctx->stream->bit_depth_params); 1020 build_clamping_params(pipe_ctx->stream); 1021 } 1022 1023 static enum dc_status build_mapped_resource( 1024 const struct dc *dc, 1025 struct dc_state *context, 1026 struct dc_stream_state *stream) 1027 { 1028 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1029 1030 /*TODO Seems unneeded anymore */ 1031 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1032 if (stream != NULL && old_context->streams[i] != NULL) { 1033 todo: shouldn't have to copy missing parameter here 1034 resource_build_bit_depth_reduction_params(stream, 1035 &stream->bit_depth_params); 1036 stream->clamping.pixel_encoding = 1037 stream->timing.pixel_encoding; 1038 1039 resource_build_bit_depth_reduction_params(stream, 1040 &stream->bit_depth_params); 1041 build_clamping_params(stream); 1042 1043 continue; 1044 } 1045 } 1046 */ 1047 1048 if (!pipe_ctx) 1049 return DC_ERROR_UNEXPECTED; 1050 1051 build_pipe_hw_param(pipe_ctx); 1052 return DC_OK; 1053 } 1054 1055 enum dc_status dcn10_add_stream_to_ctx( 1056 struct dc *dc, 1057 struct dc_state *new_ctx, 1058 struct dc_stream_state *dc_stream) 1059 { 1060 enum dc_status result = DC_ERROR_UNEXPECTED; 1061 1062 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1063 1064 if (result == DC_OK) 1065 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1066 1067 1068 if (result == DC_OK) 1069 result = build_mapped_resource(dc, new_ctx, dc_stream); 1070 1071 return result; 1072 } 1073 1074 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1075 struct dc_state *context, 1076 const struct resource_pool *pool, 1077 struct dc_stream_state *stream) 1078 { 1079 struct resource_context *res_ctx = &context->res_ctx; 1080 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1081 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool); 1082 1083 if (!head_pipe) { 1084 ASSERT(0); 1085 return NULL; 1086 } 1087 1088 if (!idle_pipe) 1089 return NULL; 1090 1091 idle_pipe->stream = head_pipe->stream; 1092 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1093 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1094 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1095 1096 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1097 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1098 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1099 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1100 1101 return idle_pipe; 1102 } 1103 1104 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1105 const struct dc_dcc_surface_param *input, 1106 struct dc_surface_dcc_cap *output) 1107 { 1108 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1109 dc->res_pool->hubbub, 1110 input, 1111 output); 1112 } 1113 1114 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1115 { 1116 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1117 1118 destruct(dcn10_pool); 1119 kfree(dcn10_pool); 1120 *pool = NULL; 1121 } 1122 1123 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1124 { 1125 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1126 && caps->max_video_width != 0 1127 && plane_state->src_rect.width > caps->max_video_width) 1128 return DC_FAIL_SURFACE_VALIDATE; 1129 1130 return DC_OK; 1131 } 1132 1133 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1134 { 1135 int i, j; 1136 bool video_down_scaled = false; 1137 bool video_large = false; 1138 bool desktop_large = false; 1139 bool dcc_disabled = false; 1140 1141 for (i = 0; i < context->stream_count; i++) { 1142 if (context->stream_status[i].plane_count == 0) 1143 continue; 1144 1145 if (context->stream_status[i].plane_count > 2) 1146 return false; 1147 1148 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1149 struct dc_plane_state *plane = 1150 context->stream_status[i].plane_states[j]; 1151 1152 1153 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1154 1155 if (plane->src_rect.width > plane->dst_rect.width || 1156 plane->src_rect.height > plane->dst_rect.height) 1157 video_down_scaled = true; 1158 1159 if (plane->src_rect.width >= 3840) 1160 video_large = true; 1161 1162 } else { 1163 if (plane->src_rect.width >= 3840) 1164 desktop_large = true; 1165 if (!plane->dcc.enable) 1166 dcc_disabled = true; 1167 } 1168 } 1169 } 1170 1171 /* 1172 * Workaround: On DCN10 there is UMC issue that causes underflow when 1173 * playing 4k video on 4k desktop with video downscaled and single channel 1174 * memory 1175 */ 1176 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1177 dc->dcn_soc->number_of_channels == 1) 1178 return DC_FAIL_SURFACE_VALIDATE; 1179 1180 return DC_OK; 1181 } 1182 1183 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1184 { 1185 enum dc_status result = DC_OK; 1186 1187 enum surface_pixel_format surf_pix_format = plane_state->format; 1188 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1189 1190 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1191 1192 if (bpp == 64) 1193 swizzle = DC_SW_64KB_D; 1194 else 1195 swizzle = DC_SW_64KB_S; 1196 1197 plane_state->tiling_info.gfx9.swizzle = swizzle; 1198 return result; 1199 } 1200 1201 static const struct dc_cap_funcs cap_funcs = { 1202 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1203 }; 1204 1205 static const struct resource_funcs dcn10_res_pool_funcs = { 1206 .destroy = dcn10_destroy_resource_pool, 1207 .link_enc_create = dcn10_link_encoder_create, 1208 .validate_bandwidth = dcn_validate_bandwidth, 1209 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1210 .validate_plane = dcn10_validate_plane, 1211 .validate_global = dcn10_validate_global, 1212 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1213 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode 1214 }; 1215 1216 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1217 { 1218 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1219 /* RV1 support max 4 pipes */ 1220 value = value & 0xf; 1221 return value; 1222 } 1223 1224 static bool construct( 1225 uint8_t num_virtual_links, 1226 struct dc *dc, 1227 struct dcn10_resource_pool *pool) 1228 { 1229 int i; 1230 int j; 1231 struct dc_context *ctx = dc->ctx; 1232 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1233 1234 ctx->dc_bios->regs = &bios_regs; 1235 1236 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1237 if (ctx->dce_version == DCN_VERSION_1_01) 1238 pool->base.res_cap = &rv2_res_cap; 1239 else 1240 #endif 1241 pool->base.res_cap = &res_cap; 1242 pool->base.funcs = &dcn10_res_pool_funcs; 1243 1244 /* 1245 * TODO fill in from actual raven resource when we create 1246 * more than virtual encoder 1247 */ 1248 1249 /************************************************* 1250 * Resource + asic cap harcoding * 1251 *************************************************/ 1252 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1253 1254 /* max pipe num for ASIC before check pipe fuses */ 1255 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1256 1257 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1258 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1259 pool->base.pipe_count = 3; 1260 #endif 1261 dc->caps.max_video_width = 3840; 1262 dc->caps.max_downscale_ratio = 200; 1263 dc->caps.i2c_speed_in_khz = 100; 1264 dc->caps.max_cursor_size = 256; 1265 dc->caps.max_slave_planes = 1; 1266 dc->caps.is_apu = true; 1267 dc->caps.post_blend_color_processing = false; 1268 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1269 dc->caps.force_dp_tps4_for_cp2520 = true; 1270 1271 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1272 dc->debug = debug_defaults_drv; 1273 else 1274 dc->debug = debug_defaults_diags; 1275 1276 /************************************************* 1277 * Create resources * 1278 *************************************************/ 1279 1280 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1281 dcn10_clock_source_create(ctx, ctx->dc_bios, 1282 CLOCK_SOURCE_COMBO_PHY_PLL0, 1283 &clk_src_regs[0], false); 1284 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1285 dcn10_clock_source_create(ctx, ctx->dc_bios, 1286 CLOCK_SOURCE_COMBO_PHY_PLL1, 1287 &clk_src_regs[1], false); 1288 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1289 dcn10_clock_source_create(ctx, ctx->dc_bios, 1290 CLOCK_SOURCE_COMBO_PHY_PLL2, 1291 &clk_src_regs[2], false); 1292 1293 #ifdef CONFIG_DRM_AMD_DC_DCN1_01 1294 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1295 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1296 dcn10_clock_source_create(ctx, ctx->dc_bios, 1297 CLOCK_SOURCE_COMBO_PHY_PLL3, 1298 &clk_src_regs[3], false); 1299 } 1300 #else 1301 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1302 dcn10_clock_source_create(ctx, ctx->dc_bios, 1303 CLOCK_SOURCE_COMBO_PHY_PLL3, 1304 &clk_src_regs[3], false); 1305 #endif 1306 1307 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1308 1309 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1310 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1311 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1312 #endif 1313 1314 pool->base.dp_clock_source = 1315 dcn10_clock_source_create(ctx, ctx->dc_bios, 1316 CLOCK_SOURCE_ID_DP_DTO, 1317 /* todo: not reuse phy_pll registers */ 1318 &clk_src_regs[0], true); 1319 1320 for (i = 0; i < pool->base.clk_src_count; i++) { 1321 if (pool->base.clock_sources[i] == NULL) { 1322 dm_error("DC: failed to create clock sources!\n"); 1323 BREAK_TO_DEBUGGER(); 1324 goto fail; 1325 } 1326 } 1327 pool->base.clk_mgr = dcn1_clk_mgr_create(ctx); 1328 if (pool->base.clk_mgr == NULL) { 1329 dm_error("DC: failed to create display clock!\n"); 1330 BREAK_TO_DEBUGGER(); 1331 goto fail; 1332 } 1333 1334 pool->base.dmcu = dcn10_dmcu_create(ctx, 1335 &dmcu_regs, 1336 &dmcu_shift, 1337 &dmcu_mask); 1338 if (pool->base.dmcu == NULL) { 1339 dm_error("DC: failed to create dmcu!\n"); 1340 BREAK_TO_DEBUGGER(); 1341 goto fail; 1342 } 1343 1344 pool->base.abm = dce_abm_create(ctx, 1345 &abm_regs, 1346 &abm_shift, 1347 &abm_mask); 1348 if (pool->base.abm == NULL) { 1349 dm_error("DC: failed to create abm!\n"); 1350 BREAK_TO_DEBUGGER(); 1351 goto fail; 1352 } 1353 1354 dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1); 1355 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1356 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1357 1358 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1359 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1360 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1361 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1362 struct display_mode_lib *dml = &dc->dml; 1363 1364 dml->ip.max_num_dpp = 3; 1365 /* TODO how to handle 23.84? */ 1366 dcn_soc->dram_clock_change_latency = 23; 1367 dcn_ip->max_num_dpp = 3; 1368 } 1369 #endif 1370 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1371 dc->dcn_soc->urgent_latency = 3; 1372 dc->debug.disable_dmcu = true; 1373 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1374 } 1375 1376 1377 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1378 ASSERT(dc->dcn_soc->number_of_channels < 3); 1379 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1380 dc->dcn_soc->number_of_channels = 2; 1381 1382 if (dc->dcn_soc->number_of_channels == 1) { 1383 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1384 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1385 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1386 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1387 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1388 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1389 } 1390 } 1391 1392 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1393 1394 if (!dc->debug.disable_pplib_clock_request) 1395 dcn_bw_update_from_pplib(dc); 1396 dcn_bw_sync_calcs_and_dml(dc); 1397 if (!dc->debug.disable_pplib_wm_range) { 1398 dc->res_pool = &pool->base; 1399 dcn_bw_notify_pplib_of_wm_ranges(dc); 1400 } 1401 1402 { 1403 struct irq_service_init_data init_data; 1404 init_data.ctx = dc->ctx; 1405 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1406 if (!pool->base.irqs) 1407 goto fail; 1408 } 1409 1410 /* index to valid pipe resource */ 1411 j = 0; 1412 /* mem input -> ipp -> dpp -> opp -> TG */ 1413 for (i = 0; i < pool->base.pipe_count; i++) { 1414 /* if pipe is disabled, skip instance of HW pipe, 1415 * i.e, skip ASIC register instance 1416 */ 1417 if ((pipe_fuses & (1 << i)) != 0) 1418 continue; 1419 1420 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1421 if (pool->base.hubps[j] == NULL) { 1422 BREAK_TO_DEBUGGER(); 1423 dm_error( 1424 "DC: failed to create memory input!\n"); 1425 goto fail; 1426 } 1427 1428 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1429 if (pool->base.ipps[j] == NULL) { 1430 BREAK_TO_DEBUGGER(); 1431 dm_error( 1432 "DC: failed to create input pixel processor!\n"); 1433 goto fail; 1434 } 1435 1436 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1437 if (pool->base.dpps[j] == NULL) { 1438 BREAK_TO_DEBUGGER(); 1439 dm_error( 1440 "DC: failed to create dpp!\n"); 1441 goto fail; 1442 } 1443 1444 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1445 if (pool->base.opps[j] == NULL) { 1446 BREAK_TO_DEBUGGER(); 1447 dm_error( 1448 "DC: failed to create output pixel processor!\n"); 1449 goto fail; 1450 } 1451 1452 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1453 ctx, i); 1454 if (pool->base.timing_generators[j] == NULL) { 1455 BREAK_TO_DEBUGGER(); 1456 dm_error("DC: failed to create tg!\n"); 1457 goto fail; 1458 } 1459 /* check next valid pipe */ 1460 j++; 1461 } 1462 1463 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1464 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1465 if (pool->base.engines[i] == NULL) { 1466 BREAK_TO_DEBUGGER(); 1467 dm_error( 1468 "DC:failed to create aux engine!!\n"); 1469 goto fail; 1470 } 1471 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1472 if (pool->base.hw_i2cs[i] == NULL) { 1473 BREAK_TO_DEBUGGER(); 1474 dm_error( 1475 "DC:failed to create hw i2c!!\n"); 1476 goto fail; 1477 } 1478 pool->base.sw_i2cs[i] = NULL; 1479 } 1480 1481 /* valid pipe num */ 1482 pool->base.pipe_count = j; 1483 pool->base.timing_generator_count = j; 1484 1485 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1486 * the value may be changed 1487 */ 1488 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1489 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1490 1491 pool->base.mpc = dcn10_mpc_create(ctx); 1492 if (pool->base.mpc == NULL) { 1493 BREAK_TO_DEBUGGER(); 1494 dm_error("DC: failed to create mpc!\n"); 1495 goto fail; 1496 } 1497 1498 pool->base.hubbub = dcn10_hubbub_create(ctx); 1499 if (pool->base.hubbub == NULL) { 1500 BREAK_TO_DEBUGGER(); 1501 dm_error("DC: failed to create hubbub!\n"); 1502 goto fail; 1503 } 1504 1505 if (!resource_construct(num_virtual_links, dc, &pool->base, 1506 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1507 &res_create_funcs : &res_create_maximus_funcs))) 1508 goto fail; 1509 1510 dcn10_hw_sequencer_construct(dc); 1511 dc->caps.max_planes = pool->base.pipe_count; 1512 1513 dc->cap_funcs = cap_funcs; 1514 1515 return true; 1516 1517 fail: 1518 1519 destruct(pool); 1520 1521 return false; 1522 } 1523 1524 struct resource_pool *dcn10_create_resource_pool( 1525 uint8_t num_virtual_links, 1526 struct dc *dc) 1527 { 1528 struct dcn10_resource_pool *pool = 1529 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1530 1531 if (!pool) 1532 return NULL; 1533 1534 if (construct(num_virtual_links, dc, pool)) 1535 return &pool->base; 1536 1537 BREAK_TO_DEBUGGER(); 1538 return NULL; 1539 } 1540