1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dcn10_resource.h" 34 #include "dcn10_ipp.h" 35 #include "dcn10_mpc.h" 36 #include "irq/dcn10/irq_service_dcn10.h" 37 #include "dcn10_dpp.h" 38 #include "dcn10_optc.h" 39 #include "dcn10_hw_sequencer.h" 40 #include "dce110/dce110_hw_sequencer.h" 41 #include "dcn10_opp.h" 42 #include "dcn10_link_encoder.h" 43 #include "dcn10_stream_encoder.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs_luma = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 157 }; 158 159 /* begin ********************* 160 * macros to expend register list macro defined in HW object header file */ 161 162 /* DCN */ 163 #define BASE_INNER(seg) \ 164 DCE_BASE__INST0_SEG ## seg 165 166 #define BASE(seg) \ 167 BASE_INNER(seg) 168 169 #define SR(reg_name)\ 170 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 171 mm ## reg_name 172 173 #define SRI(reg_name, block, id)\ 174 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 mm ## block ## id ## _ ## reg_name 176 177 178 #define SRII(reg_name, block, id)\ 179 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 180 mm ## block ## id ## _ ## reg_name 181 182 /* NBIO */ 183 #define NBIO_BASE_INNER(seg) \ 184 NBIF_BASE__INST0_SEG ## seg 185 186 #define NBIO_BASE(seg) \ 187 NBIO_BASE_INNER(seg) 188 189 #define NBIO_SR(reg_name)\ 190 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 191 mm ## reg_name 192 193 /* MMHUB */ 194 #define MMHUB_BASE_INNER(seg) \ 195 MMHUB_BASE__INST0_SEG ## seg 196 197 #define MMHUB_BASE(seg) \ 198 MMHUB_BASE_INNER(seg) 199 200 #define MMHUB_SR(reg_name)\ 201 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 202 mm ## reg_name 203 204 /* macros to expend register list macro defined in HW object header file 205 * end *********************/ 206 207 208 static const struct dce_dmcu_registers dmcu_regs = { 209 DMCU_DCN10_REG_LIST() 210 }; 211 212 static const struct dce_dmcu_shift dmcu_shift = { 213 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 214 }; 215 216 static const struct dce_dmcu_mask dmcu_mask = { 217 DMCU_MASK_SH_LIST_DCN10(_MASK) 218 }; 219 220 static const struct dce_abm_registers abm_regs = { 221 ABM_DCN10_REG_LIST(0) 222 }; 223 224 static const struct dce_abm_shift abm_shift = { 225 ABM_MASK_SH_LIST_DCN10(__SHIFT) 226 }; 227 228 static const struct dce_abm_mask abm_mask = { 229 ABM_MASK_SH_LIST_DCN10(_MASK) 230 }; 231 232 #define stream_enc_regs(id)\ 233 [id] = {\ 234 SE_DCN_REG_LIST(id)\ 235 } 236 237 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 238 stream_enc_regs(0), 239 stream_enc_regs(1), 240 stream_enc_regs(2), 241 stream_enc_regs(3), 242 }; 243 244 static const struct dcn10_stream_encoder_shift se_shift = { 245 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 246 }; 247 248 static const struct dcn10_stream_encoder_mask se_mask = { 249 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 250 }; 251 252 #define audio_regs(id)\ 253 [id] = {\ 254 AUD_COMMON_REG_LIST(id)\ 255 } 256 257 static const struct dce_audio_registers audio_regs[] = { 258 audio_regs(0), 259 audio_regs(1), 260 audio_regs(2), 261 audio_regs(3), 262 }; 263 264 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 265 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 266 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 267 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 268 269 static const struct dce_audio_shift audio_shift = { 270 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 271 }; 272 273 static const struct dce_audio_mask audio_mask = { 274 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 275 }; 276 277 #define aux_regs(id)\ 278 [id] = {\ 279 AUX_REG_LIST(id)\ 280 } 281 282 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 283 aux_regs(0), 284 aux_regs(1), 285 aux_regs(2), 286 aux_regs(3) 287 }; 288 289 #define hpd_regs(id)\ 290 [id] = {\ 291 HPD_REG_LIST(id)\ 292 } 293 294 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 295 hpd_regs(0), 296 hpd_regs(1), 297 hpd_regs(2), 298 hpd_regs(3) 299 }; 300 301 #define link_regs(id)\ 302 [id] = {\ 303 LE_DCN10_REG_LIST(id), \ 304 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 305 } 306 307 static const struct dcn10_link_enc_registers link_enc_regs[] = { 308 link_regs(0), 309 link_regs(1), 310 link_regs(2), 311 link_regs(3) 312 }; 313 314 static const struct dcn10_link_enc_shift le_shift = { 315 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 316 }; 317 318 static const struct dcn10_link_enc_mask le_mask = { 319 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 320 }; 321 322 static const struct dce110_aux_registers_shift aux_shift = { 323 DCN10_AUX_MASK_SH_LIST(__SHIFT) 324 }; 325 326 static const struct dce110_aux_registers_mask aux_mask = { 327 DCN10_AUX_MASK_SH_LIST(_MASK) 328 }; 329 330 #define ipp_regs(id)\ 331 [id] = {\ 332 IPP_REG_LIST_DCN10(id),\ 333 } 334 335 static const struct dcn10_ipp_registers ipp_regs[] = { 336 ipp_regs(0), 337 ipp_regs(1), 338 ipp_regs(2), 339 ipp_regs(3), 340 }; 341 342 static const struct dcn10_ipp_shift ipp_shift = { 343 IPP_MASK_SH_LIST_DCN10(__SHIFT) 344 }; 345 346 static const struct dcn10_ipp_mask ipp_mask = { 347 IPP_MASK_SH_LIST_DCN10(_MASK), 348 }; 349 350 #define opp_regs(id)\ 351 [id] = {\ 352 OPP_REG_LIST_DCN10(id),\ 353 } 354 355 static const struct dcn10_opp_registers opp_regs[] = { 356 opp_regs(0), 357 opp_regs(1), 358 opp_regs(2), 359 opp_regs(3), 360 }; 361 362 static const struct dcn10_opp_shift opp_shift = { 363 OPP_MASK_SH_LIST_DCN10(__SHIFT) 364 }; 365 366 static const struct dcn10_opp_mask opp_mask = { 367 OPP_MASK_SH_LIST_DCN10(_MASK), 368 }; 369 370 #define aux_engine_regs(id)\ 371 [id] = {\ 372 AUX_COMMON_REG_LIST(id), \ 373 .AUX_RESET_MASK = 0 \ 374 } 375 376 static const struct dce110_aux_registers aux_engine_regs[] = { 377 aux_engine_regs(0), 378 aux_engine_regs(1), 379 aux_engine_regs(2), 380 aux_engine_regs(3), 381 aux_engine_regs(4), 382 aux_engine_regs(5) 383 }; 384 385 #define tf_regs(id)\ 386 [id] = {\ 387 TF_REG_LIST_DCN10(id),\ 388 } 389 390 static const struct dcn_dpp_registers tf_regs[] = { 391 tf_regs(0), 392 tf_regs(1), 393 tf_regs(2), 394 tf_regs(3), 395 }; 396 397 static const struct dcn_dpp_shift tf_shift = { 398 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 399 TF_DEBUG_REG_LIST_SH_DCN10 400 401 }; 402 403 static const struct dcn_dpp_mask tf_mask = { 404 TF_REG_LIST_SH_MASK_DCN10(_MASK), 405 TF_DEBUG_REG_LIST_MASK_DCN10 406 }; 407 408 static const struct dcn_mpc_registers mpc_regs = { 409 MPC_COMMON_REG_LIST_DCN1_0(0), 410 MPC_COMMON_REG_LIST_DCN1_0(1), 411 MPC_COMMON_REG_LIST_DCN1_0(2), 412 MPC_COMMON_REG_LIST_DCN1_0(3), 413 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 414 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 415 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 416 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 417 }; 418 419 static const struct dcn_mpc_shift mpc_shift = { 420 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 421 }; 422 423 static const struct dcn_mpc_mask mpc_mask = { 424 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 425 }; 426 427 #define tg_regs(id)\ 428 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 429 430 static const struct dcn_optc_registers tg_regs[] = { 431 tg_regs(0), 432 tg_regs(1), 433 tg_regs(2), 434 tg_regs(3), 435 }; 436 437 static const struct dcn_optc_shift tg_shift = { 438 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 439 }; 440 441 static const struct dcn_optc_mask tg_mask = { 442 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 443 }; 444 445 static const struct bios_registers bios_regs = { 446 NBIO_SR(BIOS_SCRATCH_3), 447 NBIO_SR(BIOS_SCRATCH_6) 448 }; 449 450 #define hubp_regs(id)\ 451 [id] = {\ 452 HUBP_REG_LIST_DCN10(id)\ 453 } 454 455 static const struct dcn_mi_registers hubp_regs[] = { 456 hubp_regs(0), 457 hubp_regs(1), 458 hubp_regs(2), 459 hubp_regs(3), 460 }; 461 462 static const struct dcn_mi_shift hubp_shift = { 463 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 464 }; 465 466 static const struct dcn_mi_mask hubp_mask = { 467 HUBP_MASK_SH_LIST_DCN10(_MASK) 468 }; 469 470 static const struct dcn_hubbub_registers hubbub_reg = { 471 HUBBUB_REG_LIST_DCN10(0) 472 }; 473 474 static const struct dcn_hubbub_shift hubbub_shift = { 475 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 476 }; 477 478 static const struct dcn_hubbub_mask hubbub_mask = { 479 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 480 }; 481 482 static int map_transmitter_id_to_phy_instance( 483 enum transmitter transmitter) 484 { 485 switch (transmitter) { 486 case TRANSMITTER_UNIPHY_A: 487 return 0; 488 break; 489 case TRANSMITTER_UNIPHY_B: 490 return 1; 491 break; 492 case TRANSMITTER_UNIPHY_C: 493 return 2; 494 break; 495 case TRANSMITTER_UNIPHY_D: 496 return 3; 497 break; 498 default: 499 ASSERT(0); 500 return 0; 501 } 502 } 503 504 #define clk_src_regs(index, pllid)\ 505 [index] = {\ 506 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 507 } 508 509 static const struct dce110_clk_src_regs clk_src_regs[] = { 510 clk_src_regs(0, A), 511 clk_src_regs(1, B), 512 clk_src_regs(2, C), 513 clk_src_regs(3, D) 514 }; 515 516 static const struct dce110_clk_src_shift cs_shift = { 517 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 518 }; 519 520 static const struct dce110_clk_src_mask cs_mask = { 521 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 522 }; 523 524 static const struct resource_caps res_cap = { 525 .num_timing_generator = 4, 526 .num_opp = 4, 527 .num_video_plane = 4, 528 .num_audio = 4, 529 .num_stream_encoder = 4, 530 .num_pll = 4, 531 .num_ddc = 4, 532 }; 533 534 static const struct resource_caps rv2_res_cap = { 535 .num_timing_generator = 3, 536 .num_opp = 3, 537 .num_video_plane = 3, 538 .num_audio = 3, 539 .num_stream_encoder = 3, 540 .num_pll = 3, 541 .num_ddc = 4, 542 }; 543 544 static const struct dc_plane_cap plane_cap = { 545 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 546 .blends_with_above = true, 547 .blends_with_below = true, 548 .per_pixel_alpha = true, 549 550 .pixel_format_support = { 551 .argb8888 = true, 552 .nv12 = true, 553 .fp16 = true 554 }, 555 556 .max_upscale_factor = { 557 .argb8888 = 16000, 558 .nv12 = 16000, 559 .fp16 = 1 560 }, 561 562 .max_downscale_factor = { 563 .argb8888 = 250, 564 .nv12 = 250, 565 .fp16 = 1 566 } 567 }; 568 569 static const struct dc_debug_options debug_defaults_drv = { 570 .sanity_checks = true, 571 .disable_dmcu = true, 572 .force_abm_enable = false, 573 .timing_trace = false, 574 .clock_trace = true, 575 576 /* raven smu dones't allow 0 disp clk, 577 * smu min disp clk limit is 50Mhz 578 * keep min disp clk 100Mhz avoid smu hang 579 */ 580 .min_disp_clk_khz = 100000, 581 582 .disable_pplib_clock_request = false, 583 .disable_pplib_wm_range = false, 584 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 585 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 586 .force_single_disp_pipe_split = true, 587 .disable_dcc = DCC_ENABLE, 588 .voltage_align_fclk = true, 589 .disable_stereo_support = true, 590 .vsr_support = true, 591 .performance_trace = false, 592 .az_endpoint_mute_only = true, 593 .recovery_enabled = false, /*enable this by default after testing.*/ 594 .max_downscale_src_width = 3840, 595 .underflow_assert_delay_us = 0xFFFFFFFF, 596 }; 597 598 static const struct dc_debug_options debug_defaults_diags = { 599 .disable_dmcu = true, 600 .force_abm_enable = false, 601 .timing_trace = true, 602 .clock_trace = true, 603 .disable_stutter = true, 604 .disable_pplib_clock_request = true, 605 .disable_pplib_wm_range = true, 606 .underflow_assert_delay_us = 0xFFFFFFFF, 607 }; 608 609 static void dcn10_dpp_destroy(struct dpp **dpp) 610 { 611 kfree(TO_DCN10_DPP(*dpp)); 612 *dpp = NULL; 613 } 614 615 static struct dpp *dcn10_dpp_create( 616 struct dc_context *ctx, 617 uint32_t inst) 618 { 619 struct dcn10_dpp *dpp = 620 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 621 622 if (!dpp) 623 return NULL; 624 625 dpp1_construct(dpp, ctx, inst, 626 &tf_regs[inst], &tf_shift, &tf_mask); 627 return &dpp->base; 628 } 629 630 static struct input_pixel_processor *dcn10_ipp_create( 631 struct dc_context *ctx, uint32_t inst) 632 { 633 struct dcn10_ipp *ipp = 634 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 635 636 if (!ipp) { 637 BREAK_TO_DEBUGGER(); 638 return NULL; 639 } 640 641 dcn10_ipp_construct(ipp, ctx, inst, 642 &ipp_regs[inst], &ipp_shift, &ipp_mask); 643 return &ipp->base; 644 } 645 646 647 static struct output_pixel_processor *dcn10_opp_create( 648 struct dc_context *ctx, uint32_t inst) 649 { 650 struct dcn10_opp *opp = 651 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 652 653 if (!opp) { 654 BREAK_TO_DEBUGGER(); 655 return NULL; 656 } 657 658 dcn10_opp_construct(opp, ctx, inst, 659 &opp_regs[inst], &opp_shift, &opp_mask); 660 return &opp->base; 661 } 662 663 struct dce_aux *dcn10_aux_engine_create( 664 struct dc_context *ctx, 665 uint32_t inst) 666 { 667 struct aux_engine_dce110 *aux_engine = 668 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 669 670 if (!aux_engine) 671 return NULL; 672 673 dce110_aux_engine_construct(aux_engine, ctx, inst, 674 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 675 &aux_engine_regs[inst], 676 &aux_mask, 677 &aux_shift, 678 ctx->dc->caps.extended_aux_timeout_support); 679 680 return &aux_engine->base; 681 } 682 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 683 684 static const struct dce_i2c_registers i2c_hw_regs[] = { 685 i2c_inst_regs(1), 686 i2c_inst_regs(2), 687 i2c_inst_regs(3), 688 i2c_inst_regs(4), 689 i2c_inst_regs(5), 690 i2c_inst_regs(6), 691 }; 692 693 static const struct dce_i2c_shift i2c_shifts = { 694 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 695 }; 696 697 static const struct dce_i2c_mask i2c_masks = { 698 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 699 }; 700 701 struct dce_i2c_hw *dcn10_i2c_hw_create( 702 struct dc_context *ctx, 703 uint32_t inst) 704 { 705 struct dce_i2c_hw *dce_i2c_hw = 706 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 707 708 if (!dce_i2c_hw) 709 return NULL; 710 711 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 712 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 713 714 return dce_i2c_hw; 715 } 716 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 717 { 718 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 719 GFP_KERNEL); 720 721 if (!mpc10) 722 return NULL; 723 724 dcn10_mpc_construct(mpc10, ctx, 725 &mpc_regs, 726 &mpc_shift, 727 &mpc_mask, 728 4); 729 730 return &mpc10->base; 731 } 732 733 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 734 { 735 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 736 GFP_KERNEL); 737 738 if (!dcn10_hubbub) 739 return NULL; 740 741 hubbub1_construct(&dcn10_hubbub->base, ctx, 742 &hubbub_reg, 743 &hubbub_shift, 744 &hubbub_mask); 745 746 return &dcn10_hubbub->base; 747 } 748 749 static struct timing_generator *dcn10_timing_generator_create( 750 struct dc_context *ctx, 751 uint32_t instance) 752 { 753 struct optc *tgn10 = 754 kzalloc(sizeof(struct optc), GFP_KERNEL); 755 756 if (!tgn10) 757 return NULL; 758 759 tgn10->base.inst = instance; 760 tgn10->base.ctx = ctx; 761 762 tgn10->tg_regs = &tg_regs[instance]; 763 tgn10->tg_shift = &tg_shift; 764 tgn10->tg_mask = &tg_mask; 765 766 dcn10_timing_generator_init(tgn10); 767 768 return &tgn10->base; 769 } 770 771 static const struct encoder_feature_support link_enc_feature = { 772 .max_hdmi_deep_color = COLOR_DEPTH_121212, 773 .max_hdmi_pixel_clock = 600000, 774 .hdmi_ycbcr420_supported = true, 775 .dp_ycbcr420_supported = false, 776 .flags.bits.IS_HBR2_CAPABLE = true, 777 .flags.bits.IS_HBR3_CAPABLE = true, 778 .flags.bits.IS_TPS3_CAPABLE = true, 779 .flags.bits.IS_TPS4_CAPABLE = true 780 }; 781 782 struct link_encoder *dcn10_link_encoder_create( 783 const struct encoder_init_data *enc_init_data) 784 { 785 struct dcn10_link_encoder *enc10 = 786 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 787 int link_regs_id; 788 789 if (!enc10) 790 return NULL; 791 792 link_regs_id = 793 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 794 795 dcn10_link_encoder_construct(enc10, 796 enc_init_data, 797 &link_enc_feature, 798 &link_enc_regs[link_regs_id], 799 &link_enc_aux_regs[enc_init_data->channel - 1], 800 &link_enc_hpd_regs[enc_init_data->hpd_source], 801 &le_shift, 802 &le_mask); 803 804 return &enc10->base; 805 } 806 807 struct clock_source *dcn10_clock_source_create( 808 struct dc_context *ctx, 809 struct dc_bios *bios, 810 enum clock_source_id id, 811 const struct dce110_clk_src_regs *regs, 812 bool dp_clk_src) 813 { 814 struct dce110_clk_src *clk_src = 815 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 816 817 if (!clk_src) 818 return NULL; 819 820 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 821 regs, &cs_shift, &cs_mask)) { 822 clk_src->base.dp_clk_src = dp_clk_src; 823 return &clk_src->base; 824 } 825 826 kfree(clk_src); 827 BREAK_TO_DEBUGGER(); 828 return NULL; 829 } 830 831 static void read_dce_straps( 832 struct dc_context *ctx, 833 struct resource_straps *straps) 834 { 835 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 836 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 837 } 838 839 static struct audio *create_audio( 840 struct dc_context *ctx, unsigned int inst) 841 { 842 return dce_audio_create(ctx, inst, 843 &audio_regs[inst], &audio_shift, &audio_mask); 844 } 845 846 static struct stream_encoder *dcn10_stream_encoder_create( 847 enum engine_id eng_id, 848 struct dc_context *ctx) 849 { 850 struct dcn10_stream_encoder *enc1 = 851 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 852 853 if (!enc1) 854 return NULL; 855 856 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 857 &stream_enc_regs[eng_id], 858 &se_shift, &se_mask); 859 return &enc1->base; 860 } 861 862 static const struct dce_hwseq_registers hwseq_reg = { 863 HWSEQ_DCN1_REG_LIST() 864 }; 865 866 static const struct dce_hwseq_shift hwseq_shift = { 867 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 868 }; 869 870 static const struct dce_hwseq_mask hwseq_mask = { 871 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 872 }; 873 874 static struct dce_hwseq *dcn10_hwseq_create( 875 struct dc_context *ctx) 876 { 877 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 878 879 if (hws) { 880 hws->ctx = ctx; 881 hws->regs = &hwseq_reg; 882 hws->shifts = &hwseq_shift; 883 hws->masks = &hwseq_mask; 884 hws->wa.DEGVIDCN10_253 = true; 885 hws->wa.false_optc_underflow = true; 886 hws->wa.DEGVIDCN10_254 = true; 887 } 888 return hws; 889 } 890 891 static const struct resource_create_funcs res_create_funcs = { 892 .read_dce_straps = read_dce_straps, 893 .create_audio = create_audio, 894 .create_stream_encoder = dcn10_stream_encoder_create, 895 .create_hwseq = dcn10_hwseq_create, 896 }; 897 898 static const struct resource_create_funcs res_create_maximus_funcs = { 899 .read_dce_straps = NULL, 900 .create_audio = NULL, 901 .create_stream_encoder = NULL, 902 .create_hwseq = dcn10_hwseq_create, 903 }; 904 905 void dcn10_clock_source_destroy(struct clock_source **clk_src) 906 { 907 kfree(TO_DCE110_CLK_SRC(*clk_src)); 908 *clk_src = NULL; 909 } 910 911 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 912 { 913 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 914 915 if (!pp_smu) 916 return pp_smu; 917 918 dm_pp_get_funcs(ctx, pp_smu); 919 return pp_smu; 920 } 921 922 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) 923 { 924 unsigned int i; 925 926 for (i = 0; i < pool->base.stream_enc_count; i++) { 927 if (pool->base.stream_enc[i] != NULL) { 928 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 929 pool->base.stream_enc[i] = NULL; 930 } 931 } 932 933 if (pool->base.mpc != NULL) { 934 kfree(TO_DCN10_MPC(pool->base.mpc)); 935 pool->base.mpc = NULL; 936 } 937 938 if (pool->base.hubbub != NULL) { 939 kfree(pool->base.hubbub); 940 pool->base.hubbub = NULL; 941 } 942 943 for (i = 0; i < pool->base.pipe_count; i++) { 944 if (pool->base.opps[i] != NULL) 945 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 946 947 if (pool->base.dpps[i] != NULL) 948 dcn10_dpp_destroy(&pool->base.dpps[i]); 949 950 if (pool->base.ipps[i] != NULL) 951 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 952 953 if (pool->base.hubps[i] != NULL) { 954 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 955 pool->base.hubps[i] = NULL; 956 } 957 958 if (pool->base.irqs != NULL) { 959 dal_irq_service_destroy(&pool->base.irqs); 960 } 961 962 if (pool->base.timing_generators[i] != NULL) { 963 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 964 pool->base.timing_generators[i] = NULL; 965 } 966 } 967 968 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 969 if (pool->base.engines[i] != NULL) 970 dce110_engine_destroy(&pool->base.engines[i]); 971 if (pool->base.hw_i2cs[i] != NULL) { 972 kfree(pool->base.hw_i2cs[i]); 973 pool->base.hw_i2cs[i] = NULL; 974 } 975 if (pool->base.sw_i2cs[i] != NULL) { 976 kfree(pool->base.sw_i2cs[i]); 977 pool->base.sw_i2cs[i] = NULL; 978 } 979 } 980 981 for (i = 0; i < pool->base.audio_count; i++) { 982 if (pool->base.audios[i]) 983 dce_aud_destroy(&pool->base.audios[i]); 984 } 985 986 for (i = 0; i < pool->base.clk_src_count; i++) { 987 if (pool->base.clock_sources[i] != NULL) { 988 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 989 pool->base.clock_sources[i] = NULL; 990 } 991 } 992 993 if (pool->base.dp_clock_source != NULL) { 994 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 995 pool->base.dp_clock_source = NULL; 996 } 997 998 if (pool->base.abm != NULL) 999 dce_abm_destroy(&pool->base.abm); 1000 1001 if (pool->base.dmcu != NULL) 1002 dce_dmcu_destroy(&pool->base.dmcu); 1003 1004 kfree(pool->base.pp_smu); 1005 } 1006 1007 static struct hubp *dcn10_hubp_create( 1008 struct dc_context *ctx, 1009 uint32_t inst) 1010 { 1011 struct dcn10_hubp *hubp1 = 1012 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 1013 1014 if (!hubp1) 1015 return NULL; 1016 1017 dcn10_hubp_construct(hubp1, ctx, inst, 1018 &hubp_regs[inst], &hubp_shift, &hubp_mask); 1019 return &hubp1->base; 1020 } 1021 1022 static void get_pixel_clock_parameters( 1023 const struct pipe_ctx *pipe_ctx, 1024 struct pixel_clk_params *pixel_clk_params) 1025 { 1026 const struct dc_stream_state *stream = pipe_ctx->stream; 1027 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1028 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1029 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1030 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1031 /* TODO: un-hardcode*/ 1032 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1033 LINK_RATE_REF_FREQ_IN_KHZ; 1034 pixel_clk_params->flags.ENABLE_SS = 0; 1035 pixel_clk_params->color_depth = 1036 stream->timing.display_color_depth; 1037 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1038 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1039 1040 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1041 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1042 1043 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1044 pixel_clk_params->requested_pix_clk_100hz /= 2; 1045 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1046 pixel_clk_params->requested_pix_clk_100hz *= 2; 1047 1048 } 1049 1050 static void build_clamping_params(struct dc_stream_state *stream) 1051 { 1052 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1053 stream->clamping.c_depth = stream->timing.display_color_depth; 1054 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1055 } 1056 1057 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1058 { 1059 1060 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1061 1062 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1063 pipe_ctx->clock_source, 1064 &pipe_ctx->stream_res.pix_clk_params, 1065 &pipe_ctx->pll_settings); 1066 1067 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1068 1069 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1070 &pipe_ctx->stream->bit_depth_params); 1071 build_clamping_params(pipe_ctx->stream); 1072 } 1073 1074 static enum dc_status build_mapped_resource( 1075 const struct dc *dc, 1076 struct dc_state *context, 1077 struct dc_stream_state *stream) 1078 { 1079 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1080 1081 /*TODO Seems unneeded anymore */ 1082 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1083 if (stream != NULL && old_context->streams[i] != NULL) { 1084 todo: shouldn't have to copy missing parameter here 1085 resource_build_bit_depth_reduction_params(stream, 1086 &stream->bit_depth_params); 1087 stream->clamping.pixel_encoding = 1088 stream->timing.pixel_encoding; 1089 1090 resource_build_bit_depth_reduction_params(stream, 1091 &stream->bit_depth_params); 1092 build_clamping_params(stream); 1093 1094 continue; 1095 } 1096 } 1097 */ 1098 1099 if (!pipe_ctx) 1100 return DC_ERROR_UNEXPECTED; 1101 1102 build_pipe_hw_param(pipe_ctx); 1103 return DC_OK; 1104 } 1105 1106 enum dc_status dcn10_add_stream_to_ctx( 1107 struct dc *dc, 1108 struct dc_state *new_ctx, 1109 struct dc_stream_state *dc_stream) 1110 { 1111 enum dc_status result = DC_ERROR_UNEXPECTED; 1112 1113 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1114 1115 if (result == DC_OK) 1116 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1117 1118 1119 if (result == DC_OK) 1120 result = build_mapped_resource(dc, new_ctx, dc_stream); 1121 1122 return result; 1123 } 1124 1125 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1126 struct dc_state *context, 1127 const struct resource_pool *pool, 1128 struct dc_stream_state *stream) 1129 { 1130 struct resource_context *res_ctx = &context->res_ctx; 1131 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1132 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 1133 1134 if (!head_pipe) { 1135 ASSERT(0); 1136 return NULL; 1137 } 1138 1139 if (!idle_pipe) 1140 return NULL; 1141 1142 idle_pipe->stream = head_pipe->stream; 1143 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1144 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1145 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1146 1147 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1148 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1149 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1150 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1151 1152 return idle_pipe; 1153 } 1154 1155 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1156 const struct dc_dcc_surface_param *input, 1157 struct dc_surface_dcc_cap *output) 1158 { 1159 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1160 dc->res_pool->hubbub, 1161 input, 1162 output); 1163 } 1164 1165 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1166 { 1167 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1168 1169 dcn10_resource_destruct(dcn10_pool); 1170 kfree(dcn10_pool); 1171 *pool = NULL; 1172 } 1173 1174 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1175 { 1176 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1177 && caps->max_video_width != 0 1178 && plane_state->src_rect.width > caps->max_video_width) 1179 return DC_FAIL_SURFACE_VALIDATE; 1180 1181 return DC_OK; 1182 } 1183 1184 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1185 { 1186 int i, j; 1187 bool video_down_scaled = false; 1188 bool video_large = false; 1189 bool desktop_large = false; 1190 bool dcc_disabled = false; 1191 1192 for (i = 0; i < context->stream_count; i++) { 1193 if (context->stream_status[i].plane_count == 0) 1194 continue; 1195 1196 if (context->stream_status[i].plane_count > 2) 1197 return DC_FAIL_UNSUPPORTED_1; 1198 1199 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1200 struct dc_plane_state *plane = 1201 context->stream_status[i].plane_states[j]; 1202 1203 1204 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1205 1206 if (plane->src_rect.width > plane->dst_rect.width || 1207 plane->src_rect.height > plane->dst_rect.height) 1208 video_down_scaled = true; 1209 1210 if (plane->src_rect.width >= 3840) 1211 video_large = true; 1212 1213 } else { 1214 if (plane->src_rect.width >= 3840) 1215 desktop_large = true; 1216 if (!plane->dcc.enable) 1217 dcc_disabled = true; 1218 } 1219 } 1220 } 1221 1222 /* 1223 * Workaround: On DCN10 there is UMC issue that causes underflow when 1224 * playing 4k video on 4k desktop with video downscaled and single channel 1225 * memory 1226 */ 1227 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1228 dc->dcn_soc->number_of_channels == 1) 1229 return DC_FAIL_SURFACE_VALIDATE; 1230 1231 return DC_OK; 1232 } 1233 1234 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1235 { 1236 enum dc_status result = DC_OK; 1237 1238 enum surface_pixel_format surf_pix_format = plane_state->format; 1239 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1240 1241 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1242 1243 if (bpp == 64) 1244 swizzle = DC_SW_64KB_D; 1245 else 1246 swizzle = DC_SW_64KB_S; 1247 1248 plane_state->tiling_info.gfx9.swizzle = swizzle; 1249 return result; 1250 } 1251 1252 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 1253 struct resource_context *res_ctx, 1254 const struct resource_pool *pool, 1255 struct dc_stream_state *stream) 1256 { 1257 int i; 1258 int j = -1; 1259 struct dc_link *link = stream->link; 1260 1261 for (i = 0; i < pool->stream_enc_count; i++) { 1262 if (!res_ctx->is_stream_enc_acquired[i] && 1263 pool->stream_enc[i]) { 1264 /* Store first available for MST second display 1265 * in daisy chain use case 1266 */ 1267 j = i; 1268 if (pool->stream_enc[i]->id == 1269 link->link_enc->preferred_engine) 1270 return pool->stream_enc[i]; 1271 } 1272 } 1273 1274 /* 1275 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1276 */ 1277 1278 if (j >= 0) 1279 return pool->stream_enc[j]; 1280 1281 return NULL; 1282 } 1283 1284 static const struct dc_cap_funcs cap_funcs = { 1285 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1286 }; 1287 1288 static const struct resource_funcs dcn10_res_pool_funcs = { 1289 .destroy = dcn10_destroy_resource_pool, 1290 .link_enc_create = dcn10_link_encoder_create, 1291 .validate_bandwidth = dcn_validate_bandwidth, 1292 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1293 .validate_plane = dcn10_validate_plane, 1294 .validate_global = dcn10_validate_global, 1295 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1296 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode, 1297 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 1298 }; 1299 1300 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1301 { 1302 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1303 /* RV1 support max 4 pipes */ 1304 value = value & 0xf; 1305 return value; 1306 } 1307 1308 static bool dcn10_resource_construct( 1309 uint8_t num_virtual_links, 1310 struct dc *dc, 1311 struct dcn10_resource_pool *pool) 1312 { 1313 int i; 1314 int j; 1315 struct dc_context *ctx = dc->ctx; 1316 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1317 1318 ctx->dc_bios->regs = &bios_regs; 1319 1320 if (ctx->dce_version == DCN_VERSION_1_01) 1321 pool->base.res_cap = &rv2_res_cap; 1322 else 1323 pool->base.res_cap = &res_cap; 1324 pool->base.funcs = &dcn10_res_pool_funcs; 1325 1326 /* 1327 * TODO fill in from actual raven resource when we create 1328 * more than virtual encoder 1329 */ 1330 1331 /************************************************* 1332 * Resource + asic cap harcoding * 1333 *************************************************/ 1334 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1335 1336 /* max pipe num for ASIC before check pipe fuses */ 1337 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1338 1339 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1340 pool->base.pipe_count = 3; 1341 dc->caps.max_video_width = 3840; 1342 dc->caps.max_downscale_ratio = 200; 1343 dc->caps.i2c_speed_in_khz = 100; 1344 dc->caps.max_cursor_size = 256; 1345 dc->caps.max_slave_planes = 1; 1346 dc->caps.is_apu = true; 1347 dc->caps.post_blend_color_processing = false; 1348 dc->caps.extended_aux_timeout_support = false; 1349 1350 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1351 dc->caps.force_dp_tps4_for_cp2520 = true; 1352 1353 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1354 dc->debug = debug_defaults_drv; 1355 else 1356 dc->debug = debug_defaults_diags; 1357 1358 /************************************************* 1359 * Create resources * 1360 *************************************************/ 1361 1362 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1363 dcn10_clock_source_create(ctx, ctx->dc_bios, 1364 CLOCK_SOURCE_COMBO_PHY_PLL0, 1365 &clk_src_regs[0], false); 1366 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1367 dcn10_clock_source_create(ctx, ctx->dc_bios, 1368 CLOCK_SOURCE_COMBO_PHY_PLL1, 1369 &clk_src_regs[1], false); 1370 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1371 dcn10_clock_source_create(ctx, ctx->dc_bios, 1372 CLOCK_SOURCE_COMBO_PHY_PLL2, 1373 &clk_src_regs[2], false); 1374 1375 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1376 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1377 dcn10_clock_source_create(ctx, ctx->dc_bios, 1378 CLOCK_SOURCE_COMBO_PHY_PLL3, 1379 &clk_src_regs[3], false); 1380 } 1381 1382 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1383 1384 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1385 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1386 1387 pool->base.dp_clock_source = 1388 dcn10_clock_source_create(ctx, ctx->dc_bios, 1389 CLOCK_SOURCE_ID_DP_DTO, 1390 /* todo: not reuse phy_pll registers */ 1391 &clk_src_regs[0], true); 1392 1393 for (i = 0; i < pool->base.clk_src_count; i++) { 1394 if (pool->base.clock_sources[i] == NULL) { 1395 dm_error("DC: failed to create clock sources!\n"); 1396 BREAK_TO_DEBUGGER(); 1397 goto fail; 1398 } 1399 } 1400 1401 pool->base.dmcu = dcn10_dmcu_create(ctx, 1402 &dmcu_regs, 1403 &dmcu_shift, 1404 &dmcu_mask); 1405 if (pool->base.dmcu == NULL) { 1406 dm_error("DC: failed to create dmcu!\n"); 1407 BREAK_TO_DEBUGGER(); 1408 goto fail; 1409 } 1410 1411 pool->base.abm = dce_abm_create(ctx, 1412 &abm_regs, 1413 &abm_shift, 1414 &abm_mask); 1415 if (pool->base.abm == NULL) { 1416 dm_error("DC: failed to create abm!\n"); 1417 BREAK_TO_DEBUGGER(); 1418 goto fail; 1419 } 1420 1421 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1422 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1423 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1424 1425 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1426 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1427 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1428 struct display_mode_lib *dml = &dc->dml; 1429 1430 dml->ip.max_num_dpp = 3; 1431 /* TODO how to handle 23.84? */ 1432 dcn_soc->dram_clock_change_latency = 23; 1433 dcn_ip->max_num_dpp = 3; 1434 } 1435 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1436 dc->dcn_soc->urgent_latency = 3; 1437 dc->debug.disable_dmcu = true; 1438 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1439 } 1440 1441 1442 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1443 ASSERT(dc->dcn_soc->number_of_channels < 3); 1444 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1445 dc->dcn_soc->number_of_channels = 2; 1446 1447 if (dc->dcn_soc->number_of_channels == 1) { 1448 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1449 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1450 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1451 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1452 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1453 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1454 } 1455 } 1456 1457 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1458 1459 /* 1460 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * 1461 * implemented. So AZ D3 should work.For issue 197007. * 1462 */ 1463 if (pool->base.pp_smu != NULL 1464 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) 1465 dc->debug.az_endpoint_mute_only = false; 1466 1467 if (!dc->debug.disable_pplib_clock_request) 1468 dcn_bw_update_from_pplib(dc); 1469 dcn_bw_sync_calcs_and_dml(dc); 1470 if (!dc->debug.disable_pplib_wm_range) { 1471 dc->res_pool = &pool->base; 1472 dcn_bw_notify_pplib_of_wm_ranges(dc); 1473 } 1474 1475 { 1476 struct irq_service_init_data init_data; 1477 init_data.ctx = dc->ctx; 1478 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1479 if (!pool->base.irqs) 1480 goto fail; 1481 } 1482 1483 /* index to valid pipe resource */ 1484 j = 0; 1485 /* mem input -> ipp -> dpp -> opp -> TG */ 1486 for (i = 0; i < pool->base.pipe_count; i++) { 1487 /* if pipe is disabled, skip instance of HW pipe, 1488 * i.e, skip ASIC register instance 1489 */ 1490 if ((pipe_fuses & (1 << i)) != 0) 1491 continue; 1492 1493 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1494 if (pool->base.hubps[j] == NULL) { 1495 BREAK_TO_DEBUGGER(); 1496 dm_error( 1497 "DC: failed to create memory input!\n"); 1498 goto fail; 1499 } 1500 1501 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1502 if (pool->base.ipps[j] == NULL) { 1503 BREAK_TO_DEBUGGER(); 1504 dm_error( 1505 "DC: failed to create input pixel processor!\n"); 1506 goto fail; 1507 } 1508 1509 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1510 if (pool->base.dpps[j] == NULL) { 1511 BREAK_TO_DEBUGGER(); 1512 dm_error( 1513 "DC: failed to create dpp!\n"); 1514 goto fail; 1515 } 1516 1517 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1518 if (pool->base.opps[j] == NULL) { 1519 BREAK_TO_DEBUGGER(); 1520 dm_error( 1521 "DC: failed to create output pixel processor!\n"); 1522 goto fail; 1523 } 1524 1525 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1526 ctx, i); 1527 if (pool->base.timing_generators[j] == NULL) { 1528 BREAK_TO_DEBUGGER(); 1529 dm_error("DC: failed to create tg!\n"); 1530 goto fail; 1531 } 1532 /* check next valid pipe */ 1533 j++; 1534 } 1535 1536 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1537 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1538 if (pool->base.engines[i] == NULL) { 1539 BREAK_TO_DEBUGGER(); 1540 dm_error( 1541 "DC:failed to create aux engine!!\n"); 1542 goto fail; 1543 } 1544 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1545 if (pool->base.hw_i2cs[i] == NULL) { 1546 BREAK_TO_DEBUGGER(); 1547 dm_error( 1548 "DC:failed to create hw i2c!!\n"); 1549 goto fail; 1550 } 1551 pool->base.sw_i2cs[i] = NULL; 1552 } 1553 1554 /* valid pipe num */ 1555 pool->base.pipe_count = j; 1556 pool->base.timing_generator_count = j; 1557 1558 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1559 * the value may be changed 1560 */ 1561 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1562 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1563 1564 pool->base.mpc = dcn10_mpc_create(ctx); 1565 if (pool->base.mpc == NULL) { 1566 BREAK_TO_DEBUGGER(); 1567 dm_error("DC: failed to create mpc!\n"); 1568 goto fail; 1569 } 1570 1571 pool->base.hubbub = dcn10_hubbub_create(ctx); 1572 if (pool->base.hubbub == NULL) { 1573 BREAK_TO_DEBUGGER(); 1574 dm_error("DC: failed to create hubbub!\n"); 1575 goto fail; 1576 } 1577 1578 if (!resource_construct(num_virtual_links, dc, &pool->base, 1579 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1580 &res_create_funcs : &res_create_maximus_funcs))) 1581 goto fail; 1582 1583 dcn10_hw_sequencer_construct(dc); 1584 dc->caps.max_planes = pool->base.pipe_count; 1585 1586 for (i = 0; i < dc->caps.max_planes; ++i) 1587 dc->caps.planes[i] = plane_cap; 1588 1589 dc->cap_funcs = cap_funcs; 1590 1591 return true; 1592 1593 fail: 1594 1595 dcn10_resource_destruct(pool); 1596 1597 return false; 1598 } 1599 1600 struct resource_pool *dcn10_create_resource_pool( 1601 const struct dc_init_data *init_data, 1602 struct dc *dc) 1603 { 1604 struct dcn10_resource_pool *pool = 1605 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1606 1607 if (!pool) 1608 return NULL; 1609 1610 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool)) 1611 return &pool->base; 1612 1613 kfree(pool); 1614 BREAK_TO_DEBUGGER(); 1615 return NULL; 1616 } 1617