1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn10_resource.h" 32 33 #include "dcn10_ipp.h" 34 #include "dcn10_mpc.h" 35 #include "irq/dcn10/irq_service_dcn10.h" 36 #include "dcn10_dpp.h" 37 #include "dcn10_optc.h" 38 #include "dcn10_hw_sequencer.h" 39 #include "dce110/dce110_hw_sequencer.h" 40 #include "dcn10_opp.h" 41 #include "dcn10_link_encoder.h" 42 #include "dcn10_stream_encoder.h" 43 #include "dcn10_clk_mgr.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 157 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 158 #endif 159 }; 160 161 /* begin ********************* 162 * macros to expend register list macro defined in HW object header file */ 163 164 /* DCN */ 165 #define BASE_INNER(seg) \ 166 DCE_BASE__INST0_SEG ## seg 167 168 #define BASE(seg) \ 169 BASE_INNER(seg) 170 171 #define SR(reg_name)\ 172 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 173 mm ## reg_name 174 175 #define SRI(reg_name, block, id)\ 176 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 mm ## block ## id ## _ ## reg_name 178 179 180 #define SRII(reg_name, block, id)\ 181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 mm ## block ## id ## _ ## reg_name 183 184 /* NBIO */ 185 #define NBIO_BASE_INNER(seg) \ 186 NBIF_BASE__INST0_SEG ## seg 187 188 #define NBIO_BASE(seg) \ 189 NBIO_BASE_INNER(seg) 190 191 #define NBIO_SR(reg_name)\ 192 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 193 mm ## reg_name 194 195 /* MMHUB */ 196 #define MMHUB_BASE_INNER(seg) \ 197 MMHUB_BASE__INST0_SEG ## seg 198 199 #define MMHUB_BASE(seg) \ 200 MMHUB_BASE_INNER(seg) 201 202 #define MMHUB_SR(reg_name)\ 203 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 204 mm ## reg_name 205 /* macros to expend register list macro defined in HW object header file 206 * end *********************/ 207 208 209 static const struct dce_dmcu_registers dmcu_regs = { 210 DMCU_DCN10_REG_LIST() 211 }; 212 213 static const struct dce_dmcu_shift dmcu_shift = { 214 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 215 }; 216 217 static const struct dce_dmcu_mask dmcu_mask = { 218 DMCU_MASK_SH_LIST_DCN10(_MASK) 219 }; 220 221 static const struct dce_abm_registers abm_regs = { 222 ABM_DCN10_REG_LIST(0) 223 }; 224 225 static const struct dce_abm_shift abm_shift = { 226 ABM_MASK_SH_LIST_DCN10(__SHIFT) 227 }; 228 229 static const struct dce_abm_mask abm_mask = { 230 ABM_MASK_SH_LIST_DCN10(_MASK) 231 }; 232 233 #define stream_enc_regs(id)\ 234 [id] = {\ 235 SE_DCN_REG_LIST(id)\ 236 } 237 238 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 239 stream_enc_regs(0), 240 stream_enc_regs(1), 241 stream_enc_regs(2), 242 stream_enc_regs(3), 243 }; 244 245 static const struct dcn10_stream_encoder_shift se_shift = { 246 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 247 }; 248 249 static const struct dcn10_stream_encoder_mask se_mask = { 250 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 251 }; 252 253 #define audio_regs(id)\ 254 [id] = {\ 255 AUD_COMMON_REG_LIST(id)\ 256 } 257 258 static const struct dce_audio_registers audio_regs[] = { 259 audio_regs(0), 260 audio_regs(1), 261 audio_regs(2), 262 audio_regs(3), 263 }; 264 265 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 266 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 267 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 268 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 269 270 static const struct dce_audio_shift audio_shift = { 271 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dce_aduio_mask audio_mask = { 275 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 276 }; 277 278 #define aux_regs(id)\ 279 [id] = {\ 280 AUX_REG_LIST(id)\ 281 } 282 283 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 284 aux_regs(0), 285 aux_regs(1), 286 aux_regs(2), 287 aux_regs(3) 288 }; 289 290 #define hpd_regs(id)\ 291 [id] = {\ 292 HPD_REG_LIST(id)\ 293 } 294 295 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 296 hpd_regs(0), 297 hpd_regs(1), 298 hpd_regs(2), 299 hpd_regs(3) 300 }; 301 302 #define link_regs(id)\ 303 [id] = {\ 304 LE_DCN10_REG_LIST(id), \ 305 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 306 } 307 308 static const struct dcn10_link_enc_registers link_enc_regs[] = { 309 link_regs(0), 310 link_regs(1), 311 link_regs(2), 312 link_regs(3) 313 }; 314 315 static const struct dcn10_link_enc_shift le_shift = { 316 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 317 }; 318 319 static const struct dcn10_link_enc_mask le_mask = { 320 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 321 }; 322 323 #define ipp_regs(id)\ 324 [id] = {\ 325 IPP_REG_LIST_DCN10(id),\ 326 } 327 328 static const struct dcn10_ipp_registers ipp_regs[] = { 329 ipp_regs(0), 330 ipp_regs(1), 331 ipp_regs(2), 332 ipp_regs(3), 333 }; 334 335 static const struct dcn10_ipp_shift ipp_shift = { 336 IPP_MASK_SH_LIST_DCN10(__SHIFT) 337 }; 338 339 static const struct dcn10_ipp_mask ipp_mask = { 340 IPP_MASK_SH_LIST_DCN10(_MASK), 341 }; 342 343 #define opp_regs(id)\ 344 [id] = {\ 345 OPP_REG_LIST_DCN10(id),\ 346 } 347 348 static const struct dcn10_opp_registers opp_regs[] = { 349 opp_regs(0), 350 opp_regs(1), 351 opp_regs(2), 352 opp_regs(3), 353 }; 354 355 static const struct dcn10_opp_shift opp_shift = { 356 OPP_MASK_SH_LIST_DCN10(__SHIFT) 357 }; 358 359 static const struct dcn10_opp_mask opp_mask = { 360 OPP_MASK_SH_LIST_DCN10(_MASK), 361 }; 362 363 #define aux_engine_regs(id)\ 364 [id] = {\ 365 AUX_COMMON_REG_LIST(id), \ 366 .AUX_RESET_MASK = 0 \ 367 } 368 369 static const struct dce110_aux_registers aux_engine_regs[] = { 370 aux_engine_regs(0), 371 aux_engine_regs(1), 372 aux_engine_regs(2), 373 aux_engine_regs(3), 374 aux_engine_regs(4), 375 aux_engine_regs(5) 376 }; 377 378 #define tf_regs(id)\ 379 [id] = {\ 380 TF_REG_LIST_DCN10(id),\ 381 } 382 383 static const struct dcn_dpp_registers tf_regs[] = { 384 tf_regs(0), 385 tf_regs(1), 386 tf_regs(2), 387 tf_regs(3), 388 }; 389 390 static const struct dcn_dpp_shift tf_shift = { 391 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 392 TF_DEBUG_REG_LIST_SH_DCN10 393 394 }; 395 396 static const struct dcn_dpp_mask tf_mask = { 397 TF_REG_LIST_SH_MASK_DCN10(_MASK), 398 TF_DEBUG_REG_LIST_MASK_DCN10 399 }; 400 401 static const struct dcn_mpc_registers mpc_regs = { 402 MPC_COMMON_REG_LIST_DCN1_0(0), 403 MPC_COMMON_REG_LIST_DCN1_0(1), 404 MPC_COMMON_REG_LIST_DCN1_0(2), 405 MPC_COMMON_REG_LIST_DCN1_0(3), 406 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 407 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 408 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 409 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 410 }; 411 412 static const struct dcn_mpc_shift mpc_shift = { 413 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 414 }; 415 416 static const struct dcn_mpc_mask mpc_mask = { 417 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 418 }; 419 420 #define tg_regs(id)\ 421 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 422 423 static const struct dcn_optc_registers tg_regs[] = { 424 tg_regs(0), 425 tg_regs(1), 426 tg_regs(2), 427 tg_regs(3), 428 }; 429 430 static const struct dcn_optc_shift tg_shift = { 431 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 432 }; 433 434 static const struct dcn_optc_mask tg_mask = { 435 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 436 }; 437 438 static const struct bios_registers bios_regs = { 439 NBIO_SR(BIOS_SCRATCH_0), 440 NBIO_SR(BIOS_SCRATCH_3), 441 NBIO_SR(BIOS_SCRATCH_6) 442 }; 443 444 #define hubp_regs(id)\ 445 [id] = {\ 446 HUBP_REG_LIST_DCN10(id)\ 447 } 448 449 450 static const struct dcn_mi_registers hubp_regs[] = { 451 hubp_regs(0), 452 hubp_regs(1), 453 hubp_regs(2), 454 hubp_regs(3), 455 }; 456 457 static const struct dcn_mi_shift hubp_shift = { 458 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 459 }; 460 461 static const struct dcn_mi_mask hubp_mask = { 462 HUBP_MASK_SH_LIST_DCN10(_MASK) 463 }; 464 465 466 static const struct dcn_hubbub_registers hubbub_reg = { 467 HUBBUB_REG_LIST_DCN10(0) 468 }; 469 470 static const struct dcn_hubbub_shift hubbub_shift = { 471 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 472 }; 473 474 static const struct dcn_hubbub_mask hubbub_mask = { 475 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 476 }; 477 478 #define clk_src_regs(index, pllid)\ 479 [index] = {\ 480 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 481 } 482 483 static const struct dce110_clk_src_regs clk_src_regs[] = { 484 clk_src_regs(0, A), 485 clk_src_regs(1, B), 486 clk_src_regs(2, C), 487 clk_src_regs(3, D) 488 }; 489 490 static const struct dce110_clk_src_shift cs_shift = { 491 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 492 }; 493 494 static const struct dce110_clk_src_mask cs_mask = { 495 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 496 }; 497 498 static const struct resource_caps res_cap = { 499 .num_timing_generator = 4, 500 .num_opp = 4, 501 .num_video_plane = 4, 502 .num_audio = 4, 503 .num_stream_encoder = 4, 504 .num_pll = 4, 505 .num_ddc = 4, 506 }; 507 508 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 509 static const struct resource_caps rv2_res_cap = { 510 .num_timing_generator = 3, 511 .num_opp = 3, 512 .num_video_plane = 3, 513 .num_audio = 3, 514 .num_stream_encoder = 3, 515 .num_pll = 3, 516 .num_ddc = 3, 517 }; 518 #endif 519 520 static const struct dc_debug_options debug_defaults_drv = { 521 .sanity_checks = true, 522 .disable_dmcu = true, 523 .force_abm_enable = false, 524 .timing_trace = false, 525 .clock_trace = true, 526 527 /* raven smu dones't allow 0 disp clk, 528 * smu min disp clk limit is 50Mhz 529 * keep min disp clk 100Mhz avoid smu hang 530 */ 531 .min_disp_clk_khz = 100000, 532 533 .disable_pplib_clock_request = false, 534 .disable_pplib_wm_range = false, 535 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 536 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 537 .force_single_disp_pipe_split = true, 538 .disable_dcc = DCC_ENABLE, 539 .voltage_align_fclk = true, 540 .disable_stereo_support = true, 541 .vsr_support = true, 542 .performance_trace = false, 543 .az_endpoint_mute_only = true, 544 .recovery_enabled = false, /*enable this by default after testing.*/ 545 .max_downscale_src_width = 3840, 546 }; 547 548 static const struct dc_debug_options debug_defaults_diags = { 549 .disable_dmcu = true, 550 .force_abm_enable = false, 551 .timing_trace = true, 552 .clock_trace = true, 553 .disable_stutter = true, 554 .disable_pplib_clock_request = true, 555 .disable_pplib_wm_range = true 556 }; 557 558 static void dcn10_dpp_destroy(struct dpp **dpp) 559 { 560 kfree(TO_DCN10_DPP(*dpp)); 561 *dpp = NULL; 562 } 563 564 static struct dpp *dcn10_dpp_create( 565 struct dc_context *ctx, 566 uint32_t inst) 567 { 568 struct dcn10_dpp *dpp = 569 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 570 571 if (!dpp) 572 return NULL; 573 574 dpp1_construct(dpp, ctx, inst, 575 &tf_regs[inst], &tf_shift, &tf_mask); 576 return &dpp->base; 577 } 578 579 static struct input_pixel_processor *dcn10_ipp_create( 580 struct dc_context *ctx, uint32_t inst) 581 { 582 struct dcn10_ipp *ipp = 583 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 584 585 if (!ipp) { 586 BREAK_TO_DEBUGGER(); 587 return NULL; 588 } 589 590 dcn10_ipp_construct(ipp, ctx, inst, 591 &ipp_regs[inst], &ipp_shift, &ipp_mask); 592 return &ipp->base; 593 } 594 595 596 static struct output_pixel_processor *dcn10_opp_create( 597 struct dc_context *ctx, uint32_t inst) 598 { 599 struct dcn10_opp *opp = 600 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 601 602 if (!opp) { 603 BREAK_TO_DEBUGGER(); 604 return NULL; 605 } 606 607 dcn10_opp_construct(opp, ctx, inst, 608 &opp_regs[inst], &opp_shift, &opp_mask); 609 return &opp->base; 610 } 611 612 struct aux_engine *dcn10_aux_engine_create( 613 struct dc_context *ctx, 614 uint32_t inst) 615 { 616 struct aux_engine_dce110 *aux_engine = 617 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 618 619 if (!aux_engine) 620 return NULL; 621 622 dce110_aux_engine_construct(aux_engine, ctx, inst, 623 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 624 &aux_engine_regs[inst]); 625 626 return &aux_engine->base; 627 } 628 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 629 630 static const struct dce_i2c_registers i2c_hw_regs[] = { 631 i2c_inst_regs(1), 632 i2c_inst_regs(2), 633 i2c_inst_regs(3), 634 i2c_inst_regs(4), 635 i2c_inst_regs(5), 636 i2c_inst_regs(6), 637 }; 638 639 static const struct dce_i2c_shift i2c_shifts = { 640 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 641 }; 642 643 static const struct dce_i2c_mask i2c_masks = { 644 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 645 }; 646 647 struct dce_i2c_hw *dcn10_i2c_hw_create( 648 struct dc_context *ctx, 649 uint32_t inst) 650 { 651 struct dce_i2c_hw *dce_i2c_hw = 652 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 653 654 if (!dce_i2c_hw) 655 return NULL; 656 657 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 658 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 659 660 return dce_i2c_hw; 661 } 662 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 663 { 664 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 665 GFP_KERNEL); 666 667 if (!mpc10) 668 return NULL; 669 670 dcn10_mpc_construct(mpc10, ctx, 671 &mpc_regs, 672 &mpc_shift, 673 &mpc_mask, 674 4); 675 676 return &mpc10->base; 677 } 678 679 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 680 { 681 struct hubbub *hubbub = kzalloc(sizeof(struct hubbub), 682 GFP_KERNEL); 683 684 if (!hubbub) 685 return NULL; 686 687 hubbub1_construct(hubbub, ctx, 688 &hubbub_reg, 689 &hubbub_shift, 690 &hubbub_mask); 691 692 return hubbub; 693 } 694 695 static struct timing_generator *dcn10_timing_generator_create( 696 struct dc_context *ctx, 697 uint32_t instance) 698 { 699 struct optc *tgn10 = 700 kzalloc(sizeof(struct optc), GFP_KERNEL); 701 702 if (!tgn10) 703 return NULL; 704 705 tgn10->base.inst = instance; 706 tgn10->base.ctx = ctx; 707 708 tgn10->tg_regs = &tg_regs[instance]; 709 tgn10->tg_shift = &tg_shift; 710 tgn10->tg_mask = &tg_mask; 711 712 dcn10_timing_generator_init(tgn10); 713 714 return &tgn10->base; 715 } 716 717 static const struct encoder_feature_support link_enc_feature = { 718 .max_hdmi_deep_color = COLOR_DEPTH_121212, 719 .max_hdmi_pixel_clock = 600000, 720 .hdmi_ycbcr420_supported = true, 721 .dp_ycbcr420_supported = false, 722 .flags.bits.IS_HBR2_CAPABLE = true, 723 .flags.bits.IS_HBR3_CAPABLE = true, 724 .flags.bits.IS_TPS3_CAPABLE = true, 725 .flags.bits.IS_TPS4_CAPABLE = true 726 }; 727 728 struct link_encoder *dcn10_link_encoder_create( 729 const struct encoder_init_data *enc_init_data) 730 { 731 struct dcn10_link_encoder *enc10 = 732 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 733 734 if (!enc10) 735 return NULL; 736 737 dcn10_link_encoder_construct(enc10, 738 enc_init_data, 739 &link_enc_feature, 740 &link_enc_regs[enc_init_data->transmitter], 741 &link_enc_aux_regs[enc_init_data->channel - 1], 742 &link_enc_hpd_regs[enc_init_data->hpd_source], 743 &le_shift, 744 &le_mask); 745 746 return &enc10->base; 747 } 748 749 struct clock_source *dcn10_clock_source_create( 750 struct dc_context *ctx, 751 struct dc_bios *bios, 752 enum clock_source_id id, 753 const struct dce110_clk_src_regs *regs, 754 bool dp_clk_src) 755 { 756 struct dce110_clk_src *clk_src = 757 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 758 759 if (!clk_src) 760 return NULL; 761 762 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 763 regs, &cs_shift, &cs_mask)) { 764 clk_src->base.dp_clk_src = dp_clk_src; 765 return &clk_src->base; 766 } 767 768 BREAK_TO_DEBUGGER(); 769 return NULL; 770 } 771 772 static void read_dce_straps( 773 struct dc_context *ctx, 774 struct resource_straps *straps) 775 { 776 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 777 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 778 } 779 780 static struct audio *create_audio( 781 struct dc_context *ctx, unsigned int inst) 782 { 783 return dce_audio_create(ctx, inst, 784 &audio_regs[inst], &audio_shift, &audio_mask); 785 } 786 787 static struct stream_encoder *dcn10_stream_encoder_create( 788 enum engine_id eng_id, 789 struct dc_context *ctx) 790 { 791 struct dcn10_stream_encoder *enc1 = 792 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 793 794 if (!enc1) 795 return NULL; 796 797 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 798 &stream_enc_regs[eng_id], 799 &se_shift, &se_mask); 800 return &enc1->base; 801 } 802 803 static const struct dce_hwseq_registers hwseq_reg = { 804 HWSEQ_DCN1_REG_LIST() 805 }; 806 807 static const struct dce_hwseq_shift hwseq_shift = { 808 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 809 }; 810 811 static const struct dce_hwseq_mask hwseq_mask = { 812 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 813 }; 814 815 static struct dce_hwseq *dcn10_hwseq_create( 816 struct dc_context *ctx) 817 { 818 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 819 820 if (hws) { 821 hws->ctx = ctx; 822 hws->regs = &hwseq_reg; 823 hws->shifts = &hwseq_shift; 824 hws->masks = &hwseq_mask; 825 hws->wa.DEGVIDCN10_253 = true; 826 hws->wa.false_optc_underflow = true; 827 hws->wa.DEGVIDCN10_254 = true; 828 } 829 return hws; 830 } 831 832 static const struct resource_create_funcs res_create_funcs = { 833 .read_dce_straps = read_dce_straps, 834 .create_audio = create_audio, 835 .create_stream_encoder = dcn10_stream_encoder_create, 836 .create_hwseq = dcn10_hwseq_create, 837 }; 838 839 static const struct resource_create_funcs res_create_maximus_funcs = { 840 .read_dce_straps = NULL, 841 .create_audio = NULL, 842 .create_stream_encoder = NULL, 843 .create_hwseq = dcn10_hwseq_create, 844 }; 845 846 void dcn10_clock_source_destroy(struct clock_source **clk_src) 847 { 848 kfree(TO_DCE110_CLK_SRC(*clk_src)); 849 *clk_src = NULL; 850 } 851 852 static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) 853 { 854 struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 855 856 if (!pp_smu) 857 return pp_smu; 858 859 dm_pp_get_funcs_rv(ctx, pp_smu); 860 return pp_smu; 861 } 862 863 static void destruct(struct dcn10_resource_pool *pool) 864 { 865 unsigned int i; 866 867 for (i = 0; i < pool->base.stream_enc_count; i++) { 868 if (pool->base.stream_enc[i] != NULL) { 869 /* TODO: free dcn version of stream encoder once implemented 870 * rather than using virtual stream encoder 871 */ 872 kfree(pool->base.stream_enc[i]); 873 pool->base.stream_enc[i] = NULL; 874 } 875 } 876 877 if (pool->base.mpc != NULL) { 878 kfree(TO_DCN10_MPC(pool->base.mpc)); 879 pool->base.mpc = NULL; 880 } 881 882 if (pool->base.hubbub != NULL) { 883 kfree(pool->base.hubbub); 884 pool->base.hubbub = NULL; 885 } 886 887 for (i = 0; i < pool->base.pipe_count; i++) { 888 if (pool->base.opps[i] != NULL) 889 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 890 891 if (pool->base.dpps[i] != NULL) 892 dcn10_dpp_destroy(&pool->base.dpps[i]); 893 894 if (pool->base.ipps[i] != NULL) 895 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 896 897 if (pool->base.hubps[i] != NULL) { 898 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 899 pool->base.hubps[i] = NULL; 900 } 901 902 if (pool->base.irqs != NULL) { 903 dal_irq_service_destroy(&pool->base.irqs); 904 } 905 906 if (pool->base.timing_generators[i] != NULL) { 907 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 908 pool->base.timing_generators[i] = NULL; 909 } 910 } 911 912 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 913 if (pool->base.engines[i] != NULL) 914 pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]); 915 if (pool->base.hw_i2cs[i] != NULL) { 916 kfree(pool->base.hw_i2cs[i]); 917 pool->base.hw_i2cs[i] = NULL; 918 } 919 if (pool->base.sw_i2cs[i] != NULL) { 920 kfree(pool->base.sw_i2cs[i]); 921 pool->base.sw_i2cs[i] = NULL; 922 } 923 } 924 925 for (i = 0; i < pool->base.stream_enc_count; i++) 926 kfree(pool->base.stream_enc[i]); 927 928 for (i = 0; i < pool->base.audio_count; i++) { 929 if (pool->base.audios[i]) 930 dce_aud_destroy(&pool->base.audios[i]); 931 } 932 933 for (i = 0; i < pool->base.clk_src_count; i++) { 934 if (pool->base.clock_sources[i] != NULL) { 935 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 936 pool->base.clock_sources[i] = NULL; 937 } 938 } 939 940 if (pool->base.dp_clock_source != NULL) { 941 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 942 pool->base.dp_clock_source = NULL; 943 } 944 945 if (pool->base.abm != NULL) 946 dce_abm_destroy(&pool->base.abm); 947 948 if (pool->base.dmcu != NULL) 949 dce_dmcu_destroy(&pool->base.dmcu); 950 951 if (pool->base.clk_mgr != NULL) 952 dce_clk_mgr_destroy(&pool->base.clk_mgr); 953 954 kfree(pool->base.pp_smu); 955 } 956 957 static struct hubp *dcn10_hubp_create( 958 struct dc_context *ctx, 959 uint32_t inst) 960 { 961 struct dcn10_hubp *hubp1 = 962 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 963 964 if (!hubp1) 965 return NULL; 966 967 dcn10_hubp_construct(hubp1, ctx, inst, 968 &hubp_regs[inst], &hubp_shift, &hubp_mask); 969 return &hubp1->base; 970 } 971 972 static void get_pixel_clock_parameters( 973 const struct pipe_ctx *pipe_ctx, 974 struct pixel_clk_params *pixel_clk_params) 975 { 976 const struct dc_stream_state *stream = pipe_ctx->stream; 977 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 978 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 979 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 980 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 981 /* TODO: un-hardcode*/ 982 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 983 LINK_RATE_REF_FREQ_IN_KHZ; 984 pixel_clk_params->flags.ENABLE_SS = 0; 985 pixel_clk_params->color_depth = 986 stream->timing.display_color_depth; 987 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 988 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 989 990 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 991 pixel_clk_params->color_depth = COLOR_DEPTH_888; 992 993 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 994 pixel_clk_params->requested_pix_clk /= 2; 995 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 996 pixel_clk_params->requested_pix_clk *= 2; 997 998 } 999 1000 static void build_clamping_params(struct dc_stream_state *stream) 1001 { 1002 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1003 stream->clamping.c_depth = stream->timing.display_color_depth; 1004 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1005 } 1006 1007 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1008 { 1009 1010 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1011 1012 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1013 pipe_ctx->clock_source, 1014 &pipe_ctx->stream_res.pix_clk_params, 1015 &pipe_ctx->pll_settings); 1016 1017 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1018 1019 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1020 &pipe_ctx->stream->bit_depth_params); 1021 build_clamping_params(pipe_ctx->stream); 1022 } 1023 1024 static enum dc_status build_mapped_resource( 1025 const struct dc *dc, 1026 struct dc_state *context, 1027 struct dc_stream_state *stream) 1028 { 1029 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1030 1031 /*TODO Seems unneeded anymore */ 1032 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1033 if (stream != NULL && old_context->streams[i] != NULL) { 1034 todo: shouldn't have to copy missing parameter here 1035 resource_build_bit_depth_reduction_params(stream, 1036 &stream->bit_depth_params); 1037 stream->clamping.pixel_encoding = 1038 stream->timing.pixel_encoding; 1039 1040 resource_build_bit_depth_reduction_params(stream, 1041 &stream->bit_depth_params); 1042 build_clamping_params(stream); 1043 1044 continue; 1045 } 1046 } 1047 */ 1048 1049 if (!pipe_ctx) 1050 return DC_ERROR_UNEXPECTED; 1051 1052 build_pipe_hw_param(pipe_ctx); 1053 return DC_OK; 1054 } 1055 1056 enum dc_status dcn10_add_stream_to_ctx( 1057 struct dc *dc, 1058 struct dc_state *new_ctx, 1059 struct dc_stream_state *dc_stream) 1060 { 1061 enum dc_status result = DC_ERROR_UNEXPECTED; 1062 1063 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1064 1065 if (result == DC_OK) 1066 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1067 1068 1069 if (result == DC_OK) 1070 result = build_mapped_resource(dc, new_ctx, dc_stream); 1071 1072 return result; 1073 } 1074 1075 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1076 struct dc_state *context, 1077 const struct resource_pool *pool, 1078 struct dc_stream_state *stream) 1079 { 1080 struct resource_context *res_ctx = &context->res_ctx; 1081 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1082 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool); 1083 1084 if (!head_pipe) { 1085 ASSERT(0); 1086 return NULL; 1087 } 1088 1089 if (!idle_pipe) 1090 return NULL; 1091 1092 idle_pipe->stream = head_pipe->stream; 1093 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1094 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1095 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1096 1097 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1098 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1099 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1100 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1101 1102 return idle_pipe; 1103 } 1104 1105 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1106 const struct dc_dcc_surface_param *input, 1107 struct dc_surface_dcc_cap *output) 1108 { 1109 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1110 dc->res_pool->hubbub, 1111 input, 1112 output); 1113 } 1114 1115 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1116 { 1117 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1118 1119 destruct(dcn10_pool); 1120 kfree(dcn10_pool); 1121 *pool = NULL; 1122 } 1123 1124 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1125 { 1126 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1127 && caps->max_video_width != 0 1128 && plane_state->src_rect.width > caps->max_video_width) 1129 return DC_FAIL_SURFACE_VALIDATE; 1130 1131 return DC_OK; 1132 } 1133 1134 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1135 { 1136 enum dc_status result = DC_OK; 1137 1138 enum surface_pixel_format surf_pix_format = plane_state->format; 1139 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1140 1141 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1142 1143 if (bpp == 64) 1144 swizzle = DC_SW_64KB_D; 1145 else 1146 swizzle = DC_SW_64KB_S; 1147 1148 plane_state->tiling_info.gfx9.swizzle = swizzle; 1149 return result; 1150 } 1151 1152 static const struct dc_cap_funcs cap_funcs = { 1153 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1154 }; 1155 1156 static const struct resource_funcs dcn10_res_pool_funcs = { 1157 .destroy = dcn10_destroy_resource_pool, 1158 .link_enc_create = dcn10_link_encoder_create, 1159 .validate_bandwidth = dcn_validate_bandwidth, 1160 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1161 .validate_plane = dcn10_validate_plane, 1162 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1163 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode 1164 }; 1165 1166 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1167 { 1168 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1169 /* RV1 support max 4 pipes */ 1170 value = value & 0xf; 1171 return value; 1172 } 1173 1174 static bool construct( 1175 uint8_t num_virtual_links, 1176 struct dc *dc, 1177 struct dcn10_resource_pool *pool) 1178 { 1179 int i; 1180 int j; 1181 struct dc_context *ctx = dc->ctx; 1182 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1183 1184 ctx->dc_bios->regs = &bios_regs; 1185 1186 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1187 if (ctx->dce_version == DCN_VERSION_1_01) 1188 pool->base.res_cap = &rv2_res_cap; 1189 else 1190 #endif 1191 pool->base.res_cap = &res_cap; 1192 pool->base.funcs = &dcn10_res_pool_funcs; 1193 1194 /* 1195 * TODO fill in from actual raven resource when we create 1196 * more than virtual encoder 1197 */ 1198 1199 /************************************************* 1200 * Resource + asic cap harcoding * 1201 *************************************************/ 1202 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1203 1204 /* max pipe num for ASIC before check pipe fuses */ 1205 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1206 1207 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1208 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1209 pool->base.pipe_count = 3; 1210 #endif 1211 dc->caps.max_video_width = 3840; 1212 dc->caps.max_downscale_ratio = 200; 1213 dc->caps.i2c_speed_in_khz = 100; 1214 dc->caps.max_cursor_size = 256; 1215 dc->caps.max_slave_planes = 1; 1216 dc->caps.is_apu = true; 1217 dc->caps.post_blend_color_processing = false; 1218 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1219 dc->caps.force_dp_tps4_for_cp2520 = true; 1220 1221 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1222 dc->debug = debug_defaults_drv; 1223 else 1224 dc->debug = debug_defaults_diags; 1225 1226 /************************************************* 1227 * Create resources * 1228 *************************************************/ 1229 1230 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1231 dcn10_clock_source_create(ctx, ctx->dc_bios, 1232 CLOCK_SOURCE_COMBO_PHY_PLL0, 1233 &clk_src_regs[0], false); 1234 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1235 dcn10_clock_source_create(ctx, ctx->dc_bios, 1236 CLOCK_SOURCE_COMBO_PHY_PLL1, 1237 &clk_src_regs[1], false); 1238 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1239 dcn10_clock_source_create(ctx, ctx->dc_bios, 1240 CLOCK_SOURCE_COMBO_PHY_PLL2, 1241 &clk_src_regs[2], false); 1242 1243 #ifdef CONFIG_DRM_AMD_DC_DCN1_01 1244 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1245 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1246 dcn10_clock_source_create(ctx, ctx->dc_bios, 1247 CLOCK_SOURCE_COMBO_PHY_PLL3, 1248 &clk_src_regs[3], false); 1249 } 1250 #else 1251 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1252 dcn10_clock_source_create(ctx, ctx->dc_bios, 1253 CLOCK_SOURCE_COMBO_PHY_PLL3, 1254 &clk_src_regs[3], false); 1255 #endif 1256 1257 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1258 1259 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1260 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1261 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1262 #endif 1263 1264 pool->base.dp_clock_source = 1265 dcn10_clock_source_create(ctx, ctx->dc_bios, 1266 CLOCK_SOURCE_ID_DP_DTO, 1267 /* todo: not reuse phy_pll registers */ 1268 &clk_src_regs[0], true); 1269 1270 for (i = 0; i < pool->base.clk_src_count; i++) { 1271 if (pool->base.clock_sources[i] == NULL) { 1272 dm_error("DC: failed to create clock sources!\n"); 1273 BREAK_TO_DEBUGGER(); 1274 goto fail; 1275 } 1276 } 1277 pool->base.clk_mgr = dcn1_clk_mgr_create(ctx); 1278 if (pool->base.clk_mgr == NULL) { 1279 dm_error("DC: failed to create display clock!\n"); 1280 BREAK_TO_DEBUGGER(); 1281 goto fail; 1282 } 1283 1284 pool->base.dmcu = dcn10_dmcu_create(ctx, 1285 &dmcu_regs, 1286 &dmcu_shift, 1287 &dmcu_mask); 1288 if (pool->base.dmcu == NULL) { 1289 dm_error("DC: failed to create dmcu!\n"); 1290 BREAK_TO_DEBUGGER(); 1291 goto fail; 1292 } 1293 1294 pool->base.abm = dce_abm_create(ctx, 1295 &abm_regs, 1296 &abm_shift, 1297 &abm_mask); 1298 if (pool->base.abm == NULL) { 1299 dm_error("DC: failed to create abm!\n"); 1300 BREAK_TO_DEBUGGER(); 1301 goto fail; 1302 } 1303 1304 dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1); 1305 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1306 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1307 1308 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1309 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1310 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1311 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1312 struct display_mode_lib *dml = &dc->dml; 1313 1314 dml->ip.max_num_dpp = 3; 1315 /* TODO how to handle 23.84? */ 1316 dcn_soc->dram_clock_change_latency = 23; 1317 dcn_ip->max_num_dpp = 3; 1318 } 1319 #endif 1320 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1321 dc->dcn_soc->urgent_latency = 3; 1322 dc->debug.disable_dmcu = true; 1323 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1324 } 1325 1326 1327 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1328 ASSERT(dc->dcn_soc->number_of_channels < 3); 1329 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1330 dc->dcn_soc->number_of_channels = 2; 1331 1332 if (dc->dcn_soc->number_of_channels == 1) { 1333 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1334 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1335 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1336 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1337 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1338 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1339 } 1340 } 1341 1342 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1343 1344 if (!dc->debug.disable_pplib_clock_request) 1345 dcn_bw_update_from_pplib(dc); 1346 dcn_bw_sync_calcs_and_dml(dc); 1347 if (!dc->debug.disable_pplib_wm_range) { 1348 dc->res_pool = &pool->base; 1349 dcn_bw_notify_pplib_of_wm_ranges(dc); 1350 } 1351 1352 { 1353 struct irq_service_init_data init_data; 1354 init_data.ctx = dc->ctx; 1355 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1356 if (!pool->base.irqs) 1357 goto fail; 1358 } 1359 1360 /* index to valid pipe resource */ 1361 j = 0; 1362 /* mem input -> ipp -> dpp -> opp -> TG */ 1363 for (i = 0; i < pool->base.pipe_count; i++) { 1364 /* if pipe is disabled, skip instance of HW pipe, 1365 * i.e, skip ASIC register instance 1366 */ 1367 if ((pipe_fuses & (1 << i)) != 0) 1368 continue; 1369 1370 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1371 if (pool->base.hubps[j] == NULL) { 1372 BREAK_TO_DEBUGGER(); 1373 dm_error( 1374 "DC: failed to create memory input!\n"); 1375 goto fail; 1376 } 1377 1378 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1379 if (pool->base.ipps[j] == NULL) { 1380 BREAK_TO_DEBUGGER(); 1381 dm_error( 1382 "DC: failed to create input pixel processor!\n"); 1383 goto fail; 1384 } 1385 1386 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1387 if (pool->base.dpps[j] == NULL) { 1388 BREAK_TO_DEBUGGER(); 1389 dm_error( 1390 "DC: failed to create dpp!\n"); 1391 goto fail; 1392 } 1393 1394 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1395 if (pool->base.opps[j] == NULL) { 1396 BREAK_TO_DEBUGGER(); 1397 dm_error( 1398 "DC: failed to create output pixel processor!\n"); 1399 goto fail; 1400 } 1401 1402 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1403 ctx, i); 1404 if (pool->base.timing_generators[j] == NULL) { 1405 BREAK_TO_DEBUGGER(); 1406 dm_error("DC: failed to create tg!\n"); 1407 goto fail; 1408 } 1409 /* check next valid pipe */ 1410 j++; 1411 } 1412 1413 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1414 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1415 if (pool->base.engines[i] == NULL) { 1416 BREAK_TO_DEBUGGER(); 1417 dm_error( 1418 "DC:failed to create aux engine!!\n"); 1419 goto fail; 1420 } 1421 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1422 if (pool->base.hw_i2cs[i] == NULL) { 1423 BREAK_TO_DEBUGGER(); 1424 dm_error( 1425 "DC:failed to create hw i2c!!\n"); 1426 goto fail; 1427 } 1428 pool->base.sw_i2cs[i] = NULL; 1429 } 1430 1431 /* valid pipe num */ 1432 pool->base.pipe_count = j; 1433 pool->base.timing_generator_count = j; 1434 1435 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1436 * the value may be changed 1437 */ 1438 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1439 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1440 1441 pool->base.mpc = dcn10_mpc_create(ctx); 1442 if (pool->base.mpc == NULL) { 1443 BREAK_TO_DEBUGGER(); 1444 dm_error("DC: failed to create mpc!\n"); 1445 goto fail; 1446 } 1447 1448 pool->base.hubbub = dcn10_hubbub_create(ctx); 1449 if (pool->base.hubbub == NULL) { 1450 BREAK_TO_DEBUGGER(); 1451 dm_error("DC: failed to create hubbub!\n"); 1452 goto fail; 1453 } 1454 1455 if (!resource_construct(num_virtual_links, dc, &pool->base, 1456 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1457 &res_create_funcs : &res_create_maximus_funcs))) 1458 goto fail; 1459 1460 dcn10_hw_sequencer_construct(dc); 1461 dc->caps.max_planes = pool->base.pipe_count; 1462 1463 dc->cap_funcs = cap_funcs; 1464 1465 return true; 1466 1467 fail: 1468 1469 destruct(pool); 1470 1471 return false; 1472 } 1473 1474 struct resource_pool *dcn10_create_resource_pool( 1475 uint8_t num_virtual_links, 1476 struct dc *dc) 1477 { 1478 struct dcn10_resource_pool *pool = 1479 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1480 1481 if (!pool) 1482 return NULL; 1483 1484 if (construct(num_virtual_links, dc, pool)) 1485 return &pool->base; 1486 1487 BREAK_TO_DEBUGGER(); 1488 return NULL; 1489 } 1490