1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "dcn10_init.h" 32 33 #include "resource.h" 34 #include "include/irq_service_interface.h" 35 #include "dcn10_resource.h" 36 #include "dcn10_ipp.h" 37 #include "dcn10_mpc.h" 38 #include "irq/dcn10/irq_service_dcn10.h" 39 #include "dcn10_dpp.h" 40 #include "dcn10_optc.h" 41 #include "dcn10_hw_sequencer.h" 42 #include "dce110/dce110_hw_sequencer.h" 43 #include "dcn10_opp.h" 44 #include "dcn10_link_encoder.h" 45 #include "dcn10_stream_encoder.h" 46 #include "dce/dce_clock_source.h" 47 #include "dce/dce_audio.h" 48 #include "dce/dce_hwseq.h" 49 #include "virtual/virtual_stream_encoder.h" 50 #include "dce110/dce110_resource.h" 51 #include "dce112/dce112_resource.h" 52 #include "dcn10_hubp.h" 53 #include "dcn10_hubbub.h" 54 #include "dce/dce_panel_cntl.h" 55 56 #include "soc15_hw_ip.h" 57 #include "vega10_ip_offset.h" 58 59 #include "dcn/dcn_1_0_offset.h" 60 #include "dcn/dcn_1_0_sh_mask.h" 61 62 #include "nbio/nbio_7_0_offset.h" 63 64 #include "mmhub/mmhub_9_1_offset.h" 65 #include "mmhub/mmhub_9_1_sh_mask.h" 66 67 #include "reg_helper.h" 68 #include "dce/dce_abm.h" 69 #include "dce/dce_dmcu.h" 70 #include "dce/dce_aux.h" 71 #include "dce/dce_i2c.h" 72 73 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 74 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 75 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 76 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 77 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 78 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 79 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 80 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 81 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 82 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 83 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 84 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 85 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 86 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 87 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 88 #endif 89 90 91 enum dcn10_clk_src_array_id { 92 DCN10_CLK_SRC_PLL0, 93 DCN10_CLK_SRC_PLL1, 94 DCN10_CLK_SRC_PLL2, 95 DCN10_CLK_SRC_PLL3, 96 DCN10_CLK_SRC_TOTAL, 97 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 98 }; 99 100 /* begin ********************* 101 * macros to expend register list macro defined in HW object header file */ 102 103 /* DCN */ 104 #define BASE_INNER(seg) \ 105 DCE_BASE__INST0_SEG ## seg 106 107 #define BASE(seg) \ 108 BASE_INNER(seg) 109 110 #define SR(reg_name)\ 111 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 112 mm ## reg_name 113 114 #define SRI(reg_name, block, id)\ 115 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 116 mm ## block ## id ## _ ## reg_name 117 118 119 #define SRII(reg_name, block, id)\ 120 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 121 mm ## block ## id ## _ ## reg_name 122 123 #define VUPDATE_SRII(reg_name, block, id)\ 124 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \ 125 mm ## reg_name ## 0 ## _ ## block ## id 126 127 /* set field/register/bitfield name */ 128 #define SFRB(field_name, reg_name, bitfield, post_fix)\ 129 .field_name = reg_name ## __ ## bitfield ## post_fix 130 131 /* NBIO */ 132 #define NBIO_BASE_INNER(seg) \ 133 NBIF_BASE__INST0_SEG ## seg 134 135 #define NBIO_BASE(seg) \ 136 NBIO_BASE_INNER(seg) 137 138 #define NBIO_SR(reg_name)\ 139 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 140 mm ## reg_name 141 142 /* MMHUB */ 143 #define MMHUB_BASE_INNER(seg) \ 144 MMHUB_BASE__INST0_SEG ## seg 145 146 #define MMHUB_BASE(seg) \ 147 MMHUB_BASE_INNER(seg) 148 149 #define MMHUB_SR(reg_name)\ 150 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 151 mm ## reg_name 152 153 /* macros to expend register list macro defined in HW object header file 154 * end *********************/ 155 156 157 static const struct dce_dmcu_registers dmcu_regs = { 158 DMCU_DCN10_REG_LIST() 159 }; 160 161 static const struct dce_dmcu_shift dmcu_shift = { 162 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 163 }; 164 165 static const struct dce_dmcu_mask dmcu_mask = { 166 DMCU_MASK_SH_LIST_DCN10(_MASK) 167 }; 168 169 static const struct dce_abm_registers abm_regs = { 170 ABM_DCN10_REG_LIST(0) 171 }; 172 173 static const struct dce_abm_shift abm_shift = { 174 ABM_MASK_SH_LIST_DCN10(__SHIFT) 175 }; 176 177 static const struct dce_abm_mask abm_mask = { 178 ABM_MASK_SH_LIST_DCN10(_MASK) 179 }; 180 181 #define stream_enc_regs(id)\ 182 [id] = {\ 183 SE_DCN_REG_LIST(id)\ 184 } 185 186 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 187 stream_enc_regs(0), 188 stream_enc_regs(1), 189 stream_enc_regs(2), 190 stream_enc_regs(3), 191 }; 192 193 static const struct dcn10_stream_encoder_shift se_shift = { 194 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 195 }; 196 197 static const struct dcn10_stream_encoder_mask se_mask = { 198 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 199 }; 200 201 #define audio_regs(id)\ 202 [id] = {\ 203 AUD_COMMON_REG_LIST(id)\ 204 } 205 206 static const struct dce_audio_registers audio_regs[] = { 207 audio_regs(0), 208 audio_regs(1), 209 audio_regs(2), 210 audio_regs(3), 211 }; 212 213 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 214 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 215 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 216 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 217 218 static const struct dce_audio_shift audio_shift = { 219 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 220 }; 221 222 static const struct dce_audio_mask audio_mask = { 223 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 224 }; 225 226 #define aux_regs(id)\ 227 [id] = {\ 228 AUX_REG_LIST(id)\ 229 } 230 231 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 232 aux_regs(0), 233 aux_regs(1), 234 aux_regs(2), 235 aux_regs(3) 236 }; 237 238 #define hpd_regs(id)\ 239 [id] = {\ 240 HPD_REG_LIST(id)\ 241 } 242 243 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 244 hpd_regs(0), 245 hpd_regs(1), 246 hpd_regs(2), 247 hpd_regs(3) 248 }; 249 250 #define link_regs(id)\ 251 [id] = {\ 252 LE_DCN10_REG_LIST(id), \ 253 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 254 } 255 256 static const struct dcn10_link_enc_registers link_enc_regs[] = { 257 link_regs(0), 258 link_regs(1), 259 link_regs(2), 260 link_regs(3) 261 }; 262 263 static const struct dcn10_link_enc_shift le_shift = { 264 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 265 }; 266 267 static const struct dcn10_link_enc_mask le_mask = { 268 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 269 }; 270 271 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 272 { DCN_PANEL_CNTL_REG_LIST() } 273 }; 274 275 static const struct dce_panel_cntl_shift panel_cntl_shift = { 276 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 277 }; 278 279 static const struct dce_panel_cntl_mask panel_cntl_mask = { 280 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 281 }; 282 283 static const struct dce110_aux_registers_shift aux_shift = { 284 DCN10_AUX_MASK_SH_LIST(__SHIFT) 285 }; 286 287 static const struct dce110_aux_registers_mask aux_mask = { 288 DCN10_AUX_MASK_SH_LIST(_MASK) 289 }; 290 291 #define ipp_regs(id)\ 292 [id] = {\ 293 IPP_REG_LIST_DCN10(id),\ 294 } 295 296 static const struct dcn10_ipp_registers ipp_regs[] = { 297 ipp_regs(0), 298 ipp_regs(1), 299 ipp_regs(2), 300 ipp_regs(3), 301 }; 302 303 static const struct dcn10_ipp_shift ipp_shift = { 304 IPP_MASK_SH_LIST_DCN10(__SHIFT) 305 }; 306 307 static const struct dcn10_ipp_mask ipp_mask = { 308 IPP_MASK_SH_LIST_DCN10(_MASK), 309 }; 310 311 #define opp_regs(id)\ 312 [id] = {\ 313 OPP_REG_LIST_DCN10(id),\ 314 } 315 316 static const struct dcn10_opp_registers opp_regs[] = { 317 opp_regs(0), 318 opp_regs(1), 319 opp_regs(2), 320 opp_regs(3), 321 }; 322 323 static const struct dcn10_opp_shift opp_shift = { 324 OPP_MASK_SH_LIST_DCN10(__SHIFT) 325 }; 326 327 static const struct dcn10_opp_mask opp_mask = { 328 OPP_MASK_SH_LIST_DCN10(_MASK), 329 }; 330 331 #define aux_engine_regs(id)\ 332 [id] = {\ 333 AUX_COMMON_REG_LIST(id), \ 334 .AUX_RESET_MASK = 0 \ 335 } 336 337 static const struct dce110_aux_registers aux_engine_regs[] = { 338 aux_engine_regs(0), 339 aux_engine_regs(1), 340 aux_engine_regs(2), 341 aux_engine_regs(3), 342 aux_engine_regs(4), 343 aux_engine_regs(5) 344 }; 345 346 #define tf_regs(id)\ 347 [id] = {\ 348 TF_REG_LIST_DCN10(id),\ 349 } 350 351 static const struct dcn_dpp_registers tf_regs[] = { 352 tf_regs(0), 353 tf_regs(1), 354 tf_regs(2), 355 tf_regs(3), 356 }; 357 358 static const struct dcn_dpp_shift tf_shift = { 359 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 360 TF_DEBUG_REG_LIST_SH_DCN10 361 362 }; 363 364 static const struct dcn_dpp_mask tf_mask = { 365 TF_REG_LIST_SH_MASK_DCN10(_MASK), 366 TF_DEBUG_REG_LIST_MASK_DCN10 367 }; 368 369 static const struct dcn_mpc_registers mpc_regs = { 370 MPC_COMMON_REG_LIST_DCN1_0(0), 371 MPC_COMMON_REG_LIST_DCN1_0(1), 372 MPC_COMMON_REG_LIST_DCN1_0(2), 373 MPC_COMMON_REG_LIST_DCN1_0(3), 374 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 375 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 376 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 377 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 378 }; 379 380 static const struct dcn_mpc_shift mpc_shift = { 381 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\ 382 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT) 383 }; 384 385 static const struct dcn_mpc_mask mpc_mask = { 386 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\ 387 SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK) 388 }; 389 390 #define tg_regs(id)\ 391 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 392 393 static const struct dcn_optc_registers tg_regs[] = { 394 tg_regs(0), 395 tg_regs(1), 396 tg_regs(2), 397 tg_regs(3), 398 }; 399 400 static const struct dcn_optc_shift tg_shift = { 401 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 402 }; 403 404 static const struct dcn_optc_mask tg_mask = { 405 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 406 }; 407 408 static const struct bios_registers bios_regs = { 409 NBIO_SR(BIOS_SCRATCH_3), 410 NBIO_SR(BIOS_SCRATCH_6) 411 }; 412 413 #define hubp_regs(id)\ 414 [id] = {\ 415 HUBP_REG_LIST_DCN10(id)\ 416 } 417 418 static const struct dcn_mi_registers hubp_regs[] = { 419 hubp_regs(0), 420 hubp_regs(1), 421 hubp_regs(2), 422 hubp_regs(3), 423 }; 424 425 static const struct dcn_mi_shift hubp_shift = { 426 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 427 }; 428 429 static const struct dcn_mi_mask hubp_mask = { 430 HUBP_MASK_SH_LIST_DCN10(_MASK) 431 }; 432 433 static const struct dcn_hubbub_registers hubbub_reg = { 434 HUBBUB_REG_LIST_DCN10(0) 435 }; 436 437 static const struct dcn_hubbub_shift hubbub_shift = { 438 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 439 }; 440 441 static const struct dcn_hubbub_mask hubbub_mask = { 442 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 443 }; 444 445 static int map_transmitter_id_to_phy_instance( 446 enum transmitter transmitter) 447 { 448 switch (transmitter) { 449 case TRANSMITTER_UNIPHY_A: 450 return 0; 451 break; 452 case TRANSMITTER_UNIPHY_B: 453 return 1; 454 break; 455 case TRANSMITTER_UNIPHY_C: 456 return 2; 457 break; 458 case TRANSMITTER_UNIPHY_D: 459 return 3; 460 break; 461 default: 462 ASSERT(0); 463 return 0; 464 } 465 } 466 467 #define clk_src_regs(index, pllid)\ 468 [index] = {\ 469 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 470 } 471 472 static const struct dce110_clk_src_regs clk_src_regs[] = { 473 clk_src_regs(0, A), 474 clk_src_regs(1, B), 475 clk_src_regs(2, C), 476 clk_src_regs(3, D) 477 }; 478 479 static const struct dce110_clk_src_shift cs_shift = { 480 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 481 }; 482 483 static const struct dce110_clk_src_mask cs_mask = { 484 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 485 }; 486 487 static const struct resource_caps res_cap = { 488 .num_timing_generator = 4, 489 .num_opp = 4, 490 .num_video_plane = 4, 491 .num_audio = 4, 492 .num_stream_encoder = 4, 493 .num_pll = 4, 494 .num_ddc = 4, 495 }; 496 497 static const struct resource_caps rv2_res_cap = { 498 .num_timing_generator = 3, 499 .num_opp = 3, 500 .num_video_plane = 3, 501 .num_audio = 3, 502 .num_stream_encoder = 3, 503 .num_pll = 3, 504 .num_ddc = 4, 505 }; 506 507 static const struct dc_plane_cap plane_cap = { 508 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 509 .blends_with_above = true, 510 .blends_with_below = true, 511 .per_pixel_alpha = true, 512 513 .pixel_format_support = { 514 .argb8888 = true, 515 .nv12 = true, 516 .fp16 = true, 517 .p010 = true 518 }, 519 520 .max_upscale_factor = { 521 .argb8888 = 16000, 522 .nv12 = 16000, 523 .fp16 = 1 524 }, 525 526 .max_downscale_factor = { 527 .argb8888 = 250, 528 .nv12 = 250, 529 .fp16 = 1 530 } 531 }; 532 533 static const struct dc_debug_options debug_defaults_drv = { 534 .sanity_checks = true, 535 .disable_dmcu = false, 536 .force_abm_enable = false, 537 .timing_trace = false, 538 .clock_trace = true, 539 540 /* raven smu dones't allow 0 disp clk, 541 * smu min disp clk limit is 50Mhz 542 * keep min disp clk 100Mhz avoid smu hang 543 */ 544 .min_disp_clk_khz = 100000, 545 546 .disable_pplib_clock_request = false, 547 .disable_pplib_wm_range = false, 548 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 549 .pipe_split_policy = MPC_SPLIT_AVOID, 550 .force_single_disp_pipe_split = false, 551 .disable_dcc = DCC_ENABLE, 552 .voltage_align_fclk = true, 553 .disable_stereo_support = true, 554 .vsr_support = true, 555 .performance_trace = false, 556 .az_endpoint_mute_only = true, 557 .recovery_enabled = false, /*enable this by default after testing.*/ 558 .max_downscale_src_width = 3840, 559 .underflow_assert_delay_us = 0xFFFFFFFF, 560 }; 561 562 static const struct dc_debug_options debug_defaults_diags = { 563 .disable_dmcu = false, 564 .force_abm_enable = false, 565 .timing_trace = true, 566 .clock_trace = true, 567 .disable_stutter = true, 568 .disable_pplib_clock_request = true, 569 .disable_pplib_wm_range = true, 570 .underflow_assert_delay_us = 0xFFFFFFFF, 571 }; 572 573 static void dcn10_dpp_destroy(struct dpp **dpp) 574 { 575 kfree(TO_DCN10_DPP(*dpp)); 576 *dpp = NULL; 577 } 578 579 static struct dpp *dcn10_dpp_create( 580 struct dc_context *ctx, 581 uint32_t inst) 582 { 583 struct dcn10_dpp *dpp = 584 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 585 586 if (!dpp) 587 return NULL; 588 589 dpp1_construct(dpp, ctx, inst, 590 &tf_regs[inst], &tf_shift, &tf_mask); 591 return &dpp->base; 592 } 593 594 static struct input_pixel_processor *dcn10_ipp_create( 595 struct dc_context *ctx, uint32_t inst) 596 { 597 struct dcn10_ipp *ipp = 598 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 599 600 if (!ipp) { 601 BREAK_TO_DEBUGGER(); 602 return NULL; 603 } 604 605 dcn10_ipp_construct(ipp, ctx, inst, 606 &ipp_regs[inst], &ipp_shift, &ipp_mask); 607 return &ipp->base; 608 } 609 610 611 static struct output_pixel_processor *dcn10_opp_create( 612 struct dc_context *ctx, uint32_t inst) 613 { 614 struct dcn10_opp *opp = 615 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 616 617 if (!opp) { 618 BREAK_TO_DEBUGGER(); 619 return NULL; 620 } 621 622 dcn10_opp_construct(opp, ctx, inst, 623 &opp_regs[inst], &opp_shift, &opp_mask); 624 return &opp->base; 625 } 626 627 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx, 628 uint32_t inst) 629 { 630 struct aux_engine_dce110 *aux_engine = 631 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 632 633 if (!aux_engine) 634 return NULL; 635 636 dce110_aux_engine_construct(aux_engine, ctx, inst, 637 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 638 &aux_engine_regs[inst], 639 &aux_mask, 640 &aux_shift, 641 ctx->dc->caps.extended_aux_timeout_support); 642 643 return &aux_engine->base; 644 } 645 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 646 647 static const struct dce_i2c_registers i2c_hw_regs[] = { 648 i2c_inst_regs(1), 649 i2c_inst_regs(2), 650 i2c_inst_regs(3), 651 i2c_inst_regs(4), 652 i2c_inst_regs(5), 653 i2c_inst_regs(6), 654 }; 655 656 static const struct dce_i2c_shift i2c_shifts = { 657 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 658 }; 659 660 static const struct dce_i2c_mask i2c_masks = { 661 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 662 }; 663 664 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx, 665 uint32_t inst) 666 { 667 struct dce_i2c_hw *dce_i2c_hw = 668 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 669 670 if (!dce_i2c_hw) 671 return NULL; 672 673 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 674 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 675 676 return dce_i2c_hw; 677 } 678 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 679 { 680 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 681 GFP_KERNEL); 682 683 if (!mpc10) 684 return NULL; 685 686 dcn10_mpc_construct(mpc10, ctx, 687 &mpc_regs, 688 &mpc_shift, 689 &mpc_mask, 690 4); 691 692 return &mpc10->base; 693 } 694 695 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 696 { 697 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 698 GFP_KERNEL); 699 700 if (!dcn10_hubbub) 701 return NULL; 702 703 hubbub1_construct(&dcn10_hubbub->base, ctx, 704 &hubbub_reg, 705 &hubbub_shift, 706 &hubbub_mask); 707 708 return &dcn10_hubbub->base; 709 } 710 711 static struct timing_generator *dcn10_timing_generator_create( 712 struct dc_context *ctx, 713 uint32_t instance) 714 { 715 struct optc *tgn10 = 716 kzalloc(sizeof(struct optc), GFP_KERNEL); 717 718 if (!tgn10) 719 return NULL; 720 721 tgn10->base.inst = instance; 722 tgn10->base.ctx = ctx; 723 724 tgn10->tg_regs = &tg_regs[instance]; 725 tgn10->tg_shift = &tg_shift; 726 tgn10->tg_mask = &tg_mask; 727 728 dcn10_timing_generator_init(tgn10); 729 730 return &tgn10->base; 731 } 732 733 static const struct encoder_feature_support link_enc_feature = { 734 .max_hdmi_deep_color = COLOR_DEPTH_121212, 735 .max_hdmi_pixel_clock = 600000, 736 .hdmi_ycbcr420_supported = true, 737 .dp_ycbcr420_supported = true, 738 .flags.bits.IS_HBR2_CAPABLE = true, 739 .flags.bits.IS_HBR3_CAPABLE = true, 740 .flags.bits.IS_TPS3_CAPABLE = true, 741 .flags.bits.IS_TPS4_CAPABLE = true 742 }; 743 744 static struct link_encoder *dcn10_link_encoder_create( 745 const struct encoder_init_data *enc_init_data) 746 { 747 struct dcn10_link_encoder *enc10 = 748 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 749 int link_regs_id; 750 751 if (!enc10) 752 return NULL; 753 754 link_regs_id = 755 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 756 757 dcn10_link_encoder_construct(enc10, 758 enc_init_data, 759 &link_enc_feature, 760 &link_enc_regs[link_regs_id], 761 &link_enc_aux_regs[enc_init_data->channel - 1], 762 &link_enc_hpd_regs[enc_init_data->hpd_source], 763 &le_shift, 764 &le_mask); 765 766 return &enc10->base; 767 } 768 769 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data) 770 { 771 struct dce_panel_cntl *panel_cntl = 772 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 773 774 if (!panel_cntl) 775 return NULL; 776 777 dce_panel_cntl_construct(panel_cntl, 778 init_data, 779 &panel_cntl_regs[init_data->inst], 780 &panel_cntl_shift, 781 &panel_cntl_mask); 782 783 return &panel_cntl->base; 784 } 785 786 static struct clock_source *dcn10_clock_source_create( 787 struct dc_context *ctx, 788 struct dc_bios *bios, 789 enum clock_source_id id, 790 const struct dce110_clk_src_regs *regs, 791 bool dp_clk_src) 792 { 793 struct dce110_clk_src *clk_src = 794 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 795 796 if (!clk_src) 797 return NULL; 798 799 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 800 regs, &cs_shift, &cs_mask)) { 801 clk_src->base.dp_clk_src = dp_clk_src; 802 return &clk_src->base; 803 } 804 805 kfree(clk_src); 806 BREAK_TO_DEBUGGER(); 807 return NULL; 808 } 809 810 static void read_dce_straps( 811 struct dc_context *ctx, 812 struct resource_straps *straps) 813 { 814 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 815 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 816 } 817 818 static struct audio *create_audio( 819 struct dc_context *ctx, unsigned int inst) 820 { 821 return dce_audio_create(ctx, inst, 822 &audio_regs[inst], &audio_shift, &audio_mask); 823 } 824 825 static struct stream_encoder *dcn10_stream_encoder_create( 826 enum engine_id eng_id, 827 struct dc_context *ctx) 828 { 829 struct dcn10_stream_encoder *enc1 = 830 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 831 832 if (!enc1) 833 return NULL; 834 835 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 836 &stream_enc_regs[eng_id], 837 &se_shift, &se_mask); 838 return &enc1->base; 839 } 840 841 static const struct dce_hwseq_registers hwseq_reg = { 842 HWSEQ_DCN1_REG_LIST() 843 }; 844 845 static const struct dce_hwseq_shift hwseq_shift = { 846 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 847 }; 848 849 static const struct dce_hwseq_mask hwseq_mask = { 850 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 851 }; 852 853 static struct dce_hwseq *dcn10_hwseq_create( 854 struct dc_context *ctx) 855 { 856 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 857 858 if (hws) { 859 hws->ctx = ctx; 860 hws->regs = &hwseq_reg; 861 hws->shifts = &hwseq_shift; 862 hws->masks = &hwseq_mask; 863 hws->wa.DEGVIDCN10_253 = true; 864 hws->wa.false_optc_underflow = true; 865 hws->wa.DEGVIDCN10_254 = true; 866 867 if ((ctx->asic_id.chip_family == FAMILY_RV) && 868 ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev)) 869 switch (ctx->asic_id.pci_revision_id) { 870 case PRID_POLLOCK_94: 871 case PRID_POLLOCK_95: 872 case PRID_POLLOCK_E9: 873 case PRID_POLLOCK_EA: 874 case PRID_POLLOCK_EB: 875 hws->wa.wait_hubpret_read_start_during_mpo_transition = true; 876 break; 877 default: 878 hws->wa.wait_hubpret_read_start_during_mpo_transition = false; 879 break; 880 } 881 } 882 return hws; 883 } 884 885 static const struct resource_create_funcs res_create_funcs = { 886 .read_dce_straps = read_dce_straps, 887 .create_audio = create_audio, 888 .create_stream_encoder = dcn10_stream_encoder_create, 889 .create_hwseq = dcn10_hwseq_create, 890 }; 891 892 static const struct resource_create_funcs res_create_maximus_funcs = { 893 .read_dce_straps = NULL, 894 .create_audio = NULL, 895 .create_stream_encoder = NULL, 896 .create_hwseq = dcn10_hwseq_create, 897 }; 898 899 static void dcn10_clock_source_destroy(struct clock_source **clk_src) 900 { 901 kfree(TO_DCE110_CLK_SRC(*clk_src)); 902 *clk_src = NULL; 903 } 904 905 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 906 { 907 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 908 909 if (!pp_smu) 910 return pp_smu; 911 912 dm_pp_get_funcs(ctx, pp_smu); 913 return pp_smu; 914 } 915 916 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) 917 { 918 unsigned int i; 919 920 for (i = 0; i < pool->base.stream_enc_count; i++) { 921 if (pool->base.stream_enc[i] != NULL) { 922 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 923 pool->base.stream_enc[i] = NULL; 924 } 925 } 926 927 if (pool->base.mpc != NULL) { 928 kfree(TO_DCN10_MPC(pool->base.mpc)); 929 pool->base.mpc = NULL; 930 } 931 932 kfree(pool->base.hubbub); 933 pool->base.hubbub = NULL; 934 935 for (i = 0; i < pool->base.pipe_count; i++) { 936 if (pool->base.opps[i] != NULL) 937 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 938 939 if (pool->base.dpps[i] != NULL) 940 dcn10_dpp_destroy(&pool->base.dpps[i]); 941 942 if (pool->base.ipps[i] != NULL) 943 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 944 945 if (pool->base.hubps[i] != NULL) { 946 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 947 pool->base.hubps[i] = NULL; 948 } 949 950 if (pool->base.irqs != NULL) { 951 dal_irq_service_destroy(&pool->base.irqs); 952 } 953 954 if (pool->base.timing_generators[i] != NULL) { 955 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 956 pool->base.timing_generators[i] = NULL; 957 } 958 } 959 960 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 961 if (pool->base.engines[i] != NULL) 962 dce110_engine_destroy(&pool->base.engines[i]); 963 kfree(pool->base.hw_i2cs[i]); 964 pool->base.hw_i2cs[i] = NULL; 965 kfree(pool->base.sw_i2cs[i]); 966 pool->base.sw_i2cs[i] = NULL; 967 } 968 969 for (i = 0; i < pool->base.audio_count; i++) { 970 if (pool->base.audios[i]) 971 dce_aud_destroy(&pool->base.audios[i]); 972 } 973 974 for (i = 0; i < pool->base.clk_src_count; i++) { 975 if (pool->base.clock_sources[i] != NULL) { 976 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 977 pool->base.clock_sources[i] = NULL; 978 } 979 } 980 981 if (pool->base.dp_clock_source != NULL) { 982 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 983 pool->base.dp_clock_source = NULL; 984 } 985 986 if (pool->base.abm != NULL) 987 dce_abm_destroy(&pool->base.abm); 988 989 if (pool->base.dmcu != NULL) 990 dce_dmcu_destroy(&pool->base.dmcu); 991 992 kfree(pool->base.pp_smu); 993 } 994 995 static struct hubp *dcn10_hubp_create( 996 struct dc_context *ctx, 997 uint32_t inst) 998 { 999 struct dcn10_hubp *hubp1 = 1000 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 1001 1002 if (!hubp1) 1003 return NULL; 1004 1005 dcn10_hubp_construct(hubp1, ctx, inst, 1006 &hubp_regs[inst], &hubp_shift, &hubp_mask); 1007 return &hubp1->base; 1008 } 1009 1010 static void get_pixel_clock_parameters( 1011 const struct pipe_ctx *pipe_ctx, 1012 struct pixel_clk_params *pixel_clk_params) 1013 { 1014 const struct dc_stream_state *stream = pipe_ctx->stream; 1015 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1016 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1017 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1018 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1019 /* TODO: un-hardcode*/ 1020 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1021 LINK_RATE_REF_FREQ_IN_KHZ; 1022 pixel_clk_params->flags.ENABLE_SS = 0; 1023 pixel_clk_params->color_depth = 1024 stream->timing.display_color_depth; 1025 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1026 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1027 1028 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1029 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1030 1031 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1032 pixel_clk_params->requested_pix_clk_100hz /= 2; 1033 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1034 pixel_clk_params->requested_pix_clk_100hz *= 2; 1035 1036 } 1037 1038 static void build_clamping_params(struct dc_stream_state *stream) 1039 { 1040 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1041 stream->clamping.c_depth = stream->timing.display_color_depth; 1042 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1043 } 1044 1045 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1046 { 1047 1048 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1049 1050 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1051 pipe_ctx->clock_source, 1052 &pipe_ctx->stream_res.pix_clk_params, 1053 &pipe_ctx->pll_settings); 1054 1055 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1056 1057 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1058 &pipe_ctx->stream->bit_depth_params); 1059 build_clamping_params(pipe_ctx->stream); 1060 } 1061 1062 static enum dc_status build_mapped_resource( 1063 const struct dc *dc, 1064 struct dc_state *context, 1065 struct dc_stream_state *stream) 1066 { 1067 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1068 1069 if (!pipe_ctx) 1070 return DC_ERROR_UNEXPECTED; 1071 1072 build_pipe_hw_param(pipe_ctx); 1073 return DC_OK; 1074 } 1075 1076 static enum dc_status dcn10_add_stream_to_ctx( 1077 struct dc *dc, 1078 struct dc_state *new_ctx, 1079 struct dc_stream_state *dc_stream) 1080 { 1081 enum dc_status result = DC_ERROR_UNEXPECTED; 1082 1083 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1084 1085 if (result == DC_OK) 1086 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1087 1088 1089 if (result == DC_OK) 1090 result = build_mapped_resource(dc, new_ctx, dc_stream); 1091 1092 return result; 1093 } 1094 1095 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1096 struct dc_state *context, 1097 const struct resource_pool *pool, 1098 struct dc_stream_state *stream) 1099 { 1100 struct resource_context *res_ctx = &context->res_ctx; 1101 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1102 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 1103 1104 if (!head_pipe) { 1105 ASSERT(0); 1106 return NULL; 1107 } 1108 1109 if (!idle_pipe) 1110 return NULL; 1111 1112 idle_pipe->stream = head_pipe->stream; 1113 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1114 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1115 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1116 1117 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1118 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1119 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1120 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1121 1122 return idle_pipe; 1123 } 1124 1125 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1126 const struct dc_dcc_surface_param *input, 1127 struct dc_surface_dcc_cap *output) 1128 { 1129 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1130 dc->res_pool->hubbub, 1131 input, 1132 output); 1133 } 1134 1135 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1136 { 1137 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1138 1139 dcn10_resource_destruct(dcn10_pool); 1140 kfree(dcn10_pool); 1141 *pool = NULL; 1142 } 1143 1144 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1145 { 1146 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1147 && caps->max_video_width != 0 1148 && plane_state->src_rect.width > caps->max_video_width) 1149 return DC_FAIL_SURFACE_VALIDATE; 1150 1151 return DC_OK; 1152 } 1153 1154 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1155 { 1156 int i, j; 1157 bool video_down_scaled = false; 1158 bool video_large = false; 1159 bool desktop_large = false; 1160 bool dcc_disabled = false; 1161 bool mpo_enabled = false; 1162 1163 for (i = 0; i < context->stream_count; i++) { 1164 if (context->stream_status[i].plane_count == 0) 1165 continue; 1166 1167 if (context->stream_status[i].plane_count > 2) 1168 return DC_FAIL_UNSUPPORTED_1; 1169 1170 if (context->stream_status[i].plane_count > 1) 1171 mpo_enabled = true; 1172 1173 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1174 struct dc_plane_state *plane = 1175 context->stream_status[i].plane_states[j]; 1176 1177 1178 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1179 1180 if (plane->src_rect.width > plane->dst_rect.width || 1181 plane->src_rect.height > plane->dst_rect.height) 1182 video_down_scaled = true; 1183 1184 if (plane->src_rect.width >= 3840) 1185 video_large = true; 1186 1187 } else { 1188 if (plane->src_rect.width >= 3840) 1189 desktop_large = true; 1190 if (!plane->dcc.enable) 1191 dcc_disabled = true; 1192 } 1193 } 1194 } 1195 1196 /* Disable MPO in multi-display configurations. */ 1197 if (context->stream_count > 1 && mpo_enabled) 1198 return DC_FAIL_UNSUPPORTED_1; 1199 1200 /* 1201 * Workaround: On DCN10 there is UMC issue that causes underflow when 1202 * playing 4k video on 4k desktop with video downscaled and single channel 1203 * memory 1204 */ 1205 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1206 dc->dcn_soc->number_of_channels == 1) 1207 return DC_FAIL_SURFACE_VALIDATE; 1208 1209 return DC_OK; 1210 } 1211 1212 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state) 1213 { 1214 enum surface_pixel_format surf_pix_format = plane_state->format; 1215 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1216 1217 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1218 1219 if (bpp == 64) 1220 swizzle = DC_SW_64KB_D; 1221 else 1222 swizzle = DC_SW_64KB_S; 1223 1224 plane_state->tiling_info.gfx9.swizzle = swizzle; 1225 return DC_OK; 1226 } 1227 1228 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 1229 struct resource_context *res_ctx, 1230 const struct resource_pool *pool, 1231 struct dc_stream_state *stream) 1232 { 1233 int i; 1234 int j = -1; 1235 struct dc_link *link = stream->link; 1236 1237 for (i = 0; i < pool->stream_enc_count; i++) { 1238 if (!res_ctx->is_stream_enc_acquired[i] && 1239 pool->stream_enc[i]) { 1240 /* Store first available for MST second display 1241 * in daisy chain use case 1242 */ 1243 j = i; 1244 if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id == 1245 link->link_enc->preferred_engine) 1246 return pool->stream_enc[i]; 1247 } 1248 } 1249 1250 /* 1251 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1252 */ 1253 1254 if (j >= 0) 1255 return pool->stream_enc[j]; 1256 1257 return NULL; 1258 } 1259 1260 static const struct dc_cap_funcs cap_funcs = { 1261 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1262 }; 1263 1264 static const struct resource_funcs dcn10_res_pool_funcs = { 1265 .destroy = dcn10_destroy_resource_pool, 1266 .link_enc_create = dcn10_link_encoder_create, 1267 .panel_cntl_create = dcn10_panel_cntl_create, 1268 .validate_bandwidth = dcn10_validate_bandwidth, 1269 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1270 .validate_plane = dcn10_validate_plane, 1271 .validate_global = dcn10_validate_global, 1272 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1273 .patch_unknown_plane_state = dcn10_patch_unknown_plane_state, 1274 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 1275 }; 1276 1277 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1278 { 1279 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1280 /* RV1 support max 4 pipes */ 1281 value = value & 0xf; 1282 return value; 1283 } 1284 1285 /* 1286 * Some architectures don't support soft-float (e.g. aarch64), on those 1287 * this function has to be called with hardfloat enabled, make sure not 1288 * to inline it so whatever fp stuff is done stays inside 1289 */ 1290 static noinline void dcn10_resource_construct_fp( 1291 struct dc *dc) 1292 { 1293 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1294 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1295 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1296 struct display_mode_lib *dml = &dc->dml; 1297 1298 dml->ip.max_num_dpp = 3; 1299 /* TODO how to handle 23.84? */ 1300 dcn_soc->dram_clock_change_latency = 23; 1301 dcn_ip->max_num_dpp = 3; 1302 } 1303 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1304 dc->dcn_soc->urgent_latency = 3; 1305 dc->debug.disable_dmcu = true; 1306 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1307 } 1308 1309 1310 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1311 ASSERT(dc->dcn_soc->number_of_channels < 3); 1312 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1313 dc->dcn_soc->number_of_channels = 2; 1314 1315 if (dc->dcn_soc->number_of_channels == 1) { 1316 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1317 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1318 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1319 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1320 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1321 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1322 } 1323 } 1324 } 1325 1326 static bool dcn10_resource_construct( 1327 uint8_t num_virtual_links, 1328 struct dc *dc, 1329 struct dcn10_resource_pool *pool) 1330 { 1331 int i; 1332 int j; 1333 struct dc_context *ctx = dc->ctx; 1334 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1335 1336 ctx->dc_bios->regs = &bios_regs; 1337 1338 if (ctx->dce_version == DCN_VERSION_1_01) 1339 pool->base.res_cap = &rv2_res_cap; 1340 else 1341 pool->base.res_cap = &res_cap; 1342 pool->base.funcs = &dcn10_res_pool_funcs; 1343 1344 /* 1345 * TODO fill in from actual raven resource when we create 1346 * more than virtual encoder 1347 */ 1348 1349 /************************************************* 1350 * Resource + asic cap harcoding * 1351 *************************************************/ 1352 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1353 1354 /* max pipe num for ASIC before check pipe fuses */ 1355 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1356 1357 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1358 pool->base.pipe_count = 3; 1359 dc->caps.max_video_width = 3840; 1360 dc->caps.max_downscale_ratio = 200; 1361 dc->caps.i2c_speed_in_khz = 100; 1362 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 1363 dc->caps.max_cursor_size = 256; 1364 dc->caps.min_horizontal_blanking_period = 80; 1365 dc->caps.max_slave_planes = 1; 1366 dc->caps.max_slave_yuv_planes = 1; 1367 dc->caps.max_slave_rgb_planes = 0; 1368 dc->caps.is_apu = true; 1369 dc->caps.post_blend_color_processing = false; 1370 dc->caps.extended_aux_timeout_support = false; 1371 1372 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1373 dc->caps.force_dp_tps4_for_cp2520 = true; 1374 1375 /* Color pipeline capabilities */ 1376 dc->caps.color.dpp.dcn_arch = 1; 1377 dc->caps.color.dpp.input_lut_shared = 1; 1378 dc->caps.color.dpp.icsc = 1; 1379 dc->caps.color.dpp.dgam_ram = 1; 1380 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1381 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1382 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 1383 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 1384 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 1385 dc->caps.color.dpp.post_csc = 0; 1386 dc->caps.color.dpp.gamma_corr = 0; 1387 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 1388 1389 dc->caps.color.dpp.hw_3d_lut = 0; 1390 dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1 1391 dc->caps.color.dpp.ogam_rom_caps.srgb = 1; 1392 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1; 1393 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1394 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1395 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1396 dc->caps.color.dpp.ocsc = 1; 1397 1398 /* no post-blend color operations */ 1399 dc->caps.color.mpc.gamut_remap = 0; 1400 dc->caps.color.mpc.num_3dluts = 0; 1401 dc->caps.color.mpc.shared_3d_lut = 0; 1402 dc->caps.color.mpc.ogam_ram = 0; 1403 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1404 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1405 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1406 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1407 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1408 dc->caps.color.mpc.ocsc = 0; 1409 1410 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1411 dc->debug = debug_defaults_drv; 1412 else 1413 dc->debug = debug_defaults_diags; 1414 1415 /************************************************* 1416 * Create resources * 1417 *************************************************/ 1418 1419 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1420 dcn10_clock_source_create(ctx, ctx->dc_bios, 1421 CLOCK_SOURCE_COMBO_PHY_PLL0, 1422 &clk_src_regs[0], false); 1423 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1424 dcn10_clock_source_create(ctx, ctx->dc_bios, 1425 CLOCK_SOURCE_COMBO_PHY_PLL1, 1426 &clk_src_regs[1], false); 1427 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1428 dcn10_clock_source_create(ctx, ctx->dc_bios, 1429 CLOCK_SOURCE_COMBO_PHY_PLL2, 1430 &clk_src_regs[2], false); 1431 1432 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1433 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1434 dcn10_clock_source_create(ctx, ctx->dc_bios, 1435 CLOCK_SOURCE_COMBO_PHY_PLL3, 1436 &clk_src_regs[3], false); 1437 } 1438 1439 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1440 1441 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1442 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1443 1444 pool->base.dp_clock_source = 1445 dcn10_clock_source_create(ctx, ctx->dc_bios, 1446 CLOCK_SOURCE_ID_DP_DTO, 1447 /* todo: not reuse phy_pll registers */ 1448 &clk_src_regs[0], true); 1449 1450 for (i = 0; i < pool->base.clk_src_count; i++) { 1451 if (pool->base.clock_sources[i] == NULL) { 1452 dm_error("DC: failed to create clock sources!\n"); 1453 BREAK_TO_DEBUGGER(); 1454 goto fail; 1455 } 1456 } 1457 1458 pool->base.dmcu = dcn10_dmcu_create(ctx, 1459 &dmcu_regs, 1460 &dmcu_shift, 1461 &dmcu_mask); 1462 if (pool->base.dmcu == NULL) { 1463 dm_error("DC: failed to create dmcu!\n"); 1464 BREAK_TO_DEBUGGER(); 1465 goto fail; 1466 } 1467 1468 pool->base.abm = dce_abm_create(ctx, 1469 &abm_regs, 1470 &abm_shift, 1471 &abm_mask); 1472 if (pool->base.abm == NULL) { 1473 dm_error("DC: failed to create abm!\n"); 1474 BREAK_TO_DEBUGGER(); 1475 goto fail; 1476 } 1477 1478 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1479 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1480 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1481 1482 /* Other architectures we build for build this with soft-float */ 1483 dcn10_resource_construct_fp(dc); 1484 1485 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1486 1487 /* 1488 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * 1489 * implemented. So AZ D3 should work.For issue 197007. * 1490 */ 1491 if (pool->base.pp_smu != NULL 1492 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) 1493 dc->debug.az_endpoint_mute_only = false; 1494 1495 if (!dc->debug.disable_pplib_clock_request) 1496 dcn_bw_update_from_pplib(dc); 1497 dcn_bw_sync_calcs_and_dml(dc); 1498 if (!dc->debug.disable_pplib_wm_range) { 1499 dc->res_pool = &pool->base; 1500 dcn_bw_notify_pplib_of_wm_ranges(dc); 1501 } 1502 1503 { 1504 struct irq_service_init_data init_data; 1505 init_data.ctx = dc->ctx; 1506 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1507 if (!pool->base.irqs) 1508 goto fail; 1509 } 1510 1511 /* index to valid pipe resource */ 1512 j = 0; 1513 /* mem input -> ipp -> dpp -> opp -> TG */ 1514 for (i = 0; i < pool->base.pipe_count; i++) { 1515 /* if pipe is disabled, skip instance of HW pipe, 1516 * i.e, skip ASIC register instance 1517 */ 1518 if ((pipe_fuses & (1 << i)) != 0) 1519 continue; 1520 1521 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1522 if (pool->base.hubps[j] == NULL) { 1523 BREAK_TO_DEBUGGER(); 1524 dm_error( 1525 "DC: failed to create memory input!\n"); 1526 goto fail; 1527 } 1528 1529 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1530 if (pool->base.ipps[j] == NULL) { 1531 BREAK_TO_DEBUGGER(); 1532 dm_error( 1533 "DC: failed to create input pixel processor!\n"); 1534 goto fail; 1535 } 1536 1537 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1538 if (pool->base.dpps[j] == NULL) { 1539 BREAK_TO_DEBUGGER(); 1540 dm_error( 1541 "DC: failed to create dpp!\n"); 1542 goto fail; 1543 } 1544 1545 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1546 if (pool->base.opps[j] == NULL) { 1547 BREAK_TO_DEBUGGER(); 1548 dm_error( 1549 "DC: failed to create output pixel processor!\n"); 1550 goto fail; 1551 } 1552 1553 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1554 ctx, i); 1555 if (pool->base.timing_generators[j] == NULL) { 1556 BREAK_TO_DEBUGGER(); 1557 dm_error("DC: failed to create tg!\n"); 1558 goto fail; 1559 } 1560 /* check next valid pipe */ 1561 j++; 1562 } 1563 1564 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1565 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1566 if (pool->base.engines[i] == NULL) { 1567 BREAK_TO_DEBUGGER(); 1568 dm_error( 1569 "DC:failed to create aux engine!!\n"); 1570 goto fail; 1571 } 1572 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1573 if (pool->base.hw_i2cs[i] == NULL) { 1574 BREAK_TO_DEBUGGER(); 1575 dm_error( 1576 "DC:failed to create hw i2c!!\n"); 1577 goto fail; 1578 } 1579 pool->base.sw_i2cs[i] = NULL; 1580 } 1581 1582 /* valid pipe num */ 1583 pool->base.pipe_count = j; 1584 pool->base.timing_generator_count = j; 1585 1586 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1587 * the value may be changed 1588 */ 1589 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1590 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1591 1592 pool->base.mpc = dcn10_mpc_create(ctx); 1593 if (pool->base.mpc == NULL) { 1594 BREAK_TO_DEBUGGER(); 1595 dm_error("DC: failed to create mpc!\n"); 1596 goto fail; 1597 } 1598 1599 pool->base.hubbub = dcn10_hubbub_create(ctx); 1600 if (pool->base.hubbub == NULL) { 1601 BREAK_TO_DEBUGGER(); 1602 dm_error("DC: failed to create hubbub!\n"); 1603 goto fail; 1604 } 1605 1606 if (!resource_construct(num_virtual_links, dc, &pool->base, 1607 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1608 &res_create_funcs : &res_create_maximus_funcs))) 1609 goto fail; 1610 1611 dcn10_hw_sequencer_construct(dc); 1612 dc->caps.max_planes = pool->base.pipe_count; 1613 1614 for (i = 0; i < dc->caps.max_planes; ++i) 1615 dc->caps.planes[i] = plane_cap; 1616 1617 dc->cap_funcs = cap_funcs; 1618 1619 return true; 1620 1621 fail: 1622 1623 dcn10_resource_destruct(pool); 1624 1625 return false; 1626 } 1627 1628 struct resource_pool *dcn10_create_resource_pool( 1629 const struct dc_init_data *init_data, 1630 struct dc *dc) 1631 { 1632 struct dcn10_resource_pool *pool = 1633 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1634 1635 if (!pool) 1636 return NULL; 1637 1638 if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool)) 1639 return &pool->base; 1640 1641 kfree(pool); 1642 BREAK_TO_DEBUGGER(); 1643 return NULL; 1644 } 1645