1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn10/dcn10_resource.h" 32 33 #include "dcn10/dcn10_ipp.h" 34 #include "dcn10/dcn10_mpc.h" 35 #include "irq/dcn10/irq_service_dcn10.h" 36 #include "dcn10/dcn10_dpp.h" 37 #include "dcn10_optc.h" 38 #include "dcn10/dcn10_hw_sequencer.h" 39 #include "dce110/dce110_hw_sequencer.h" 40 #include "dcn10/dcn10_opp.h" 41 #include "dcn10/dcn10_link_encoder.h" 42 #include "dcn10/dcn10_stream_encoder.h" 43 #include "dce/dce_clocks.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "../virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 68 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 69 .rob_buffer_size_kbytes = 64, 70 .det_buffer_size_kbytes = 164, 71 .dpte_buffer_size_in_pte_reqs = 42, 72 .dpp_output_buffer_pixels = 2560, 73 .opp_output_buffer_lines = 1, 74 .pixel_chunk_size_kbytes = 8, 75 .pte_enable = 1, 76 .pte_chunk_size_kbytes = 2, 77 .meta_chunk_size_kbytes = 2, 78 .writeback_chunk_size_kbytes = 2, 79 .line_buffer_size_bits = 589824, 80 .max_line_buffer_lines = 12, 81 .IsLineBufferBppFixed = 0, 82 .LineBufferFixedBpp = -1, 83 .writeback_luma_buffer_size_kbytes = 12, 84 .writeback_chroma_buffer_size_kbytes = 8, 85 .max_num_dpp = 4, 86 .max_num_wb = 2, 87 .max_dchub_pscl_bw_pix_per_clk = 4, 88 .max_pscl_lb_bw_pix_per_clk = 2, 89 .max_lb_vscl_bw_pix_per_clk = 4, 90 .max_vscl_hscl_bw_pix_per_clk = 4, 91 .max_hscl_ratio = 4, 92 .max_vscl_ratio = 4, 93 .hscl_mults = 4, 94 .vscl_mults = 4, 95 .max_hscl_taps = 8, 96 .max_vscl_taps = 8, 97 .dispclk_ramp_margin_percent = 1, 98 .underscan_factor = 1.10, 99 .min_vblank_lines = 14, 100 .dppclk_delay_subtotal = 90, 101 .dispclk_delay_subtotal = 42, 102 .dcfclk_cstate_latency = 10, 103 .max_inter_dcn_tile_repeaters = 8, 104 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 105 .bug_forcing_LC_req_same_size_fixed = 0, 106 }; 107 108 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 109 .sr_exit_time_us = 9.0, 110 .sr_enter_plus_exit_time_us = 11.0, 111 .urgent_latency_us = 4.0, 112 .writeback_latency_us = 12.0, 113 .ideal_dram_bw_after_urgent_percent = 80.0, 114 .max_request_size_bytes = 256, 115 .downspread_percent = 0.5, 116 .dram_page_open_time_ns = 50.0, 117 .dram_rw_turnaround_time_ns = 17.5, 118 .dram_return_buffer_per_channel_bytes = 8192, 119 .round_trip_ping_latency_dcfclk_cycles = 128, 120 .urgent_out_of_order_return_per_channel_bytes = 256, 121 .channel_interleave_bytes = 256, 122 .num_banks = 8, 123 .num_chans = 2, 124 .vmm_page_size_bytes = 4096, 125 .dram_clock_change_latency_us = 17.0, 126 .writeback_dram_clock_change_latency_us = 23.0, 127 .return_bus_width_bytes = 64, 128 }; 129 130 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 131 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 132 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 133 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 134 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 136 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 138 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 140 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 142 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 144 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #endif 146 147 148 enum dcn10_clk_src_array_id { 149 DCN10_CLK_SRC_PLL0, 150 DCN10_CLK_SRC_PLL1, 151 DCN10_CLK_SRC_PLL2, 152 DCN10_CLK_SRC_PLL3, 153 DCN10_CLK_SRC_TOTAL 154 }; 155 156 /* begin ********************* 157 * macros to expend register list macro defined in HW object header file */ 158 159 /* DCN */ 160 #define BASE_INNER(seg) \ 161 DCE_BASE__INST0_SEG ## seg 162 163 #define BASE(seg) \ 164 BASE_INNER(seg) 165 166 #define SR(reg_name)\ 167 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 168 mm ## reg_name 169 170 #define SRI(reg_name, block, id)\ 171 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 172 mm ## block ## id ## _ ## reg_name 173 174 175 #define SRII(reg_name, block, id)\ 176 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 mm ## block ## id ## _ ## reg_name 178 179 /* NBIO */ 180 #define NBIO_BASE_INNER(seg) \ 181 NBIF_BASE__INST0_SEG ## seg 182 183 #define NBIO_BASE(seg) \ 184 NBIO_BASE_INNER(seg) 185 186 #define NBIO_SR(reg_name)\ 187 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 188 mm ## reg_name 189 190 /* MMHUB */ 191 #define MMHUB_BASE_INNER(seg) \ 192 MMHUB_BASE__INST0_SEG ## seg 193 194 #define MMHUB_BASE(seg) \ 195 MMHUB_BASE_INNER(seg) 196 197 #define MMHUB_SR(reg_name)\ 198 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 199 mm ## reg_name 200 201 /* macros to expend register list macro defined in HW object header file 202 * end *********************/ 203 204 205 static const struct dce_dmcu_registers dmcu_regs = { 206 DMCU_DCN10_REG_LIST() 207 }; 208 209 static const struct dce_dmcu_shift dmcu_shift = { 210 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 211 }; 212 213 static const struct dce_dmcu_mask dmcu_mask = { 214 DMCU_MASK_SH_LIST_DCN10(_MASK) 215 }; 216 217 static const struct dce_abm_registers abm_regs = { 218 ABM_DCN10_REG_LIST(0) 219 }; 220 221 static const struct dce_abm_shift abm_shift = { 222 ABM_MASK_SH_LIST_DCN10(__SHIFT) 223 }; 224 225 static const struct dce_abm_mask abm_mask = { 226 ABM_MASK_SH_LIST_DCN10(_MASK) 227 }; 228 229 #define stream_enc_regs(id)\ 230 [id] = {\ 231 SE_DCN_REG_LIST(id)\ 232 } 233 234 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 235 stream_enc_regs(0), 236 stream_enc_regs(1), 237 stream_enc_regs(2), 238 stream_enc_regs(3), 239 }; 240 241 static const struct dcn10_stream_encoder_shift se_shift = { 242 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 243 }; 244 245 static const struct dcn10_stream_encoder_mask se_mask = { 246 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 247 }; 248 249 #define audio_regs(id)\ 250 [id] = {\ 251 AUD_COMMON_REG_LIST(id)\ 252 } 253 254 static const struct dce_audio_registers audio_regs[] = { 255 audio_regs(0), 256 audio_regs(1), 257 audio_regs(2), 258 audio_regs(3), 259 }; 260 261 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 262 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 263 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 264 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 265 266 static const struct dce_audio_shift audio_shift = { 267 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 268 }; 269 270 static const struct dce_aduio_mask audio_mask = { 271 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 272 }; 273 274 #define aux_regs(id)\ 275 [id] = {\ 276 AUX_REG_LIST(id)\ 277 } 278 279 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 280 aux_regs(0), 281 aux_regs(1), 282 aux_regs(2), 283 aux_regs(3) 284 }; 285 286 #define hpd_regs(id)\ 287 [id] = {\ 288 HPD_REG_LIST(id)\ 289 } 290 291 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 292 hpd_regs(0), 293 hpd_regs(1), 294 hpd_regs(2), 295 hpd_regs(3) 296 }; 297 298 #define link_regs(id)\ 299 [id] = {\ 300 LE_DCN10_REG_LIST(id), \ 301 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 302 } 303 304 static const struct dcn10_link_enc_registers link_enc_regs[] = { 305 link_regs(0), 306 link_regs(1), 307 link_regs(2), 308 link_regs(3) 309 }; 310 311 static const struct dcn10_link_enc_shift le_shift = { 312 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 313 }; 314 315 static const struct dcn10_link_enc_mask le_mask = { 316 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 317 }; 318 319 #define ipp_regs(id)\ 320 [id] = {\ 321 IPP_REG_LIST_DCN10(id),\ 322 } 323 324 static const struct dcn10_ipp_registers ipp_regs[] = { 325 ipp_regs(0), 326 ipp_regs(1), 327 ipp_regs(2), 328 ipp_regs(3), 329 }; 330 331 static const struct dcn10_ipp_shift ipp_shift = { 332 IPP_MASK_SH_LIST_DCN10(__SHIFT) 333 }; 334 335 static const struct dcn10_ipp_mask ipp_mask = { 336 IPP_MASK_SH_LIST_DCN10(_MASK), 337 }; 338 339 #define opp_regs(id)\ 340 [id] = {\ 341 OPP_REG_LIST_DCN10(id),\ 342 } 343 344 static const struct dcn10_opp_registers opp_regs[] = { 345 opp_regs(0), 346 opp_regs(1), 347 opp_regs(2), 348 opp_regs(3), 349 }; 350 351 static const struct dcn10_opp_shift opp_shift = { 352 OPP_MASK_SH_LIST_DCN10(__SHIFT) 353 }; 354 355 static const struct dcn10_opp_mask opp_mask = { 356 OPP_MASK_SH_LIST_DCN10(_MASK), 357 }; 358 359 #define tf_regs(id)\ 360 [id] = {\ 361 TF_REG_LIST_DCN10(id),\ 362 } 363 364 static const struct dcn_dpp_registers tf_regs[] = { 365 tf_regs(0), 366 tf_regs(1), 367 tf_regs(2), 368 tf_regs(3), 369 }; 370 371 static const struct dcn_dpp_shift tf_shift = { 372 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 373 TF_DEBUG_REG_LIST_SH_DCN10 374 375 }; 376 377 static const struct dcn_dpp_mask tf_mask = { 378 TF_REG_LIST_SH_MASK_DCN10(_MASK), 379 TF_DEBUG_REG_LIST_MASK_DCN10 380 }; 381 382 static const struct dcn_mpc_registers mpc_regs = { 383 MPC_COMMON_REG_LIST_DCN1_0(0), 384 MPC_COMMON_REG_LIST_DCN1_0(1), 385 MPC_COMMON_REG_LIST_DCN1_0(2), 386 MPC_COMMON_REG_LIST_DCN1_0(3), 387 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 388 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 389 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 390 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 391 }; 392 393 static const struct dcn_mpc_shift mpc_shift = { 394 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 395 }; 396 397 static const struct dcn_mpc_mask mpc_mask = { 398 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 399 }; 400 401 #define tg_regs(id)\ 402 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 403 404 static const struct dcn_optc_registers tg_regs[] = { 405 tg_regs(0), 406 tg_regs(1), 407 tg_regs(2), 408 tg_regs(3), 409 }; 410 411 static const struct dcn_optc_shift tg_shift = { 412 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 413 }; 414 415 static const struct dcn_optc_mask tg_mask = { 416 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 417 }; 418 419 420 static const struct bios_registers bios_regs = { 421 NBIO_SR(BIOS_SCRATCH_3), 422 NBIO_SR(BIOS_SCRATCH_6) 423 }; 424 425 #define hubp_regs(id)\ 426 [id] = {\ 427 HUBP_REG_LIST_DCN10(id)\ 428 } 429 430 431 static const struct dcn_mi_registers hubp_regs[] = { 432 hubp_regs(0), 433 hubp_regs(1), 434 hubp_regs(2), 435 hubp_regs(3), 436 }; 437 438 static const struct dcn_mi_shift hubp_shift = { 439 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 440 }; 441 442 static const struct dcn_mi_mask hubp_mask = { 443 HUBP_MASK_SH_LIST_DCN10(_MASK) 444 }; 445 446 447 static const struct dcn_hubbub_registers hubbub_reg = { 448 HUBBUB_REG_LIST_DCN10(0) 449 }; 450 451 static const struct dcn_hubbub_shift hubbub_shift = { 452 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 453 }; 454 455 static const struct dcn_hubbub_mask hubbub_mask = { 456 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 457 }; 458 459 #define clk_src_regs(index, pllid)\ 460 [index] = {\ 461 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 462 } 463 464 static const struct dce110_clk_src_regs clk_src_regs[] = { 465 clk_src_regs(0, A), 466 clk_src_regs(1, B), 467 clk_src_regs(2, C), 468 clk_src_regs(3, D) 469 }; 470 471 static const struct dce110_clk_src_shift cs_shift = { 472 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 473 }; 474 475 static const struct dce110_clk_src_mask cs_mask = { 476 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 477 }; 478 479 480 static const struct resource_caps res_cap = { 481 .num_timing_generator = 4, 482 .num_opp = 4, 483 .num_video_plane = 4, 484 .num_audio = 4, 485 .num_stream_encoder = 4, 486 .num_pll = 4, 487 }; 488 489 static const struct dc_debug debug_defaults_drv = { 490 .sanity_checks = true, 491 .disable_dmcu = true, 492 .force_abm_enable = false, 493 .timing_trace = false, 494 .clock_trace = true, 495 496 /* raven smu dones't allow 0 disp clk, 497 * smu min disp clk limit is 50Mhz 498 * keep min disp clk 100Mhz avoid smu hang 499 */ 500 .min_disp_clk_khz = 100000, 501 502 .disable_pplib_clock_request = false, 503 .disable_pplib_wm_range = false, 504 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 505 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 506 .force_single_disp_pipe_split = true, 507 .disable_dcc = DCC_ENABLE, 508 .voltage_align_fclk = true, 509 .disable_stereo_support = true, 510 .vsr_support = true, 511 .performance_trace = false, 512 .az_endpoint_mute_only = true, 513 .recovery_enabled = false, /*enable this by default after testing.*/ 514 .max_downscale_src_width = 3840, 515 }; 516 517 static const struct dc_debug debug_defaults_diags = { 518 .disable_dmcu = true, 519 .force_abm_enable = false, 520 .timing_trace = true, 521 .clock_trace = true, 522 .disable_stutter = true, 523 .disable_pplib_clock_request = true, 524 .disable_pplib_wm_range = true 525 }; 526 527 static void dcn10_dpp_destroy(struct dpp **dpp) 528 { 529 kfree(TO_DCN10_DPP(*dpp)); 530 *dpp = NULL; 531 } 532 533 static struct dpp *dcn10_dpp_create( 534 struct dc_context *ctx, 535 uint32_t inst) 536 { 537 struct dcn10_dpp *dpp = 538 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 539 540 if (!dpp) 541 return NULL; 542 543 dpp1_construct(dpp, ctx, inst, 544 &tf_regs[inst], &tf_shift, &tf_mask); 545 return &dpp->base; 546 } 547 548 static struct input_pixel_processor *dcn10_ipp_create( 549 struct dc_context *ctx, uint32_t inst) 550 { 551 struct dcn10_ipp *ipp = 552 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 553 554 if (!ipp) { 555 BREAK_TO_DEBUGGER(); 556 return NULL; 557 } 558 559 dcn10_ipp_construct(ipp, ctx, inst, 560 &ipp_regs[inst], &ipp_shift, &ipp_mask); 561 return &ipp->base; 562 } 563 564 565 static struct output_pixel_processor *dcn10_opp_create( 566 struct dc_context *ctx, uint32_t inst) 567 { 568 struct dcn10_opp *opp = 569 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 570 571 if (!opp) { 572 BREAK_TO_DEBUGGER(); 573 return NULL; 574 } 575 576 dcn10_opp_construct(opp, ctx, inst, 577 &opp_regs[inst], &opp_shift, &opp_mask); 578 return &opp->base; 579 } 580 581 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 582 { 583 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 584 GFP_KERNEL); 585 586 if (!mpc10) 587 return NULL; 588 589 dcn10_mpc_construct(mpc10, ctx, 590 &mpc_regs, 591 &mpc_shift, 592 &mpc_mask, 593 4); 594 595 return &mpc10->base; 596 } 597 598 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 599 { 600 struct hubbub *hubbub = kzalloc(sizeof(struct hubbub), 601 GFP_KERNEL); 602 603 if (!hubbub) 604 return NULL; 605 606 hubbub1_construct(hubbub, ctx, 607 &hubbub_reg, 608 &hubbub_shift, 609 &hubbub_mask); 610 611 return hubbub; 612 } 613 614 static struct timing_generator *dcn10_timing_generator_create( 615 struct dc_context *ctx, 616 uint32_t instance) 617 { 618 struct optc *tgn10 = 619 kzalloc(sizeof(struct optc), GFP_KERNEL); 620 621 if (!tgn10) 622 return NULL; 623 624 tgn10->base.inst = instance; 625 tgn10->base.ctx = ctx; 626 627 tgn10->tg_regs = &tg_regs[instance]; 628 tgn10->tg_shift = &tg_shift; 629 tgn10->tg_mask = &tg_mask; 630 631 dcn10_timing_generator_init(tgn10); 632 633 return &tgn10->base; 634 } 635 636 static const struct encoder_feature_support link_enc_feature = { 637 .max_hdmi_deep_color = COLOR_DEPTH_121212, 638 .max_hdmi_pixel_clock = 600000, 639 .ycbcr420_supported = true, 640 .flags.bits.IS_HBR2_CAPABLE = true, 641 .flags.bits.IS_HBR3_CAPABLE = true, 642 .flags.bits.IS_TPS3_CAPABLE = true, 643 .flags.bits.IS_TPS4_CAPABLE = true, 644 .flags.bits.IS_YCBCR_CAPABLE = true 645 }; 646 647 struct link_encoder *dcn10_link_encoder_create( 648 const struct encoder_init_data *enc_init_data) 649 { 650 struct dcn10_link_encoder *enc10 = 651 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 652 653 if (!enc10) 654 return NULL; 655 656 dcn10_link_encoder_construct(enc10, 657 enc_init_data, 658 &link_enc_feature, 659 &link_enc_regs[enc_init_data->transmitter], 660 &link_enc_aux_regs[enc_init_data->channel - 1], 661 &link_enc_hpd_regs[enc_init_data->hpd_source], 662 &le_shift, 663 &le_mask); 664 665 return &enc10->base; 666 } 667 668 struct clock_source *dcn10_clock_source_create( 669 struct dc_context *ctx, 670 struct dc_bios *bios, 671 enum clock_source_id id, 672 const struct dce110_clk_src_regs *regs, 673 bool dp_clk_src) 674 { 675 struct dce110_clk_src *clk_src = 676 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 677 678 if (!clk_src) 679 return NULL; 680 681 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 682 regs, &cs_shift, &cs_mask)) { 683 clk_src->base.dp_clk_src = dp_clk_src; 684 return &clk_src->base; 685 } 686 687 BREAK_TO_DEBUGGER(); 688 return NULL; 689 } 690 691 static void read_dce_straps( 692 struct dc_context *ctx, 693 struct resource_straps *straps) 694 { 695 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 696 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 697 } 698 699 static struct audio *create_audio( 700 struct dc_context *ctx, unsigned int inst) 701 { 702 return dce_audio_create(ctx, inst, 703 &audio_regs[inst], &audio_shift, &audio_mask); 704 } 705 706 static struct stream_encoder *dcn10_stream_encoder_create( 707 enum engine_id eng_id, 708 struct dc_context *ctx) 709 { 710 struct dcn10_stream_encoder *enc1 = 711 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 712 713 if (!enc1) 714 return NULL; 715 716 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 717 &stream_enc_regs[eng_id], 718 &se_shift, &se_mask); 719 return &enc1->base; 720 } 721 722 static const struct dce_hwseq_registers hwseq_reg = { 723 HWSEQ_DCN1_REG_LIST() 724 }; 725 726 static const struct dce_hwseq_shift hwseq_shift = { 727 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 728 }; 729 730 static const struct dce_hwseq_mask hwseq_mask = { 731 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 732 }; 733 734 static struct dce_hwseq *dcn10_hwseq_create( 735 struct dc_context *ctx) 736 { 737 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 738 739 if (hws) { 740 hws->ctx = ctx; 741 hws->regs = &hwseq_reg; 742 hws->shifts = &hwseq_shift; 743 hws->masks = &hwseq_mask; 744 hws->wa.DEGVIDCN10_253 = true; 745 hws->wa.false_optc_underflow = true; 746 hws->wa.DEGVIDCN10_254 = true; 747 } 748 return hws; 749 } 750 751 static const struct resource_create_funcs res_create_funcs = { 752 .read_dce_straps = read_dce_straps, 753 .create_audio = create_audio, 754 .create_stream_encoder = dcn10_stream_encoder_create, 755 .create_hwseq = dcn10_hwseq_create, 756 }; 757 758 static const struct resource_create_funcs res_create_maximus_funcs = { 759 .read_dce_straps = NULL, 760 .create_audio = NULL, 761 .create_stream_encoder = NULL, 762 .create_hwseq = dcn10_hwseq_create, 763 }; 764 765 void dcn10_clock_source_destroy(struct clock_source **clk_src) 766 { 767 kfree(TO_DCE110_CLK_SRC(*clk_src)); 768 *clk_src = NULL; 769 } 770 771 static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) 772 { 773 struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 774 775 if (!pp_smu) 776 return pp_smu; 777 778 dm_pp_get_funcs_rv(ctx, pp_smu); 779 return pp_smu; 780 } 781 782 static void destruct(struct dcn10_resource_pool *pool) 783 { 784 unsigned int i; 785 786 for (i = 0; i < pool->base.stream_enc_count; i++) { 787 if (pool->base.stream_enc[i] != NULL) { 788 /* TODO: free dcn version of stream encoder once implemented 789 * rather than using virtual stream encoder 790 */ 791 kfree(pool->base.stream_enc[i]); 792 pool->base.stream_enc[i] = NULL; 793 } 794 } 795 796 if (pool->base.mpc != NULL) { 797 kfree(TO_DCN10_MPC(pool->base.mpc)); 798 pool->base.mpc = NULL; 799 } 800 801 if (pool->base.hubbub != NULL) { 802 kfree(pool->base.hubbub); 803 pool->base.hubbub = NULL; 804 } 805 806 for (i = 0; i < pool->base.pipe_count; i++) { 807 if (pool->base.opps[i] != NULL) 808 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 809 810 if (pool->base.dpps[i] != NULL) 811 dcn10_dpp_destroy(&pool->base.dpps[i]); 812 813 if (pool->base.ipps[i] != NULL) 814 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 815 816 if (pool->base.hubps[i] != NULL) { 817 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 818 pool->base.hubps[i] = NULL; 819 } 820 821 if (pool->base.irqs != NULL) { 822 dal_irq_service_destroy(&pool->base.irqs); 823 } 824 825 if (pool->base.timing_generators[i] != NULL) { 826 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 827 pool->base.timing_generators[i] = NULL; 828 } 829 } 830 831 for (i = 0; i < pool->base.stream_enc_count; i++) 832 kfree(pool->base.stream_enc[i]); 833 834 for (i = 0; i < pool->base.audio_count; i++) { 835 if (pool->base.audios[i]) 836 dce_aud_destroy(&pool->base.audios[i]); 837 } 838 839 for (i = 0; i < pool->base.clk_src_count; i++) { 840 if (pool->base.clock_sources[i] != NULL) { 841 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 842 pool->base.clock_sources[i] = NULL; 843 } 844 } 845 846 if (pool->base.dp_clock_source != NULL) { 847 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 848 pool->base.dp_clock_source = NULL; 849 } 850 851 if (pool->base.abm != NULL) 852 dce_abm_destroy(&pool->base.abm); 853 854 if (pool->base.dmcu != NULL) 855 dce_dmcu_destroy(&pool->base.dmcu); 856 857 if (pool->base.dccg != NULL) 858 dce_dccg_destroy(&pool->base.dccg); 859 860 kfree(pool->base.pp_smu); 861 } 862 863 static struct hubp *dcn10_hubp_create( 864 struct dc_context *ctx, 865 uint32_t inst) 866 { 867 struct dcn10_hubp *hubp1 = 868 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 869 870 if (!hubp1) 871 return NULL; 872 873 dcn10_hubp_construct(hubp1, ctx, inst, 874 &hubp_regs[inst], &hubp_shift, &hubp_mask); 875 return &hubp1->base; 876 } 877 878 static void get_pixel_clock_parameters( 879 const struct pipe_ctx *pipe_ctx, 880 struct pixel_clk_params *pixel_clk_params) 881 { 882 const struct dc_stream_state *stream = pipe_ctx->stream; 883 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 884 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 885 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 886 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 887 /* TODO: un-hardcode*/ 888 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 889 LINK_RATE_REF_FREQ_IN_KHZ; 890 pixel_clk_params->flags.ENABLE_SS = 0; 891 pixel_clk_params->color_depth = 892 stream->timing.display_color_depth; 893 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 894 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 895 896 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 897 pixel_clk_params->color_depth = COLOR_DEPTH_888; 898 899 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 900 pixel_clk_params->requested_pix_clk /= 2; 901 902 } 903 904 static void build_clamping_params(struct dc_stream_state *stream) 905 { 906 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 907 stream->clamping.c_depth = stream->timing.display_color_depth; 908 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 909 } 910 911 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 912 { 913 914 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 915 916 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 917 pipe_ctx->clock_source, 918 &pipe_ctx->stream_res.pix_clk_params, 919 &pipe_ctx->pll_settings); 920 921 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 922 923 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 924 &pipe_ctx->stream->bit_depth_params); 925 build_clamping_params(pipe_ctx->stream); 926 } 927 928 static enum dc_status build_mapped_resource( 929 const struct dc *dc, 930 struct dc_state *context, 931 struct dc_stream_state *stream) 932 { 933 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 934 935 /*TODO Seems unneeded anymore */ 936 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 937 if (stream != NULL && old_context->streams[i] != NULL) { 938 todo: shouldn't have to copy missing parameter here 939 resource_build_bit_depth_reduction_params(stream, 940 &stream->bit_depth_params); 941 stream->clamping.pixel_encoding = 942 stream->timing.pixel_encoding; 943 944 resource_build_bit_depth_reduction_params(stream, 945 &stream->bit_depth_params); 946 build_clamping_params(stream); 947 948 continue; 949 } 950 } 951 */ 952 953 if (!pipe_ctx) 954 return DC_ERROR_UNEXPECTED; 955 956 build_pipe_hw_param(pipe_ctx); 957 return DC_OK; 958 } 959 960 enum dc_status dcn10_add_stream_to_ctx( 961 struct dc *dc, 962 struct dc_state *new_ctx, 963 struct dc_stream_state *dc_stream) 964 { 965 enum dc_status result = DC_ERROR_UNEXPECTED; 966 967 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 968 969 if (result == DC_OK) 970 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 971 972 973 if (result == DC_OK) 974 result = build_mapped_resource(dc, new_ctx, dc_stream); 975 976 return result; 977 } 978 979 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 980 struct dc_state *context, 981 const struct resource_pool *pool, 982 struct dc_stream_state *stream) 983 { 984 struct resource_context *res_ctx = &context->res_ctx; 985 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 986 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool); 987 988 if (!head_pipe) { 989 ASSERT(0); 990 return NULL; 991 } 992 993 if (!idle_pipe) 994 return NULL; 995 996 idle_pipe->stream = head_pipe->stream; 997 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 998 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 999 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1000 1001 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1002 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1003 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1004 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1005 1006 return idle_pipe; 1007 } 1008 1009 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1010 const struct dc_dcc_surface_param *input, 1011 struct dc_surface_dcc_cap *output) 1012 { 1013 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1014 dc->res_pool->hubbub, 1015 input, 1016 output); 1017 } 1018 1019 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1020 { 1021 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1022 1023 destruct(dcn10_pool); 1024 kfree(dcn10_pool); 1025 *pool = NULL; 1026 } 1027 1028 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1029 { 1030 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1031 && caps->max_video_width != 0 1032 && plane_state->src_rect.width > caps->max_video_width) 1033 return DC_FAIL_SURFACE_VALIDATE; 1034 1035 return DC_OK; 1036 } 1037 1038 static const struct dc_cap_funcs cap_funcs = { 1039 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1040 }; 1041 1042 static const struct resource_funcs dcn10_res_pool_funcs = { 1043 .destroy = dcn10_destroy_resource_pool, 1044 .link_enc_create = dcn10_link_encoder_create, 1045 .validate_bandwidth = dcn_validate_bandwidth, 1046 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1047 .validate_plane = dcn10_validate_plane, 1048 .add_stream_to_ctx = dcn10_add_stream_to_ctx 1049 }; 1050 1051 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1052 { 1053 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1054 /* RV1 support max 4 pipes */ 1055 value = value & 0xf; 1056 return value; 1057 } 1058 1059 static bool construct( 1060 uint8_t num_virtual_links, 1061 struct dc *dc, 1062 struct dcn10_resource_pool *pool) 1063 { 1064 int i; 1065 int j; 1066 struct dc_context *ctx = dc->ctx; 1067 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1068 1069 ctx->dc_bios->regs = &bios_regs; 1070 1071 pool->base.res_cap = &res_cap; 1072 pool->base.funcs = &dcn10_res_pool_funcs; 1073 1074 /* 1075 * TODO fill in from actual raven resource when we create 1076 * more than virtual encoder 1077 */ 1078 1079 /************************************************* 1080 * Resource + asic cap harcoding * 1081 *************************************************/ 1082 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1083 1084 /* max pipe num for ASIC before check pipe fuses */ 1085 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1086 1087 dc->caps.max_video_width = 3840; 1088 dc->caps.max_downscale_ratio = 200; 1089 dc->caps.i2c_speed_in_khz = 100; 1090 dc->caps.max_cursor_size = 256; 1091 dc->caps.max_slave_planes = 1; 1092 dc->caps.is_apu = true; 1093 dc->caps.post_blend_color_processing = false; 1094 1095 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1096 dc->debug = debug_defaults_drv; 1097 else 1098 dc->debug = debug_defaults_diags; 1099 1100 /************************************************* 1101 * Create resources * 1102 *************************************************/ 1103 1104 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1105 dcn10_clock_source_create(ctx, ctx->dc_bios, 1106 CLOCK_SOURCE_COMBO_PHY_PLL0, 1107 &clk_src_regs[0], false); 1108 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1109 dcn10_clock_source_create(ctx, ctx->dc_bios, 1110 CLOCK_SOURCE_COMBO_PHY_PLL1, 1111 &clk_src_regs[1], false); 1112 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1113 dcn10_clock_source_create(ctx, ctx->dc_bios, 1114 CLOCK_SOURCE_COMBO_PHY_PLL2, 1115 &clk_src_regs[2], false); 1116 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1117 dcn10_clock_source_create(ctx, ctx->dc_bios, 1118 CLOCK_SOURCE_COMBO_PHY_PLL3, 1119 &clk_src_regs[3], false); 1120 1121 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1122 1123 pool->base.dp_clock_source = 1124 dcn10_clock_source_create(ctx, ctx->dc_bios, 1125 CLOCK_SOURCE_ID_DP_DTO, 1126 /* todo: not reuse phy_pll registers */ 1127 &clk_src_regs[0], true); 1128 1129 for (i = 0; i < pool->base.clk_src_count; i++) { 1130 if (pool->base.clock_sources[i] == NULL) { 1131 dm_error("DC: failed to create clock sources!\n"); 1132 BREAK_TO_DEBUGGER(); 1133 goto fail; 1134 } 1135 } 1136 1137 pool->base.dccg = dcn1_dccg_create(ctx); 1138 if (pool->base.dccg == NULL) { 1139 dm_error("DC: failed to create display clock!\n"); 1140 BREAK_TO_DEBUGGER(); 1141 goto fail; 1142 } 1143 1144 pool->base.dmcu = dcn10_dmcu_create(ctx, 1145 &dmcu_regs, 1146 &dmcu_shift, 1147 &dmcu_mask); 1148 if (pool->base.dmcu == NULL) { 1149 dm_error("DC: failed to create dmcu!\n"); 1150 BREAK_TO_DEBUGGER(); 1151 goto fail; 1152 } 1153 1154 pool->base.abm = dce_abm_create(ctx, 1155 &abm_regs, 1156 &abm_shift, 1157 &abm_mask); 1158 if (pool->base.abm == NULL) { 1159 dm_error("DC: failed to create abm!\n"); 1160 BREAK_TO_DEBUGGER(); 1161 goto fail; 1162 } 1163 1164 dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1); 1165 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1166 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1167 1168 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1169 dc->dcn_soc->urgent_latency = 3; 1170 dc->debug.disable_dmcu = true; 1171 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1172 } 1173 1174 1175 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1176 ASSERT(dc->dcn_soc->number_of_channels < 3); 1177 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1178 dc->dcn_soc->number_of_channels = 2; 1179 1180 if (dc->dcn_soc->number_of_channels == 1) { 1181 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1182 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1183 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1184 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1185 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1186 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1187 } 1188 } 1189 1190 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1191 1192 if (!dc->debug.disable_pplib_clock_request) 1193 dcn_bw_update_from_pplib(dc); 1194 dcn_bw_sync_calcs_and_dml(dc); 1195 if (!dc->debug.disable_pplib_wm_range) { 1196 dc->res_pool = &pool->base; 1197 dcn_bw_notify_pplib_of_wm_ranges(dc); 1198 } 1199 1200 { 1201 struct irq_service_init_data init_data; 1202 init_data.ctx = dc->ctx; 1203 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1204 if (!pool->base.irqs) 1205 goto fail; 1206 } 1207 1208 /* index to valid pipe resource */ 1209 j = 0; 1210 /* mem input -> ipp -> dpp -> opp -> TG */ 1211 for (i = 0; i < pool->base.pipe_count; i++) { 1212 /* if pipe is disabled, skip instance of HW pipe, 1213 * i.e, skip ASIC register instance 1214 */ 1215 if ((pipe_fuses & (1 << i)) != 0) 1216 continue; 1217 1218 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1219 if (pool->base.hubps[j] == NULL) { 1220 BREAK_TO_DEBUGGER(); 1221 dm_error( 1222 "DC: failed to create memory input!\n"); 1223 goto fail; 1224 } 1225 1226 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1227 if (pool->base.ipps[j] == NULL) { 1228 BREAK_TO_DEBUGGER(); 1229 dm_error( 1230 "DC: failed to create input pixel processor!\n"); 1231 goto fail; 1232 } 1233 1234 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1235 if (pool->base.dpps[j] == NULL) { 1236 BREAK_TO_DEBUGGER(); 1237 dm_error( 1238 "DC: failed to create dpp!\n"); 1239 goto fail; 1240 } 1241 1242 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1243 if (pool->base.opps[j] == NULL) { 1244 BREAK_TO_DEBUGGER(); 1245 dm_error( 1246 "DC: failed to create output pixel processor!\n"); 1247 goto fail; 1248 } 1249 1250 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1251 ctx, i); 1252 if (pool->base.timing_generators[j] == NULL) { 1253 BREAK_TO_DEBUGGER(); 1254 dm_error("DC: failed to create tg!\n"); 1255 goto fail; 1256 } 1257 1258 /* check next valid pipe */ 1259 j++; 1260 } 1261 1262 /* valid pipe num */ 1263 pool->base.pipe_count = j; 1264 pool->base.timing_generator_count = j; 1265 1266 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1267 * the value may be changed 1268 */ 1269 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1270 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1271 1272 pool->base.mpc = dcn10_mpc_create(ctx); 1273 if (pool->base.mpc == NULL) { 1274 BREAK_TO_DEBUGGER(); 1275 dm_error("DC: failed to create mpc!\n"); 1276 goto fail; 1277 } 1278 1279 pool->base.hubbub = dcn10_hubbub_create(ctx); 1280 if (pool->base.hubbub == NULL) { 1281 BREAK_TO_DEBUGGER(); 1282 dm_error("DC: failed to create hubbub!\n"); 1283 goto fail; 1284 } 1285 1286 if (!resource_construct(num_virtual_links, dc, &pool->base, 1287 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1288 &res_create_funcs : &res_create_maximus_funcs))) 1289 goto fail; 1290 1291 dcn10_hw_sequencer_construct(dc); 1292 dc->caps.max_planes = pool->base.pipe_count; 1293 1294 dc->cap_funcs = cap_funcs; 1295 1296 return true; 1297 1298 fail: 1299 1300 destruct(pool); 1301 1302 return false; 1303 } 1304 1305 struct resource_pool *dcn10_create_resource_pool( 1306 uint8_t num_virtual_links, 1307 struct dc *dc) 1308 { 1309 struct dcn10_resource_pool *pool = 1310 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1311 1312 if (!pool) 1313 return NULL; 1314 1315 if (construct(num_virtual_links, dc, pool)) 1316 return &pool->base; 1317 1318 BREAK_TO_DEBUGGER(); 1319 return NULL; 1320 } 1321