1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn10_resource.h" 32 #include "dcn10_ipp.h" 33 #include "dcn10_mpc.h" 34 #include "irq/dcn10/irq_service_dcn10.h" 35 #include "dcn10_dpp.h" 36 #include "dcn10_optc.h" 37 #include "dcn10_hw_sequencer.h" 38 #include "dce110/dce110_hw_sequencer.h" 39 #include "dcn10_opp.h" 40 #include "dcn10_link_encoder.h" 41 #include "dcn10_stream_encoder.h" 42 #include "dce/dce_clock_source.h" 43 #include "dce/dce_audio.h" 44 #include "dce/dce_hwseq.h" 45 #include "virtual/virtual_stream_encoder.h" 46 #include "dce110/dce110_resource.h" 47 #include "dce112/dce112_resource.h" 48 #include "dcn10_hubp.h" 49 #include "dcn10_hubbub.h" 50 51 #include "soc15_hw_ip.h" 52 #include "vega10_ip_offset.h" 53 54 #include "dcn/dcn_1_0_offset.h" 55 #include "dcn/dcn_1_0_sh_mask.h" 56 57 #include "nbio/nbio_7_0_offset.h" 58 59 #include "mmhub/mmhub_9_1_offset.h" 60 #include "mmhub/mmhub_9_1_sh_mask.h" 61 62 #include "reg_helper.h" 63 #include "dce/dce_abm.h" 64 #include "dce/dce_dmcu.h" 65 #include "dce/dce_aux.h" 66 #include "dce/dce_i2c.h" 67 68 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 69 .rob_buffer_size_kbytes = 64, 70 .det_buffer_size_kbytes = 164, 71 .dpte_buffer_size_in_pte_reqs_luma = 42, 72 .dpp_output_buffer_pixels = 2560, 73 .opp_output_buffer_lines = 1, 74 .pixel_chunk_size_kbytes = 8, 75 .pte_enable = 1, 76 .pte_chunk_size_kbytes = 2, 77 .meta_chunk_size_kbytes = 2, 78 .writeback_chunk_size_kbytes = 2, 79 .line_buffer_size_bits = 589824, 80 .max_line_buffer_lines = 12, 81 .IsLineBufferBppFixed = 0, 82 .LineBufferFixedBpp = -1, 83 .writeback_luma_buffer_size_kbytes = 12, 84 .writeback_chroma_buffer_size_kbytes = 8, 85 .max_num_dpp = 4, 86 .max_num_wb = 2, 87 .max_dchub_pscl_bw_pix_per_clk = 4, 88 .max_pscl_lb_bw_pix_per_clk = 2, 89 .max_lb_vscl_bw_pix_per_clk = 4, 90 .max_vscl_hscl_bw_pix_per_clk = 4, 91 .max_hscl_ratio = 4, 92 .max_vscl_ratio = 4, 93 .hscl_mults = 4, 94 .vscl_mults = 4, 95 .max_hscl_taps = 8, 96 .max_vscl_taps = 8, 97 .dispclk_ramp_margin_percent = 1, 98 .underscan_factor = 1.10, 99 .min_vblank_lines = 14, 100 .dppclk_delay_subtotal = 90, 101 .dispclk_delay_subtotal = 42, 102 .dcfclk_cstate_latency = 10, 103 .max_inter_dcn_tile_repeaters = 8, 104 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 105 .bug_forcing_LC_req_same_size_fixed = 0, 106 }; 107 108 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 109 .sr_exit_time_us = 9.0, 110 .sr_enter_plus_exit_time_us = 11.0, 111 .urgent_latency_us = 4.0, 112 .writeback_latency_us = 12.0, 113 .ideal_dram_bw_after_urgent_percent = 80.0, 114 .max_request_size_bytes = 256, 115 .downspread_percent = 0.5, 116 .dram_page_open_time_ns = 50.0, 117 .dram_rw_turnaround_time_ns = 17.5, 118 .dram_return_buffer_per_channel_bytes = 8192, 119 .round_trip_ping_latency_dcfclk_cycles = 128, 120 .urgent_out_of_order_return_per_channel_bytes = 256, 121 .channel_interleave_bytes = 256, 122 .num_banks = 8, 123 .num_chans = 2, 124 .vmm_page_size_bytes = 4096, 125 .dram_clock_change_latency_us = 17.0, 126 .writeback_dram_clock_change_latency_us = 23.0, 127 .return_bus_width_bytes = 64, 128 }; 129 130 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 131 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 132 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 133 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 134 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 136 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 138 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 140 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 142 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 144 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #endif 146 147 148 enum dcn10_clk_src_array_id { 149 DCN10_CLK_SRC_PLL0, 150 DCN10_CLK_SRC_PLL1, 151 DCN10_CLK_SRC_PLL2, 152 DCN10_CLK_SRC_PLL3, 153 DCN10_CLK_SRC_TOTAL, 154 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 155 }; 156 157 /* begin ********************* 158 * macros to expend register list macro defined in HW object header file */ 159 160 /* DCN */ 161 #define BASE_INNER(seg) \ 162 DCE_BASE__INST0_SEG ## seg 163 164 #define BASE(seg) \ 165 BASE_INNER(seg) 166 167 #define SR(reg_name)\ 168 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 169 mm ## reg_name 170 171 #define SRI(reg_name, block, id)\ 172 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 173 mm ## block ## id ## _ ## reg_name 174 175 176 #define SRII(reg_name, block, id)\ 177 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 178 mm ## block ## id ## _ ## reg_name 179 180 /* NBIO */ 181 #define NBIO_BASE_INNER(seg) \ 182 NBIF_BASE__INST0_SEG ## seg 183 184 #define NBIO_BASE(seg) \ 185 NBIO_BASE_INNER(seg) 186 187 #define NBIO_SR(reg_name)\ 188 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 189 mm ## reg_name 190 191 /* MMHUB */ 192 #define MMHUB_BASE_INNER(seg) \ 193 MMHUB_BASE__INST0_SEG ## seg 194 195 #define MMHUB_BASE(seg) \ 196 MMHUB_BASE_INNER(seg) 197 198 #define MMHUB_SR(reg_name)\ 199 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 200 mm ## reg_name 201 202 /* macros to expend register list macro defined in HW object header file 203 * end *********************/ 204 205 206 static const struct dce_dmcu_registers dmcu_regs = { 207 DMCU_DCN10_REG_LIST() 208 }; 209 210 static const struct dce_dmcu_shift dmcu_shift = { 211 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 212 }; 213 214 static const struct dce_dmcu_mask dmcu_mask = { 215 DMCU_MASK_SH_LIST_DCN10(_MASK) 216 }; 217 218 static const struct dce_abm_registers abm_regs = { 219 ABM_DCN10_REG_LIST(0) 220 }; 221 222 static const struct dce_abm_shift abm_shift = { 223 ABM_MASK_SH_LIST_DCN10(__SHIFT) 224 }; 225 226 static const struct dce_abm_mask abm_mask = { 227 ABM_MASK_SH_LIST_DCN10(_MASK) 228 }; 229 230 #define stream_enc_regs(id)\ 231 [id] = {\ 232 SE_DCN_REG_LIST(id)\ 233 } 234 235 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 236 stream_enc_regs(0), 237 stream_enc_regs(1), 238 stream_enc_regs(2), 239 stream_enc_regs(3), 240 }; 241 242 static const struct dcn10_stream_encoder_shift se_shift = { 243 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 244 }; 245 246 static const struct dcn10_stream_encoder_mask se_mask = { 247 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 248 }; 249 250 #define audio_regs(id)\ 251 [id] = {\ 252 AUD_COMMON_REG_LIST(id)\ 253 } 254 255 static const struct dce_audio_registers audio_regs[] = { 256 audio_regs(0), 257 audio_regs(1), 258 audio_regs(2), 259 audio_regs(3), 260 }; 261 262 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 263 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 264 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 265 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 266 267 static const struct dce_audio_shift audio_shift = { 268 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 269 }; 270 271 static const struct dce_aduio_mask audio_mask = { 272 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 273 }; 274 275 #define aux_regs(id)\ 276 [id] = {\ 277 AUX_REG_LIST(id)\ 278 } 279 280 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 281 aux_regs(0), 282 aux_regs(1), 283 aux_regs(2), 284 aux_regs(3) 285 }; 286 287 #define hpd_regs(id)\ 288 [id] = {\ 289 HPD_REG_LIST(id)\ 290 } 291 292 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 293 hpd_regs(0), 294 hpd_regs(1), 295 hpd_regs(2), 296 hpd_regs(3) 297 }; 298 299 #define link_regs(id)\ 300 [id] = {\ 301 LE_DCN10_REG_LIST(id), \ 302 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 303 } 304 305 static const struct dcn10_link_enc_registers link_enc_regs[] = { 306 link_regs(0), 307 link_regs(1), 308 link_regs(2), 309 link_regs(3) 310 }; 311 312 static const struct dcn10_link_enc_shift le_shift = { 313 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 314 }; 315 316 static const struct dcn10_link_enc_mask le_mask = { 317 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 318 }; 319 320 #define ipp_regs(id)\ 321 [id] = {\ 322 IPP_REG_LIST_DCN10(id),\ 323 } 324 325 static const struct dcn10_ipp_registers ipp_regs[] = { 326 ipp_regs(0), 327 ipp_regs(1), 328 ipp_regs(2), 329 ipp_regs(3), 330 }; 331 332 static const struct dcn10_ipp_shift ipp_shift = { 333 IPP_MASK_SH_LIST_DCN10(__SHIFT) 334 }; 335 336 static const struct dcn10_ipp_mask ipp_mask = { 337 IPP_MASK_SH_LIST_DCN10(_MASK), 338 }; 339 340 #define opp_regs(id)\ 341 [id] = {\ 342 OPP_REG_LIST_DCN10(id),\ 343 } 344 345 static const struct dcn10_opp_registers opp_regs[] = { 346 opp_regs(0), 347 opp_regs(1), 348 opp_regs(2), 349 opp_regs(3), 350 }; 351 352 static const struct dcn10_opp_shift opp_shift = { 353 OPP_MASK_SH_LIST_DCN10(__SHIFT) 354 }; 355 356 static const struct dcn10_opp_mask opp_mask = { 357 OPP_MASK_SH_LIST_DCN10(_MASK), 358 }; 359 360 #define aux_engine_regs(id)\ 361 [id] = {\ 362 AUX_COMMON_REG_LIST(id), \ 363 .AUX_RESET_MASK = 0 \ 364 } 365 366 static const struct dce110_aux_registers aux_engine_regs[] = { 367 aux_engine_regs(0), 368 aux_engine_regs(1), 369 aux_engine_regs(2), 370 aux_engine_regs(3), 371 aux_engine_regs(4), 372 aux_engine_regs(5) 373 }; 374 375 #define tf_regs(id)\ 376 [id] = {\ 377 TF_REG_LIST_DCN10(id),\ 378 } 379 380 static const struct dcn_dpp_registers tf_regs[] = { 381 tf_regs(0), 382 tf_regs(1), 383 tf_regs(2), 384 tf_regs(3), 385 }; 386 387 static const struct dcn_dpp_shift tf_shift = { 388 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 389 TF_DEBUG_REG_LIST_SH_DCN10 390 391 }; 392 393 static const struct dcn_dpp_mask tf_mask = { 394 TF_REG_LIST_SH_MASK_DCN10(_MASK), 395 TF_DEBUG_REG_LIST_MASK_DCN10 396 }; 397 398 static const struct dcn_mpc_registers mpc_regs = { 399 MPC_COMMON_REG_LIST_DCN1_0(0), 400 MPC_COMMON_REG_LIST_DCN1_0(1), 401 MPC_COMMON_REG_LIST_DCN1_0(2), 402 MPC_COMMON_REG_LIST_DCN1_0(3), 403 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 404 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 405 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 406 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 407 }; 408 409 static const struct dcn_mpc_shift mpc_shift = { 410 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 411 }; 412 413 static const struct dcn_mpc_mask mpc_mask = { 414 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 415 }; 416 417 #define tg_regs(id)\ 418 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 419 420 static const struct dcn_optc_registers tg_regs[] = { 421 tg_regs(0), 422 tg_regs(1), 423 tg_regs(2), 424 tg_regs(3), 425 }; 426 427 static const struct dcn_optc_shift tg_shift = { 428 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 429 }; 430 431 static const struct dcn_optc_mask tg_mask = { 432 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 433 }; 434 435 static const struct bios_registers bios_regs = { 436 NBIO_SR(BIOS_SCRATCH_3), 437 NBIO_SR(BIOS_SCRATCH_6) 438 }; 439 440 #define hubp_regs(id)\ 441 [id] = {\ 442 HUBP_REG_LIST_DCN10(id)\ 443 } 444 445 static const struct dcn_mi_registers hubp_regs[] = { 446 hubp_regs(0), 447 hubp_regs(1), 448 hubp_regs(2), 449 hubp_regs(3), 450 }; 451 452 static const struct dcn_mi_shift hubp_shift = { 453 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 454 }; 455 456 static const struct dcn_mi_mask hubp_mask = { 457 HUBP_MASK_SH_LIST_DCN10(_MASK) 458 }; 459 460 static const struct dcn_hubbub_registers hubbub_reg = { 461 HUBBUB_REG_LIST_DCN10(0) 462 }; 463 464 static const struct dcn_hubbub_shift hubbub_shift = { 465 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 466 }; 467 468 static const struct dcn_hubbub_mask hubbub_mask = { 469 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 470 }; 471 472 #define clk_src_regs(index, pllid)\ 473 [index] = {\ 474 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 475 } 476 477 static const struct dce110_clk_src_regs clk_src_regs[] = { 478 clk_src_regs(0, A), 479 clk_src_regs(1, B), 480 clk_src_regs(2, C), 481 clk_src_regs(3, D) 482 }; 483 484 static const struct dce110_clk_src_shift cs_shift = { 485 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 486 }; 487 488 static const struct dce110_clk_src_mask cs_mask = { 489 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 490 }; 491 492 static const struct resource_caps res_cap = { 493 .num_timing_generator = 4, 494 .num_opp = 4, 495 .num_video_plane = 4, 496 .num_audio = 4, 497 .num_stream_encoder = 4, 498 .num_pll = 4, 499 .num_ddc = 4, 500 }; 501 502 static const struct resource_caps rv2_res_cap = { 503 .num_timing_generator = 3, 504 .num_opp = 3, 505 .num_video_plane = 3, 506 .num_audio = 3, 507 .num_stream_encoder = 3, 508 .num_pll = 3, 509 .num_ddc = 3, 510 }; 511 512 static const struct dc_plane_cap plane_cap = { 513 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 514 .blends_with_above = true, 515 .blends_with_below = true, 516 .per_pixel_alpha = true, 517 518 .pixel_format_support = { 519 .argb8888 = true, 520 .nv12 = true, 521 .fp16 = true 522 }, 523 524 .max_upscale_factor = { 525 .argb8888 = 16000, 526 .nv12 = 16000, 527 .fp16 = 1 528 }, 529 530 .max_downscale_factor = { 531 .argb8888 = 250, 532 .nv12 = 250, 533 .fp16 = 1 534 } 535 }; 536 537 static const struct dc_debug_options debug_defaults_drv = { 538 .sanity_checks = true, 539 .disable_dmcu = true, 540 .force_abm_enable = false, 541 .timing_trace = false, 542 .clock_trace = true, 543 544 /* raven smu dones't allow 0 disp clk, 545 * smu min disp clk limit is 50Mhz 546 * keep min disp clk 100Mhz avoid smu hang 547 */ 548 .min_disp_clk_khz = 100000, 549 550 .disable_pplib_clock_request = false, 551 .disable_pplib_wm_range = false, 552 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 553 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 554 .force_single_disp_pipe_split = true, 555 .disable_dcc = DCC_ENABLE, 556 .voltage_align_fclk = true, 557 .disable_stereo_support = true, 558 .vsr_support = true, 559 .performance_trace = false, 560 .az_endpoint_mute_only = true, 561 .recovery_enabled = false, /*enable this by default after testing.*/ 562 .max_downscale_src_width = 3840, 563 }; 564 565 static const struct dc_debug_options debug_defaults_diags = { 566 .disable_dmcu = true, 567 .force_abm_enable = false, 568 .timing_trace = true, 569 .clock_trace = true, 570 .disable_stutter = true, 571 .disable_pplib_clock_request = true, 572 .disable_pplib_wm_range = true 573 }; 574 575 static void dcn10_dpp_destroy(struct dpp **dpp) 576 { 577 kfree(TO_DCN10_DPP(*dpp)); 578 *dpp = NULL; 579 } 580 581 static struct dpp *dcn10_dpp_create( 582 struct dc_context *ctx, 583 uint32_t inst) 584 { 585 struct dcn10_dpp *dpp = 586 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 587 588 if (!dpp) 589 return NULL; 590 591 dpp1_construct(dpp, ctx, inst, 592 &tf_regs[inst], &tf_shift, &tf_mask); 593 return &dpp->base; 594 } 595 596 static struct input_pixel_processor *dcn10_ipp_create( 597 struct dc_context *ctx, uint32_t inst) 598 { 599 struct dcn10_ipp *ipp = 600 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 601 602 if (!ipp) { 603 BREAK_TO_DEBUGGER(); 604 return NULL; 605 } 606 607 dcn10_ipp_construct(ipp, ctx, inst, 608 &ipp_regs[inst], &ipp_shift, &ipp_mask); 609 return &ipp->base; 610 } 611 612 613 static struct output_pixel_processor *dcn10_opp_create( 614 struct dc_context *ctx, uint32_t inst) 615 { 616 struct dcn10_opp *opp = 617 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 618 619 if (!opp) { 620 BREAK_TO_DEBUGGER(); 621 return NULL; 622 } 623 624 dcn10_opp_construct(opp, ctx, inst, 625 &opp_regs[inst], &opp_shift, &opp_mask); 626 return &opp->base; 627 } 628 629 struct dce_aux *dcn10_aux_engine_create( 630 struct dc_context *ctx, 631 uint32_t inst) 632 { 633 struct aux_engine_dce110 *aux_engine = 634 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 635 636 if (!aux_engine) 637 return NULL; 638 639 dce110_aux_engine_construct(aux_engine, ctx, inst, 640 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 641 &aux_engine_regs[inst]); 642 643 return &aux_engine->base; 644 } 645 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 646 647 static const struct dce_i2c_registers i2c_hw_regs[] = { 648 i2c_inst_regs(1), 649 i2c_inst_regs(2), 650 i2c_inst_regs(3), 651 i2c_inst_regs(4), 652 i2c_inst_regs(5), 653 i2c_inst_regs(6), 654 }; 655 656 static const struct dce_i2c_shift i2c_shifts = { 657 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 658 }; 659 660 static const struct dce_i2c_mask i2c_masks = { 661 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 662 }; 663 664 struct dce_i2c_hw *dcn10_i2c_hw_create( 665 struct dc_context *ctx, 666 uint32_t inst) 667 { 668 struct dce_i2c_hw *dce_i2c_hw = 669 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 670 671 if (!dce_i2c_hw) 672 return NULL; 673 674 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 675 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 676 677 return dce_i2c_hw; 678 } 679 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 680 { 681 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 682 GFP_KERNEL); 683 684 if (!mpc10) 685 return NULL; 686 687 dcn10_mpc_construct(mpc10, ctx, 688 &mpc_regs, 689 &mpc_shift, 690 &mpc_mask, 691 4); 692 693 return &mpc10->base; 694 } 695 696 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 697 { 698 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 699 GFP_KERNEL); 700 701 if (!dcn10_hubbub) 702 return NULL; 703 704 hubbub1_construct(&dcn10_hubbub->base, ctx, 705 &hubbub_reg, 706 &hubbub_shift, 707 &hubbub_mask); 708 709 return &dcn10_hubbub->base; 710 } 711 712 static struct timing_generator *dcn10_timing_generator_create( 713 struct dc_context *ctx, 714 uint32_t instance) 715 { 716 struct optc *tgn10 = 717 kzalloc(sizeof(struct optc), GFP_KERNEL); 718 719 if (!tgn10) 720 return NULL; 721 722 tgn10->base.inst = instance; 723 tgn10->base.ctx = ctx; 724 725 tgn10->tg_regs = &tg_regs[instance]; 726 tgn10->tg_shift = &tg_shift; 727 tgn10->tg_mask = &tg_mask; 728 729 dcn10_timing_generator_init(tgn10); 730 731 return &tgn10->base; 732 } 733 734 static const struct encoder_feature_support link_enc_feature = { 735 .max_hdmi_deep_color = COLOR_DEPTH_121212, 736 .max_hdmi_pixel_clock = 600000, 737 .hdmi_ycbcr420_supported = true, 738 .dp_ycbcr420_supported = false, 739 .flags.bits.IS_HBR2_CAPABLE = true, 740 .flags.bits.IS_HBR3_CAPABLE = true, 741 .flags.bits.IS_TPS3_CAPABLE = true, 742 .flags.bits.IS_TPS4_CAPABLE = true 743 }; 744 745 struct link_encoder *dcn10_link_encoder_create( 746 const struct encoder_init_data *enc_init_data) 747 { 748 struct dcn10_link_encoder *enc10 = 749 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 750 751 if (!enc10) 752 return NULL; 753 754 dcn10_link_encoder_construct(enc10, 755 enc_init_data, 756 &link_enc_feature, 757 &link_enc_regs[enc_init_data->transmitter], 758 &link_enc_aux_regs[enc_init_data->channel - 1], 759 &link_enc_hpd_regs[enc_init_data->hpd_source], 760 &le_shift, 761 &le_mask); 762 763 return &enc10->base; 764 } 765 766 struct clock_source *dcn10_clock_source_create( 767 struct dc_context *ctx, 768 struct dc_bios *bios, 769 enum clock_source_id id, 770 const struct dce110_clk_src_regs *regs, 771 bool dp_clk_src) 772 { 773 struct dce110_clk_src *clk_src = 774 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 775 776 if (!clk_src) 777 return NULL; 778 779 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 780 regs, &cs_shift, &cs_mask)) { 781 clk_src->base.dp_clk_src = dp_clk_src; 782 return &clk_src->base; 783 } 784 785 BREAK_TO_DEBUGGER(); 786 return NULL; 787 } 788 789 static void read_dce_straps( 790 struct dc_context *ctx, 791 struct resource_straps *straps) 792 { 793 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 794 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 795 } 796 797 static struct audio *create_audio( 798 struct dc_context *ctx, unsigned int inst) 799 { 800 return dce_audio_create(ctx, inst, 801 &audio_regs[inst], &audio_shift, &audio_mask); 802 } 803 804 static struct stream_encoder *dcn10_stream_encoder_create( 805 enum engine_id eng_id, 806 struct dc_context *ctx) 807 { 808 struct dcn10_stream_encoder *enc1 = 809 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 810 811 if (!enc1) 812 return NULL; 813 814 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 815 &stream_enc_regs[eng_id], 816 &se_shift, &se_mask); 817 return &enc1->base; 818 } 819 820 static const struct dce_hwseq_registers hwseq_reg = { 821 HWSEQ_DCN1_REG_LIST() 822 }; 823 824 static const struct dce_hwseq_shift hwseq_shift = { 825 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 826 }; 827 828 static const struct dce_hwseq_mask hwseq_mask = { 829 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 830 }; 831 832 static struct dce_hwseq *dcn10_hwseq_create( 833 struct dc_context *ctx) 834 { 835 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 836 837 if (hws) { 838 hws->ctx = ctx; 839 hws->regs = &hwseq_reg; 840 hws->shifts = &hwseq_shift; 841 hws->masks = &hwseq_mask; 842 hws->wa.DEGVIDCN10_253 = true; 843 hws->wa.false_optc_underflow = true; 844 hws->wa.DEGVIDCN10_254 = true; 845 } 846 return hws; 847 } 848 849 static const struct resource_create_funcs res_create_funcs = { 850 .read_dce_straps = read_dce_straps, 851 .create_audio = create_audio, 852 .create_stream_encoder = dcn10_stream_encoder_create, 853 .create_hwseq = dcn10_hwseq_create, 854 }; 855 856 static const struct resource_create_funcs res_create_maximus_funcs = { 857 .read_dce_straps = NULL, 858 .create_audio = NULL, 859 .create_stream_encoder = NULL, 860 .create_hwseq = dcn10_hwseq_create, 861 }; 862 863 void dcn10_clock_source_destroy(struct clock_source **clk_src) 864 { 865 kfree(TO_DCE110_CLK_SRC(*clk_src)); 866 *clk_src = NULL; 867 } 868 869 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 870 { 871 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 872 873 if (!pp_smu) 874 return pp_smu; 875 876 dm_pp_get_funcs(ctx, pp_smu); 877 return pp_smu; 878 } 879 880 static void destruct(struct dcn10_resource_pool *pool) 881 { 882 unsigned int i; 883 884 for (i = 0; i < pool->base.stream_enc_count; i++) { 885 if (pool->base.stream_enc[i] != NULL) { 886 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 887 pool->base.stream_enc[i] = NULL; 888 } 889 } 890 891 if (pool->base.mpc != NULL) { 892 kfree(TO_DCN10_MPC(pool->base.mpc)); 893 pool->base.mpc = NULL; 894 } 895 896 if (pool->base.hubbub != NULL) { 897 kfree(pool->base.hubbub); 898 pool->base.hubbub = NULL; 899 } 900 901 for (i = 0; i < pool->base.pipe_count; i++) { 902 if (pool->base.opps[i] != NULL) 903 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 904 905 if (pool->base.dpps[i] != NULL) 906 dcn10_dpp_destroy(&pool->base.dpps[i]); 907 908 if (pool->base.ipps[i] != NULL) 909 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 910 911 if (pool->base.hubps[i] != NULL) { 912 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 913 pool->base.hubps[i] = NULL; 914 } 915 916 if (pool->base.irqs != NULL) { 917 dal_irq_service_destroy(&pool->base.irqs); 918 } 919 920 if (pool->base.timing_generators[i] != NULL) { 921 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 922 pool->base.timing_generators[i] = NULL; 923 } 924 } 925 926 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 927 if (pool->base.engines[i] != NULL) 928 dce110_engine_destroy(&pool->base.engines[i]); 929 if (pool->base.hw_i2cs[i] != NULL) { 930 kfree(pool->base.hw_i2cs[i]); 931 pool->base.hw_i2cs[i] = NULL; 932 } 933 if (pool->base.sw_i2cs[i] != NULL) { 934 kfree(pool->base.sw_i2cs[i]); 935 pool->base.sw_i2cs[i] = NULL; 936 } 937 } 938 939 for (i = 0; i < pool->base.audio_count; i++) { 940 if (pool->base.audios[i]) 941 dce_aud_destroy(&pool->base.audios[i]); 942 } 943 944 for (i = 0; i < pool->base.clk_src_count; i++) { 945 if (pool->base.clock_sources[i] != NULL) { 946 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 947 pool->base.clock_sources[i] = NULL; 948 } 949 } 950 951 if (pool->base.dp_clock_source != NULL) { 952 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 953 pool->base.dp_clock_source = NULL; 954 } 955 956 if (pool->base.abm != NULL) 957 dce_abm_destroy(&pool->base.abm); 958 959 if (pool->base.dmcu != NULL) 960 dce_dmcu_destroy(&pool->base.dmcu); 961 962 kfree(pool->base.pp_smu); 963 } 964 965 static struct hubp *dcn10_hubp_create( 966 struct dc_context *ctx, 967 uint32_t inst) 968 { 969 struct dcn10_hubp *hubp1 = 970 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 971 972 if (!hubp1) 973 return NULL; 974 975 dcn10_hubp_construct(hubp1, ctx, inst, 976 &hubp_regs[inst], &hubp_shift, &hubp_mask); 977 return &hubp1->base; 978 } 979 980 static void get_pixel_clock_parameters( 981 const struct pipe_ctx *pipe_ctx, 982 struct pixel_clk_params *pixel_clk_params) 983 { 984 const struct dc_stream_state *stream = pipe_ctx->stream; 985 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 986 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 987 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 988 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 989 /* TODO: un-hardcode*/ 990 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 991 LINK_RATE_REF_FREQ_IN_KHZ; 992 pixel_clk_params->flags.ENABLE_SS = 0; 993 pixel_clk_params->color_depth = 994 stream->timing.display_color_depth; 995 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 996 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 997 998 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 999 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1000 1001 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1002 pixel_clk_params->requested_pix_clk_100hz /= 2; 1003 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1004 pixel_clk_params->requested_pix_clk_100hz *= 2; 1005 1006 } 1007 1008 static void build_clamping_params(struct dc_stream_state *stream) 1009 { 1010 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1011 stream->clamping.c_depth = stream->timing.display_color_depth; 1012 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1013 } 1014 1015 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1016 { 1017 1018 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1019 1020 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1021 pipe_ctx->clock_source, 1022 &pipe_ctx->stream_res.pix_clk_params, 1023 &pipe_ctx->pll_settings); 1024 1025 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1026 1027 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1028 &pipe_ctx->stream->bit_depth_params); 1029 build_clamping_params(pipe_ctx->stream); 1030 } 1031 1032 static enum dc_status build_mapped_resource( 1033 const struct dc *dc, 1034 struct dc_state *context, 1035 struct dc_stream_state *stream) 1036 { 1037 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1038 1039 /*TODO Seems unneeded anymore */ 1040 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1041 if (stream != NULL && old_context->streams[i] != NULL) { 1042 todo: shouldn't have to copy missing parameter here 1043 resource_build_bit_depth_reduction_params(stream, 1044 &stream->bit_depth_params); 1045 stream->clamping.pixel_encoding = 1046 stream->timing.pixel_encoding; 1047 1048 resource_build_bit_depth_reduction_params(stream, 1049 &stream->bit_depth_params); 1050 build_clamping_params(stream); 1051 1052 continue; 1053 } 1054 } 1055 */ 1056 1057 if (!pipe_ctx) 1058 return DC_ERROR_UNEXPECTED; 1059 1060 build_pipe_hw_param(pipe_ctx); 1061 return DC_OK; 1062 } 1063 1064 enum dc_status dcn10_add_stream_to_ctx( 1065 struct dc *dc, 1066 struct dc_state *new_ctx, 1067 struct dc_stream_state *dc_stream) 1068 { 1069 enum dc_status result = DC_ERROR_UNEXPECTED; 1070 1071 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1072 1073 if (result == DC_OK) 1074 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1075 1076 1077 if (result == DC_OK) 1078 result = build_mapped_resource(dc, new_ctx, dc_stream); 1079 1080 return result; 1081 } 1082 1083 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1084 struct dc_state *context, 1085 const struct resource_pool *pool, 1086 struct dc_stream_state *stream) 1087 { 1088 struct resource_context *res_ctx = &context->res_ctx; 1089 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1090 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 1091 1092 if (!head_pipe) { 1093 ASSERT(0); 1094 return NULL; 1095 } 1096 1097 if (!idle_pipe) 1098 return NULL; 1099 1100 idle_pipe->stream = head_pipe->stream; 1101 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1102 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1103 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1104 1105 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1106 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1107 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1108 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1109 1110 return idle_pipe; 1111 } 1112 1113 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1114 const struct dc_dcc_surface_param *input, 1115 struct dc_surface_dcc_cap *output) 1116 { 1117 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1118 dc->res_pool->hubbub, 1119 input, 1120 output); 1121 } 1122 1123 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1124 { 1125 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1126 1127 destruct(dcn10_pool); 1128 kfree(dcn10_pool); 1129 *pool = NULL; 1130 } 1131 1132 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1133 { 1134 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1135 && caps->max_video_width != 0 1136 && plane_state->src_rect.width > caps->max_video_width) 1137 return DC_FAIL_SURFACE_VALIDATE; 1138 1139 return DC_OK; 1140 } 1141 1142 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1143 { 1144 int i, j; 1145 bool video_down_scaled = false; 1146 bool video_large = false; 1147 bool desktop_large = false; 1148 bool dcc_disabled = false; 1149 1150 for (i = 0; i < context->stream_count; i++) { 1151 if (context->stream_status[i].plane_count == 0) 1152 continue; 1153 1154 if (context->stream_status[i].plane_count > 2) 1155 return DC_FAIL_UNSUPPORTED_1; 1156 1157 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1158 struct dc_plane_state *plane = 1159 context->stream_status[i].plane_states[j]; 1160 1161 1162 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1163 1164 if (plane->src_rect.width > plane->dst_rect.width || 1165 plane->src_rect.height > plane->dst_rect.height) 1166 video_down_scaled = true; 1167 1168 if (plane->src_rect.width >= 3840) 1169 video_large = true; 1170 1171 } else { 1172 if (plane->src_rect.width >= 3840) 1173 desktop_large = true; 1174 if (!plane->dcc.enable) 1175 dcc_disabled = true; 1176 } 1177 } 1178 } 1179 1180 /* 1181 * Workaround: On DCN10 there is UMC issue that causes underflow when 1182 * playing 4k video on 4k desktop with video downscaled and single channel 1183 * memory 1184 */ 1185 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1186 dc->dcn_soc->number_of_channels == 1) 1187 return DC_FAIL_SURFACE_VALIDATE; 1188 1189 return DC_OK; 1190 } 1191 1192 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1193 { 1194 enum dc_status result = DC_OK; 1195 1196 enum surface_pixel_format surf_pix_format = plane_state->format; 1197 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1198 1199 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1200 1201 if (bpp == 64) 1202 swizzle = DC_SW_64KB_D; 1203 else 1204 swizzle = DC_SW_64KB_S; 1205 1206 plane_state->tiling_info.gfx9.swizzle = swizzle; 1207 return result; 1208 } 1209 1210 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 1211 struct resource_context *res_ctx, 1212 const struct resource_pool *pool, 1213 struct dc_stream_state *stream) 1214 { 1215 int i; 1216 int j = -1; 1217 struct dc_link *link = stream->link; 1218 1219 for (i = 0; i < pool->stream_enc_count; i++) { 1220 if (!res_ctx->is_stream_enc_acquired[i] && 1221 pool->stream_enc[i]) { 1222 /* Store first available for MST second display 1223 * in daisy chain use case 1224 */ 1225 j = i; 1226 if (pool->stream_enc[i]->id == 1227 link->link_enc->preferred_engine) 1228 return pool->stream_enc[i]; 1229 } 1230 } 1231 1232 /* 1233 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1234 */ 1235 1236 if (j >= 0) 1237 return pool->stream_enc[j]; 1238 1239 return NULL; 1240 } 1241 1242 static const struct dc_cap_funcs cap_funcs = { 1243 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1244 }; 1245 1246 static const struct resource_funcs dcn10_res_pool_funcs = { 1247 .destroy = dcn10_destroy_resource_pool, 1248 .link_enc_create = dcn10_link_encoder_create, 1249 .validate_bandwidth = dcn_validate_bandwidth, 1250 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1251 .validate_plane = dcn10_validate_plane, 1252 .validate_global = dcn10_validate_global, 1253 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1254 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode, 1255 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 1256 }; 1257 1258 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1259 { 1260 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1261 /* RV1 support max 4 pipes */ 1262 value = value & 0xf; 1263 return value; 1264 } 1265 1266 static bool construct( 1267 uint8_t num_virtual_links, 1268 struct dc *dc, 1269 struct dcn10_resource_pool *pool) 1270 { 1271 int i; 1272 int j; 1273 struct dc_context *ctx = dc->ctx; 1274 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1275 1276 ctx->dc_bios->regs = &bios_regs; 1277 1278 if (ctx->dce_version == DCN_VERSION_1_01) 1279 pool->base.res_cap = &rv2_res_cap; 1280 else 1281 pool->base.res_cap = &res_cap; 1282 pool->base.funcs = &dcn10_res_pool_funcs; 1283 1284 /* 1285 * TODO fill in from actual raven resource when we create 1286 * more than virtual encoder 1287 */ 1288 1289 /************************************************* 1290 * Resource + asic cap harcoding * 1291 *************************************************/ 1292 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1293 1294 /* max pipe num for ASIC before check pipe fuses */ 1295 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1296 1297 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1298 pool->base.pipe_count = 3; 1299 dc->caps.max_video_width = 3840; 1300 dc->caps.max_downscale_ratio = 200; 1301 dc->caps.i2c_speed_in_khz = 100; 1302 dc->caps.max_cursor_size = 256; 1303 dc->caps.max_slave_planes = 1; 1304 dc->caps.is_apu = true; 1305 dc->caps.post_blend_color_processing = false; 1306 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1307 dc->caps.force_dp_tps4_for_cp2520 = true; 1308 1309 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1310 dc->debug = debug_defaults_drv; 1311 else 1312 dc->debug = debug_defaults_diags; 1313 1314 /************************************************* 1315 * Create resources * 1316 *************************************************/ 1317 1318 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1319 dcn10_clock_source_create(ctx, ctx->dc_bios, 1320 CLOCK_SOURCE_COMBO_PHY_PLL0, 1321 &clk_src_regs[0], false); 1322 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1323 dcn10_clock_source_create(ctx, ctx->dc_bios, 1324 CLOCK_SOURCE_COMBO_PHY_PLL1, 1325 &clk_src_regs[1], false); 1326 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1327 dcn10_clock_source_create(ctx, ctx->dc_bios, 1328 CLOCK_SOURCE_COMBO_PHY_PLL2, 1329 &clk_src_regs[2], false); 1330 1331 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1332 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1333 dcn10_clock_source_create(ctx, ctx->dc_bios, 1334 CLOCK_SOURCE_COMBO_PHY_PLL3, 1335 &clk_src_regs[3], false); 1336 } 1337 1338 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1339 1340 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1341 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1342 1343 pool->base.dp_clock_source = 1344 dcn10_clock_source_create(ctx, ctx->dc_bios, 1345 CLOCK_SOURCE_ID_DP_DTO, 1346 /* todo: not reuse phy_pll registers */ 1347 &clk_src_regs[0], true); 1348 1349 for (i = 0; i < pool->base.clk_src_count; i++) { 1350 if (pool->base.clock_sources[i] == NULL) { 1351 dm_error("DC: failed to create clock sources!\n"); 1352 BREAK_TO_DEBUGGER(); 1353 goto fail; 1354 } 1355 } 1356 1357 pool->base.dmcu = dcn10_dmcu_create(ctx, 1358 &dmcu_regs, 1359 &dmcu_shift, 1360 &dmcu_mask); 1361 if (pool->base.dmcu == NULL) { 1362 dm_error("DC: failed to create dmcu!\n"); 1363 BREAK_TO_DEBUGGER(); 1364 goto fail; 1365 } 1366 1367 pool->base.abm = dce_abm_create(ctx, 1368 &abm_regs, 1369 &abm_shift, 1370 &abm_mask); 1371 if (pool->base.abm == NULL) { 1372 dm_error("DC: failed to create abm!\n"); 1373 BREAK_TO_DEBUGGER(); 1374 goto fail; 1375 } 1376 1377 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1378 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1379 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1380 1381 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1382 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1383 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1384 struct display_mode_lib *dml = &dc->dml; 1385 1386 dml->ip.max_num_dpp = 3; 1387 /* TODO how to handle 23.84? */ 1388 dcn_soc->dram_clock_change_latency = 23; 1389 dcn_ip->max_num_dpp = 3; 1390 } 1391 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1392 dc->dcn_soc->urgent_latency = 3; 1393 dc->debug.disable_dmcu = true; 1394 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1395 } 1396 1397 1398 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1399 ASSERT(dc->dcn_soc->number_of_channels < 3); 1400 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1401 dc->dcn_soc->number_of_channels = 2; 1402 1403 if (dc->dcn_soc->number_of_channels == 1) { 1404 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1405 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1406 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1407 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1408 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1409 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1410 } 1411 } 1412 1413 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1414 1415 if (!dc->debug.disable_pplib_clock_request) 1416 dcn_bw_update_from_pplib(dc); 1417 dcn_bw_sync_calcs_and_dml(dc); 1418 if (!dc->debug.disable_pplib_wm_range) { 1419 dc->res_pool = &pool->base; 1420 dcn_bw_notify_pplib_of_wm_ranges(dc); 1421 } 1422 1423 { 1424 struct irq_service_init_data init_data; 1425 init_data.ctx = dc->ctx; 1426 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1427 if (!pool->base.irqs) 1428 goto fail; 1429 } 1430 1431 /* index to valid pipe resource */ 1432 j = 0; 1433 /* mem input -> ipp -> dpp -> opp -> TG */ 1434 for (i = 0; i < pool->base.pipe_count; i++) { 1435 /* if pipe is disabled, skip instance of HW pipe, 1436 * i.e, skip ASIC register instance 1437 */ 1438 if ((pipe_fuses & (1 << i)) != 0) 1439 continue; 1440 1441 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1442 if (pool->base.hubps[j] == NULL) { 1443 BREAK_TO_DEBUGGER(); 1444 dm_error( 1445 "DC: failed to create memory input!\n"); 1446 goto fail; 1447 } 1448 1449 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1450 if (pool->base.ipps[j] == NULL) { 1451 BREAK_TO_DEBUGGER(); 1452 dm_error( 1453 "DC: failed to create input pixel processor!\n"); 1454 goto fail; 1455 } 1456 1457 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1458 if (pool->base.dpps[j] == NULL) { 1459 BREAK_TO_DEBUGGER(); 1460 dm_error( 1461 "DC: failed to create dpp!\n"); 1462 goto fail; 1463 } 1464 1465 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1466 if (pool->base.opps[j] == NULL) { 1467 BREAK_TO_DEBUGGER(); 1468 dm_error( 1469 "DC: failed to create output pixel processor!\n"); 1470 goto fail; 1471 } 1472 1473 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1474 ctx, i); 1475 if (pool->base.timing_generators[j] == NULL) { 1476 BREAK_TO_DEBUGGER(); 1477 dm_error("DC: failed to create tg!\n"); 1478 goto fail; 1479 } 1480 /* check next valid pipe */ 1481 j++; 1482 } 1483 1484 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1485 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1486 if (pool->base.engines[i] == NULL) { 1487 BREAK_TO_DEBUGGER(); 1488 dm_error( 1489 "DC:failed to create aux engine!!\n"); 1490 goto fail; 1491 } 1492 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1493 if (pool->base.hw_i2cs[i] == NULL) { 1494 BREAK_TO_DEBUGGER(); 1495 dm_error( 1496 "DC:failed to create hw i2c!!\n"); 1497 goto fail; 1498 } 1499 pool->base.sw_i2cs[i] = NULL; 1500 } 1501 1502 /* valid pipe num */ 1503 pool->base.pipe_count = j; 1504 pool->base.timing_generator_count = j; 1505 1506 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1507 * the value may be changed 1508 */ 1509 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1510 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1511 1512 pool->base.mpc = dcn10_mpc_create(ctx); 1513 if (pool->base.mpc == NULL) { 1514 BREAK_TO_DEBUGGER(); 1515 dm_error("DC: failed to create mpc!\n"); 1516 goto fail; 1517 } 1518 1519 pool->base.hubbub = dcn10_hubbub_create(ctx); 1520 if (pool->base.hubbub == NULL) { 1521 BREAK_TO_DEBUGGER(); 1522 dm_error("DC: failed to create hubbub!\n"); 1523 goto fail; 1524 } 1525 1526 if (!resource_construct(num_virtual_links, dc, &pool->base, 1527 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1528 &res_create_funcs : &res_create_maximus_funcs))) 1529 goto fail; 1530 1531 dcn10_hw_sequencer_construct(dc); 1532 dc->caps.max_planes = pool->base.pipe_count; 1533 1534 for (i = 0; i < dc->caps.max_planes; ++i) 1535 dc->caps.planes[i] = plane_cap; 1536 1537 dc->cap_funcs = cap_funcs; 1538 1539 return true; 1540 1541 fail: 1542 1543 destruct(pool); 1544 1545 return false; 1546 } 1547 1548 struct resource_pool *dcn10_create_resource_pool( 1549 const struct dc_init_data *init_data, 1550 struct dc *dc) 1551 { 1552 struct dcn10_resource_pool *pool = 1553 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1554 1555 if (!pool) 1556 return NULL; 1557 1558 if (construct(init_data->num_virtual_links, dc, pool)) 1559 return &pool->base; 1560 1561 BREAK_TO_DEBUGGER(); 1562 return NULL; 1563 } 1564