1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn10/dcn10_resource.h" 32 33 #include "dcn10/dcn10_ipp.h" 34 #include "dcn10/dcn10_mpc.h" 35 #include "irq/dcn10/irq_service_dcn10.h" 36 #include "dcn10/dcn10_dpp.h" 37 #include "dcn10_optc.h" 38 #include "dcn10/dcn10_hw_sequencer.h" 39 #include "dce110/dce110_hw_sequencer.h" 40 #include "dcn10/dcn10_opp.h" 41 #include "dcn10/dcn10_link_encoder.h" 42 #include "dcn10/dcn10_stream_encoder.h" 43 #include "dce/dce_clocks.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "../virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 157 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 158 #endif 159 }; 160 161 /* begin ********************* 162 * macros to expend register list macro defined in HW object header file */ 163 164 /* DCN */ 165 #define BASE_INNER(seg) \ 166 DCE_BASE__INST0_SEG ## seg 167 168 #define BASE(seg) \ 169 BASE_INNER(seg) 170 171 #define SR(reg_name)\ 172 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 173 mm ## reg_name 174 175 #define SRI(reg_name, block, id)\ 176 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 mm ## block ## id ## _ ## reg_name 178 179 180 #define SRII(reg_name, block, id)\ 181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 mm ## block ## id ## _ ## reg_name 183 184 /* NBIO */ 185 #define NBIO_BASE_INNER(seg) \ 186 NBIF_BASE__INST0_SEG ## seg 187 188 #define NBIO_BASE(seg) \ 189 NBIO_BASE_INNER(seg) 190 191 #define NBIO_SR(reg_name)\ 192 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 193 mm ## reg_name 194 195 /* MMHUB */ 196 #define MMHUB_BASE_INNER(seg) \ 197 MMHUB_BASE__INST0_SEG ## seg 198 199 #define MMHUB_BASE(seg) \ 200 MMHUB_BASE_INNER(seg) 201 202 #define MMHUB_SR(reg_name)\ 203 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 204 mm ## reg_name 205 206 /* macros to expend register list macro defined in HW object header file 207 * end *********************/ 208 209 210 static const struct dce_dmcu_registers dmcu_regs = { 211 DMCU_DCN10_REG_LIST() 212 }; 213 214 static const struct dce_dmcu_shift dmcu_shift = { 215 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 216 }; 217 218 static const struct dce_dmcu_mask dmcu_mask = { 219 DMCU_MASK_SH_LIST_DCN10(_MASK) 220 }; 221 222 static const struct dce_abm_registers abm_regs = { 223 ABM_DCN10_REG_LIST(0) 224 }; 225 226 static const struct dce_abm_shift abm_shift = { 227 ABM_MASK_SH_LIST_DCN10(__SHIFT) 228 }; 229 230 static const struct dce_abm_mask abm_mask = { 231 ABM_MASK_SH_LIST_DCN10(_MASK) 232 }; 233 234 #define stream_enc_regs(id)\ 235 [id] = {\ 236 SE_DCN_REG_LIST(id)\ 237 } 238 239 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 240 stream_enc_regs(0), 241 stream_enc_regs(1), 242 stream_enc_regs(2), 243 stream_enc_regs(3), 244 }; 245 246 static const struct dcn10_stream_encoder_shift se_shift = { 247 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 248 }; 249 250 static const struct dcn10_stream_encoder_mask se_mask = { 251 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 252 }; 253 254 #define audio_regs(id)\ 255 [id] = {\ 256 AUD_COMMON_REG_LIST(id)\ 257 } 258 259 static const struct dce_audio_registers audio_regs[] = { 260 audio_regs(0), 261 audio_regs(1), 262 audio_regs(2), 263 audio_regs(3), 264 }; 265 266 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 267 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 268 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 269 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 270 271 static const struct dce_audio_shift audio_shift = { 272 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 273 }; 274 275 static const struct dce_aduio_mask audio_mask = { 276 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 277 }; 278 279 #define aux_regs(id)\ 280 [id] = {\ 281 AUX_REG_LIST(id)\ 282 } 283 284 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 285 aux_regs(0), 286 aux_regs(1), 287 aux_regs(2), 288 aux_regs(3) 289 }; 290 291 #define hpd_regs(id)\ 292 [id] = {\ 293 HPD_REG_LIST(id)\ 294 } 295 296 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 297 hpd_regs(0), 298 hpd_regs(1), 299 hpd_regs(2), 300 hpd_regs(3) 301 }; 302 303 #define link_regs(id)\ 304 [id] = {\ 305 LE_DCN10_REG_LIST(id), \ 306 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 307 } 308 309 static const struct dcn10_link_enc_registers link_enc_regs[] = { 310 link_regs(0), 311 link_regs(1), 312 link_regs(2), 313 link_regs(3) 314 }; 315 316 static const struct dcn10_link_enc_shift le_shift = { 317 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 318 }; 319 320 static const struct dcn10_link_enc_mask le_mask = { 321 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 322 }; 323 324 #define ipp_regs(id)\ 325 [id] = {\ 326 IPP_REG_LIST_DCN10(id),\ 327 } 328 329 static const struct dcn10_ipp_registers ipp_regs[] = { 330 ipp_regs(0), 331 ipp_regs(1), 332 ipp_regs(2), 333 ipp_regs(3), 334 }; 335 336 static const struct dcn10_ipp_shift ipp_shift = { 337 IPP_MASK_SH_LIST_DCN10(__SHIFT) 338 }; 339 340 static const struct dcn10_ipp_mask ipp_mask = { 341 IPP_MASK_SH_LIST_DCN10(_MASK), 342 }; 343 344 #define opp_regs(id)\ 345 [id] = {\ 346 OPP_REG_LIST_DCN10(id),\ 347 } 348 349 static const struct dcn10_opp_registers opp_regs[] = { 350 opp_regs(0), 351 opp_regs(1), 352 opp_regs(2), 353 opp_regs(3), 354 }; 355 356 static const struct dcn10_opp_shift opp_shift = { 357 OPP_MASK_SH_LIST_DCN10(__SHIFT) 358 }; 359 360 static const struct dcn10_opp_mask opp_mask = { 361 OPP_MASK_SH_LIST_DCN10(_MASK), 362 }; 363 364 #define aux_engine_regs(id)\ 365 [id] = {\ 366 AUX_COMMON_REG_LIST(id), \ 367 .AUX_RESET_MASK = 0 \ 368 } 369 370 static const struct dce110_aux_registers aux_engine_regs[] = { 371 aux_engine_regs(0), 372 aux_engine_regs(1), 373 aux_engine_regs(2), 374 aux_engine_regs(3), 375 aux_engine_regs(4), 376 aux_engine_regs(5) 377 }; 378 379 #define tf_regs(id)\ 380 [id] = {\ 381 TF_REG_LIST_DCN10(id),\ 382 } 383 384 static const struct dcn_dpp_registers tf_regs[] = { 385 tf_regs(0), 386 tf_regs(1), 387 tf_regs(2), 388 tf_regs(3), 389 }; 390 391 static const struct dcn_dpp_shift tf_shift = { 392 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 393 TF_DEBUG_REG_LIST_SH_DCN10 394 395 }; 396 397 static const struct dcn_dpp_mask tf_mask = { 398 TF_REG_LIST_SH_MASK_DCN10(_MASK), 399 TF_DEBUG_REG_LIST_MASK_DCN10 400 }; 401 402 static const struct dcn_mpc_registers mpc_regs = { 403 MPC_COMMON_REG_LIST_DCN1_0(0), 404 MPC_COMMON_REG_LIST_DCN1_0(1), 405 MPC_COMMON_REG_LIST_DCN1_0(2), 406 MPC_COMMON_REG_LIST_DCN1_0(3), 407 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 408 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 409 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 410 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 411 }; 412 413 static const struct dcn_mpc_shift mpc_shift = { 414 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 415 }; 416 417 static const struct dcn_mpc_mask mpc_mask = { 418 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 419 }; 420 421 #define tg_regs(id)\ 422 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 423 424 static const struct dcn_optc_registers tg_regs[] = { 425 tg_regs(0), 426 tg_regs(1), 427 tg_regs(2), 428 tg_regs(3), 429 }; 430 431 static const struct dcn_optc_shift tg_shift = { 432 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 433 }; 434 435 static const struct dcn_optc_mask tg_mask = { 436 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 437 }; 438 439 440 static const struct bios_registers bios_regs = { 441 NBIO_SR(BIOS_SCRATCH_3), 442 NBIO_SR(BIOS_SCRATCH_6) 443 }; 444 445 #define hubp_regs(id)\ 446 [id] = {\ 447 HUBP_REG_LIST_DCN10(id)\ 448 } 449 450 451 static const struct dcn_mi_registers hubp_regs[] = { 452 hubp_regs(0), 453 hubp_regs(1), 454 hubp_regs(2), 455 hubp_regs(3), 456 }; 457 458 static const struct dcn_mi_shift hubp_shift = { 459 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 460 }; 461 462 static const struct dcn_mi_mask hubp_mask = { 463 HUBP_MASK_SH_LIST_DCN10(_MASK) 464 }; 465 466 467 static const struct dcn_hubbub_registers hubbub_reg = { 468 HUBBUB_REG_LIST_DCN10(0) 469 }; 470 471 static const struct dcn_hubbub_shift hubbub_shift = { 472 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 473 }; 474 475 static const struct dcn_hubbub_mask hubbub_mask = { 476 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 477 }; 478 479 #define clk_src_regs(index, pllid)\ 480 [index] = {\ 481 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 482 } 483 484 static const struct dce110_clk_src_regs clk_src_regs[] = { 485 clk_src_regs(0, A), 486 clk_src_regs(1, B), 487 clk_src_regs(2, C), 488 clk_src_regs(3, D) 489 }; 490 491 static const struct dce110_clk_src_shift cs_shift = { 492 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 493 }; 494 495 static const struct dce110_clk_src_mask cs_mask = { 496 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 497 }; 498 499 500 static const struct resource_caps res_cap = { 501 .num_timing_generator = 4, 502 .num_opp = 4, 503 .num_video_plane = 4, 504 .num_audio = 4, 505 .num_stream_encoder = 4, 506 .num_pll = 4, 507 .num_ddc = 4, 508 }; 509 510 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 511 static const struct resource_caps rv2_res_cap = { 512 .num_timing_generator = 3, 513 .num_opp = 3, 514 .num_video_plane = 3, 515 .num_audio = 3, 516 .num_stream_encoder = 3, 517 .num_pll = 3, 518 .num_ddc = 3, 519 }; 520 #endif 521 522 static const struct dc_debug_options debug_defaults_drv = { 523 .sanity_checks = true, 524 .disable_dmcu = true, 525 .force_abm_enable = false, 526 .timing_trace = false, 527 .clock_trace = true, 528 529 /* raven smu dones't allow 0 disp clk, 530 * smu min disp clk limit is 50Mhz 531 * keep min disp clk 100Mhz avoid smu hang 532 */ 533 .min_disp_clk_khz = 100000, 534 535 .disable_pplib_clock_request = false, 536 .disable_pplib_wm_range = false, 537 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 538 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 539 .force_single_disp_pipe_split = true, 540 .disable_dcc = DCC_ENABLE, 541 .voltage_align_fclk = true, 542 .disable_stereo_support = true, 543 .vsr_support = true, 544 .performance_trace = false, 545 .az_endpoint_mute_only = true, 546 .recovery_enabled = false, /*enable this by default after testing.*/ 547 .max_downscale_src_width = 3840, 548 }; 549 550 static const struct dc_debug_options debug_defaults_diags = { 551 .disable_dmcu = true, 552 .force_abm_enable = false, 553 .timing_trace = true, 554 .clock_trace = true, 555 .disable_stutter = true, 556 .disable_pplib_clock_request = true, 557 .disable_pplib_wm_range = true 558 }; 559 560 static void dcn10_dpp_destroy(struct dpp **dpp) 561 { 562 kfree(TO_DCN10_DPP(*dpp)); 563 *dpp = NULL; 564 } 565 566 static struct dpp *dcn10_dpp_create( 567 struct dc_context *ctx, 568 uint32_t inst) 569 { 570 struct dcn10_dpp *dpp = 571 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 572 573 if (!dpp) 574 return NULL; 575 576 dpp1_construct(dpp, ctx, inst, 577 &tf_regs[inst], &tf_shift, &tf_mask); 578 return &dpp->base; 579 } 580 581 static struct input_pixel_processor *dcn10_ipp_create( 582 struct dc_context *ctx, uint32_t inst) 583 { 584 struct dcn10_ipp *ipp = 585 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 586 587 if (!ipp) { 588 BREAK_TO_DEBUGGER(); 589 return NULL; 590 } 591 592 dcn10_ipp_construct(ipp, ctx, inst, 593 &ipp_regs[inst], &ipp_shift, &ipp_mask); 594 return &ipp->base; 595 } 596 597 598 static struct output_pixel_processor *dcn10_opp_create( 599 struct dc_context *ctx, uint32_t inst) 600 { 601 struct dcn10_opp *opp = 602 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 603 604 if (!opp) { 605 BREAK_TO_DEBUGGER(); 606 return NULL; 607 } 608 609 dcn10_opp_construct(opp, ctx, inst, 610 &opp_regs[inst], &opp_shift, &opp_mask); 611 return &opp->base; 612 } 613 614 struct aux_engine *dcn10_aux_engine_create( 615 struct dc_context *ctx, 616 uint32_t inst) 617 { 618 struct aux_engine_dce110 *aux_engine = 619 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 620 621 if (!aux_engine) 622 return NULL; 623 624 dce110_aux_engine_construct(aux_engine, ctx, inst, 625 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 626 &aux_engine_regs[inst]); 627 628 return &aux_engine->base; 629 } 630 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 631 632 static const struct dce_i2c_registers i2c_hw_regs[] = { 633 i2c_inst_regs(1), 634 i2c_inst_regs(2), 635 i2c_inst_regs(3), 636 i2c_inst_regs(4), 637 i2c_inst_regs(5), 638 i2c_inst_regs(6), 639 }; 640 641 static const struct dce_i2c_shift i2c_shifts = { 642 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 643 }; 644 645 static const struct dce_i2c_mask i2c_masks = { 646 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 647 }; 648 649 struct dce_i2c_hw *dcn10_i2c_hw_create( 650 struct dc_context *ctx, 651 uint32_t inst) 652 { 653 struct dce_i2c_hw *dce_i2c_hw = 654 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 655 656 if (!dce_i2c_hw) 657 return NULL; 658 659 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 660 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 661 662 return dce_i2c_hw; 663 } 664 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 665 { 666 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 667 GFP_KERNEL); 668 669 if (!mpc10) 670 return NULL; 671 672 dcn10_mpc_construct(mpc10, ctx, 673 &mpc_regs, 674 &mpc_shift, 675 &mpc_mask, 676 4); 677 678 return &mpc10->base; 679 } 680 681 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 682 { 683 struct hubbub *hubbub = kzalloc(sizeof(struct hubbub), 684 GFP_KERNEL); 685 686 if (!hubbub) 687 return NULL; 688 689 hubbub1_construct(hubbub, ctx, 690 &hubbub_reg, 691 &hubbub_shift, 692 &hubbub_mask); 693 694 return hubbub; 695 } 696 697 static struct timing_generator *dcn10_timing_generator_create( 698 struct dc_context *ctx, 699 uint32_t instance) 700 { 701 struct optc *tgn10 = 702 kzalloc(sizeof(struct optc), GFP_KERNEL); 703 704 if (!tgn10) 705 return NULL; 706 707 tgn10->base.inst = instance; 708 tgn10->base.ctx = ctx; 709 710 tgn10->tg_regs = &tg_regs[instance]; 711 tgn10->tg_shift = &tg_shift; 712 tgn10->tg_mask = &tg_mask; 713 714 dcn10_timing_generator_init(tgn10); 715 716 return &tgn10->base; 717 } 718 719 static const struct encoder_feature_support link_enc_feature = { 720 .max_hdmi_deep_color = COLOR_DEPTH_121212, 721 .max_hdmi_pixel_clock = 600000, 722 .ycbcr420_supported = true, 723 .flags.bits.IS_HBR2_CAPABLE = true, 724 .flags.bits.IS_HBR3_CAPABLE = true, 725 .flags.bits.IS_TPS3_CAPABLE = true, 726 .flags.bits.IS_TPS4_CAPABLE = true 727 }; 728 729 struct link_encoder *dcn10_link_encoder_create( 730 const struct encoder_init_data *enc_init_data) 731 { 732 struct dcn10_link_encoder *enc10 = 733 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 734 735 if (!enc10) 736 return NULL; 737 738 dcn10_link_encoder_construct(enc10, 739 enc_init_data, 740 &link_enc_feature, 741 &link_enc_regs[enc_init_data->transmitter], 742 &link_enc_aux_regs[enc_init_data->channel - 1], 743 &link_enc_hpd_regs[enc_init_data->hpd_source], 744 &le_shift, 745 &le_mask); 746 747 return &enc10->base; 748 } 749 750 struct clock_source *dcn10_clock_source_create( 751 struct dc_context *ctx, 752 struct dc_bios *bios, 753 enum clock_source_id id, 754 const struct dce110_clk_src_regs *regs, 755 bool dp_clk_src) 756 { 757 struct dce110_clk_src *clk_src = 758 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 759 760 if (!clk_src) 761 return NULL; 762 763 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 764 regs, &cs_shift, &cs_mask)) { 765 clk_src->base.dp_clk_src = dp_clk_src; 766 return &clk_src->base; 767 } 768 769 BREAK_TO_DEBUGGER(); 770 return NULL; 771 } 772 773 static void read_dce_straps( 774 struct dc_context *ctx, 775 struct resource_straps *straps) 776 { 777 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 778 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 779 } 780 781 static struct audio *create_audio( 782 struct dc_context *ctx, unsigned int inst) 783 { 784 return dce_audio_create(ctx, inst, 785 &audio_regs[inst], &audio_shift, &audio_mask); 786 } 787 788 static struct stream_encoder *dcn10_stream_encoder_create( 789 enum engine_id eng_id, 790 struct dc_context *ctx) 791 { 792 struct dcn10_stream_encoder *enc1 = 793 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 794 795 if (!enc1) 796 return NULL; 797 798 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 799 &stream_enc_regs[eng_id], 800 &se_shift, &se_mask); 801 return &enc1->base; 802 } 803 804 static const struct dce_hwseq_registers hwseq_reg = { 805 HWSEQ_DCN1_REG_LIST() 806 }; 807 808 static const struct dce_hwseq_shift hwseq_shift = { 809 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 810 }; 811 812 static const struct dce_hwseq_mask hwseq_mask = { 813 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 814 }; 815 816 static struct dce_hwseq *dcn10_hwseq_create( 817 struct dc_context *ctx) 818 { 819 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 820 821 if (hws) { 822 hws->ctx = ctx; 823 hws->regs = &hwseq_reg; 824 hws->shifts = &hwseq_shift; 825 hws->masks = &hwseq_mask; 826 hws->wa.DEGVIDCN10_253 = true; 827 hws->wa.false_optc_underflow = true; 828 hws->wa.DEGVIDCN10_254 = true; 829 } 830 return hws; 831 } 832 833 static const struct resource_create_funcs res_create_funcs = { 834 .read_dce_straps = read_dce_straps, 835 .create_audio = create_audio, 836 .create_stream_encoder = dcn10_stream_encoder_create, 837 .create_hwseq = dcn10_hwseq_create, 838 }; 839 840 static const struct resource_create_funcs res_create_maximus_funcs = { 841 .read_dce_straps = NULL, 842 .create_audio = NULL, 843 .create_stream_encoder = NULL, 844 .create_hwseq = dcn10_hwseq_create, 845 }; 846 847 void dcn10_clock_source_destroy(struct clock_source **clk_src) 848 { 849 kfree(TO_DCE110_CLK_SRC(*clk_src)); 850 *clk_src = NULL; 851 } 852 853 static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) 854 { 855 struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 856 857 if (!pp_smu) 858 return pp_smu; 859 860 dm_pp_get_funcs_rv(ctx, pp_smu); 861 return pp_smu; 862 } 863 864 static void destruct(struct dcn10_resource_pool *pool) 865 { 866 unsigned int i; 867 868 for (i = 0; i < pool->base.stream_enc_count; i++) { 869 if (pool->base.stream_enc[i] != NULL) { 870 /* TODO: free dcn version of stream encoder once implemented 871 * rather than using virtual stream encoder 872 */ 873 kfree(pool->base.stream_enc[i]); 874 pool->base.stream_enc[i] = NULL; 875 } 876 } 877 878 if (pool->base.mpc != NULL) { 879 kfree(TO_DCN10_MPC(pool->base.mpc)); 880 pool->base.mpc = NULL; 881 } 882 883 if (pool->base.hubbub != NULL) { 884 kfree(pool->base.hubbub); 885 pool->base.hubbub = NULL; 886 } 887 888 for (i = 0; i < pool->base.pipe_count; i++) { 889 if (pool->base.opps[i] != NULL) 890 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 891 892 if (pool->base.dpps[i] != NULL) 893 dcn10_dpp_destroy(&pool->base.dpps[i]); 894 895 if (pool->base.ipps[i] != NULL) 896 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 897 898 if (pool->base.hubps[i] != NULL) { 899 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 900 pool->base.hubps[i] = NULL; 901 } 902 903 if (pool->base.irqs != NULL) { 904 dal_irq_service_destroy(&pool->base.irqs); 905 } 906 907 if (pool->base.timing_generators[i] != NULL) { 908 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 909 pool->base.timing_generators[i] = NULL; 910 } 911 } 912 913 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 914 if (pool->base.engines[i] != NULL) 915 pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]); 916 if (pool->base.hw_i2cs[i] != NULL) { 917 kfree(pool->base.hw_i2cs[i]); 918 pool->base.hw_i2cs[i] = NULL; 919 } 920 if (pool->base.sw_i2cs[i] != NULL) { 921 kfree(pool->base.sw_i2cs[i]); 922 pool->base.sw_i2cs[i] = NULL; 923 } 924 } 925 926 for (i = 0; i < pool->base.stream_enc_count; i++) 927 kfree(pool->base.stream_enc[i]); 928 929 for (i = 0; i < pool->base.audio_count; i++) { 930 if (pool->base.audios[i]) 931 dce_aud_destroy(&pool->base.audios[i]); 932 } 933 934 for (i = 0; i < pool->base.clk_src_count; i++) { 935 if (pool->base.clock_sources[i] != NULL) { 936 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 937 pool->base.clock_sources[i] = NULL; 938 } 939 } 940 941 if (pool->base.dp_clock_source != NULL) { 942 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 943 pool->base.dp_clock_source = NULL; 944 } 945 946 if (pool->base.abm != NULL) 947 dce_abm_destroy(&pool->base.abm); 948 949 if (pool->base.dmcu != NULL) 950 dce_dmcu_destroy(&pool->base.dmcu); 951 952 if (pool->base.dccg != NULL) 953 dce_dccg_destroy(&pool->base.dccg); 954 955 kfree(pool->base.pp_smu); 956 } 957 958 static struct hubp *dcn10_hubp_create( 959 struct dc_context *ctx, 960 uint32_t inst) 961 { 962 struct dcn10_hubp *hubp1 = 963 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 964 965 if (!hubp1) 966 return NULL; 967 968 dcn10_hubp_construct(hubp1, ctx, inst, 969 &hubp_regs[inst], &hubp_shift, &hubp_mask); 970 return &hubp1->base; 971 } 972 973 static void get_pixel_clock_parameters( 974 const struct pipe_ctx *pipe_ctx, 975 struct pixel_clk_params *pixel_clk_params) 976 { 977 const struct dc_stream_state *stream = pipe_ctx->stream; 978 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 979 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 980 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 981 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 982 /* TODO: un-hardcode*/ 983 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 984 LINK_RATE_REF_FREQ_IN_KHZ; 985 pixel_clk_params->flags.ENABLE_SS = 0; 986 pixel_clk_params->color_depth = 987 stream->timing.display_color_depth; 988 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 989 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 990 991 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 992 pixel_clk_params->color_depth = COLOR_DEPTH_888; 993 994 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 995 pixel_clk_params->requested_pix_clk /= 2; 996 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 997 pixel_clk_params->requested_pix_clk *= 2; 998 999 } 1000 1001 static void build_clamping_params(struct dc_stream_state *stream) 1002 { 1003 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1004 stream->clamping.c_depth = stream->timing.display_color_depth; 1005 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1006 } 1007 1008 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1009 { 1010 1011 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1012 1013 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1014 pipe_ctx->clock_source, 1015 &pipe_ctx->stream_res.pix_clk_params, 1016 &pipe_ctx->pll_settings); 1017 1018 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1019 1020 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1021 &pipe_ctx->stream->bit_depth_params); 1022 build_clamping_params(pipe_ctx->stream); 1023 } 1024 1025 static enum dc_status build_mapped_resource( 1026 const struct dc *dc, 1027 struct dc_state *context, 1028 struct dc_stream_state *stream) 1029 { 1030 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1031 1032 /*TODO Seems unneeded anymore */ 1033 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1034 if (stream != NULL && old_context->streams[i] != NULL) { 1035 todo: shouldn't have to copy missing parameter here 1036 resource_build_bit_depth_reduction_params(stream, 1037 &stream->bit_depth_params); 1038 stream->clamping.pixel_encoding = 1039 stream->timing.pixel_encoding; 1040 1041 resource_build_bit_depth_reduction_params(stream, 1042 &stream->bit_depth_params); 1043 build_clamping_params(stream); 1044 1045 continue; 1046 } 1047 } 1048 */ 1049 1050 if (!pipe_ctx) 1051 return DC_ERROR_UNEXPECTED; 1052 1053 build_pipe_hw_param(pipe_ctx); 1054 return DC_OK; 1055 } 1056 1057 enum dc_status dcn10_add_stream_to_ctx( 1058 struct dc *dc, 1059 struct dc_state *new_ctx, 1060 struct dc_stream_state *dc_stream) 1061 { 1062 enum dc_status result = DC_ERROR_UNEXPECTED; 1063 1064 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1065 1066 if (result == DC_OK) 1067 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1068 1069 1070 if (result == DC_OK) 1071 result = build_mapped_resource(dc, new_ctx, dc_stream); 1072 1073 return result; 1074 } 1075 1076 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1077 struct dc_state *context, 1078 const struct resource_pool *pool, 1079 struct dc_stream_state *stream) 1080 { 1081 struct resource_context *res_ctx = &context->res_ctx; 1082 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1083 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool); 1084 1085 if (!head_pipe) { 1086 ASSERT(0); 1087 return NULL; 1088 } 1089 1090 if (!idle_pipe) 1091 return NULL; 1092 1093 idle_pipe->stream = head_pipe->stream; 1094 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1095 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1096 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1097 1098 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1099 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1100 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1101 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1102 1103 return idle_pipe; 1104 } 1105 1106 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1107 const struct dc_dcc_surface_param *input, 1108 struct dc_surface_dcc_cap *output) 1109 { 1110 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1111 dc->res_pool->hubbub, 1112 input, 1113 output); 1114 } 1115 1116 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1117 { 1118 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1119 1120 destruct(dcn10_pool); 1121 kfree(dcn10_pool); 1122 *pool = NULL; 1123 } 1124 1125 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1126 { 1127 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1128 && caps->max_video_width != 0 1129 && plane_state->src_rect.width > caps->max_video_width) 1130 return DC_FAIL_SURFACE_VALIDATE; 1131 1132 return DC_OK; 1133 } 1134 1135 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1136 { 1137 enum dc_status result = DC_OK; 1138 1139 enum surface_pixel_format surf_pix_format = plane_state->format; 1140 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1141 1142 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1143 1144 if (bpp == 64) 1145 swizzle = DC_SW_64KB_D; 1146 else 1147 swizzle = DC_SW_64KB_S; 1148 1149 plane_state->tiling_info.gfx9.swizzle = swizzle; 1150 return result; 1151 } 1152 1153 static const struct dc_cap_funcs cap_funcs = { 1154 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1155 }; 1156 1157 static const struct resource_funcs dcn10_res_pool_funcs = { 1158 .destroy = dcn10_destroy_resource_pool, 1159 .link_enc_create = dcn10_link_encoder_create, 1160 .validate_bandwidth = dcn_validate_bandwidth, 1161 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1162 .validate_plane = dcn10_validate_plane, 1163 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1164 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode 1165 }; 1166 1167 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1168 { 1169 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1170 /* RV1 support max 4 pipes */ 1171 value = value & 0xf; 1172 return value; 1173 } 1174 1175 static bool construct( 1176 uint8_t num_virtual_links, 1177 struct dc *dc, 1178 struct dcn10_resource_pool *pool) 1179 { 1180 int i; 1181 int j; 1182 struct dc_context *ctx = dc->ctx; 1183 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1184 1185 ctx->dc_bios->regs = &bios_regs; 1186 1187 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1188 if (ctx->dce_version == DCN_VERSION_1_01) 1189 pool->base.res_cap = &rv2_res_cap; 1190 else 1191 #endif 1192 pool->base.res_cap = &res_cap; 1193 pool->base.funcs = &dcn10_res_pool_funcs; 1194 1195 /* 1196 * TODO fill in from actual raven resource when we create 1197 * more than virtual encoder 1198 */ 1199 1200 /************************************************* 1201 * Resource + asic cap harcoding * 1202 *************************************************/ 1203 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1204 1205 /* max pipe num for ASIC before check pipe fuses */ 1206 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1207 1208 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1209 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1210 pool->base.pipe_count = 3; 1211 #endif 1212 dc->caps.max_video_width = 3840; 1213 dc->caps.max_downscale_ratio = 200; 1214 dc->caps.i2c_speed_in_khz = 100; 1215 dc->caps.max_cursor_size = 256; 1216 dc->caps.max_slave_planes = 1; 1217 dc->caps.is_apu = true; 1218 dc->caps.post_blend_color_processing = false; 1219 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1220 dc->caps.force_dp_tps4_for_cp2520 = true; 1221 1222 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1223 dc->debug = debug_defaults_drv; 1224 else 1225 dc->debug = debug_defaults_diags; 1226 1227 /************************************************* 1228 * Create resources * 1229 *************************************************/ 1230 1231 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1232 dcn10_clock_source_create(ctx, ctx->dc_bios, 1233 CLOCK_SOURCE_COMBO_PHY_PLL0, 1234 &clk_src_regs[0], false); 1235 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1236 dcn10_clock_source_create(ctx, ctx->dc_bios, 1237 CLOCK_SOURCE_COMBO_PHY_PLL1, 1238 &clk_src_regs[1], false); 1239 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1240 dcn10_clock_source_create(ctx, ctx->dc_bios, 1241 CLOCK_SOURCE_COMBO_PHY_PLL2, 1242 &clk_src_regs[2], false); 1243 1244 #ifdef CONFIG_DRM_AMD_DC_DCN1_01 1245 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1246 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1247 dcn10_clock_source_create(ctx, ctx->dc_bios, 1248 CLOCK_SOURCE_COMBO_PHY_PLL3, 1249 &clk_src_regs[3], false); 1250 } 1251 #else 1252 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1253 dcn10_clock_source_create(ctx, ctx->dc_bios, 1254 CLOCK_SOURCE_COMBO_PHY_PLL3, 1255 &clk_src_regs[3], false); 1256 #endif 1257 1258 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1259 1260 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1261 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1262 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1263 #endif 1264 1265 pool->base.dp_clock_source = 1266 dcn10_clock_source_create(ctx, ctx->dc_bios, 1267 CLOCK_SOURCE_ID_DP_DTO, 1268 /* todo: not reuse phy_pll registers */ 1269 &clk_src_regs[0], true); 1270 1271 for (i = 0; i < pool->base.clk_src_count; i++) { 1272 if (pool->base.clock_sources[i] == NULL) { 1273 dm_error("DC: failed to create clock sources!\n"); 1274 BREAK_TO_DEBUGGER(); 1275 goto fail; 1276 } 1277 } 1278 1279 pool->base.dccg = dcn1_dccg_create(ctx); 1280 if (pool->base.dccg == NULL) { 1281 dm_error("DC: failed to create display clock!\n"); 1282 BREAK_TO_DEBUGGER(); 1283 goto fail; 1284 } 1285 1286 pool->base.dmcu = dcn10_dmcu_create(ctx, 1287 &dmcu_regs, 1288 &dmcu_shift, 1289 &dmcu_mask); 1290 if (pool->base.dmcu == NULL) { 1291 dm_error("DC: failed to create dmcu!\n"); 1292 BREAK_TO_DEBUGGER(); 1293 goto fail; 1294 } 1295 1296 pool->base.abm = dce_abm_create(ctx, 1297 &abm_regs, 1298 &abm_shift, 1299 &abm_mask); 1300 if (pool->base.abm == NULL) { 1301 dm_error("DC: failed to create abm!\n"); 1302 BREAK_TO_DEBUGGER(); 1303 goto fail; 1304 } 1305 1306 dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1); 1307 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1308 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1309 1310 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1311 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1312 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1313 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1314 struct display_mode_lib *dml = &dc->dml; 1315 1316 dml->ip.max_num_dpp = 3; 1317 /* TODO how to handle 23.84? */ 1318 dcn_soc->dram_clock_change_latency = 23; 1319 dcn_ip->max_num_dpp = 3; 1320 } 1321 #endif 1322 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1323 dc->dcn_soc->urgent_latency = 3; 1324 dc->debug.disable_dmcu = true; 1325 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1326 } 1327 1328 1329 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1330 ASSERT(dc->dcn_soc->number_of_channels < 3); 1331 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1332 dc->dcn_soc->number_of_channels = 2; 1333 1334 if (dc->dcn_soc->number_of_channels == 1) { 1335 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1336 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1337 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1338 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1339 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1340 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1341 } 1342 } 1343 1344 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1345 1346 if (!dc->debug.disable_pplib_clock_request) 1347 dcn_bw_update_from_pplib(dc); 1348 dcn_bw_sync_calcs_and_dml(dc); 1349 if (!dc->debug.disable_pplib_wm_range) { 1350 dc->res_pool = &pool->base; 1351 dcn_bw_notify_pplib_of_wm_ranges(dc); 1352 } 1353 1354 { 1355 struct irq_service_init_data init_data; 1356 init_data.ctx = dc->ctx; 1357 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1358 if (!pool->base.irqs) 1359 goto fail; 1360 } 1361 1362 /* index to valid pipe resource */ 1363 j = 0; 1364 /* mem input -> ipp -> dpp -> opp -> TG */ 1365 for (i = 0; i < pool->base.pipe_count; i++) { 1366 /* if pipe is disabled, skip instance of HW pipe, 1367 * i.e, skip ASIC register instance 1368 */ 1369 if ((pipe_fuses & (1 << i)) != 0) 1370 continue; 1371 1372 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1373 if (pool->base.hubps[j] == NULL) { 1374 BREAK_TO_DEBUGGER(); 1375 dm_error( 1376 "DC: failed to create memory input!\n"); 1377 goto fail; 1378 } 1379 1380 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1381 if (pool->base.ipps[j] == NULL) { 1382 BREAK_TO_DEBUGGER(); 1383 dm_error( 1384 "DC: failed to create input pixel processor!\n"); 1385 goto fail; 1386 } 1387 1388 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1389 if (pool->base.dpps[j] == NULL) { 1390 BREAK_TO_DEBUGGER(); 1391 dm_error( 1392 "DC: failed to create dpp!\n"); 1393 goto fail; 1394 } 1395 1396 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1397 if (pool->base.opps[j] == NULL) { 1398 BREAK_TO_DEBUGGER(); 1399 dm_error( 1400 "DC: failed to create output pixel processor!\n"); 1401 goto fail; 1402 } 1403 1404 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1405 ctx, i); 1406 if (pool->base.timing_generators[j] == NULL) { 1407 BREAK_TO_DEBUGGER(); 1408 dm_error("DC: failed to create tg!\n"); 1409 goto fail; 1410 } 1411 /* check next valid pipe */ 1412 j++; 1413 } 1414 1415 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1416 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1417 if (pool->base.engines[i] == NULL) { 1418 BREAK_TO_DEBUGGER(); 1419 dm_error( 1420 "DC:failed to create aux engine!!\n"); 1421 goto fail; 1422 } 1423 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1424 if (pool->base.hw_i2cs[i] == NULL) { 1425 BREAK_TO_DEBUGGER(); 1426 dm_error( 1427 "DC:failed to create hw i2c!!\n"); 1428 goto fail; 1429 } 1430 pool->base.sw_i2cs[i] = NULL; 1431 } 1432 1433 /* valid pipe num */ 1434 pool->base.pipe_count = j; 1435 pool->base.timing_generator_count = j; 1436 1437 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1438 * the value may be changed 1439 */ 1440 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1441 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1442 1443 pool->base.mpc = dcn10_mpc_create(ctx); 1444 if (pool->base.mpc == NULL) { 1445 BREAK_TO_DEBUGGER(); 1446 dm_error("DC: failed to create mpc!\n"); 1447 goto fail; 1448 } 1449 1450 pool->base.hubbub = dcn10_hubbub_create(ctx); 1451 if (pool->base.hubbub == NULL) { 1452 BREAK_TO_DEBUGGER(); 1453 dm_error("DC: failed to create hubbub!\n"); 1454 goto fail; 1455 } 1456 1457 if (!resource_construct(num_virtual_links, dc, &pool->base, 1458 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1459 &res_create_funcs : &res_create_maximus_funcs))) 1460 goto fail; 1461 1462 dcn10_hw_sequencer_construct(dc); 1463 dc->caps.max_planes = pool->base.pipe_count; 1464 1465 dc->cap_funcs = cap_funcs; 1466 1467 return true; 1468 1469 fail: 1470 1471 destruct(pool); 1472 1473 return false; 1474 } 1475 1476 struct resource_pool *dcn10_create_resource_pool( 1477 uint8_t num_virtual_links, 1478 struct dc *dc) 1479 { 1480 struct dcn10_resource_pool *pool = 1481 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1482 1483 if (!pool) 1484 return NULL; 1485 1486 if (construct(num_virtual_links, dc, pool)) 1487 return &pool->base; 1488 1489 BREAK_TO_DEBUGGER(); 1490 return NULL; 1491 } 1492