1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dcn10_resource.h" 34 #include "dcn10_ipp.h" 35 #include "dcn10_mpc.h" 36 #include "irq/dcn10/irq_service_dcn10.h" 37 #include "dcn10_dpp.h" 38 #include "dcn10_optc.h" 39 #include "dcn10_hw_sequencer.h" 40 #include "dce110/dce110_hw_sequencer.h" 41 #include "dcn10_opp.h" 42 #include "dcn10_link_encoder.h" 43 #include "dcn10_stream_encoder.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs_luma = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 157 }; 158 159 /* begin ********************* 160 * macros to expend register list macro defined in HW object header file */ 161 162 /* DCN */ 163 #define BASE_INNER(seg) \ 164 DCE_BASE__INST0_SEG ## seg 165 166 #define BASE(seg) \ 167 BASE_INNER(seg) 168 169 #define SR(reg_name)\ 170 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 171 mm ## reg_name 172 173 #define SRI(reg_name, block, id)\ 174 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 mm ## block ## id ## _ ## reg_name 176 177 178 #define SRII(reg_name, block, id)\ 179 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 180 mm ## block ## id ## _ ## reg_name 181 182 /* NBIO */ 183 #define NBIO_BASE_INNER(seg) \ 184 NBIF_BASE__INST0_SEG ## seg 185 186 #define NBIO_BASE(seg) \ 187 NBIO_BASE_INNER(seg) 188 189 #define NBIO_SR(reg_name)\ 190 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 191 mm ## reg_name 192 193 /* MMHUB */ 194 #define MMHUB_BASE_INNER(seg) \ 195 MMHUB_BASE__INST0_SEG ## seg 196 197 #define MMHUB_BASE(seg) \ 198 MMHUB_BASE_INNER(seg) 199 200 #define MMHUB_SR(reg_name)\ 201 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 202 mm ## reg_name 203 204 /* macros to expend register list macro defined in HW object header file 205 * end *********************/ 206 207 208 static const struct dce_dmcu_registers dmcu_regs = { 209 DMCU_DCN10_REG_LIST() 210 }; 211 212 static const struct dce_dmcu_shift dmcu_shift = { 213 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 214 }; 215 216 static const struct dce_dmcu_mask dmcu_mask = { 217 DMCU_MASK_SH_LIST_DCN10(_MASK) 218 }; 219 220 static const struct dce_abm_registers abm_regs = { 221 ABM_DCN10_REG_LIST(0) 222 }; 223 224 static const struct dce_abm_shift abm_shift = { 225 ABM_MASK_SH_LIST_DCN10(__SHIFT) 226 }; 227 228 static const struct dce_abm_mask abm_mask = { 229 ABM_MASK_SH_LIST_DCN10(_MASK) 230 }; 231 232 #define stream_enc_regs(id)\ 233 [id] = {\ 234 SE_DCN_REG_LIST(id)\ 235 } 236 237 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 238 stream_enc_regs(0), 239 stream_enc_regs(1), 240 stream_enc_regs(2), 241 stream_enc_regs(3), 242 }; 243 244 static const struct dcn10_stream_encoder_shift se_shift = { 245 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 246 }; 247 248 static const struct dcn10_stream_encoder_mask se_mask = { 249 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 250 }; 251 252 #define audio_regs(id)\ 253 [id] = {\ 254 AUD_COMMON_REG_LIST(id)\ 255 } 256 257 static const struct dce_audio_registers audio_regs[] = { 258 audio_regs(0), 259 audio_regs(1), 260 audio_regs(2), 261 audio_regs(3), 262 }; 263 264 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 265 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 266 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 267 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 268 269 static const struct dce_audio_shift audio_shift = { 270 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 271 }; 272 273 static const struct dce_audio_mask audio_mask = { 274 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 275 }; 276 277 #define aux_regs(id)\ 278 [id] = {\ 279 AUX_REG_LIST(id)\ 280 } 281 282 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 283 aux_regs(0), 284 aux_regs(1), 285 aux_regs(2), 286 aux_regs(3) 287 }; 288 289 #define hpd_regs(id)\ 290 [id] = {\ 291 HPD_REG_LIST(id)\ 292 } 293 294 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 295 hpd_regs(0), 296 hpd_regs(1), 297 hpd_regs(2), 298 hpd_regs(3) 299 }; 300 301 #define link_regs(id)\ 302 [id] = {\ 303 LE_DCN10_REG_LIST(id), \ 304 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 305 } 306 307 static const struct dcn10_link_enc_registers link_enc_regs[] = { 308 link_regs(0), 309 link_regs(1), 310 link_regs(2), 311 link_regs(3) 312 }; 313 314 static const struct dcn10_link_enc_shift le_shift = { 315 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 316 }; 317 318 static const struct dcn10_link_enc_mask le_mask = { 319 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 320 }; 321 322 #define ipp_regs(id)\ 323 [id] = {\ 324 IPP_REG_LIST_DCN10(id),\ 325 } 326 327 static const struct dcn10_ipp_registers ipp_regs[] = { 328 ipp_regs(0), 329 ipp_regs(1), 330 ipp_regs(2), 331 ipp_regs(3), 332 }; 333 334 static const struct dcn10_ipp_shift ipp_shift = { 335 IPP_MASK_SH_LIST_DCN10(__SHIFT) 336 }; 337 338 static const struct dcn10_ipp_mask ipp_mask = { 339 IPP_MASK_SH_LIST_DCN10(_MASK), 340 }; 341 342 #define opp_regs(id)\ 343 [id] = {\ 344 OPP_REG_LIST_DCN10(id),\ 345 } 346 347 static const struct dcn10_opp_registers opp_regs[] = { 348 opp_regs(0), 349 opp_regs(1), 350 opp_regs(2), 351 opp_regs(3), 352 }; 353 354 static const struct dcn10_opp_shift opp_shift = { 355 OPP_MASK_SH_LIST_DCN10(__SHIFT) 356 }; 357 358 static const struct dcn10_opp_mask opp_mask = { 359 OPP_MASK_SH_LIST_DCN10(_MASK), 360 }; 361 362 #define aux_engine_regs(id)\ 363 [id] = {\ 364 AUX_COMMON_REG_LIST(id), \ 365 .AUX_RESET_MASK = 0 \ 366 } 367 368 static const struct dce110_aux_registers aux_engine_regs[] = { 369 aux_engine_regs(0), 370 aux_engine_regs(1), 371 aux_engine_regs(2), 372 aux_engine_regs(3), 373 aux_engine_regs(4), 374 aux_engine_regs(5) 375 }; 376 377 #define tf_regs(id)\ 378 [id] = {\ 379 TF_REG_LIST_DCN10(id),\ 380 } 381 382 static const struct dcn_dpp_registers tf_regs[] = { 383 tf_regs(0), 384 tf_regs(1), 385 tf_regs(2), 386 tf_regs(3), 387 }; 388 389 static const struct dcn_dpp_shift tf_shift = { 390 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 391 TF_DEBUG_REG_LIST_SH_DCN10 392 393 }; 394 395 static const struct dcn_dpp_mask tf_mask = { 396 TF_REG_LIST_SH_MASK_DCN10(_MASK), 397 TF_DEBUG_REG_LIST_MASK_DCN10 398 }; 399 400 static const struct dcn_mpc_registers mpc_regs = { 401 MPC_COMMON_REG_LIST_DCN1_0(0), 402 MPC_COMMON_REG_LIST_DCN1_0(1), 403 MPC_COMMON_REG_LIST_DCN1_0(2), 404 MPC_COMMON_REG_LIST_DCN1_0(3), 405 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 406 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 407 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 408 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 409 }; 410 411 static const struct dcn_mpc_shift mpc_shift = { 412 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 413 }; 414 415 static const struct dcn_mpc_mask mpc_mask = { 416 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 417 }; 418 419 #define tg_regs(id)\ 420 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 421 422 static const struct dcn_optc_registers tg_regs[] = { 423 tg_regs(0), 424 tg_regs(1), 425 tg_regs(2), 426 tg_regs(3), 427 }; 428 429 static const struct dcn_optc_shift tg_shift = { 430 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 431 }; 432 433 static const struct dcn_optc_mask tg_mask = { 434 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 435 }; 436 437 static const struct bios_registers bios_regs = { 438 NBIO_SR(BIOS_SCRATCH_3), 439 NBIO_SR(BIOS_SCRATCH_6) 440 }; 441 442 #define hubp_regs(id)\ 443 [id] = {\ 444 HUBP_REG_LIST_DCN10(id)\ 445 } 446 447 static const struct dcn_mi_registers hubp_regs[] = { 448 hubp_regs(0), 449 hubp_regs(1), 450 hubp_regs(2), 451 hubp_regs(3), 452 }; 453 454 static const struct dcn_mi_shift hubp_shift = { 455 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 456 }; 457 458 static const struct dcn_mi_mask hubp_mask = { 459 HUBP_MASK_SH_LIST_DCN10(_MASK) 460 }; 461 462 static const struct dcn_hubbub_registers hubbub_reg = { 463 HUBBUB_REG_LIST_DCN10(0) 464 }; 465 466 static const struct dcn_hubbub_shift hubbub_shift = { 467 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 468 }; 469 470 static const struct dcn_hubbub_mask hubbub_mask = { 471 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 472 }; 473 474 #define clk_src_regs(index, pllid)\ 475 [index] = {\ 476 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 477 } 478 479 static const struct dce110_clk_src_regs clk_src_regs[] = { 480 clk_src_regs(0, A), 481 clk_src_regs(1, B), 482 clk_src_regs(2, C), 483 clk_src_regs(3, D) 484 }; 485 486 static const struct dce110_clk_src_shift cs_shift = { 487 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 488 }; 489 490 static const struct dce110_clk_src_mask cs_mask = { 491 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 492 }; 493 494 static const struct resource_caps res_cap = { 495 .num_timing_generator = 4, 496 .num_opp = 4, 497 .num_video_plane = 4, 498 .num_audio = 4, 499 .num_stream_encoder = 4, 500 .num_pll = 4, 501 .num_ddc = 4, 502 }; 503 504 static const struct resource_caps rv2_res_cap = { 505 .num_timing_generator = 3, 506 .num_opp = 3, 507 .num_video_plane = 3, 508 .num_audio = 3, 509 .num_stream_encoder = 3, 510 .num_pll = 3, 511 .num_ddc = 4, 512 }; 513 514 static const struct dc_plane_cap plane_cap = { 515 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 516 .blends_with_above = true, 517 .blends_with_below = true, 518 .per_pixel_alpha = true, 519 520 .pixel_format_support = { 521 .argb8888 = true, 522 .nv12 = true, 523 .fp16 = true 524 }, 525 526 .max_upscale_factor = { 527 .argb8888 = 16000, 528 .nv12 = 16000, 529 .fp16 = 1 530 }, 531 532 .max_downscale_factor = { 533 .argb8888 = 250, 534 .nv12 = 250, 535 .fp16 = 1 536 } 537 }; 538 539 static const struct dc_debug_options debug_defaults_drv = { 540 .sanity_checks = true, 541 .disable_dmcu = true, 542 .force_abm_enable = false, 543 .timing_trace = false, 544 .clock_trace = true, 545 546 /* raven smu dones't allow 0 disp clk, 547 * smu min disp clk limit is 50Mhz 548 * keep min disp clk 100Mhz avoid smu hang 549 */ 550 .min_disp_clk_khz = 100000, 551 552 .disable_pplib_clock_request = false, 553 .disable_pplib_wm_range = false, 554 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 555 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 556 .force_single_disp_pipe_split = true, 557 .disable_dcc = DCC_ENABLE, 558 .voltage_align_fclk = true, 559 .disable_stereo_support = true, 560 .vsr_support = true, 561 .performance_trace = false, 562 .az_endpoint_mute_only = true, 563 .recovery_enabled = false, /*enable this by default after testing.*/ 564 .max_downscale_src_width = 3840, 565 .underflow_assert_delay_us = 0xFFFFFFFF, 566 }; 567 568 static const struct dc_debug_options debug_defaults_diags = { 569 .disable_dmcu = true, 570 .force_abm_enable = false, 571 .timing_trace = true, 572 .clock_trace = true, 573 .disable_stutter = true, 574 .disable_pplib_clock_request = true, 575 .disable_pplib_wm_range = true, 576 .underflow_assert_delay_us = 0xFFFFFFFF, 577 }; 578 579 static void dcn10_dpp_destroy(struct dpp **dpp) 580 { 581 kfree(TO_DCN10_DPP(*dpp)); 582 *dpp = NULL; 583 } 584 585 static struct dpp *dcn10_dpp_create( 586 struct dc_context *ctx, 587 uint32_t inst) 588 { 589 struct dcn10_dpp *dpp = 590 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 591 592 if (!dpp) 593 return NULL; 594 595 dpp1_construct(dpp, ctx, inst, 596 &tf_regs[inst], &tf_shift, &tf_mask); 597 return &dpp->base; 598 } 599 600 static struct input_pixel_processor *dcn10_ipp_create( 601 struct dc_context *ctx, uint32_t inst) 602 { 603 struct dcn10_ipp *ipp = 604 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 605 606 if (!ipp) { 607 BREAK_TO_DEBUGGER(); 608 return NULL; 609 } 610 611 dcn10_ipp_construct(ipp, ctx, inst, 612 &ipp_regs[inst], &ipp_shift, &ipp_mask); 613 return &ipp->base; 614 } 615 616 617 static struct output_pixel_processor *dcn10_opp_create( 618 struct dc_context *ctx, uint32_t inst) 619 { 620 struct dcn10_opp *opp = 621 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 622 623 if (!opp) { 624 BREAK_TO_DEBUGGER(); 625 return NULL; 626 } 627 628 dcn10_opp_construct(opp, ctx, inst, 629 &opp_regs[inst], &opp_shift, &opp_mask); 630 return &opp->base; 631 } 632 633 struct dce_aux *dcn10_aux_engine_create( 634 struct dc_context *ctx, 635 uint32_t inst) 636 { 637 struct aux_engine_dce110 *aux_engine = 638 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 639 640 if (!aux_engine) 641 return NULL; 642 643 dce110_aux_engine_construct(aux_engine, ctx, inst, 644 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 645 &aux_engine_regs[inst]); 646 647 return &aux_engine->base; 648 } 649 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 650 651 static const struct dce_i2c_registers i2c_hw_regs[] = { 652 i2c_inst_regs(1), 653 i2c_inst_regs(2), 654 i2c_inst_regs(3), 655 i2c_inst_regs(4), 656 i2c_inst_regs(5), 657 i2c_inst_regs(6), 658 }; 659 660 static const struct dce_i2c_shift i2c_shifts = { 661 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 662 }; 663 664 static const struct dce_i2c_mask i2c_masks = { 665 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 666 }; 667 668 struct dce_i2c_hw *dcn10_i2c_hw_create( 669 struct dc_context *ctx, 670 uint32_t inst) 671 { 672 struct dce_i2c_hw *dce_i2c_hw = 673 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 674 675 if (!dce_i2c_hw) 676 return NULL; 677 678 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 679 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 680 681 return dce_i2c_hw; 682 } 683 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 684 { 685 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 686 GFP_KERNEL); 687 688 if (!mpc10) 689 return NULL; 690 691 dcn10_mpc_construct(mpc10, ctx, 692 &mpc_regs, 693 &mpc_shift, 694 &mpc_mask, 695 4); 696 697 return &mpc10->base; 698 } 699 700 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 701 { 702 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 703 GFP_KERNEL); 704 705 if (!dcn10_hubbub) 706 return NULL; 707 708 hubbub1_construct(&dcn10_hubbub->base, ctx, 709 &hubbub_reg, 710 &hubbub_shift, 711 &hubbub_mask); 712 713 return &dcn10_hubbub->base; 714 } 715 716 static struct timing_generator *dcn10_timing_generator_create( 717 struct dc_context *ctx, 718 uint32_t instance) 719 { 720 struct optc *tgn10 = 721 kzalloc(sizeof(struct optc), GFP_KERNEL); 722 723 if (!tgn10) 724 return NULL; 725 726 tgn10->base.inst = instance; 727 tgn10->base.ctx = ctx; 728 729 tgn10->tg_regs = &tg_regs[instance]; 730 tgn10->tg_shift = &tg_shift; 731 tgn10->tg_mask = &tg_mask; 732 733 dcn10_timing_generator_init(tgn10); 734 735 return &tgn10->base; 736 } 737 738 static const struct encoder_feature_support link_enc_feature = { 739 .max_hdmi_deep_color = COLOR_DEPTH_121212, 740 .max_hdmi_pixel_clock = 600000, 741 .hdmi_ycbcr420_supported = true, 742 .dp_ycbcr420_supported = false, 743 .flags.bits.IS_HBR2_CAPABLE = true, 744 .flags.bits.IS_HBR3_CAPABLE = true, 745 .flags.bits.IS_TPS3_CAPABLE = true, 746 .flags.bits.IS_TPS4_CAPABLE = true 747 }; 748 749 struct link_encoder *dcn10_link_encoder_create( 750 const struct encoder_init_data *enc_init_data) 751 { 752 struct dcn10_link_encoder *enc10 = 753 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 754 755 if (!enc10) 756 return NULL; 757 758 dcn10_link_encoder_construct(enc10, 759 enc_init_data, 760 &link_enc_feature, 761 &link_enc_regs[enc_init_data->transmitter], 762 &link_enc_aux_regs[enc_init_data->channel - 1], 763 &link_enc_hpd_regs[enc_init_data->hpd_source], 764 &le_shift, 765 &le_mask); 766 767 return &enc10->base; 768 } 769 770 struct clock_source *dcn10_clock_source_create( 771 struct dc_context *ctx, 772 struct dc_bios *bios, 773 enum clock_source_id id, 774 const struct dce110_clk_src_regs *regs, 775 bool dp_clk_src) 776 { 777 struct dce110_clk_src *clk_src = 778 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 779 780 if (!clk_src) 781 return NULL; 782 783 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 784 regs, &cs_shift, &cs_mask)) { 785 clk_src->base.dp_clk_src = dp_clk_src; 786 return &clk_src->base; 787 } 788 789 kfree(clk_src); 790 BREAK_TO_DEBUGGER(); 791 return NULL; 792 } 793 794 static void read_dce_straps( 795 struct dc_context *ctx, 796 struct resource_straps *straps) 797 { 798 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 799 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 800 } 801 802 static struct audio *create_audio( 803 struct dc_context *ctx, unsigned int inst) 804 { 805 return dce_audio_create(ctx, inst, 806 &audio_regs[inst], &audio_shift, &audio_mask); 807 } 808 809 static struct stream_encoder *dcn10_stream_encoder_create( 810 enum engine_id eng_id, 811 struct dc_context *ctx) 812 { 813 struct dcn10_stream_encoder *enc1 = 814 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 815 816 if (!enc1) 817 return NULL; 818 819 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 820 &stream_enc_regs[eng_id], 821 &se_shift, &se_mask); 822 return &enc1->base; 823 } 824 825 static const struct dce_hwseq_registers hwseq_reg = { 826 HWSEQ_DCN1_REG_LIST() 827 }; 828 829 static const struct dce_hwseq_shift hwseq_shift = { 830 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 831 }; 832 833 static const struct dce_hwseq_mask hwseq_mask = { 834 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 835 }; 836 837 static struct dce_hwseq *dcn10_hwseq_create( 838 struct dc_context *ctx) 839 { 840 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 841 842 if (hws) { 843 hws->ctx = ctx; 844 hws->regs = &hwseq_reg; 845 hws->shifts = &hwseq_shift; 846 hws->masks = &hwseq_mask; 847 hws->wa.DEGVIDCN10_253 = true; 848 hws->wa.false_optc_underflow = true; 849 hws->wa.DEGVIDCN10_254 = true; 850 } 851 return hws; 852 } 853 854 static const struct resource_create_funcs res_create_funcs = { 855 .read_dce_straps = read_dce_straps, 856 .create_audio = create_audio, 857 .create_stream_encoder = dcn10_stream_encoder_create, 858 .create_hwseq = dcn10_hwseq_create, 859 }; 860 861 static const struct resource_create_funcs res_create_maximus_funcs = { 862 .read_dce_straps = NULL, 863 .create_audio = NULL, 864 .create_stream_encoder = NULL, 865 .create_hwseq = dcn10_hwseq_create, 866 }; 867 868 void dcn10_clock_source_destroy(struct clock_source **clk_src) 869 { 870 kfree(TO_DCE110_CLK_SRC(*clk_src)); 871 *clk_src = NULL; 872 } 873 874 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 875 { 876 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 877 878 if (!pp_smu) 879 return pp_smu; 880 881 dm_pp_get_funcs(ctx, pp_smu); 882 return pp_smu; 883 } 884 885 static void destruct(struct dcn10_resource_pool *pool) 886 { 887 unsigned int i; 888 889 for (i = 0; i < pool->base.stream_enc_count; i++) { 890 if (pool->base.stream_enc[i] != NULL) { 891 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 892 pool->base.stream_enc[i] = NULL; 893 } 894 } 895 896 if (pool->base.mpc != NULL) { 897 kfree(TO_DCN10_MPC(pool->base.mpc)); 898 pool->base.mpc = NULL; 899 } 900 901 if (pool->base.hubbub != NULL) { 902 kfree(pool->base.hubbub); 903 pool->base.hubbub = NULL; 904 } 905 906 for (i = 0; i < pool->base.pipe_count; i++) { 907 if (pool->base.opps[i] != NULL) 908 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 909 910 if (pool->base.dpps[i] != NULL) 911 dcn10_dpp_destroy(&pool->base.dpps[i]); 912 913 if (pool->base.ipps[i] != NULL) 914 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 915 916 if (pool->base.hubps[i] != NULL) { 917 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 918 pool->base.hubps[i] = NULL; 919 } 920 921 if (pool->base.irqs != NULL) { 922 dal_irq_service_destroy(&pool->base.irqs); 923 } 924 925 if (pool->base.timing_generators[i] != NULL) { 926 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 927 pool->base.timing_generators[i] = NULL; 928 } 929 } 930 931 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 932 if (pool->base.engines[i] != NULL) 933 dce110_engine_destroy(&pool->base.engines[i]); 934 if (pool->base.hw_i2cs[i] != NULL) { 935 kfree(pool->base.hw_i2cs[i]); 936 pool->base.hw_i2cs[i] = NULL; 937 } 938 if (pool->base.sw_i2cs[i] != NULL) { 939 kfree(pool->base.sw_i2cs[i]); 940 pool->base.sw_i2cs[i] = NULL; 941 } 942 } 943 944 for (i = 0; i < pool->base.audio_count; i++) { 945 if (pool->base.audios[i]) 946 dce_aud_destroy(&pool->base.audios[i]); 947 } 948 949 for (i = 0; i < pool->base.clk_src_count; i++) { 950 if (pool->base.clock_sources[i] != NULL) { 951 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 952 pool->base.clock_sources[i] = NULL; 953 } 954 } 955 956 if (pool->base.dp_clock_source != NULL) { 957 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 958 pool->base.dp_clock_source = NULL; 959 } 960 961 if (pool->base.abm != NULL) 962 dce_abm_destroy(&pool->base.abm); 963 964 if (pool->base.dmcu != NULL) 965 dce_dmcu_destroy(&pool->base.dmcu); 966 967 kfree(pool->base.pp_smu); 968 } 969 970 static struct hubp *dcn10_hubp_create( 971 struct dc_context *ctx, 972 uint32_t inst) 973 { 974 struct dcn10_hubp *hubp1 = 975 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 976 977 if (!hubp1) 978 return NULL; 979 980 dcn10_hubp_construct(hubp1, ctx, inst, 981 &hubp_regs[inst], &hubp_shift, &hubp_mask); 982 return &hubp1->base; 983 } 984 985 static void get_pixel_clock_parameters( 986 const struct pipe_ctx *pipe_ctx, 987 struct pixel_clk_params *pixel_clk_params) 988 { 989 const struct dc_stream_state *stream = pipe_ctx->stream; 990 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 991 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 992 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 993 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 994 /* TODO: un-hardcode*/ 995 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 996 LINK_RATE_REF_FREQ_IN_KHZ; 997 pixel_clk_params->flags.ENABLE_SS = 0; 998 pixel_clk_params->color_depth = 999 stream->timing.display_color_depth; 1000 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1001 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1002 1003 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1004 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1005 1006 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1007 pixel_clk_params->requested_pix_clk_100hz /= 2; 1008 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1009 pixel_clk_params->requested_pix_clk_100hz *= 2; 1010 1011 } 1012 1013 static void build_clamping_params(struct dc_stream_state *stream) 1014 { 1015 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1016 stream->clamping.c_depth = stream->timing.display_color_depth; 1017 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1018 } 1019 1020 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1021 { 1022 1023 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1024 1025 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1026 pipe_ctx->clock_source, 1027 &pipe_ctx->stream_res.pix_clk_params, 1028 &pipe_ctx->pll_settings); 1029 1030 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1031 1032 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1033 &pipe_ctx->stream->bit_depth_params); 1034 build_clamping_params(pipe_ctx->stream); 1035 } 1036 1037 static enum dc_status build_mapped_resource( 1038 const struct dc *dc, 1039 struct dc_state *context, 1040 struct dc_stream_state *stream) 1041 { 1042 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1043 1044 /*TODO Seems unneeded anymore */ 1045 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1046 if (stream != NULL && old_context->streams[i] != NULL) { 1047 todo: shouldn't have to copy missing parameter here 1048 resource_build_bit_depth_reduction_params(stream, 1049 &stream->bit_depth_params); 1050 stream->clamping.pixel_encoding = 1051 stream->timing.pixel_encoding; 1052 1053 resource_build_bit_depth_reduction_params(stream, 1054 &stream->bit_depth_params); 1055 build_clamping_params(stream); 1056 1057 continue; 1058 } 1059 } 1060 */ 1061 1062 if (!pipe_ctx) 1063 return DC_ERROR_UNEXPECTED; 1064 1065 build_pipe_hw_param(pipe_ctx); 1066 return DC_OK; 1067 } 1068 1069 enum dc_status dcn10_add_stream_to_ctx( 1070 struct dc *dc, 1071 struct dc_state *new_ctx, 1072 struct dc_stream_state *dc_stream) 1073 { 1074 enum dc_status result = DC_ERROR_UNEXPECTED; 1075 1076 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1077 1078 if (result == DC_OK) 1079 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1080 1081 1082 if (result == DC_OK) 1083 result = build_mapped_resource(dc, new_ctx, dc_stream); 1084 1085 return result; 1086 } 1087 1088 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1089 struct dc_state *context, 1090 const struct resource_pool *pool, 1091 struct dc_stream_state *stream) 1092 { 1093 struct resource_context *res_ctx = &context->res_ctx; 1094 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1095 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 1096 1097 if (!head_pipe) { 1098 ASSERT(0); 1099 return NULL; 1100 } 1101 1102 if (!idle_pipe) 1103 return NULL; 1104 1105 idle_pipe->stream = head_pipe->stream; 1106 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1107 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1108 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1109 1110 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1111 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1112 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1113 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1114 1115 return idle_pipe; 1116 } 1117 1118 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1119 const struct dc_dcc_surface_param *input, 1120 struct dc_surface_dcc_cap *output) 1121 { 1122 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1123 dc->res_pool->hubbub, 1124 input, 1125 output); 1126 } 1127 1128 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1129 { 1130 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1131 1132 destruct(dcn10_pool); 1133 kfree(dcn10_pool); 1134 *pool = NULL; 1135 } 1136 1137 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1138 { 1139 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1140 && caps->max_video_width != 0 1141 && plane_state->src_rect.width > caps->max_video_width) 1142 return DC_FAIL_SURFACE_VALIDATE; 1143 1144 return DC_OK; 1145 } 1146 1147 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1148 { 1149 int i, j; 1150 bool video_down_scaled = false; 1151 bool video_large = false; 1152 bool desktop_large = false; 1153 bool dcc_disabled = false; 1154 1155 for (i = 0; i < context->stream_count; i++) { 1156 if (context->stream_status[i].plane_count == 0) 1157 continue; 1158 1159 if (context->stream_status[i].plane_count > 2) 1160 return DC_FAIL_UNSUPPORTED_1; 1161 1162 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1163 struct dc_plane_state *plane = 1164 context->stream_status[i].plane_states[j]; 1165 1166 1167 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1168 1169 if (plane->src_rect.width > plane->dst_rect.width || 1170 plane->src_rect.height > plane->dst_rect.height) 1171 video_down_scaled = true; 1172 1173 if (plane->src_rect.width >= 3840) 1174 video_large = true; 1175 1176 } else { 1177 if (plane->src_rect.width >= 3840) 1178 desktop_large = true; 1179 if (!plane->dcc.enable) 1180 dcc_disabled = true; 1181 } 1182 } 1183 } 1184 1185 /* 1186 * Workaround: On DCN10 there is UMC issue that causes underflow when 1187 * playing 4k video on 4k desktop with video downscaled and single channel 1188 * memory 1189 */ 1190 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1191 dc->dcn_soc->number_of_channels == 1) 1192 return DC_FAIL_SURFACE_VALIDATE; 1193 1194 return DC_OK; 1195 } 1196 1197 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1198 { 1199 enum dc_status result = DC_OK; 1200 1201 enum surface_pixel_format surf_pix_format = plane_state->format; 1202 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1203 1204 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1205 1206 if (bpp == 64) 1207 swizzle = DC_SW_64KB_D; 1208 else 1209 swizzle = DC_SW_64KB_S; 1210 1211 plane_state->tiling_info.gfx9.swizzle = swizzle; 1212 return result; 1213 } 1214 1215 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 1216 struct resource_context *res_ctx, 1217 const struct resource_pool *pool, 1218 struct dc_stream_state *stream) 1219 { 1220 int i; 1221 int j = -1; 1222 struct dc_link *link = stream->link; 1223 1224 for (i = 0; i < pool->stream_enc_count; i++) { 1225 if (!res_ctx->is_stream_enc_acquired[i] && 1226 pool->stream_enc[i]) { 1227 /* Store first available for MST second display 1228 * in daisy chain use case 1229 */ 1230 j = i; 1231 if (pool->stream_enc[i]->id == 1232 link->link_enc->preferred_engine) 1233 return pool->stream_enc[i]; 1234 } 1235 } 1236 1237 /* 1238 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1239 */ 1240 1241 if (j >= 0) 1242 return pool->stream_enc[j]; 1243 1244 return NULL; 1245 } 1246 1247 static const struct dc_cap_funcs cap_funcs = { 1248 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1249 }; 1250 1251 static const struct resource_funcs dcn10_res_pool_funcs = { 1252 .destroy = dcn10_destroy_resource_pool, 1253 .link_enc_create = dcn10_link_encoder_create, 1254 .validate_bandwidth = dcn_validate_bandwidth, 1255 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1256 .validate_plane = dcn10_validate_plane, 1257 .validate_global = dcn10_validate_global, 1258 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1259 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode, 1260 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 1261 }; 1262 1263 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1264 { 1265 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1266 /* RV1 support max 4 pipes */ 1267 value = value & 0xf; 1268 return value; 1269 } 1270 1271 static bool construct( 1272 uint8_t num_virtual_links, 1273 struct dc *dc, 1274 struct dcn10_resource_pool *pool) 1275 { 1276 int i; 1277 int j; 1278 struct dc_context *ctx = dc->ctx; 1279 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1280 1281 ctx->dc_bios->regs = &bios_regs; 1282 1283 if (ctx->dce_version == DCN_VERSION_1_01) 1284 pool->base.res_cap = &rv2_res_cap; 1285 else 1286 pool->base.res_cap = &res_cap; 1287 pool->base.funcs = &dcn10_res_pool_funcs; 1288 1289 /* 1290 * TODO fill in from actual raven resource when we create 1291 * more than virtual encoder 1292 */ 1293 1294 /************************************************* 1295 * Resource + asic cap harcoding * 1296 *************************************************/ 1297 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1298 1299 /* max pipe num for ASIC before check pipe fuses */ 1300 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1301 1302 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1303 pool->base.pipe_count = 3; 1304 dc->caps.max_video_width = 3840; 1305 dc->caps.max_downscale_ratio = 200; 1306 dc->caps.i2c_speed_in_khz = 100; 1307 dc->caps.max_cursor_size = 256; 1308 dc->caps.max_slave_planes = 1; 1309 dc->caps.is_apu = true; 1310 dc->caps.post_blend_color_processing = false; 1311 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1312 dc->caps.force_dp_tps4_for_cp2520 = true; 1313 1314 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1315 dc->debug = debug_defaults_drv; 1316 else 1317 dc->debug = debug_defaults_diags; 1318 1319 /************************************************* 1320 * Create resources * 1321 *************************************************/ 1322 1323 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1324 dcn10_clock_source_create(ctx, ctx->dc_bios, 1325 CLOCK_SOURCE_COMBO_PHY_PLL0, 1326 &clk_src_regs[0], false); 1327 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1328 dcn10_clock_source_create(ctx, ctx->dc_bios, 1329 CLOCK_SOURCE_COMBO_PHY_PLL1, 1330 &clk_src_regs[1], false); 1331 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1332 dcn10_clock_source_create(ctx, ctx->dc_bios, 1333 CLOCK_SOURCE_COMBO_PHY_PLL2, 1334 &clk_src_regs[2], false); 1335 1336 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1337 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1338 dcn10_clock_source_create(ctx, ctx->dc_bios, 1339 CLOCK_SOURCE_COMBO_PHY_PLL3, 1340 &clk_src_regs[3], false); 1341 } 1342 1343 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1344 1345 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1346 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1347 1348 pool->base.dp_clock_source = 1349 dcn10_clock_source_create(ctx, ctx->dc_bios, 1350 CLOCK_SOURCE_ID_DP_DTO, 1351 /* todo: not reuse phy_pll registers */ 1352 &clk_src_regs[0], true); 1353 1354 for (i = 0; i < pool->base.clk_src_count; i++) { 1355 if (pool->base.clock_sources[i] == NULL) { 1356 dm_error("DC: failed to create clock sources!\n"); 1357 BREAK_TO_DEBUGGER(); 1358 goto fail; 1359 } 1360 } 1361 1362 pool->base.dmcu = dcn10_dmcu_create(ctx, 1363 &dmcu_regs, 1364 &dmcu_shift, 1365 &dmcu_mask); 1366 if (pool->base.dmcu == NULL) { 1367 dm_error("DC: failed to create dmcu!\n"); 1368 BREAK_TO_DEBUGGER(); 1369 goto fail; 1370 } 1371 1372 pool->base.abm = dce_abm_create(ctx, 1373 &abm_regs, 1374 &abm_shift, 1375 &abm_mask); 1376 if (pool->base.abm == NULL) { 1377 dm_error("DC: failed to create abm!\n"); 1378 BREAK_TO_DEBUGGER(); 1379 goto fail; 1380 } 1381 1382 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1383 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1384 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1385 1386 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1387 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1388 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1389 struct display_mode_lib *dml = &dc->dml; 1390 1391 dml->ip.max_num_dpp = 3; 1392 /* TODO how to handle 23.84? */ 1393 dcn_soc->dram_clock_change_latency = 23; 1394 dcn_ip->max_num_dpp = 3; 1395 } 1396 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1397 dc->dcn_soc->urgent_latency = 3; 1398 dc->debug.disable_dmcu = true; 1399 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1400 } 1401 1402 1403 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1404 ASSERT(dc->dcn_soc->number_of_channels < 3); 1405 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1406 dc->dcn_soc->number_of_channels = 2; 1407 1408 if (dc->dcn_soc->number_of_channels == 1) { 1409 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1410 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1411 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1412 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1413 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1414 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1415 } 1416 } 1417 1418 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1419 1420 /* 1421 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * 1422 * implemented. So AZ D3 should work.For issue 197007. * 1423 */ 1424 if (pool->base.pp_smu != NULL 1425 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) 1426 dc->debug.az_endpoint_mute_only = false; 1427 1428 if (!dc->debug.disable_pplib_clock_request) 1429 dcn_bw_update_from_pplib(dc); 1430 dcn_bw_sync_calcs_and_dml(dc); 1431 if (!dc->debug.disable_pplib_wm_range) { 1432 dc->res_pool = &pool->base; 1433 dcn_bw_notify_pplib_of_wm_ranges(dc); 1434 } 1435 1436 { 1437 struct irq_service_init_data init_data; 1438 init_data.ctx = dc->ctx; 1439 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1440 if (!pool->base.irqs) 1441 goto fail; 1442 } 1443 1444 /* index to valid pipe resource */ 1445 j = 0; 1446 /* mem input -> ipp -> dpp -> opp -> TG */ 1447 for (i = 0; i < pool->base.pipe_count; i++) { 1448 /* if pipe is disabled, skip instance of HW pipe, 1449 * i.e, skip ASIC register instance 1450 */ 1451 if ((pipe_fuses & (1 << i)) != 0) 1452 continue; 1453 1454 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1455 if (pool->base.hubps[j] == NULL) { 1456 BREAK_TO_DEBUGGER(); 1457 dm_error( 1458 "DC: failed to create memory input!\n"); 1459 goto fail; 1460 } 1461 1462 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1463 if (pool->base.ipps[j] == NULL) { 1464 BREAK_TO_DEBUGGER(); 1465 dm_error( 1466 "DC: failed to create input pixel processor!\n"); 1467 goto fail; 1468 } 1469 1470 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1471 if (pool->base.dpps[j] == NULL) { 1472 BREAK_TO_DEBUGGER(); 1473 dm_error( 1474 "DC: failed to create dpp!\n"); 1475 goto fail; 1476 } 1477 1478 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1479 if (pool->base.opps[j] == NULL) { 1480 BREAK_TO_DEBUGGER(); 1481 dm_error( 1482 "DC: failed to create output pixel processor!\n"); 1483 goto fail; 1484 } 1485 1486 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1487 ctx, i); 1488 if (pool->base.timing_generators[j] == NULL) { 1489 BREAK_TO_DEBUGGER(); 1490 dm_error("DC: failed to create tg!\n"); 1491 goto fail; 1492 } 1493 /* check next valid pipe */ 1494 j++; 1495 } 1496 1497 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1498 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1499 if (pool->base.engines[i] == NULL) { 1500 BREAK_TO_DEBUGGER(); 1501 dm_error( 1502 "DC:failed to create aux engine!!\n"); 1503 goto fail; 1504 } 1505 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1506 if (pool->base.hw_i2cs[i] == NULL) { 1507 BREAK_TO_DEBUGGER(); 1508 dm_error( 1509 "DC:failed to create hw i2c!!\n"); 1510 goto fail; 1511 } 1512 pool->base.sw_i2cs[i] = NULL; 1513 } 1514 1515 /* valid pipe num */ 1516 pool->base.pipe_count = j; 1517 pool->base.timing_generator_count = j; 1518 1519 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1520 * the value may be changed 1521 */ 1522 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1523 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1524 1525 pool->base.mpc = dcn10_mpc_create(ctx); 1526 if (pool->base.mpc == NULL) { 1527 BREAK_TO_DEBUGGER(); 1528 dm_error("DC: failed to create mpc!\n"); 1529 goto fail; 1530 } 1531 1532 pool->base.hubbub = dcn10_hubbub_create(ctx); 1533 if (pool->base.hubbub == NULL) { 1534 BREAK_TO_DEBUGGER(); 1535 dm_error("DC: failed to create hubbub!\n"); 1536 goto fail; 1537 } 1538 1539 if (!resource_construct(num_virtual_links, dc, &pool->base, 1540 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1541 &res_create_funcs : &res_create_maximus_funcs))) 1542 goto fail; 1543 1544 dcn10_hw_sequencer_construct(dc); 1545 dc->caps.max_planes = pool->base.pipe_count; 1546 1547 for (i = 0; i < dc->caps.max_planes; ++i) 1548 dc->caps.planes[i] = plane_cap; 1549 1550 dc->cap_funcs = cap_funcs; 1551 1552 return true; 1553 1554 fail: 1555 1556 destruct(pool); 1557 1558 return false; 1559 } 1560 1561 struct resource_pool *dcn10_create_resource_pool( 1562 const struct dc_init_data *init_data, 1563 struct dc *dc) 1564 { 1565 struct dcn10_resource_pool *pool = 1566 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1567 1568 if (!pool) 1569 return NULL; 1570 1571 if (construct(init_data->num_virtual_links, dc, pool)) 1572 return &pool->base; 1573 1574 kfree(pool); 1575 BREAK_TO_DEBUGGER(); 1576 return NULL; 1577 } 1578