1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn10_resource.h" 32 33 #include "dcn10_ipp.h" 34 #include "dcn10_mpc.h" 35 #include "irq/dcn10/irq_service_dcn10.h" 36 #include "dcn10_dpp.h" 37 #include "dcn10_optc.h" 38 #include "dcn10_hw_sequencer.h" 39 #include "dce110/dce110_hw_sequencer.h" 40 #include "dcn10_opp.h" 41 #include "dcn10_link_encoder.h" 42 #include "dcn10_stream_encoder.h" 43 #include "dcn10_clk_mgr.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 157 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 158 #endif 159 }; 160 161 /* begin ********************* 162 * macros to expend register list macro defined in HW object header file */ 163 164 /* DCN */ 165 #define BASE_INNER(seg) \ 166 DCE_BASE__INST0_SEG ## seg 167 168 #define BASE(seg) \ 169 BASE_INNER(seg) 170 171 #define SR(reg_name)\ 172 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 173 mm ## reg_name 174 175 #define SRI(reg_name, block, id)\ 176 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 mm ## block ## id ## _ ## reg_name 178 179 180 #define SRII(reg_name, block, id)\ 181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 mm ## block ## id ## _ ## reg_name 183 184 /* NBIO */ 185 #define NBIO_BASE_INNER(seg) \ 186 NBIF_BASE__INST0_SEG ## seg 187 188 #define NBIO_BASE(seg) \ 189 NBIO_BASE_INNER(seg) 190 191 #define NBIO_SR(reg_name)\ 192 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 193 mm ## reg_name 194 195 /* MMHUB */ 196 #define MMHUB_BASE_INNER(seg) \ 197 MMHUB_BASE__INST0_SEG ## seg 198 199 #define MMHUB_BASE(seg) \ 200 MMHUB_BASE_INNER(seg) 201 202 #define MMHUB_SR(reg_name)\ 203 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 204 mm ## reg_name 205 206 /* macros to expend register list macro defined in HW object header file 207 * end *********************/ 208 209 210 static const struct dce_dmcu_registers dmcu_regs = { 211 DMCU_DCN10_REG_LIST() 212 }; 213 214 static const struct dce_dmcu_shift dmcu_shift = { 215 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 216 }; 217 218 static const struct dce_dmcu_mask dmcu_mask = { 219 DMCU_MASK_SH_LIST_DCN10(_MASK) 220 }; 221 222 static const struct dce_abm_registers abm_regs = { 223 ABM_DCN10_REG_LIST(0) 224 }; 225 226 static const struct dce_abm_shift abm_shift = { 227 ABM_MASK_SH_LIST_DCN10(__SHIFT) 228 }; 229 230 static const struct dce_abm_mask abm_mask = { 231 ABM_MASK_SH_LIST_DCN10(_MASK) 232 }; 233 234 #define stream_enc_regs(id)\ 235 [id] = {\ 236 SE_DCN_REG_LIST(id)\ 237 } 238 239 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 240 stream_enc_regs(0), 241 stream_enc_regs(1), 242 stream_enc_regs(2), 243 stream_enc_regs(3), 244 }; 245 246 static const struct dcn10_stream_encoder_shift se_shift = { 247 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 248 }; 249 250 static const struct dcn10_stream_encoder_mask se_mask = { 251 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 252 }; 253 254 #define audio_regs(id)\ 255 [id] = {\ 256 AUD_COMMON_REG_LIST(id)\ 257 } 258 259 static const struct dce_audio_registers audio_regs[] = { 260 audio_regs(0), 261 audio_regs(1), 262 audio_regs(2), 263 audio_regs(3), 264 }; 265 266 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 267 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 268 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 269 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 270 271 static const struct dce_audio_shift audio_shift = { 272 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 273 }; 274 275 static const struct dce_aduio_mask audio_mask = { 276 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 277 }; 278 279 #define aux_regs(id)\ 280 [id] = {\ 281 AUX_REG_LIST(id)\ 282 } 283 284 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 285 aux_regs(0), 286 aux_regs(1), 287 aux_regs(2), 288 aux_regs(3) 289 }; 290 291 #define hpd_regs(id)\ 292 [id] = {\ 293 HPD_REG_LIST(id)\ 294 } 295 296 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 297 hpd_regs(0), 298 hpd_regs(1), 299 hpd_regs(2), 300 hpd_regs(3) 301 }; 302 303 #define link_regs(id)\ 304 [id] = {\ 305 LE_DCN10_REG_LIST(id), \ 306 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 307 } 308 309 static const struct dcn10_link_enc_registers link_enc_regs[] = { 310 link_regs(0), 311 link_regs(1), 312 link_regs(2), 313 link_regs(3) 314 }; 315 316 static const struct dcn10_link_enc_shift le_shift = { 317 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 318 }; 319 320 static const struct dcn10_link_enc_mask le_mask = { 321 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 322 }; 323 324 #define ipp_regs(id)\ 325 [id] = {\ 326 IPP_REG_LIST_DCN10(id),\ 327 } 328 329 static const struct dcn10_ipp_registers ipp_regs[] = { 330 ipp_regs(0), 331 ipp_regs(1), 332 ipp_regs(2), 333 ipp_regs(3), 334 }; 335 336 static const struct dcn10_ipp_shift ipp_shift = { 337 IPP_MASK_SH_LIST_DCN10(__SHIFT) 338 }; 339 340 static const struct dcn10_ipp_mask ipp_mask = { 341 IPP_MASK_SH_LIST_DCN10(_MASK), 342 }; 343 344 #define opp_regs(id)\ 345 [id] = {\ 346 OPP_REG_LIST_DCN10(id),\ 347 } 348 349 static const struct dcn10_opp_registers opp_regs[] = { 350 opp_regs(0), 351 opp_regs(1), 352 opp_regs(2), 353 opp_regs(3), 354 }; 355 356 static const struct dcn10_opp_shift opp_shift = { 357 OPP_MASK_SH_LIST_DCN10(__SHIFT) 358 }; 359 360 static const struct dcn10_opp_mask opp_mask = { 361 OPP_MASK_SH_LIST_DCN10(_MASK), 362 }; 363 364 #define aux_engine_regs(id)\ 365 [id] = {\ 366 AUX_COMMON_REG_LIST(id), \ 367 .AUX_RESET_MASK = 0 \ 368 } 369 370 static const struct dce110_aux_registers aux_engine_regs[] = { 371 aux_engine_regs(0), 372 aux_engine_regs(1), 373 aux_engine_regs(2), 374 aux_engine_regs(3), 375 aux_engine_regs(4), 376 aux_engine_regs(5) 377 }; 378 379 #define tf_regs(id)\ 380 [id] = {\ 381 TF_REG_LIST_DCN10(id),\ 382 } 383 384 static const struct dcn_dpp_registers tf_regs[] = { 385 tf_regs(0), 386 tf_regs(1), 387 tf_regs(2), 388 tf_regs(3), 389 }; 390 391 static const struct dcn_dpp_shift tf_shift = { 392 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 393 TF_DEBUG_REG_LIST_SH_DCN10 394 395 }; 396 397 static const struct dcn_dpp_mask tf_mask = { 398 TF_REG_LIST_SH_MASK_DCN10(_MASK), 399 TF_DEBUG_REG_LIST_MASK_DCN10 400 }; 401 402 static const struct dcn_mpc_registers mpc_regs = { 403 MPC_COMMON_REG_LIST_DCN1_0(0), 404 MPC_COMMON_REG_LIST_DCN1_0(1), 405 MPC_COMMON_REG_LIST_DCN1_0(2), 406 MPC_COMMON_REG_LIST_DCN1_0(3), 407 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 408 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 409 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 410 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 411 }; 412 413 static const struct dcn_mpc_shift mpc_shift = { 414 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 415 }; 416 417 static const struct dcn_mpc_mask mpc_mask = { 418 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 419 }; 420 421 #define tg_regs(id)\ 422 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 423 424 static const struct dcn_optc_registers tg_regs[] = { 425 tg_regs(0), 426 tg_regs(1), 427 tg_regs(2), 428 tg_regs(3), 429 }; 430 431 static const struct dcn_optc_shift tg_shift = { 432 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 433 }; 434 435 static const struct dcn_optc_mask tg_mask = { 436 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 437 }; 438 439 440 static const struct bios_registers bios_regs = { 441 NBIO_SR(BIOS_SCRATCH_0), 442 NBIO_SR(BIOS_SCRATCH_3), 443 NBIO_SR(BIOS_SCRATCH_6) 444 }; 445 446 #define hubp_regs(id)\ 447 [id] = {\ 448 HUBP_REG_LIST_DCN10(id)\ 449 } 450 451 452 static const struct dcn_mi_registers hubp_regs[] = { 453 hubp_regs(0), 454 hubp_regs(1), 455 hubp_regs(2), 456 hubp_regs(3), 457 }; 458 459 static const struct dcn_mi_shift hubp_shift = { 460 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 461 }; 462 463 static const struct dcn_mi_mask hubp_mask = { 464 HUBP_MASK_SH_LIST_DCN10(_MASK) 465 }; 466 467 468 static const struct dcn_hubbub_registers hubbub_reg = { 469 HUBBUB_REG_LIST_DCN10(0) 470 }; 471 472 static const struct dcn_hubbub_shift hubbub_shift = { 473 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 474 }; 475 476 static const struct dcn_hubbub_mask hubbub_mask = { 477 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 478 }; 479 480 #define clk_src_regs(index, pllid)\ 481 [index] = {\ 482 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 483 } 484 485 static const struct dce110_clk_src_regs clk_src_regs[] = { 486 clk_src_regs(0, A), 487 clk_src_regs(1, B), 488 clk_src_regs(2, C), 489 clk_src_regs(3, D) 490 }; 491 492 static const struct dce110_clk_src_shift cs_shift = { 493 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 494 }; 495 496 static const struct dce110_clk_src_mask cs_mask = { 497 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 498 }; 499 500 501 static const struct resource_caps res_cap = { 502 .num_timing_generator = 4, 503 .num_opp = 4, 504 .num_video_plane = 4, 505 .num_audio = 4, 506 .num_stream_encoder = 4, 507 .num_pll = 4, 508 .num_ddc = 4, 509 }; 510 511 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 512 static const struct resource_caps rv2_res_cap = { 513 .num_timing_generator = 3, 514 .num_opp = 3, 515 .num_video_plane = 3, 516 .num_audio = 3, 517 .num_stream_encoder = 3, 518 .num_pll = 3, 519 .num_ddc = 3, 520 }; 521 #endif 522 523 static const struct dc_debug_options debug_defaults_drv = { 524 .sanity_checks = true, 525 .disable_dmcu = true, 526 .force_abm_enable = false, 527 .timing_trace = false, 528 .clock_trace = true, 529 530 /* raven smu dones't allow 0 disp clk, 531 * smu min disp clk limit is 50Mhz 532 * keep min disp clk 100Mhz avoid smu hang 533 */ 534 .min_disp_clk_khz = 100000, 535 536 .disable_pplib_clock_request = false, 537 .disable_pplib_wm_range = false, 538 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 539 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 540 .force_single_disp_pipe_split = true, 541 .disable_dcc = DCC_ENABLE, 542 .voltage_align_fclk = true, 543 .disable_stereo_support = true, 544 .vsr_support = true, 545 .performance_trace = false, 546 .az_endpoint_mute_only = true, 547 .recovery_enabled = false, /*enable this by default after testing.*/ 548 .max_downscale_src_width = 3840, 549 }; 550 551 static const struct dc_debug_options debug_defaults_diags = { 552 .disable_dmcu = true, 553 .force_abm_enable = false, 554 .timing_trace = true, 555 .clock_trace = true, 556 .disable_stutter = true, 557 .disable_pplib_clock_request = true, 558 .disable_pplib_wm_range = true 559 }; 560 561 static void dcn10_dpp_destroy(struct dpp **dpp) 562 { 563 kfree(TO_DCN10_DPP(*dpp)); 564 *dpp = NULL; 565 } 566 567 static struct dpp *dcn10_dpp_create( 568 struct dc_context *ctx, 569 uint32_t inst) 570 { 571 struct dcn10_dpp *dpp = 572 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 573 574 if (!dpp) 575 return NULL; 576 577 dpp1_construct(dpp, ctx, inst, 578 &tf_regs[inst], &tf_shift, &tf_mask); 579 return &dpp->base; 580 } 581 582 static struct input_pixel_processor *dcn10_ipp_create( 583 struct dc_context *ctx, uint32_t inst) 584 { 585 struct dcn10_ipp *ipp = 586 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 587 588 if (!ipp) { 589 BREAK_TO_DEBUGGER(); 590 return NULL; 591 } 592 593 dcn10_ipp_construct(ipp, ctx, inst, 594 &ipp_regs[inst], &ipp_shift, &ipp_mask); 595 return &ipp->base; 596 } 597 598 599 static struct output_pixel_processor *dcn10_opp_create( 600 struct dc_context *ctx, uint32_t inst) 601 { 602 struct dcn10_opp *opp = 603 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 604 605 if (!opp) { 606 BREAK_TO_DEBUGGER(); 607 return NULL; 608 } 609 610 dcn10_opp_construct(opp, ctx, inst, 611 &opp_regs[inst], &opp_shift, &opp_mask); 612 return &opp->base; 613 } 614 615 struct aux_engine *dcn10_aux_engine_create( 616 struct dc_context *ctx, 617 uint32_t inst) 618 { 619 struct aux_engine_dce110 *aux_engine = 620 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 621 622 if (!aux_engine) 623 return NULL; 624 625 dce110_aux_engine_construct(aux_engine, ctx, inst, 626 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 627 &aux_engine_regs[inst]); 628 629 return &aux_engine->base; 630 } 631 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 632 633 static const struct dce_i2c_registers i2c_hw_regs[] = { 634 i2c_inst_regs(1), 635 i2c_inst_regs(2), 636 i2c_inst_regs(3), 637 i2c_inst_regs(4), 638 i2c_inst_regs(5), 639 i2c_inst_regs(6), 640 }; 641 642 static const struct dce_i2c_shift i2c_shifts = { 643 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 644 }; 645 646 static const struct dce_i2c_mask i2c_masks = { 647 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 648 }; 649 650 struct dce_i2c_hw *dcn10_i2c_hw_create( 651 struct dc_context *ctx, 652 uint32_t inst) 653 { 654 struct dce_i2c_hw *dce_i2c_hw = 655 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 656 657 if (!dce_i2c_hw) 658 return NULL; 659 660 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 661 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 662 663 return dce_i2c_hw; 664 } 665 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 666 { 667 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 668 GFP_KERNEL); 669 670 if (!mpc10) 671 return NULL; 672 673 dcn10_mpc_construct(mpc10, ctx, 674 &mpc_regs, 675 &mpc_shift, 676 &mpc_mask, 677 4); 678 679 return &mpc10->base; 680 } 681 682 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 683 { 684 struct hubbub *hubbub = kzalloc(sizeof(struct hubbub), 685 GFP_KERNEL); 686 687 if (!hubbub) 688 return NULL; 689 690 hubbub1_construct(hubbub, ctx, 691 &hubbub_reg, 692 &hubbub_shift, 693 &hubbub_mask); 694 695 return hubbub; 696 } 697 698 static struct timing_generator *dcn10_timing_generator_create( 699 struct dc_context *ctx, 700 uint32_t instance) 701 { 702 struct optc *tgn10 = 703 kzalloc(sizeof(struct optc), GFP_KERNEL); 704 705 if (!tgn10) 706 return NULL; 707 708 tgn10->base.inst = instance; 709 tgn10->base.ctx = ctx; 710 711 tgn10->tg_regs = &tg_regs[instance]; 712 tgn10->tg_shift = &tg_shift; 713 tgn10->tg_mask = &tg_mask; 714 715 dcn10_timing_generator_init(tgn10); 716 717 return &tgn10->base; 718 } 719 720 static const struct encoder_feature_support link_enc_feature = { 721 .max_hdmi_deep_color = COLOR_DEPTH_121212, 722 .max_hdmi_pixel_clock = 600000, 723 .hdmi_ycbcr420_supported = true, 724 .dp_ycbcr420_supported = false, 725 .flags.bits.IS_HBR2_CAPABLE = true, 726 .flags.bits.IS_HBR3_CAPABLE = true, 727 .flags.bits.IS_TPS3_CAPABLE = true, 728 .flags.bits.IS_TPS4_CAPABLE = true 729 }; 730 731 struct link_encoder *dcn10_link_encoder_create( 732 const struct encoder_init_data *enc_init_data) 733 { 734 struct dcn10_link_encoder *enc10 = 735 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 736 737 if (!enc10) 738 return NULL; 739 740 dcn10_link_encoder_construct(enc10, 741 enc_init_data, 742 &link_enc_feature, 743 &link_enc_regs[enc_init_data->transmitter], 744 &link_enc_aux_regs[enc_init_data->channel - 1], 745 &link_enc_hpd_regs[enc_init_data->hpd_source], 746 &le_shift, 747 &le_mask); 748 749 return &enc10->base; 750 } 751 752 struct clock_source *dcn10_clock_source_create( 753 struct dc_context *ctx, 754 struct dc_bios *bios, 755 enum clock_source_id id, 756 const struct dce110_clk_src_regs *regs, 757 bool dp_clk_src) 758 { 759 struct dce110_clk_src *clk_src = 760 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 761 762 if (!clk_src) 763 return NULL; 764 765 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 766 regs, &cs_shift, &cs_mask)) { 767 clk_src->base.dp_clk_src = dp_clk_src; 768 return &clk_src->base; 769 } 770 771 BREAK_TO_DEBUGGER(); 772 return NULL; 773 } 774 775 static void read_dce_straps( 776 struct dc_context *ctx, 777 struct resource_straps *straps) 778 { 779 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 780 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 781 } 782 783 static struct audio *create_audio( 784 struct dc_context *ctx, unsigned int inst) 785 { 786 return dce_audio_create(ctx, inst, 787 &audio_regs[inst], &audio_shift, &audio_mask); 788 } 789 790 static struct stream_encoder *dcn10_stream_encoder_create( 791 enum engine_id eng_id, 792 struct dc_context *ctx) 793 { 794 struct dcn10_stream_encoder *enc1 = 795 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 796 797 if (!enc1) 798 return NULL; 799 800 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 801 &stream_enc_regs[eng_id], 802 &se_shift, &se_mask); 803 return &enc1->base; 804 } 805 806 static const struct dce_hwseq_registers hwseq_reg = { 807 HWSEQ_DCN1_REG_LIST() 808 }; 809 810 static const struct dce_hwseq_shift hwseq_shift = { 811 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 812 }; 813 814 static const struct dce_hwseq_mask hwseq_mask = { 815 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 816 }; 817 818 static struct dce_hwseq *dcn10_hwseq_create( 819 struct dc_context *ctx) 820 { 821 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 822 823 if (hws) { 824 hws->ctx = ctx; 825 hws->regs = &hwseq_reg; 826 hws->shifts = &hwseq_shift; 827 hws->masks = &hwseq_mask; 828 hws->wa.DEGVIDCN10_253 = true; 829 hws->wa.false_optc_underflow = true; 830 hws->wa.DEGVIDCN10_254 = true; 831 } 832 return hws; 833 } 834 835 static const struct resource_create_funcs res_create_funcs = { 836 .read_dce_straps = read_dce_straps, 837 .create_audio = create_audio, 838 .create_stream_encoder = dcn10_stream_encoder_create, 839 .create_hwseq = dcn10_hwseq_create, 840 }; 841 842 static const struct resource_create_funcs res_create_maximus_funcs = { 843 .read_dce_straps = NULL, 844 .create_audio = NULL, 845 .create_stream_encoder = NULL, 846 .create_hwseq = dcn10_hwseq_create, 847 }; 848 849 void dcn10_clock_source_destroy(struct clock_source **clk_src) 850 { 851 kfree(TO_DCE110_CLK_SRC(*clk_src)); 852 *clk_src = NULL; 853 } 854 855 static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) 856 { 857 struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 858 859 if (!pp_smu) 860 return pp_smu; 861 862 dm_pp_get_funcs_rv(ctx, pp_smu); 863 return pp_smu; 864 } 865 866 static void destruct(struct dcn10_resource_pool *pool) 867 { 868 unsigned int i; 869 870 for (i = 0; i < pool->base.stream_enc_count; i++) { 871 if (pool->base.stream_enc[i] != NULL) { 872 /* TODO: free dcn version of stream encoder once implemented 873 * rather than using virtual stream encoder 874 */ 875 kfree(pool->base.stream_enc[i]); 876 pool->base.stream_enc[i] = NULL; 877 } 878 } 879 880 if (pool->base.mpc != NULL) { 881 kfree(TO_DCN10_MPC(pool->base.mpc)); 882 pool->base.mpc = NULL; 883 } 884 885 if (pool->base.hubbub != NULL) { 886 kfree(pool->base.hubbub); 887 pool->base.hubbub = NULL; 888 } 889 890 for (i = 0; i < pool->base.pipe_count; i++) { 891 if (pool->base.opps[i] != NULL) 892 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 893 894 if (pool->base.dpps[i] != NULL) 895 dcn10_dpp_destroy(&pool->base.dpps[i]); 896 897 if (pool->base.ipps[i] != NULL) 898 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 899 900 if (pool->base.hubps[i] != NULL) { 901 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 902 pool->base.hubps[i] = NULL; 903 } 904 905 if (pool->base.irqs != NULL) { 906 dal_irq_service_destroy(&pool->base.irqs); 907 } 908 909 if (pool->base.timing_generators[i] != NULL) { 910 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 911 pool->base.timing_generators[i] = NULL; 912 } 913 } 914 915 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 916 if (pool->base.engines[i] != NULL) 917 pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]); 918 if (pool->base.hw_i2cs[i] != NULL) { 919 kfree(pool->base.hw_i2cs[i]); 920 pool->base.hw_i2cs[i] = NULL; 921 } 922 if (pool->base.sw_i2cs[i] != NULL) { 923 kfree(pool->base.sw_i2cs[i]); 924 pool->base.sw_i2cs[i] = NULL; 925 } 926 } 927 928 for (i = 0; i < pool->base.stream_enc_count; i++) 929 kfree(pool->base.stream_enc[i]); 930 931 for (i = 0; i < pool->base.audio_count; i++) { 932 if (pool->base.audios[i]) 933 dce_aud_destroy(&pool->base.audios[i]); 934 } 935 936 for (i = 0; i < pool->base.clk_src_count; i++) { 937 if (pool->base.clock_sources[i] != NULL) { 938 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 939 pool->base.clock_sources[i] = NULL; 940 } 941 } 942 943 if (pool->base.dp_clock_source != NULL) { 944 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 945 pool->base.dp_clock_source = NULL; 946 } 947 948 if (pool->base.abm != NULL) 949 dce_abm_destroy(&pool->base.abm); 950 951 if (pool->base.dmcu != NULL) 952 dce_dmcu_destroy(&pool->base.dmcu); 953 954 if (pool->base.clk_mgr != NULL) 955 dce_clk_mgr_destroy(&pool->base.clk_mgr); 956 957 kfree(pool->base.pp_smu); 958 } 959 960 static struct hubp *dcn10_hubp_create( 961 struct dc_context *ctx, 962 uint32_t inst) 963 { 964 struct dcn10_hubp *hubp1 = 965 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 966 967 if (!hubp1) 968 return NULL; 969 970 dcn10_hubp_construct(hubp1, ctx, inst, 971 &hubp_regs[inst], &hubp_shift, &hubp_mask); 972 return &hubp1->base; 973 } 974 975 static void get_pixel_clock_parameters( 976 const struct pipe_ctx *pipe_ctx, 977 struct pixel_clk_params *pixel_clk_params) 978 { 979 const struct dc_stream_state *stream = pipe_ctx->stream; 980 pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; 981 pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; 982 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 983 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 984 /* TODO: un-hardcode*/ 985 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 986 LINK_RATE_REF_FREQ_IN_KHZ; 987 pixel_clk_params->flags.ENABLE_SS = 0; 988 pixel_clk_params->color_depth = 989 stream->timing.display_color_depth; 990 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 991 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 992 993 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 994 pixel_clk_params->color_depth = COLOR_DEPTH_888; 995 996 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 997 pixel_clk_params->requested_pix_clk /= 2; 998 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 999 pixel_clk_params->requested_pix_clk *= 2; 1000 1001 } 1002 1003 static void build_clamping_params(struct dc_stream_state *stream) 1004 { 1005 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1006 stream->clamping.c_depth = stream->timing.display_color_depth; 1007 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1008 } 1009 1010 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1011 { 1012 1013 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1014 1015 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1016 pipe_ctx->clock_source, 1017 &pipe_ctx->stream_res.pix_clk_params, 1018 &pipe_ctx->pll_settings); 1019 1020 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1021 1022 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1023 &pipe_ctx->stream->bit_depth_params); 1024 build_clamping_params(pipe_ctx->stream); 1025 } 1026 1027 static enum dc_status build_mapped_resource( 1028 const struct dc *dc, 1029 struct dc_state *context, 1030 struct dc_stream_state *stream) 1031 { 1032 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1033 1034 /*TODO Seems unneeded anymore */ 1035 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1036 if (stream != NULL && old_context->streams[i] != NULL) { 1037 todo: shouldn't have to copy missing parameter here 1038 resource_build_bit_depth_reduction_params(stream, 1039 &stream->bit_depth_params); 1040 stream->clamping.pixel_encoding = 1041 stream->timing.pixel_encoding; 1042 1043 resource_build_bit_depth_reduction_params(stream, 1044 &stream->bit_depth_params); 1045 build_clamping_params(stream); 1046 1047 continue; 1048 } 1049 } 1050 */ 1051 1052 if (!pipe_ctx) 1053 return DC_ERROR_UNEXPECTED; 1054 1055 build_pipe_hw_param(pipe_ctx); 1056 return DC_OK; 1057 } 1058 1059 enum dc_status dcn10_add_stream_to_ctx( 1060 struct dc *dc, 1061 struct dc_state *new_ctx, 1062 struct dc_stream_state *dc_stream) 1063 { 1064 enum dc_status result = DC_ERROR_UNEXPECTED; 1065 1066 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1067 1068 if (result == DC_OK) 1069 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1070 1071 1072 if (result == DC_OK) 1073 result = build_mapped_resource(dc, new_ctx, dc_stream); 1074 1075 return result; 1076 } 1077 1078 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1079 struct dc_state *context, 1080 const struct resource_pool *pool, 1081 struct dc_stream_state *stream) 1082 { 1083 struct resource_context *res_ctx = &context->res_ctx; 1084 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1085 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool); 1086 1087 if (!head_pipe) { 1088 ASSERT(0); 1089 return NULL; 1090 } 1091 1092 if (!idle_pipe) 1093 return NULL; 1094 1095 idle_pipe->stream = head_pipe->stream; 1096 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1097 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1098 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1099 1100 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1101 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1102 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1103 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1104 1105 return idle_pipe; 1106 } 1107 1108 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1109 const struct dc_dcc_surface_param *input, 1110 struct dc_surface_dcc_cap *output) 1111 { 1112 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1113 dc->res_pool->hubbub, 1114 input, 1115 output); 1116 } 1117 1118 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1119 { 1120 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1121 1122 destruct(dcn10_pool); 1123 kfree(dcn10_pool); 1124 *pool = NULL; 1125 } 1126 1127 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1128 { 1129 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1130 && caps->max_video_width != 0 1131 && plane_state->src_rect.width > caps->max_video_width) 1132 return DC_FAIL_SURFACE_VALIDATE; 1133 1134 return DC_OK; 1135 } 1136 1137 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1138 { 1139 enum dc_status result = DC_OK; 1140 1141 enum surface_pixel_format surf_pix_format = plane_state->format; 1142 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1143 1144 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1145 1146 if (bpp == 64) 1147 swizzle = DC_SW_64KB_D; 1148 else 1149 swizzle = DC_SW_64KB_S; 1150 1151 plane_state->tiling_info.gfx9.swizzle = swizzle; 1152 return result; 1153 } 1154 1155 static const struct dc_cap_funcs cap_funcs = { 1156 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1157 }; 1158 1159 static const struct resource_funcs dcn10_res_pool_funcs = { 1160 .destroy = dcn10_destroy_resource_pool, 1161 .link_enc_create = dcn10_link_encoder_create, 1162 .validate_bandwidth = dcn_validate_bandwidth, 1163 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1164 .validate_plane = dcn10_validate_plane, 1165 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1166 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode 1167 }; 1168 1169 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1170 { 1171 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1172 /* RV1 support max 4 pipes */ 1173 value = value & 0xf; 1174 return value; 1175 } 1176 1177 static bool construct( 1178 uint8_t num_virtual_links, 1179 struct dc *dc, 1180 struct dcn10_resource_pool *pool) 1181 { 1182 int i; 1183 int j; 1184 struct dc_context *ctx = dc->ctx; 1185 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1186 1187 ctx->dc_bios->regs = &bios_regs; 1188 1189 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1190 if (ctx->dce_version == DCN_VERSION_1_01) 1191 pool->base.res_cap = &rv2_res_cap; 1192 else 1193 #endif 1194 pool->base.res_cap = &res_cap; 1195 pool->base.funcs = &dcn10_res_pool_funcs; 1196 1197 /* 1198 * TODO fill in from actual raven resource when we create 1199 * more than virtual encoder 1200 */ 1201 1202 /************************************************* 1203 * Resource + asic cap harcoding * 1204 *************************************************/ 1205 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1206 1207 /* max pipe num for ASIC before check pipe fuses */ 1208 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1209 1210 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1211 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1212 pool->base.pipe_count = 3; 1213 #endif 1214 dc->caps.max_video_width = 3840; 1215 dc->caps.max_downscale_ratio = 200; 1216 dc->caps.i2c_speed_in_khz = 100; 1217 dc->caps.max_cursor_size = 256; 1218 dc->caps.max_slave_planes = 1; 1219 dc->caps.is_apu = true; 1220 dc->caps.post_blend_color_processing = false; 1221 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1222 dc->caps.force_dp_tps4_for_cp2520 = true; 1223 1224 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1225 dc->debug = debug_defaults_drv; 1226 else 1227 dc->debug = debug_defaults_diags; 1228 1229 /************************************************* 1230 * Create resources * 1231 *************************************************/ 1232 1233 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1234 dcn10_clock_source_create(ctx, ctx->dc_bios, 1235 CLOCK_SOURCE_COMBO_PHY_PLL0, 1236 &clk_src_regs[0], false); 1237 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1238 dcn10_clock_source_create(ctx, ctx->dc_bios, 1239 CLOCK_SOURCE_COMBO_PHY_PLL1, 1240 &clk_src_regs[1], false); 1241 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1242 dcn10_clock_source_create(ctx, ctx->dc_bios, 1243 CLOCK_SOURCE_COMBO_PHY_PLL2, 1244 &clk_src_regs[2], false); 1245 1246 #ifdef CONFIG_DRM_AMD_DC_DCN1_01 1247 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1248 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1249 dcn10_clock_source_create(ctx, ctx->dc_bios, 1250 CLOCK_SOURCE_COMBO_PHY_PLL3, 1251 &clk_src_regs[3], false); 1252 } 1253 #else 1254 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1255 dcn10_clock_source_create(ctx, ctx->dc_bios, 1256 CLOCK_SOURCE_COMBO_PHY_PLL3, 1257 &clk_src_regs[3], false); 1258 #endif 1259 1260 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1261 1262 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1263 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1264 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1265 #endif 1266 1267 pool->base.dp_clock_source = 1268 dcn10_clock_source_create(ctx, ctx->dc_bios, 1269 CLOCK_SOURCE_ID_DP_DTO, 1270 /* todo: not reuse phy_pll registers */ 1271 &clk_src_regs[0], true); 1272 1273 for (i = 0; i < pool->base.clk_src_count; i++) { 1274 if (pool->base.clock_sources[i] == NULL) { 1275 dm_error("DC: failed to create clock sources!\n"); 1276 BREAK_TO_DEBUGGER(); 1277 goto fail; 1278 } 1279 } 1280 1281 pool->base.clk_mgr = dcn1_clk_mgr_create(ctx); 1282 if (pool->base.clk_mgr == NULL) { 1283 dm_error("DC: failed to create display clock!\n"); 1284 BREAK_TO_DEBUGGER(); 1285 goto fail; 1286 } 1287 1288 pool->base.dmcu = dcn10_dmcu_create(ctx, 1289 &dmcu_regs, 1290 &dmcu_shift, 1291 &dmcu_mask); 1292 if (pool->base.dmcu == NULL) { 1293 dm_error("DC: failed to create dmcu!\n"); 1294 BREAK_TO_DEBUGGER(); 1295 goto fail; 1296 } 1297 1298 pool->base.abm = dce_abm_create(ctx, 1299 &abm_regs, 1300 &abm_shift, 1301 &abm_mask); 1302 if (pool->base.abm == NULL) { 1303 dm_error("DC: failed to create abm!\n"); 1304 BREAK_TO_DEBUGGER(); 1305 goto fail; 1306 } 1307 1308 dml_init_instance(&dc->dml, DML_PROJECT_RAVEN1); 1309 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1310 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1311 1312 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1313 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1314 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1315 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1316 struct display_mode_lib *dml = &dc->dml; 1317 1318 dml->ip.max_num_dpp = 3; 1319 /* TODO how to handle 23.84? */ 1320 dcn_soc->dram_clock_change_latency = 23; 1321 dcn_ip->max_num_dpp = 3; 1322 } 1323 #endif 1324 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1325 dc->dcn_soc->urgent_latency = 3; 1326 dc->debug.disable_dmcu = true; 1327 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1328 } 1329 1330 1331 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1332 ASSERT(dc->dcn_soc->number_of_channels < 3); 1333 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1334 dc->dcn_soc->number_of_channels = 2; 1335 1336 if (dc->dcn_soc->number_of_channels == 1) { 1337 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1338 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1339 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1340 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1341 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1342 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1343 } 1344 } 1345 1346 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1347 1348 if (!dc->debug.disable_pplib_clock_request) 1349 dcn_bw_update_from_pplib(dc); 1350 dcn_bw_sync_calcs_and_dml(dc); 1351 if (!dc->debug.disable_pplib_wm_range) { 1352 dc->res_pool = &pool->base; 1353 dcn_bw_notify_pplib_of_wm_ranges(dc); 1354 } 1355 1356 { 1357 struct irq_service_init_data init_data; 1358 init_data.ctx = dc->ctx; 1359 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1360 if (!pool->base.irqs) 1361 goto fail; 1362 } 1363 1364 /* index to valid pipe resource */ 1365 j = 0; 1366 /* mem input -> ipp -> dpp -> opp -> TG */ 1367 for (i = 0; i < pool->base.pipe_count; i++) { 1368 /* if pipe is disabled, skip instance of HW pipe, 1369 * i.e, skip ASIC register instance 1370 */ 1371 if ((pipe_fuses & (1 << i)) != 0) 1372 continue; 1373 1374 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1375 if (pool->base.hubps[j] == NULL) { 1376 BREAK_TO_DEBUGGER(); 1377 dm_error( 1378 "DC: failed to create memory input!\n"); 1379 goto fail; 1380 } 1381 1382 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1383 if (pool->base.ipps[j] == NULL) { 1384 BREAK_TO_DEBUGGER(); 1385 dm_error( 1386 "DC: failed to create input pixel processor!\n"); 1387 goto fail; 1388 } 1389 1390 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1391 if (pool->base.dpps[j] == NULL) { 1392 BREAK_TO_DEBUGGER(); 1393 dm_error( 1394 "DC: failed to create dpp!\n"); 1395 goto fail; 1396 } 1397 1398 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1399 if (pool->base.opps[j] == NULL) { 1400 BREAK_TO_DEBUGGER(); 1401 dm_error( 1402 "DC: failed to create output pixel processor!\n"); 1403 goto fail; 1404 } 1405 1406 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1407 ctx, i); 1408 if (pool->base.timing_generators[j] == NULL) { 1409 BREAK_TO_DEBUGGER(); 1410 dm_error("DC: failed to create tg!\n"); 1411 goto fail; 1412 } 1413 /* check next valid pipe */ 1414 j++; 1415 } 1416 1417 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1418 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1419 if (pool->base.engines[i] == NULL) { 1420 BREAK_TO_DEBUGGER(); 1421 dm_error( 1422 "DC:failed to create aux engine!!\n"); 1423 goto fail; 1424 } 1425 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1426 if (pool->base.hw_i2cs[i] == NULL) { 1427 BREAK_TO_DEBUGGER(); 1428 dm_error( 1429 "DC:failed to create hw i2c!!\n"); 1430 goto fail; 1431 } 1432 pool->base.sw_i2cs[i] = NULL; 1433 } 1434 1435 /* valid pipe num */ 1436 pool->base.pipe_count = j; 1437 pool->base.timing_generator_count = j; 1438 1439 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1440 * the value may be changed 1441 */ 1442 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1443 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1444 1445 pool->base.mpc = dcn10_mpc_create(ctx); 1446 if (pool->base.mpc == NULL) { 1447 BREAK_TO_DEBUGGER(); 1448 dm_error("DC: failed to create mpc!\n"); 1449 goto fail; 1450 } 1451 1452 pool->base.hubbub = dcn10_hubbub_create(ctx); 1453 if (pool->base.hubbub == NULL) { 1454 BREAK_TO_DEBUGGER(); 1455 dm_error("DC: failed to create hubbub!\n"); 1456 goto fail; 1457 } 1458 1459 if (!resource_construct(num_virtual_links, dc, &pool->base, 1460 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1461 &res_create_funcs : &res_create_maximus_funcs))) 1462 goto fail; 1463 1464 dcn10_hw_sequencer_construct(dc); 1465 dc->caps.max_planes = pool->base.pipe_count; 1466 1467 dc->cap_funcs = cap_funcs; 1468 1469 return true; 1470 1471 fail: 1472 1473 destruct(pool); 1474 1475 return false; 1476 } 1477 1478 struct resource_pool *dcn10_create_resource_pool( 1479 uint8_t num_virtual_links, 1480 struct dc *dc) 1481 { 1482 struct dcn10_resource_pool *pool = 1483 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1484 1485 if (!pool) 1486 return NULL; 1487 1488 if (construct(num_virtual_links, dc, pool)) 1489 return &pool->base; 1490 1491 BREAK_TO_DEBUGGER(); 1492 return NULL; 1493 } 1494