1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 #include "dc.h"
28 
29 #include "dcn10_init.h"
30 
31 #include "resource.h"
32 #include "include/irq_service_interface.h"
33 #include "dcn10_resource.h"
34 #include "dcn10_ipp.h"
35 #include "dcn10_mpc.h"
36 #include "irq/dcn10/irq_service_dcn10.h"
37 #include "dcn10_dpp.h"
38 #include "dcn10_optc.h"
39 #include "dcn10_hw_sequencer.h"
40 #include "dce110/dce110_hw_sequencer.h"
41 #include "dcn10_opp.h"
42 #include "dcn10_link_encoder.h"
43 #include "dcn10_stream_encoder.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_audio.h"
46 #include "dce/dce_hwseq.h"
47 #include "virtual/virtual_stream_encoder.h"
48 #include "dce110/dce110_resource.h"
49 #include "dce112/dce112_resource.h"
50 #include "dcn10_hubp.h"
51 #include "dcn10_hubbub.h"
52 #include "dce/dce_panel_cntl.h"
53 
54 #include "soc15_hw_ip.h"
55 #include "vega10_ip_offset.h"
56 
57 #include "dcn/dcn_1_0_offset.h"
58 #include "dcn/dcn_1_0_sh_mask.h"
59 
60 #include "nbio/nbio_7_0_offset.h"
61 
62 #include "mmhub/mmhub_9_1_offset.h"
63 #include "mmhub/mmhub_9_1_sh_mask.h"
64 
65 #include "reg_helper.h"
66 #include "dce/dce_abm.h"
67 #include "dce/dce_dmcu.h"
68 #include "dce/dce_aux.h"
69 #include "dce/dce_i2c.h"
70 
71 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
72 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
73 	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
74 	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
75 	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
76 	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
77 	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
78 	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
79 	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
80 	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
81 	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
82 	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
83 	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
84 	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
85 	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
86 #endif
87 
88 
89 enum dcn10_clk_src_array_id {
90 	DCN10_CLK_SRC_PLL0,
91 	DCN10_CLK_SRC_PLL1,
92 	DCN10_CLK_SRC_PLL2,
93 	DCN10_CLK_SRC_PLL3,
94 	DCN10_CLK_SRC_TOTAL,
95 	DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
96 };
97 
98 /* begin *********************
99  * macros to expend register list macro defined in HW object header file */
100 
101 /* DCN */
102 #define BASE_INNER(seg) \
103 	DCE_BASE__INST0_SEG ## seg
104 
105 #define BASE(seg) \
106 	BASE_INNER(seg)
107 
108 #define SR(reg_name)\
109 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
110 					mm ## reg_name
111 
112 #define SRI(reg_name, block, id)\
113 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
114 					mm ## block ## id ## _ ## reg_name
115 
116 
117 #define SRII(reg_name, block, id)\
118 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
119 					mm ## block ## id ## _ ## reg_name
120 
121 #define VUPDATE_SRII(reg_name, block, id)\
122 	.reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
123 					mm ## reg_name ## 0 ## _ ## block ## id
124 
125 /* set field/register/bitfield name */
126 #define SFRB(field_name, reg_name, bitfield, post_fix)\
127 	.field_name = reg_name ## __ ## bitfield ## post_fix
128 
129 /* NBIO */
130 #define NBIO_BASE_INNER(seg) \
131 	NBIF_BASE__INST0_SEG ## seg
132 
133 #define NBIO_BASE(seg) \
134 	NBIO_BASE_INNER(seg)
135 
136 #define NBIO_SR(reg_name)\
137 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) +  \
138 					mm ## reg_name
139 
140 /* MMHUB */
141 #define MMHUB_BASE_INNER(seg) \
142 	MMHUB_BASE__INST0_SEG ## seg
143 
144 #define MMHUB_BASE(seg) \
145 	MMHUB_BASE_INNER(seg)
146 
147 #define MMHUB_SR(reg_name)\
148 		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) +  \
149 					mm ## reg_name
150 
151 /* macros to expend register list macro defined in HW object header file
152  * end *********************/
153 
154 
155 static const struct dce_dmcu_registers dmcu_regs = {
156 		DMCU_DCN10_REG_LIST()
157 };
158 
159 static const struct dce_dmcu_shift dmcu_shift = {
160 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
161 };
162 
163 static const struct dce_dmcu_mask dmcu_mask = {
164 		DMCU_MASK_SH_LIST_DCN10(_MASK)
165 };
166 
167 static const struct dce_abm_registers abm_regs = {
168 		ABM_DCN10_REG_LIST(0)
169 };
170 
171 static const struct dce_abm_shift abm_shift = {
172 		ABM_MASK_SH_LIST_DCN10(__SHIFT)
173 };
174 
175 static const struct dce_abm_mask abm_mask = {
176 		ABM_MASK_SH_LIST_DCN10(_MASK)
177 };
178 
179 #define stream_enc_regs(id)\
180 [id] = {\
181 	SE_DCN_REG_LIST(id)\
182 }
183 
184 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
185 	stream_enc_regs(0),
186 	stream_enc_regs(1),
187 	stream_enc_regs(2),
188 	stream_enc_regs(3),
189 };
190 
191 static const struct dcn10_stream_encoder_shift se_shift = {
192 		SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
193 };
194 
195 static const struct dcn10_stream_encoder_mask se_mask = {
196 		SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
197 };
198 
199 #define audio_regs(id)\
200 [id] = {\
201 		AUD_COMMON_REG_LIST(id)\
202 }
203 
204 static const struct dce_audio_registers audio_regs[] = {
205 	audio_regs(0),
206 	audio_regs(1),
207 	audio_regs(2),
208 	audio_regs(3),
209 };
210 
211 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
212 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
213 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
214 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
215 
216 static const struct dce_audio_shift audio_shift = {
217 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
218 };
219 
220 static const struct dce_audio_mask audio_mask = {
221 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
222 };
223 
224 #define aux_regs(id)\
225 [id] = {\
226 	AUX_REG_LIST(id)\
227 }
228 
229 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
230 		aux_regs(0),
231 		aux_regs(1),
232 		aux_regs(2),
233 		aux_regs(3)
234 };
235 
236 #define hpd_regs(id)\
237 [id] = {\
238 	HPD_REG_LIST(id)\
239 }
240 
241 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
242 		hpd_regs(0),
243 		hpd_regs(1),
244 		hpd_regs(2),
245 		hpd_regs(3)
246 };
247 
248 #define link_regs(id)\
249 [id] = {\
250 	LE_DCN10_REG_LIST(id), \
251 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
252 }
253 
254 static const struct dcn10_link_enc_registers link_enc_regs[] = {
255 	link_regs(0),
256 	link_regs(1),
257 	link_regs(2),
258 	link_regs(3)
259 };
260 
261 static const struct dcn10_link_enc_shift le_shift = {
262 		LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
263 };
264 
265 static const struct dcn10_link_enc_mask le_mask = {
266 		LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
267 };
268 
269 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
270 	{ DCN_PANEL_CNTL_REG_LIST() }
271 };
272 
273 static const struct dce_panel_cntl_shift panel_cntl_shift = {
274 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
275 };
276 
277 static const struct dce_panel_cntl_mask panel_cntl_mask = {
278 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
279 };
280 
281 static const struct dce110_aux_registers_shift aux_shift = {
282 	DCN10_AUX_MASK_SH_LIST(__SHIFT)
283 };
284 
285 static const struct dce110_aux_registers_mask aux_mask = {
286 	DCN10_AUX_MASK_SH_LIST(_MASK)
287 };
288 
289 #define ipp_regs(id)\
290 [id] = {\
291 	IPP_REG_LIST_DCN10(id),\
292 }
293 
294 static const struct dcn10_ipp_registers ipp_regs[] = {
295 	ipp_regs(0),
296 	ipp_regs(1),
297 	ipp_regs(2),
298 	ipp_regs(3),
299 };
300 
301 static const struct dcn10_ipp_shift ipp_shift = {
302 		IPP_MASK_SH_LIST_DCN10(__SHIFT)
303 };
304 
305 static const struct dcn10_ipp_mask ipp_mask = {
306 		IPP_MASK_SH_LIST_DCN10(_MASK),
307 };
308 
309 #define opp_regs(id)\
310 [id] = {\
311 	OPP_REG_LIST_DCN10(id),\
312 }
313 
314 static const struct dcn10_opp_registers opp_regs[] = {
315 	opp_regs(0),
316 	opp_regs(1),
317 	opp_regs(2),
318 	opp_regs(3),
319 };
320 
321 static const struct dcn10_opp_shift opp_shift = {
322 		OPP_MASK_SH_LIST_DCN10(__SHIFT)
323 };
324 
325 static const struct dcn10_opp_mask opp_mask = {
326 		OPP_MASK_SH_LIST_DCN10(_MASK),
327 };
328 
329 #define aux_engine_regs(id)\
330 [id] = {\
331 	AUX_COMMON_REG_LIST(id), \
332 	.AUX_RESET_MASK = 0 \
333 }
334 
335 static const struct dce110_aux_registers aux_engine_regs[] = {
336 		aux_engine_regs(0),
337 		aux_engine_regs(1),
338 		aux_engine_regs(2),
339 		aux_engine_regs(3),
340 		aux_engine_regs(4),
341 		aux_engine_regs(5)
342 };
343 
344 #define tf_regs(id)\
345 [id] = {\
346 	TF_REG_LIST_DCN10(id),\
347 }
348 
349 static const struct dcn_dpp_registers tf_regs[] = {
350 	tf_regs(0),
351 	tf_regs(1),
352 	tf_regs(2),
353 	tf_regs(3),
354 };
355 
356 static const struct dcn_dpp_shift tf_shift = {
357 	TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
358 	TF_DEBUG_REG_LIST_SH_DCN10
359 
360 };
361 
362 static const struct dcn_dpp_mask tf_mask = {
363 	TF_REG_LIST_SH_MASK_DCN10(_MASK),
364 	TF_DEBUG_REG_LIST_MASK_DCN10
365 };
366 
367 static const struct dcn_mpc_registers mpc_regs = {
368 		MPC_COMMON_REG_LIST_DCN1_0(0),
369 		MPC_COMMON_REG_LIST_DCN1_0(1),
370 		MPC_COMMON_REG_LIST_DCN1_0(2),
371 		MPC_COMMON_REG_LIST_DCN1_0(3),
372 		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0),
373 		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1),
374 		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2),
375 		MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3)
376 };
377 
378 static const struct dcn_mpc_shift mpc_shift = {
379 	MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\
380 	SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT)
381 };
382 
383 static const struct dcn_mpc_mask mpc_mask = {
384 	MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\
385 	SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK)
386 };
387 
388 #define tg_regs(id)\
389 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
390 
391 static const struct dcn_optc_registers tg_regs[] = {
392 	tg_regs(0),
393 	tg_regs(1),
394 	tg_regs(2),
395 	tg_regs(3),
396 };
397 
398 static const struct dcn_optc_shift tg_shift = {
399 	TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
400 };
401 
402 static const struct dcn_optc_mask tg_mask = {
403 	TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
404 };
405 
406 static const struct bios_registers bios_regs = {
407 		NBIO_SR(BIOS_SCRATCH_3),
408 		NBIO_SR(BIOS_SCRATCH_6)
409 };
410 
411 #define hubp_regs(id)\
412 [id] = {\
413 	HUBP_REG_LIST_DCN10(id)\
414 }
415 
416 static const struct dcn_mi_registers hubp_regs[] = {
417 	hubp_regs(0),
418 	hubp_regs(1),
419 	hubp_regs(2),
420 	hubp_regs(3),
421 };
422 
423 static const struct dcn_mi_shift hubp_shift = {
424 		HUBP_MASK_SH_LIST_DCN10(__SHIFT)
425 };
426 
427 static const struct dcn_mi_mask hubp_mask = {
428 		HUBP_MASK_SH_LIST_DCN10(_MASK)
429 };
430 
431 static const struct dcn_hubbub_registers hubbub_reg = {
432 		HUBBUB_REG_LIST_DCN10(0)
433 };
434 
435 static const struct dcn_hubbub_shift hubbub_shift = {
436 		HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)
437 };
438 
439 static const struct dcn_hubbub_mask hubbub_mask = {
440 		HUBBUB_MASK_SH_LIST_DCN10(_MASK)
441 };
442 
443 static int map_transmitter_id_to_phy_instance(
444 	enum transmitter transmitter)
445 {
446 	switch (transmitter) {
447 	case TRANSMITTER_UNIPHY_A:
448 		return 0;
449 	break;
450 	case TRANSMITTER_UNIPHY_B:
451 		return 1;
452 	break;
453 	case TRANSMITTER_UNIPHY_C:
454 		return 2;
455 	break;
456 	case TRANSMITTER_UNIPHY_D:
457 		return 3;
458 	break;
459 	default:
460 		ASSERT(0);
461 		return 0;
462 	}
463 }
464 
465 #define clk_src_regs(index, pllid)\
466 [index] = {\
467 	CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
468 }
469 
470 static const struct dce110_clk_src_regs clk_src_regs[] = {
471 	clk_src_regs(0, A),
472 	clk_src_regs(1, B),
473 	clk_src_regs(2, C),
474 	clk_src_regs(3, D)
475 };
476 
477 static const struct dce110_clk_src_shift cs_shift = {
478 		CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
479 };
480 
481 static const struct dce110_clk_src_mask cs_mask = {
482 		CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
483 };
484 
485 static const struct resource_caps res_cap = {
486 		.num_timing_generator = 4,
487 		.num_opp = 4,
488 		.num_video_plane = 4,
489 		.num_audio = 4,
490 		.num_stream_encoder = 4,
491 		.num_pll = 4,
492 		.num_ddc = 4,
493 };
494 
495 static const struct resource_caps rv2_res_cap = {
496 		.num_timing_generator = 3,
497 		.num_opp = 3,
498 		.num_video_plane = 3,
499 		.num_audio = 3,
500 		.num_stream_encoder = 3,
501 		.num_pll = 3,
502 		.num_ddc = 4,
503 };
504 
505 static const struct dc_plane_cap plane_cap = {
506 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
507 	.per_pixel_alpha = true,
508 
509 	.pixel_format_support = {
510 			.argb8888 = true,
511 			.nv12 = true,
512 			.fp16 = true,
513 			.p010 = true
514 	},
515 
516 	.max_upscale_factor = {
517 			.argb8888 = 16000,
518 			.nv12 = 16000,
519 			.fp16 = 1
520 	},
521 
522 	.max_downscale_factor = {
523 			.argb8888 = 250,
524 			.nv12 = 250,
525 			.fp16 = 1
526 	}
527 };
528 
529 static const struct dc_debug_options debug_defaults_drv = {
530 		.sanity_checks = true,
531 		.disable_dmcu = false,
532 		.force_abm_enable = false,
533 		.timing_trace = false,
534 		.clock_trace = true,
535 
536 		/* raven smu dones't allow 0 disp clk,
537 		 * smu min disp clk limit is 50Mhz
538 		 * keep min disp clk 100Mhz avoid smu hang
539 		 */
540 		.min_disp_clk_khz = 100000,
541 
542 		.disable_pplib_clock_request = false,
543 		.disable_pplib_wm_range = false,
544 		.pplib_wm_report_mode = WM_REPORT_DEFAULT,
545 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
546 		.force_single_disp_pipe_split = true,
547 		.disable_dcc = DCC_ENABLE,
548 		.voltage_align_fclk = true,
549 		.disable_stereo_support = true,
550 		.vsr_support = true,
551 		.performance_trace = false,
552 		.az_endpoint_mute_only = true,
553 		.recovery_enabled = false, /*enable this by default after testing.*/
554 		.max_downscale_src_width = 3840,
555 		.underflow_assert_delay_us = 0xFFFFFFFF,
556 		.enable_legacy_fast_update = true,
557 };
558 
559 static const struct dc_debug_options debug_defaults_diags = {
560 		.disable_dmcu = false,
561 		.force_abm_enable = false,
562 		.timing_trace = true,
563 		.clock_trace = true,
564 		.disable_stutter = true,
565 		.disable_pplib_clock_request = true,
566 		.disable_pplib_wm_range = true,
567 		.underflow_assert_delay_us = 0xFFFFFFFF,
568 };
569 
570 static void dcn10_dpp_destroy(struct dpp **dpp)
571 {
572 	kfree(TO_DCN10_DPP(*dpp));
573 	*dpp = NULL;
574 }
575 
576 static struct dpp *dcn10_dpp_create(
577 	struct dc_context *ctx,
578 	uint32_t inst)
579 {
580 	struct dcn10_dpp *dpp =
581 		kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL);
582 
583 	if (!dpp)
584 		return NULL;
585 
586 	dpp1_construct(dpp, ctx, inst,
587 		       &tf_regs[inst], &tf_shift, &tf_mask);
588 	return &dpp->base;
589 }
590 
591 static struct input_pixel_processor *dcn10_ipp_create(
592 	struct dc_context *ctx, uint32_t inst)
593 {
594 	struct dcn10_ipp *ipp =
595 		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
596 
597 	if (!ipp) {
598 		BREAK_TO_DEBUGGER();
599 		return NULL;
600 	}
601 
602 	dcn10_ipp_construct(ipp, ctx, inst,
603 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
604 	return &ipp->base;
605 }
606 
607 
608 static struct output_pixel_processor *dcn10_opp_create(
609 	struct dc_context *ctx, uint32_t inst)
610 {
611 	struct dcn10_opp *opp =
612 		kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL);
613 
614 	if (!opp) {
615 		BREAK_TO_DEBUGGER();
616 		return NULL;
617 	}
618 
619 	dcn10_opp_construct(opp, ctx, inst,
620 			&opp_regs[inst], &opp_shift, &opp_mask);
621 	return &opp->base;
622 }
623 
624 static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx,
625 					       uint32_t inst)
626 {
627 	struct aux_engine_dce110 *aux_engine =
628 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
629 
630 	if (!aux_engine)
631 		return NULL;
632 
633 	dce110_aux_engine_construct(aux_engine, ctx, inst,
634 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
635 				    &aux_engine_regs[inst],
636 					&aux_mask,
637 					&aux_shift,
638 					ctx->dc->caps.extended_aux_timeout_support);
639 
640 	return &aux_engine->base;
641 }
642 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
643 
644 static const struct dce_i2c_registers i2c_hw_regs[] = {
645 		i2c_inst_regs(1),
646 		i2c_inst_regs(2),
647 		i2c_inst_regs(3),
648 		i2c_inst_regs(4),
649 		i2c_inst_regs(5),
650 		i2c_inst_regs(6),
651 };
652 
653 static const struct dce_i2c_shift i2c_shifts = {
654 		I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
655 };
656 
657 static const struct dce_i2c_mask i2c_masks = {
658 		I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
659 };
660 
661 static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx,
662 					      uint32_t inst)
663 {
664 	struct dce_i2c_hw *dce_i2c_hw =
665 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
666 
667 	if (!dce_i2c_hw)
668 		return NULL;
669 
670 	dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst,
671 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
672 
673 	return dce_i2c_hw;
674 }
675 static struct mpc *dcn10_mpc_create(struct dc_context *ctx)
676 {
677 	struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc),
678 					  GFP_KERNEL);
679 
680 	if (!mpc10)
681 		return NULL;
682 
683 	dcn10_mpc_construct(mpc10, ctx,
684 			&mpc_regs,
685 			&mpc_shift,
686 			&mpc_mask,
687 			4);
688 
689 	return &mpc10->base;
690 }
691 
692 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)
693 {
694 	struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub),
695 					  GFP_KERNEL);
696 
697 	if (!dcn10_hubbub)
698 		return NULL;
699 
700 	hubbub1_construct(&dcn10_hubbub->base, ctx,
701 			&hubbub_reg,
702 			&hubbub_shift,
703 			&hubbub_mask);
704 
705 	return &dcn10_hubbub->base;
706 }
707 
708 static struct timing_generator *dcn10_timing_generator_create(
709 		struct dc_context *ctx,
710 		uint32_t instance)
711 {
712 	struct optc *tgn10 =
713 		kzalloc(sizeof(struct optc), GFP_KERNEL);
714 
715 	if (!tgn10)
716 		return NULL;
717 
718 	tgn10->base.inst = instance;
719 	tgn10->base.ctx = ctx;
720 
721 	tgn10->tg_regs = &tg_regs[instance];
722 	tgn10->tg_shift = &tg_shift;
723 	tgn10->tg_mask = &tg_mask;
724 
725 	dcn10_timing_generator_init(tgn10);
726 
727 	return &tgn10->base;
728 }
729 
730 static const struct encoder_feature_support link_enc_feature = {
731 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
732 		.max_hdmi_pixel_clock = 600000,
733 		.hdmi_ycbcr420_supported = true,
734 		.dp_ycbcr420_supported = true,
735 		.flags.bits.IS_HBR2_CAPABLE = true,
736 		.flags.bits.IS_HBR3_CAPABLE = true,
737 		.flags.bits.IS_TPS3_CAPABLE = true,
738 		.flags.bits.IS_TPS4_CAPABLE = true
739 };
740 
741 static struct link_encoder *dcn10_link_encoder_create(
742 	struct dc_context *ctx,
743 	const struct encoder_init_data *enc_init_data)
744 {
745 	struct dcn10_link_encoder *enc10 =
746 		kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
747 	int link_regs_id;
748 
749 	if (!enc10)
750 		return NULL;
751 
752 	link_regs_id =
753 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
754 
755 	dcn10_link_encoder_construct(enc10,
756 				      enc_init_data,
757 				      &link_enc_feature,
758 				      &link_enc_regs[link_regs_id],
759 				      &link_enc_aux_regs[enc_init_data->channel - 1],
760 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
761 				      &le_shift,
762 				      &le_mask);
763 
764 	return &enc10->base;
765 }
766 
767 static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data)
768 {
769 	struct dce_panel_cntl *panel_cntl =
770 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
771 
772 	if (!panel_cntl)
773 		return NULL;
774 
775 	dce_panel_cntl_construct(panel_cntl,
776 			init_data,
777 			&panel_cntl_regs[init_data->inst],
778 			&panel_cntl_shift,
779 			&panel_cntl_mask);
780 
781 	return &panel_cntl->base;
782 }
783 
784 static struct clock_source *dcn10_clock_source_create(
785 	struct dc_context *ctx,
786 	struct dc_bios *bios,
787 	enum clock_source_id id,
788 	const struct dce110_clk_src_regs *regs,
789 	bool dp_clk_src)
790 {
791 	struct dce110_clk_src *clk_src =
792 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
793 
794 	if (!clk_src)
795 		return NULL;
796 
797 	if (dce112_clk_src_construct(clk_src, ctx, bios, id,
798 			regs, &cs_shift, &cs_mask)) {
799 		clk_src->base.dp_clk_src = dp_clk_src;
800 		return &clk_src->base;
801 	}
802 
803 	kfree(clk_src);
804 	BREAK_TO_DEBUGGER();
805 	return NULL;
806 }
807 
808 static void read_dce_straps(
809 	struct dc_context *ctx,
810 	struct resource_straps *straps)
811 {
812 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
813 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
814 }
815 
816 static struct audio *create_audio(
817 		struct dc_context *ctx, unsigned int inst)
818 {
819 	return dce_audio_create(ctx, inst,
820 			&audio_regs[inst], &audio_shift, &audio_mask);
821 }
822 
823 static struct stream_encoder *dcn10_stream_encoder_create(
824 	enum engine_id eng_id,
825 	struct dc_context *ctx)
826 {
827 	struct dcn10_stream_encoder *enc1 =
828 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
829 
830 	if (!enc1)
831 		return NULL;
832 
833 	dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
834 					&stream_enc_regs[eng_id],
835 					&se_shift, &se_mask);
836 	return &enc1->base;
837 }
838 
839 static const struct dce_hwseq_registers hwseq_reg = {
840 		HWSEQ_DCN1_REG_LIST()
841 };
842 
843 static const struct dce_hwseq_shift hwseq_shift = {
844 		HWSEQ_DCN1_MASK_SH_LIST(__SHIFT)
845 };
846 
847 static const struct dce_hwseq_mask hwseq_mask = {
848 		HWSEQ_DCN1_MASK_SH_LIST(_MASK)
849 };
850 
851 static struct dce_hwseq *dcn10_hwseq_create(
852 	struct dc_context *ctx)
853 {
854 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
855 
856 	if (hws) {
857 		hws->ctx = ctx;
858 		hws->regs = &hwseq_reg;
859 		hws->shifts = &hwseq_shift;
860 		hws->masks = &hwseq_mask;
861 		hws->wa.DEGVIDCN10_253 = true;
862 		hws->wa.false_optc_underflow = true;
863 		hws->wa.DEGVIDCN10_254 = true;
864 
865 		if ((ctx->asic_id.chip_family == FAMILY_RV) &&
866 			ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev))
867 			switch (ctx->asic_id.pci_revision_id) {
868 			case PRID_POLLOCK_94:
869 			case PRID_POLLOCK_95:
870 			case PRID_POLLOCK_E9:
871 			case PRID_POLLOCK_EA:
872 			case PRID_POLLOCK_EB:
873 				hws->wa.wait_hubpret_read_start_during_mpo_transition = true;
874 				break;
875 			default:
876 				hws->wa.wait_hubpret_read_start_during_mpo_transition = false;
877 				break;
878 			}
879 	}
880 	return hws;
881 }
882 
883 static const struct resource_create_funcs res_create_funcs = {
884 	.read_dce_straps = read_dce_straps,
885 	.create_audio = create_audio,
886 	.create_stream_encoder = dcn10_stream_encoder_create,
887 	.create_hwseq = dcn10_hwseq_create,
888 };
889 
890 static void dcn10_clock_source_destroy(struct clock_source **clk_src)
891 {
892 	kfree(TO_DCE110_CLK_SRC(*clk_src));
893 	*clk_src = NULL;
894 }
895 
896 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx)
897 {
898 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
899 
900 	if (!pp_smu)
901 		return pp_smu;
902 
903 	dm_pp_get_funcs(ctx, pp_smu);
904 	return pp_smu;
905 }
906 
907 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool)
908 {
909 	unsigned int i;
910 
911 	for (i = 0; i < pool->base.stream_enc_count; i++) {
912 		if (pool->base.stream_enc[i] != NULL) {
913 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
914 			pool->base.stream_enc[i] = NULL;
915 		}
916 	}
917 
918 	if (pool->base.mpc != NULL) {
919 		kfree(TO_DCN10_MPC(pool->base.mpc));
920 		pool->base.mpc = NULL;
921 	}
922 
923 	kfree(pool->base.hubbub);
924 	pool->base.hubbub = NULL;
925 
926 	for (i = 0; i < pool->base.pipe_count; i++) {
927 		if (pool->base.opps[i] != NULL)
928 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
929 
930 		if (pool->base.dpps[i] != NULL)
931 			dcn10_dpp_destroy(&pool->base.dpps[i]);
932 
933 		if (pool->base.ipps[i] != NULL)
934 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
935 
936 		if (pool->base.hubps[i] != NULL) {
937 			kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
938 			pool->base.hubps[i] = NULL;
939 		}
940 
941 		if (pool->base.irqs != NULL) {
942 			dal_irq_service_destroy(&pool->base.irqs);
943 		}
944 
945 		if (pool->base.timing_generators[i] != NULL)	{
946 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
947 			pool->base.timing_generators[i] = NULL;
948 		}
949 	}
950 
951 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
952 		if (pool->base.engines[i] != NULL)
953 			dce110_engine_destroy(&pool->base.engines[i]);
954 		kfree(pool->base.hw_i2cs[i]);
955 		pool->base.hw_i2cs[i] = NULL;
956 		kfree(pool->base.sw_i2cs[i]);
957 		pool->base.sw_i2cs[i] = NULL;
958 	}
959 
960 	for (i = 0; i < pool->base.audio_count; i++) {
961 		if (pool->base.audios[i])
962 			dce_aud_destroy(&pool->base.audios[i]);
963 	}
964 
965 	for (i = 0; i < pool->base.clk_src_count; i++) {
966 		if (pool->base.clock_sources[i] != NULL) {
967 			dcn10_clock_source_destroy(&pool->base.clock_sources[i]);
968 			pool->base.clock_sources[i] = NULL;
969 		}
970 	}
971 
972 	if (pool->base.dp_clock_source != NULL) {
973 		dcn10_clock_source_destroy(&pool->base.dp_clock_source);
974 		pool->base.dp_clock_source = NULL;
975 	}
976 
977 	if (pool->base.abm != NULL)
978 		dce_abm_destroy(&pool->base.abm);
979 
980 	if (pool->base.dmcu != NULL)
981 		dce_dmcu_destroy(&pool->base.dmcu);
982 
983 	kfree(pool->base.pp_smu);
984 }
985 
986 static struct hubp *dcn10_hubp_create(
987 	struct dc_context *ctx,
988 	uint32_t inst)
989 {
990 	struct dcn10_hubp *hubp1 =
991 		kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL);
992 
993 	if (!hubp1)
994 		return NULL;
995 
996 	dcn10_hubp_construct(hubp1, ctx, inst,
997 			     &hubp_regs[inst], &hubp_shift, &hubp_mask);
998 	return &hubp1->base;
999 }
1000 
1001 static void get_pixel_clock_parameters(
1002 	const struct pipe_ctx *pipe_ctx,
1003 	struct pixel_clk_params *pixel_clk_params)
1004 {
1005 	const struct dc_stream_state *stream = pipe_ctx->stream;
1006 	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1007 	pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1008 	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1009 	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1010 	/* TODO: un-hardcode*/
1011 	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1012 		LINK_RATE_REF_FREQ_IN_KHZ;
1013 	pixel_clk_params->flags.ENABLE_SS = 0;
1014 	pixel_clk_params->color_depth =
1015 		stream->timing.display_color_depth;
1016 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1017 	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1018 
1019 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1020 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
1021 
1022 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1023 		pixel_clk_params->requested_pix_clk_100hz  /= 2;
1024 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1025 		pixel_clk_params->requested_pix_clk_100hz *= 2;
1026 
1027 }
1028 
1029 static void build_clamping_params(struct dc_stream_state *stream)
1030 {
1031 	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1032 	stream->clamping.c_depth = stream->timing.display_color_depth;
1033 	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1034 }
1035 
1036 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1037 {
1038 
1039 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1040 
1041 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1042 		pipe_ctx->clock_source,
1043 		&pipe_ctx->stream_res.pix_clk_params,
1044 		&pipe_ctx->pll_settings);
1045 
1046 	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1047 
1048 	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1049 					&pipe_ctx->stream->bit_depth_params);
1050 	build_clamping_params(pipe_ctx->stream);
1051 }
1052 
1053 static enum dc_status build_mapped_resource(
1054 		const struct dc *dc,
1055 		struct dc_state *context,
1056 		struct dc_stream_state *stream)
1057 {
1058 	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1059 
1060 	if (!pipe_ctx)
1061 		return DC_ERROR_UNEXPECTED;
1062 
1063 	build_pipe_hw_param(pipe_ctx);
1064 	return DC_OK;
1065 }
1066 
1067 static enum dc_status dcn10_add_stream_to_ctx(
1068 		struct dc *dc,
1069 		struct dc_state *new_ctx,
1070 		struct dc_stream_state *dc_stream)
1071 {
1072 	enum dc_status result = DC_ERROR_UNEXPECTED;
1073 
1074 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1075 
1076 	if (result == DC_OK)
1077 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1078 
1079 
1080 	if (result == DC_OK)
1081 		result = build_mapped_resource(dc, new_ctx, dc_stream);
1082 
1083 	return result;
1084 }
1085 
1086 static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(
1087 		const struct dc_state *cur_ctx,
1088 		struct dc_state *new_ctx,
1089 		const struct resource_pool *pool,
1090 		const struct pipe_ctx *opp_head_pipe)
1091 {
1092 	struct resource_context *res_ctx = &new_ctx->res_ctx;
1093 	struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, opp_head_pipe->stream);
1094 	struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, head_pipe);
1095 
1096 	if (!head_pipe) {
1097 		ASSERT(0);
1098 		return NULL;
1099 	}
1100 
1101 	if (!idle_pipe)
1102 		return NULL;
1103 
1104 	idle_pipe->stream = head_pipe->stream;
1105 	idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1106 	idle_pipe->stream_res.abm = head_pipe->stream_res.abm;
1107 	idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1108 
1109 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1110 	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1111 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1112 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1113 
1114 	return idle_pipe;
1115 }
1116 
1117 static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
1118 		const struct dc_dcc_surface_param *input,
1119 		struct dc_surface_dcc_cap *output)
1120 {
1121 	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1122 			dc->res_pool->hubbub,
1123 			input,
1124 			output);
1125 }
1126 
1127 static void dcn10_destroy_resource_pool(struct resource_pool **pool)
1128 {
1129 	struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
1130 
1131 	dcn10_resource_destruct(dcn10_pool);
1132 	kfree(dcn10_pool);
1133 	*pool = NULL;
1134 }
1135 
1136 static bool dcn10_validate_bandwidth(
1137 		struct dc *dc,
1138 		struct dc_state *context,
1139 		bool fast_validate)
1140 {
1141 	bool voltage_supported;
1142 
1143 	DC_FP_START();
1144 	voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate);
1145 	DC_FP_END();
1146 
1147 	return voltage_supported;
1148 }
1149 
1150 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
1151 {
1152 	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1153 			&& caps->max_video_width != 0
1154 			&& plane_state->src_rect.width > caps->max_video_width)
1155 		return DC_FAIL_SURFACE_VALIDATE;
1156 
1157 	return DC_OK;
1158 }
1159 
1160 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context)
1161 {
1162 	int i, j;
1163 	bool video_down_scaled = false;
1164 	bool video_large = false;
1165 	bool desktop_large = false;
1166 	bool dcc_disabled = false;
1167 	bool mpo_enabled = false;
1168 
1169 	for (i = 0; i < context->stream_count; i++) {
1170 		if (context->stream_status[i].plane_count == 0)
1171 			continue;
1172 
1173 		if (context->stream_status[i].plane_count > 2)
1174 			return DC_FAIL_UNSUPPORTED_1;
1175 
1176 		if (context->stream_status[i].plane_count > 1)
1177 			mpo_enabled = true;
1178 
1179 		for (j = 0; j < context->stream_status[i].plane_count; j++) {
1180 			struct dc_plane_state *plane =
1181 				context->stream_status[i].plane_states[j];
1182 
1183 
1184 			if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1185 
1186 				if (plane->src_rect.width > plane->dst_rect.width ||
1187 						plane->src_rect.height > plane->dst_rect.height)
1188 					video_down_scaled = true;
1189 
1190 				if (plane->src_rect.width >= 3840)
1191 					video_large = true;
1192 
1193 			} else {
1194 				if (plane->src_rect.width >= 3840)
1195 					desktop_large = true;
1196 				if (!plane->dcc.enable)
1197 					dcc_disabled = true;
1198 			}
1199 		}
1200 	}
1201 
1202 	/* Disable MPO in multi-display configurations. */
1203 	if (context->stream_count > 1 && mpo_enabled)
1204 		return DC_FAIL_UNSUPPORTED_1;
1205 
1206 	/*
1207 	 * Workaround: On DCN10 there is UMC issue that causes underflow when
1208 	 * playing 4k video on 4k desktop with video downscaled and single channel
1209 	 * memory
1210 	 */
1211 	if (video_large && desktop_large && video_down_scaled && dcc_disabled &&
1212 			dc->dcn_soc->number_of_channels == 1)
1213 		return DC_FAIL_SURFACE_VALIDATE;
1214 
1215 	return DC_OK;
1216 }
1217 
1218 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1219 {
1220 	enum surface_pixel_format surf_pix_format = plane_state->format;
1221 	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
1222 
1223 	enum swizzle_mode_values swizzle = DC_SW_LINEAR;
1224 
1225 	if (bpp == 64)
1226 		swizzle = DC_SW_64KB_D;
1227 	else
1228 		swizzle = DC_SW_64KB_S;
1229 
1230 	plane_state->tiling_info.gfx9.swizzle = swizzle;
1231 	return DC_OK;
1232 }
1233 
1234 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
1235 		struct resource_context *res_ctx,
1236 		const struct resource_pool *pool,
1237 		struct dc_stream_state *stream)
1238 {
1239 	int i;
1240 	int j = -1;
1241 	struct dc_link *link = stream->link;
1242 
1243 	for (i = 0; i < pool->stream_enc_count; i++) {
1244 		if (!res_ctx->is_stream_enc_acquired[i] &&
1245 				pool->stream_enc[i]) {
1246 			/* Store first available for MST second display
1247 			 * in daisy chain use case
1248 			 */
1249 			j = i;
1250 			if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id ==
1251 					link->link_enc->preferred_engine)
1252 				return pool->stream_enc[i];
1253 		}
1254 	}
1255 
1256 	/*
1257 	 * For CZ and later, we can allow DIG FE and BE to differ for all display types
1258 	 */
1259 
1260 	if (j >= 0)
1261 		return pool->stream_enc[j];
1262 
1263 	return NULL;
1264 }
1265 
1266 static const struct dc_cap_funcs cap_funcs = {
1267 	.get_dcc_compression_cap = dcn10_get_dcc_compression_cap
1268 };
1269 
1270 static const struct resource_funcs dcn10_res_pool_funcs = {
1271 	.destroy = dcn10_destroy_resource_pool,
1272 	.link_enc_create = dcn10_link_encoder_create,
1273 	.panel_cntl_create = dcn10_panel_cntl_create,
1274 	.validate_bandwidth = dcn10_validate_bandwidth,
1275 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer,
1276 	.validate_plane = dcn10_validate_plane,
1277 	.validate_global = dcn10_validate_global,
1278 	.add_stream_to_ctx = dcn10_add_stream_to_ctx,
1279 	.patch_unknown_plane_state = dcn10_patch_unknown_plane_state,
1280 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1281 };
1282 
1283 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1284 {
1285 	uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0);
1286 	/* RV1 support max 4 pipes */
1287 	value = value & 0xf;
1288 	return value;
1289 }
1290 
1291 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1292 {
1293 	int i;
1294 
1295 	if (clks->num_levels == 0)
1296 		return false;
1297 
1298 	for (i = 0; i < clks->num_levels; i++)
1299 		/* Ensure that the result is sane */
1300 		if (clks->data[i].clocks_in_khz == 0)
1301 			return false;
1302 
1303 	return true;
1304 }
1305 
1306 static bool dcn10_resource_construct(
1307 	uint8_t num_virtual_links,
1308 	struct dc *dc,
1309 	struct dcn10_resource_pool *pool)
1310 {
1311 	int i;
1312 	int j;
1313 	struct dc_context *ctx = dc->ctx;
1314 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1315 	struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1316 	int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1317 	bool res;
1318 
1319 	ctx->dc_bios->regs = &bios_regs;
1320 
1321 	if (ctx->dce_version == DCN_VERSION_1_01)
1322 		pool->base.res_cap = &rv2_res_cap;
1323 	else
1324 		pool->base.res_cap = &res_cap;
1325 	pool->base.funcs = &dcn10_res_pool_funcs;
1326 
1327 	/*
1328 	 * TODO fill in from actual raven resource when we create
1329 	 * more than virtual encoder
1330 	 */
1331 
1332 	/*************************************************
1333 	 *  Resource + asic cap harcoding                *
1334 	 *************************************************/
1335 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1336 
1337 	/* max pipe num for ASIC before check pipe fuses */
1338 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1339 
1340 	if (dc->ctx->dce_version == DCN_VERSION_1_01)
1341 		pool->base.pipe_count = 3;
1342 	dc->caps.max_video_width = 3840;
1343 	dc->caps.max_downscale_ratio = 200;
1344 	dc->caps.i2c_speed_in_khz = 100;
1345 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
1346 	dc->caps.max_cursor_size = 256;
1347 	dc->caps.min_horizontal_blanking_period = 80;
1348 	dc->caps.max_slave_planes = 1;
1349 	dc->caps.max_slave_yuv_planes = 1;
1350 	dc->caps.max_slave_rgb_planes = 0;
1351 	dc->caps.is_apu = true;
1352 	dc->caps.post_blend_color_processing = false;
1353 	dc->caps.extended_aux_timeout_support = false;
1354 
1355 	/* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */
1356 	dc->caps.force_dp_tps4_for_cp2520 = true;
1357 
1358 	/* Color pipeline capabilities */
1359 	dc->caps.color.dpp.dcn_arch = 1;
1360 	dc->caps.color.dpp.input_lut_shared = 1;
1361 	dc->caps.color.dpp.icsc = 1;
1362 	dc->caps.color.dpp.dgam_ram = 1;
1363 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1364 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1365 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1366 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1367 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1368 	dc->caps.color.dpp.post_csc = 0;
1369 	dc->caps.color.dpp.gamma_corr = 0;
1370 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1371 
1372 	dc->caps.color.dpp.hw_3d_lut = 0;
1373 	dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1
1374 	dc->caps.color.dpp.ogam_rom_caps.srgb = 1;
1375 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;
1376 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1377 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1378 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1379 	dc->caps.color.dpp.ocsc = 1;
1380 
1381 	/* no post-blend color operations */
1382 	dc->caps.color.mpc.gamut_remap = 0;
1383 	dc->caps.color.mpc.num_3dluts = 0;
1384 	dc->caps.color.mpc.shared_3d_lut = 0;
1385 	dc->caps.color.mpc.ogam_ram = 0;
1386 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1387 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1388 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1389 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1390 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1391 	dc->caps.color.mpc.ocsc = 0;
1392 
1393 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1394 		dc->debug = debug_defaults_drv;
1395 	else
1396 		dc->debug = debug_defaults_diags;
1397 
1398 	/*************************************************
1399 	 *  Create resources                             *
1400 	 *************************************************/
1401 
1402 	pool->base.clock_sources[DCN10_CLK_SRC_PLL0] =
1403 			dcn10_clock_source_create(ctx, ctx->dc_bios,
1404 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1405 				&clk_src_regs[0], false);
1406 	pool->base.clock_sources[DCN10_CLK_SRC_PLL1] =
1407 			dcn10_clock_source_create(ctx, ctx->dc_bios,
1408 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1409 				&clk_src_regs[1], false);
1410 	pool->base.clock_sources[DCN10_CLK_SRC_PLL2] =
1411 			dcn10_clock_source_create(ctx, ctx->dc_bios,
1412 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1413 				&clk_src_regs[2], false);
1414 
1415 	if (dc->ctx->dce_version == DCN_VERSION_1_0) {
1416 		pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1417 				dcn10_clock_source_create(ctx, ctx->dc_bios,
1418 					CLOCK_SOURCE_COMBO_PHY_PLL3,
1419 					&clk_src_regs[3], false);
1420 	}
1421 
1422 	pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
1423 
1424 	if (dc->ctx->dce_version == DCN_VERSION_1_01)
1425 		pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1426 
1427 	pool->base.dp_clock_source =
1428 			dcn10_clock_source_create(ctx, ctx->dc_bios,
1429 				CLOCK_SOURCE_ID_DP_DTO,
1430 				/* todo: not reuse phy_pll registers */
1431 				&clk_src_regs[0], true);
1432 
1433 	for (i = 0; i < pool->base.clk_src_count; i++) {
1434 		if (pool->base.clock_sources[i] == NULL) {
1435 			dm_error("DC: failed to create clock sources!\n");
1436 			BREAK_TO_DEBUGGER();
1437 			goto fail;
1438 		}
1439 	}
1440 
1441 	pool->base.dmcu = dcn10_dmcu_create(ctx,
1442 			&dmcu_regs,
1443 			&dmcu_shift,
1444 			&dmcu_mask);
1445 	if (pool->base.dmcu == NULL) {
1446 		dm_error("DC: failed to create dmcu!\n");
1447 		BREAK_TO_DEBUGGER();
1448 		goto fail;
1449 	}
1450 
1451 	pool->base.abm = dce_abm_create(ctx,
1452 			&abm_regs,
1453 			&abm_shift,
1454 			&abm_mask);
1455 	if (pool->base.abm == NULL) {
1456 		dm_error("DC: failed to create abm!\n");
1457 		BREAK_TO_DEBUGGER();
1458 		goto fail;
1459 	}
1460 
1461 	dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1462 	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
1463 	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
1464 
1465 	DC_FP_START();
1466 	dcn10_resource_construct_fp(dc);
1467 	DC_FP_END();
1468 
1469 	if (!dc->config.is_vmin_only_asic)
1470 		if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev))
1471 			switch (dc->ctx->asic_id.pci_revision_id) {
1472 			case PRID_DALI_DE:
1473 			case PRID_DALI_DF:
1474 			case PRID_DALI_E3:
1475 			case PRID_DALI_E4:
1476 			case PRID_POLLOCK_94:
1477 			case PRID_POLLOCK_95:
1478 			case PRID_POLLOCK_E9:
1479 			case PRID_POLLOCK_EA:
1480 			case PRID_POLLOCK_EB:
1481 				dc->config.is_vmin_only_asic = true;
1482 				break;
1483 			default:
1484 				break;
1485 			}
1486 
1487 	pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1488 
1489 	/*
1490 	 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
1491 	 * implemented. So AZ D3 should work.For issue 197007.                   *
1492 	 */
1493 	if (pool->base.pp_smu != NULL
1494 			&& pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
1495 		dc->debug.az_endpoint_mute_only = false;
1496 
1497 
1498 	if (!dc->debug.disable_pplib_clock_request) {
1499 		/*
1500 		 * TODO: This is not the proper way to obtain
1501 		 * fabric_and_dram_bandwidth, should be min(fclk, memclk).
1502 		 */
1503 		res = dm_pp_get_clock_levels_by_type_with_voltage(
1504 				ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1505 
1506 		DC_FP_START();
1507 
1508 		if (res)
1509 			res = verify_clock_values(&fclks);
1510 
1511 		if (res)
1512 			dcn_bw_update_from_pplib_fclks(dc, &fclks);
1513 		else
1514 			BREAK_TO_DEBUGGER();
1515 
1516 		DC_FP_END();
1517 
1518 		res = dm_pp_get_clock_levels_by_type_with_voltage(
1519 			ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1520 
1521 		DC_FP_START();
1522 
1523 		if (res)
1524 			res = verify_clock_values(&dcfclks);
1525 
1526 		if (res)
1527 			dcn_bw_update_from_pplib_dcfclks(dc, &dcfclks);
1528 		else
1529 			BREAK_TO_DEBUGGER();
1530 
1531 		DC_FP_END();
1532 	}
1533 
1534 	dcn_bw_sync_calcs_and_dml(dc);
1535 	if (!dc->debug.disable_pplib_wm_range) {
1536 		dc->res_pool = &pool->base;
1537 		DC_FP_START();
1538 		dcn_get_soc_clks(
1539 			dc, &min_fclk_khz, &min_dcfclk_khz, &socclk_khz);
1540 		DC_FP_END();
1541 		dcn_bw_notify_pplib_of_wm_ranges(
1542 			dc, min_fclk_khz, min_dcfclk_khz, socclk_khz);
1543 	}
1544 
1545 	{
1546 		struct irq_service_init_data init_data;
1547 		init_data.ctx = dc->ctx;
1548 		pool->base.irqs = dal_irq_service_dcn10_create(&init_data);
1549 		if (!pool->base.irqs)
1550 			goto fail;
1551 	}
1552 
1553 	/* index to valid pipe resource  */
1554 	j = 0;
1555 	/* mem input -> ipp -> dpp -> opp -> TG */
1556 	for (i = 0; i < pool->base.pipe_count; i++) {
1557 		/* if pipe is disabled, skip instance of HW pipe,
1558 		 * i.e, skip ASIC register instance
1559 		 */
1560 		if ((pipe_fuses & (1 << i)) != 0)
1561 			continue;
1562 
1563 		pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
1564 		if (pool->base.hubps[j] == NULL) {
1565 			BREAK_TO_DEBUGGER();
1566 			dm_error(
1567 				"DC: failed to create memory input!\n");
1568 			goto fail;
1569 		}
1570 
1571 		pool->base.ipps[j] = dcn10_ipp_create(ctx, i);
1572 		if (pool->base.ipps[j] == NULL) {
1573 			BREAK_TO_DEBUGGER();
1574 			dm_error(
1575 				"DC: failed to create input pixel processor!\n");
1576 			goto fail;
1577 		}
1578 
1579 		pool->base.dpps[j] = dcn10_dpp_create(ctx, i);
1580 		if (pool->base.dpps[j] == NULL) {
1581 			BREAK_TO_DEBUGGER();
1582 			dm_error(
1583 				"DC: failed to create dpp!\n");
1584 			goto fail;
1585 		}
1586 
1587 		pool->base.opps[j] = dcn10_opp_create(ctx, i);
1588 		if (pool->base.opps[j] == NULL) {
1589 			BREAK_TO_DEBUGGER();
1590 			dm_error(
1591 				"DC: failed to create output pixel processor!\n");
1592 			goto fail;
1593 		}
1594 
1595 		pool->base.timing_generators[j] = dcn10_timing_generator_create(
1596 				ctx, i);
1597 		if (pool->base.timing_generators[j] == NULL) {
1598 			BREAK_TO_DEBUGGER();
1599 			dm_error("DC: failed to create tg!\n");
1600 			goto fail;
1601 		}
1602 		/* check next valid pipe */
1603 		j++;
1604 	}
1605 
1606 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1607 		pool->base.engines[i] = dcn10_aux_engine_create(ctx, i);
1608 		if (pool->base.engines[i] == NULL) {
1609 			BREAK_TO_DEBUGGER();
1610 			dm_error(
1611 				"DC:failed to create aux engine!!\n");
1612 			goto fail;
1613 		}
1614 		pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i);
1615 		if (pool->base.hw_i2cs[i] == NULL) {
1616 			BREAK_TO_DEBUGGER();
1617 			dm_error(
1618 				"DC:failed to create hw i2c!!\n");
1619 			goto fail;
1620 		}
1621 		pool->base.sw_i2cs[i] = NULL;
1622 	}
1623 
1624 	/* valid pipe num */
1625 	pool->base.pipe_count = j;
1626 	pool->base.timing_generator_count = j;
1627 
1628 	/* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1629 	 * the value may be changed
1630 	 */
1631 	dc->dml.ip.max_num_dpp = pool->base.pipe_count;
1632 	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
1633 
1634 	pool->base.mpc = dcn10_mpc_create(ctx);
1635 	if (pool->base.mpc == NULL) {
1636 		BREAK_TO_DEBUGGER();
1637 		dm_error("DC: failed to create mpc!\n");
1638 		goto fail;
1639 	}
1640 
1641 	pool->base.hubbub = dcn10_hubbub_create(ctx);
1642 	if (pool->base.hubbub == NULL) {
1643 		BREAK_TO_DEBUGGER();
1644 		dm_error("DC: failed to create hubbub!\n");
1645 		goto fail;
1646 	}
1647 
1648 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1649 			&res_create_funcs))
1650 		goto fail;
1651 
1652 	dcn10_hw_sequencer_construct(dc);
1653 	dc->caps.max_planes =  pool->base.pipe_count;
1654 
1655 	for (i = 0; i < dc->caps.max_planes; ++i)
1656 		dc->caps.planes[i] = plane_cap;
1657 
1658 	dc->cap_funcs = cap_funcs;
1659 
1660 	return true;
1661 
1662 fail:
1663 
1664 	dcn10_resource_destruct(pool);
1665 
1666 	return false;
1667 }
1668 
1669 struct resource_pool *dcn10_create_resource_pool(
1670 		const struct dc_init_data *init_data,
1671 		struct dc *dc)
1672 {
1673 	struct dcn10_resource_pool *pool =
1674 		kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL);
1675 
1676 	if (!pool)
1677 		return NULL;
1678 
1679 	if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
1680 		return &pool->base;
1681 
1682 	kfree(pool);
1683 	BREAK_TO_DEBUGGER();
1684 	return NULL;
1685 }
1686