1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn10_resource.h" 32 33 #include "dcn10_ipp.h" 34 #include "dcn10_mpc.h" 35 #include "irq/dcn10/irq_service_dcn10.h" 36 #include "dcn10_dpp.h" 37 #include "dcn10_optc.h" 38 #include "dcn10_hw_sequencer.h" 39 #include "dce110/dce110_hw_sequencer.h" 40 #include "dcn10_opp.h" 41 #include "dcn10_link_encoder.h" 42 #include "dcn10_stream_encoder.h" 43 #include "dcn10_clk_mgr.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs_luma = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 157 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 158 #endif 159 }; 160 161 /* begin ********************* 162 * macros to expend register list macro defined in HW object header file */ 163 164 /* DCN */ 165 #define BASE_INNER(seg) \ 166 DCE_BASE__INST0_SEG ## seg 167 168 #define BASE(seg) \ 169 BASE_INNER(seg) 170 171 #define SR(reg_name)\ 172 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 173 mm ## reg_name 174 175 #define SRI(reg_name, block, id)\ 176 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 mm ## block ## id ## _ ## reg_name 178 179 180 #define SRII(reg_name, block, id)\ 181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 mm ## block ## id ## _ ## reg_name 183 184 /* NBIO */ 185 #define NBIO_BASE_INNER(seg) \ 186 NBIF_BASE__INST0_SEG ## seg 187 188 #define NBIO_BASE(seg) \ 189 NBIO_BASE_INNER(seg) 190 191 #define NBIO_SR(reg_name)\ 192 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 193 mm ## reg_name 194 195 /* MMHUB */ 196 #define MMHUB_BASE_INNER(seg) \ 197 MMHUB_BASE__INST0_SEG ## seg 198 199 #define MMHUB_BASE(seg) \ 200 MMHUB_BASE_INNER(seg) 201 202 #define MMHUB_SR(reg_name)\ 203 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 204 mm ## reg_name 205 /* macros to expend register list macro defined in HW object header file 206 * end *********************/ 207 208 209 static const struct dce_dmcu_registers dmcu_regs = { 210 DMCU_DCN10_REG_LIST() 211 }; 212 213 static const struct dce_dmcu_shift dmcu_shift = { 214 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 215 }; 216 217 static const struct dce_dmcu_mask dmcu_mask = { 218 DMCU_MASK_SH_LIST_DCN10(_MASK) 219 }; 220 221 static const struct dce_abm_registers abm_regs = { 222 ABM_DCN10_REG_LIST(0) 223 }; 224 225 static const struct dce_abm_shift abm_shift = { 226 ABM_MASK_SH_LIST_DCN10(__SHIFT) 227 }; 228 229 static const struct dce_abm_mask abm_mask = { 230 ABM_MASK_SH_LIST_DCN10(_MASK) 231 }; 232 233 #define stream_enc_regs(id)\ 234 [id] = {\ 235 SE_DCN_REG_LIST(id)\ 236 } 237 238 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 239 stream_enc_regs(0), 240 stream_enc_regs(1), 241 stream_enc_regs(2), 242 stream_enc_regs(3), 243 }; 244 245 static const struct dcn10_stream_encoder_shift se_shift = { 246 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 247 }; 248 249 static const struct dcn10_stream_encoder_mask se_mask = { 250 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 251 }; 252 253 #define audio_regs(id)\ 254 [id] = {\ 255 AUD_COMMON_REG_LIST(id)\ 256 } 257 258 static const struct dce_audio_registers audio_regs[] = { 259 audio_regs(0), 260 audio_regs(1), 261 audio_regs(2), 262 audio_regs(3), 263 }; 264 265 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 266 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 267 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 268 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 269 270 static const struct dce_audio_shift audio_shift = { 271 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dce_aduio_mask audio_mask = { 275 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 276 }; 277 278 #define aux_regs(id)\ 279 [id] = {\ 280 AUX_REG_LIST(id)\ 281 } 282 283 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 284 aux_regs(0), 285 aux_regs(1), 286 aux_regs(2), 287 aux_regs(3) 288 }; 289 290 #define hpd_regs(id)\ 291 [id] = {\ 292 HPD_REG_LIST(id)\ 293 } 294 295 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 296 hpd_regs(0), 297 hpd_regs(1), 298 hpd_regs(2), 299 hpd_regs(3) 300 }; 301 302 #define link_regs(id)\ 303 [id] = {\ 304 LE_DCN10_REG_LIST(id), \ 305 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 306 } 307 308 static const struct dcn10_link_enc_registers link_enc_regs[] = { 309 link_regs(0), 310 link_regs(1), 311 link_regs(2), 312 link_regs(3) 313 }; 314 315 static const struct dcn10_link_enc_shift le_shift = { 316 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 317 }; 318 319 static const struct dcn10_link_enc_mask le_mask = { 320 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 321 }; 322 323 #define ipp_regs(id)\ 324 [id] = {\ 325 IPP_REG_LIST_DCN10(id),\ 326 } 327 328 static const struct dcn10_ipp_registers ipp_regs[] = { 329 ipp_regs(0), 330 ipp_regs(1), 331 ipp_regs(2), 332 ipp_regs(3), 333 }; 334 335 static const struct dcn10_ipp_shift ipp_shift = { 336 IPP_MASK_SH_LIST_DCN10(__SHIFT) 337 }; 338 339 static const struct dcn10_ipp_mask ipp_mask = { 340 IPP_MASK_SH_LIST_DCN10(_MASK), 341 }; 342 343 #define opp_regs(id)\ 344 [id] = {\ 345 OPP_REG_LIST_DCN10(id),\ 346 } 347 348 static const struct dcn10_opp_registers opp_regs[] = { 349 opp_regs(0), 350 opp_regs(1), 351 opp_regs(2), 352 opp_regs(3), 353 }; 354 355 static const struct dcn10_opp_shift opp_shift = { 356 OPP_MASK_SH_LIST_DCN10(__SHIFT) 357 }; 358 359 static const struct dcn10_opp_mask opp_mask = { 360 OPP_MASK_SH_LIST_DCN10(_MASK), 361 }; 362 363 #define aux_engine_regs(id)\ 364 [id] = {\ 365 AUX_COMMON_REG_LIST(id), \ 366 .AUX_RESET_MASK = 0 \ 367 } 368 369 static const struct dce110_aux_registers aux_engine_regs[] = { 370 aux_engine_regs(0), 371 aux_engine_regs(1), 372 aux_engine_regs(2), 373 aux_engine_regs(3), 374 aux_engine_regs(4), 375 aux_engine_regs(5) 376 }; 377 378 #define tf_regs(id)\ 379 [id] = {\ 380 TF_REG_LIST_DCN10(id),\ 381 } 382 383 static const struct dcn_dpp_registers tf_regs[] = { 384 tf_regs(0), 385 tf_regs(1), 386 tf_regs(2), 387 tf_regs(3), 388 }; 389 390 static const struct dcn_dpp_shift tf_shift = { 391 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 392 TF_DEBUG_REG_LIST_SH_DCN10 393 394 }; 395 396 static const struct dcn_dpp_mask tf_mask = { 397 TF_REG_LIST_SH_MASK_DCN10(_MASK), 398 TF_DEBUG_REG_LIST_MASK_DCN10 399 }; 400 401 static const struct dcn_mpc_registers mpc_regs = { 402 MPC_COMMON_REG_LIST_DCN1_0(0), 403 MPC_COMMON_REG_LIST_DCN1_0(1), 404 MPC_COMMON_REG_LIST_DCN1_0(2), 405 MPC_COMMON_REG_LIST_DCN1_0(3), 406 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 407 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 408 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 409 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 410 }; 411 412 static const struct dcn_mpc_shift mpc_shift = { 413 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 414 }; 415 416 static const struct dcn_mpc_mask mpc_mask = { 417 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 418 }; 419 420 #define tg_regs(id)\ 421 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 422 423 static const struct dcn_optc_registers tg_regs[] = { 424 tg_regs(0), 425 tg_regs(1), 426 tg_regs(2), 427 tg_regs(3), 428 }; 429 430 static const struct dcn_optc_shift tg_shift = { 431 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 432 }; 433 434 static const struct dcn_optc_mask tg_mask = { 435 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 436 }; 437 438 static const struct bios_registers bios_regs = { 439 NBIO_SR(BIOS_SCRATCH_3), 440 NBIO_SR(BIOS_SCRATCH_6) 441 }; 442 443 #define hubp_regs(id)\ 444 [id] = {\ 445 HUBP_REG_LIST_DCN10(id)\ 446 } 447 448 449 static const struct dcn_mi_registers hubp_regs[] = { 450 hubp_regs(0), 451 hubp_regs(1), 452 hubp_regs(2), 453 hubp_regs(3), 454 }; 455 456 static const struct dcn_mi_shift hubp_shift = { 457 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 458 }; 459 460 static const struct dcn_mi_mask hubp_mask = { 461 HUBP_MASK_SH_LIST_DCN10(_MASK) 462 }; 463 464 465 static const struct dcn_hubbub_registers hubbub_reg = { 466 HUBBUB_REG_LIST_DCN10(0) 467 }; 468 469 static const struct dcn_hubbub_shift hubbub_shift = { 470 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 471 }; 472 473 static const struct dcn_hubbub_mask hubbub_mask = { 474 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 475 }; 476 477 #define clk_src_regs(index, pllid)\ 478 [index] = {\ 479 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 480 } 481 482 static const struct dce110_clk_src_regs clk_src_regs[] = { 483 clk_src_regs(0, A), 484 clk_src_regs(1, B), 485 clk_src_regs(2, C), 486 clk_src_regs(3, D) 487 }; 488 489 static const struct dce110_clk_src_shift cs_shift = { 490 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 491 }; 492 493 static const struct dce110_clk_src_mask cs_mask = { 494 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 495 }; 496 497 static const struct resource_caps res_cap = { 498 .num_timing_generator = 4, 499 .num_opp = 4, 500 .num_video_plane = 4, 501 .num_audio = 4, 502 .num_stream_encoder = 4, 503 .num_pll = 4, 504 .num_ddc = 4, 505 }; 506 507 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 508 static const struct resource_caps rv2_res_cap = { 509 .num_timing_generator = 3, 510 .num_opp = 3, 511 .num_video_plane = 3, 512 .num_audio = 3, 513 .num_stream_encoder = 3, 514 .num_pll = 3, 515 .num_ddc = 3, 516 }; 517 #endif 518 519 static const struct dc_plane_cap plane_cap = { 520 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 521 .blends_with_above = true, 522 .blends_with_below = true, 523 .per_pixel_alpha = true, 524 .supports_argb8888 = true, 525 .supports_nv12 = true 526 }; 527 528 static const struct dc_debug_options debug_defaults_drv = { 529 .sanity_checks = true, 530 .disable_dmcu = true, 531 .force_abm_enable = false, 532 .timing_trace = false, 533 .clock_trace = true, 534 535 /* raven smu dones't allow 0 disp clk, 536 * smu min disp clk limit is 50Mhz 537 * keep min disp clk 100Mhz avoid smu hang 538 */ 539 .min_disp_clk_khz = 100000, 540 541 .disable_pplib_clock_request = false, 542 .disable_pplib_wm_range = false, 543 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 544 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 545 .force_single_disp_pipe_split = true, 546 .disable_dcc = DCC_ENABLE, 547 .voltage_align_fclk = true, 548 .disable_stereo_support = true, 549 .vsr_support = true, 550 .performance_trace = false, 551 .az_endpoint_mute_only = true, 552 .recovery_enabled = false, /*enable this by default after testing.*/ 553 .max_downscale_src_width = 3840, 554 }; 555 556 static const struct dc_debug_options debug_defaults_diags = { 557 .disable_dmcu = true, 558 .force_abm_enable = false, 559 .timing_trace = true, 560 .clock_trace = true, 561 .disable_stutter = true, 562 .disable_pplib_clock_request = true, 563 .disable_pplib_wm_range = true 564 }; 565 566 static void dcn10_dpp_destroy(struct dpp **dpp) 567 { 568 kfree(TO_DCN10_DPP(*dpp)); 569 *dpp = NULL; 570 } 571 572 static struct dpp *dcn10_dpp_create( 573 struct dc_context *ctx, 574 uint32_t inst) 575 { 576 struct dcn10_dpp *dpp = 577 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 578 579 if (!dpp) 580 return NULL; 581 582 dpp1_construct(dpp, ctx, inst, 583 &tf_regs[inst], &tf_shift, &tf_mask); 584 return &dpp->base; 585 } 586 587 static struct input_pixel_processor *dcn10_ipp_create( 588 struct dc_context *ctx, uint32_t inst) 589 { 590 struct dcn10_ipp *ipp = 591 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 592 593 if (!ipp) { 594 BREAK_TO_DEBUGGER(); 595 return NULL; 596 } 597 598 dcn10_ipp_construct(ipp, ctx, inst, 599 &ipp_regs[inst], &ipp_shift, &ipp_mask); 600 return &ipp->base; 601 } 602 603 604 static struct output_pixel_processor *dcn10_opp_create( 605 struct dc_context *ctx, uint32_t inst) 606 { 607 struct dcn10_opp *opp = 608 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 609 610 if (!opp) { 611 BREAK_TO_DEBUGGER(); 612 return NULL; 613 } 614 615 dcn10_opp_construct(opp, ctx, inst, 616 &opp_regs[inst], &opp_shift, &opp_mask); 617 return &opp->base; 618 } 619 620 struct dce_aux *dcn10_aux_engine_create( 621 struct dc_context *ctx, 622 uint32_t inst) 623 { 624 struct aux_engine_dce110 *aux_engine = 625 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 626 627 if (!aux_engine) 628 return NULL; 629 630 dce110_aux_engine_construct(aux_engine, ctx, inst, 631 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 632 &aux_engine_regs[inst]); 633 634 return &aux_engine->base; 635 } 636 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 637 638 static const struct dce_i2c_registers i2c_hw_regs[] = { 639 i2c_inst_regs(1), 640 i2c_inst_regs(2), 641 i2c_inst_regs(3), 642 i2c_inst_regs(4), 643 i2c_inst_regs(5), 644 i2c_inst_regs(6), 645 }; 646 647 static const struct dce_i2c_shift i2c_shifts = { 648 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 649 }; 650 651 static const struct dce_i2c_mask i2c_masks = { 652 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 653 }; 654 655 struct dce_i2c_hw *dcn10_i2c_hw_create( 656 struct dc_context *ctx, 657 uint32_t inst) 658 { 659 struct dce_i2c_hw *dce_i2c_hw = 660 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 661 662 if (!dce_i2c_hw) 663 return NULL; 664 665 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 666 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 667 668 return dce_i2c_hw; 669 } 670 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 671 { 672 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 673 GFP_KERNEL); 674 675 if (!mpc10) 676 return NULL; 677 678 dcn10_mpc_construct(mpc10, ctx, 679 &mpc_regs, 680 &mpc_shift, 681 &mpc_mask, 682 4); 683 684 return &mpc10->base; 685 } 686 687 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 688 { 689 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 690 GFP_KERNEL); 691 692 if (!dcn10_hubbub) 693 return NULL; 694 695 hubbub1_construct(&dcn10_hubbub->base, ctx, 696 &hubbub_reg, 697 &hubbub_shift, 698 &hubbub_mask); 699 700 return &dcn10_hubbub->base; 701 } 702 703 static struct timing_generator *dcn10_timing_generator_create( 704 struct dc_context *ctx, 705 uint32_t instance) 706 { 707 struct optc *tgn10 = 708 kzalloc(sizeof(struct optc), GFP_KERNEL); 709 710 if (!tgn10) 711 return NULL; 712 713 tgn10->base.inst = instance; 714 tgn10->base.ctx = ctx; 715 716 tgn10->tg_regs = &tg_regs[instance]; 717 tgn10->tg_shift = &tg_shift; 718 tgn10->tg_mask = &tg_mask; 719 720 dcn10_timing_generator_init(tgn10); 721 722 return &tgn10->base; 723 } 724 725 static const struct encoder_feature_support link_enc_feature = { 726 .max_hdmi_deep_color = COLOR_DEPTH_121212, 727 .max_hdmi_pixel_clock = 600000, 728 .hdmi_ycbcr420_supported = true, 729 .dp_ycbcr420_supported = false, 730 .flags.bits.IS_HBR2_CAPABLE = true, 731 .flags.bits.IS_HBR3_CAPABLE = true, 732 .flags.bits.IS_TPS3_CAPABLE = true, 733 .flags.bits.IS_TPS4_CAPABLE = true 734 }; 735 736 struct link_encoder *dcn10_link_encoder_create( 737 const struct encoder_init_data *enc_init_data) 738 { 739 struct dcn10_link_encoder *enc10 = 740 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 741 742 if (!enc10) 743 return NULL; 744 745 dcn10_link_encoder_construct(enc10, 746 enc_init_data, 747 &link_enc_feature, 748 &link_enc_regs[enc_init_data->transmitter], 749 &link_enc_aux_regs[enc_init_data->channel - 1], 750 &link_enc_hpd_regs[enc_init_data->hpd_source], 751 &le_shift, 752 &le_mask); 753 754 return &enc10->base; 755 } 756 757 struct clock_source *dcn10_clock_source_create( 758 struct dc_context *ctx, 759 struct dc_bios *bios, 760 enum clock_source_id id, 761 const struct dce110_clk_src_regs *regs, 762 bool dp_clk_src) 763 { 764 struct dce110_clk_src *clk_src = 765 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 766 767 if (!clk_src) 768 return NULL; 769 770 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 771 regs, &cs_shift, &cs_mask)) { 772 clk_src->base.dp_clk_src = dp_clk_src; 773 return &clk_src->base; 774 } 775 776 BREAK_TO_DEBUGGER(); 777 return NULL; 778 } 779 780 static void read_dce_straps( 781 struct dc_context *ctx, 782 struct resource_straps *straps) 783 { 784 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 785 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 786 } 787 788 static struct audio *create_audio( 789 struct dc_context *ctx, unsigned int inst) 790 { 791 return dce_audio_create(ctx, inst, 792 &audio_regs[inst], &audio_shift, &audio_mask); 793 } 794 795 static struct stream_encoder *dcn10_stream_encoder_create( 796 enum engine_id eng_id, 797 struct dc_context *ctx) 798 { 799 struct dcn10_stream_encoder *enc1 = 800 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 801 802 if (!enc1) 803 return NULL; 804 805 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 806 &stream_enc_regs[eng_id], 807 &se_shift, &se_mask); 808 return &enc1->base; 809 } 810 811 static const struct dce_hwseq_registers hwseq_reg = { 812 HWSEQ_DCN1_REG_LIST() 813 }; 814 815 static const struct dce_hwseq_shift hwseq_shift = { 816 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 817 }; 818 819 static const struct dce_hwseq_mask hwseq_mask = { 820 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 821 }; 822 823 static struct dce_hwseq *dcn10_hwseq_create( 824 struct dc_context *ctx) 825 { 826 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 827 828 if (hws) { 829 hws->ctx = ctx; 830 hws->regs = &hwseq_reg; 831 hws->shifts = &hwseq_shift; 832 hws->masks = &hwseq_mask; 833 hws->wa.DEGVIDCN10_253 = true; 834 hws->wa.false_optc_underflow = true; 835 hws->wa.DEGVIDCN10_254 = true; 836 } 837 return hws; 838 } 839 840 static const struct resource_create_funcs res_create_funcs = { 841 .read_dce_straps = read_dce_straps, 842 .create_audio = create_audio, 843 .create_stream_encoder = dcn10_stream_encoder_create, 844 .create_hwseq = dcn10_hwseq_create, 845 }; 846 847 static const struct resource_create_funcs res_create_maximus_funcs = { 848 .read_dce_straps = NULL, 849 .create_audio = NULL, 850 .create_stream_encoder = NULL, 851 .create_hwseq = dcn10_hwseq_create, 852 }; 853 854 void dcn10_clock_source_destroy(struct clock_source **clk_src) 855 { 856 kfree(TO_DCE110_CLK_SRC(*clk_src)); 857 *clk_src = NULL; 858 } 859 860 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 861 { 862 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 863 864 if (!pp_smu) 865 return pp_smu; 866 867 dm_pp_get_funcs(ctx, pp_smu); 868 return pp_smu; 869 } 870 871 static void destruct(struct dcn10_resource_pool *pool) 872 { 873 unsigned int i; 874 875 for (i = 0; i < pool->base.stream_enc_count; i++) { 876 if (pool->base.stream_enc[i] != NULL) { 877 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 878 pool->base.stream_enc[i] = NULL; 879 } 880 } 881 882 if (pool->base.mpc != NULL) { 883 kfree(TO_DCN10_MPC(pool->base.mpc)); 884 pool->base.mpc = NULL; 885 } 886 887 if (pool->base.hubbub != NULL) { 888 kfree(pool->base.hubbub); 889 pool->base.hubbub = NULL; 890 } 891 892 for (i = 0; i < pool->base.pipe_count; i++) { 893 if (pool->base.opps[i] != NULL) 894 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 895 896 if (pool->base.dpps[i] != NULL) 897 dcn10_dpp_destroy(&pool->base.dpps[i]); 898 899 if (pool->base.ipps[i] != NULL) 900 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 901 902 if (pool->base.hubps[i] != NULL) { 903 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 904 pool->base.hubps[i] = NULL; 905 } 906 907 if (pool->base.irqs != NULL) { 908 dal_irq_service_destroy(&pool->base.irqs); 909 } 910 911 if (pool->base.timing_generators[i] != NULL) { 912 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 913 pool->base.timing_generators[i] = NULL; 914 } 915 } 916 917 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 918 if (pool->base.engines[i] != NULL) 919 dce110_engine_destroy(&pool->base.engines[i]); 920 if (pool->base.hw_i2cs[i] != NULL) { 921 kfree(pool->base.hw_i2cs[i]); 922 pool->base.hw_i2cs[i] = NULL; 923 } 924 if (pool->base.sw_i2cs[i] != NULL) { 925 kfree(pool->base.sw_i2cs[i]); 926 pool->base.sw_i2cs[i] = NULL; 927 } 928 } 929 930 for (i = 0; i < pool->base.audio_count; i++) { 931 if (pool->base.audios[i]) 932 dce_aud_destroy(&pool->base.audios[i]); 933 } 934 935 for (i = 0; i < pool->base.clk_src_count; i++) { 936 if (pool->base.clock_sources[i] != NULL) { 937 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 938 pool->base.clock_sources[i] = NULL; 939 } 940 } 941 942 if (pool->base.dp_clock_source != NULL) { 943 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 944 pool->base.dp_clock_source = NULL; 945 } 946 947 if (pool->base.abm != NULL) 948 dce_abm_destroy(&pool->base.abm); 949 950 if (pool->base.dmcu != NULL) 951 dce_dmcu_destroy(&pool->base.dmcu); 952 953 if (pool->base.clk_mgr != NULL) 954 dce_clk_mgr_destroy(&pool->base.clk_mgr); 955 956 kfree(pool->base.pp_smu); 957 } 958 959 static struct hubp *dcn10_hubp_create( 960 struct dc_context *ctx, 961 uint32_t inst) 962 { 963 struct dcn10_hubp *hubp1 = 964 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 965 966 if (!hubp1) 967 return NULL; 968 969 dcn10_hubp_construct(hubp1, ctx, inst, 970 &hubp_regs[inst], &hubp_shift, &hubp_mask); 971 return &hubp1->base; 972 } 973 974 static void get_pixel_clock_parameters( 975 const struct pipe_ctx *pipe_ctx, 976 struct pixel_clk_params *pixel_clk_params) 977 { 978 const struct dc_stream_state *stream = pipe_ctx->stream; 979 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 980 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 981 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 982 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 983 /* TODO: un-hardcode*/ 984 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 985 LINK_RATE_REF_FREQ_IN_KHZ; 986 pixel_clk_params->flags.ENABLE_SS = 0; 987 pixel_clk_params->color_depth = 988 stream->timing.display_color_depth; 989 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 990 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 991 992 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 993 pixel_clk_params->color_depth = COLOR_DEPTH_888; 994 995 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 996 pixel_clk_params->requested_pix_clk_100hz /= 2; 997 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 998 pixel_clk_params->requested_pix_clk_100hz *= 2; 999 1000 } 1001 1002 static void build_clamping_params(struct dc_stream_state *stream) 1003 { 1004 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1005 stream->clamping.c_depth = stream->timing.display_color_depth; 1006 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1007 } 1008 1009 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1010 { 1011 1012 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1013 1014 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1015 pipe_ctx->clock_source, 1016 &pipe_ctx->stream_res.pix_clk_params, 1017 &pipe_ctx->pll_settings); 1018 1019 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1020 1021 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1022 &pipe_ctx->stream->bit_depth_params); 1023 build_clamping_params(pipe_ctx->stream); 1024 } 1025 1026 static enum dc_status build_mapped_resource( 1027 const struct dc *dc, 1028 struct dc_state *context, 1029 struct dc_stream_state *stream) 1030 { 1031 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1032 1033 /*TODO Seems unneeded anymore */ 1034 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1035 if (stream != NULL && old_context->streams[i] != NULL) { 1036 todo: shouldn't have to copy missing parameter here 1037 resource_build_bit_depth_reduction_params(stream, 1038 &stream->bit_depth_params); 1039 stream->clamping.pixel_encoding = 1040 stream->timing.pixel_encoding; 1041 1042 resource_build_bit_depth_reduction_params(stream, 1043 &stream->bit_depth_params); 1044 build_clamping_params(stream); 1045 1046 continue; 1047 } 1048 } 1049 */ 1050 1051 if (!pipe_ctx) 1052 return DC_ERROR_UNEXPECTED; 1053 1054 build_pipe_hw_param(pipe_ctx); 1055 return DC_OK; 1056 } 1057 1058 enum dc_status dcn10_add_stream_to_ctx( 1059 struct dc *dc, 1060 struct dc_state *new_ctx, 1061 struct dc_stream_state *dc_stream) 1062 { 1063 enum dc_status result = DC_ERROR_UNEXPECTED; 1064 1065 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1066 1067 if (result == DC_OK) 1068 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1069 1070 1071 if (result == DC_OK) 1072 result = build_mapped_resource(dc, new_ctx, dc_stream); 1073 1074 return result; 1075 } 1076 1077 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1078 struct dc_state *context, 1079 const struct resource_pool *pool, 1080 struct dc_stream_state *stream) 1081 { 1082 struct resource_context *res_ctx = &context->res_ctx; 1083 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1084 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 1085 1086 if (!head_pipe) { 1087 ASSERT(0); 1088 return NULL; 1089 } 1090 1091 if (!idle_pipe) 1092 return NULL; 1093 1094 idle_pipe->stream = head_pipe->stream; 1095 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1096 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1097 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1098 1099 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1100 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1101 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1102 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1103 1104 return idle_pipe; 1105 } 1106 1107 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1108 const struct dc_dcc_surface_param *input, 1109 struct dc_surface_dcc_cap *output) 1110 { 1111 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1112 dc->res_pool->hubbub, 1113 input, 1114 output); 1115 } 1116 1117 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1118 { 1119 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1120 1121 destruct(dcn10_pool); 1122 kfree(dcn10_pool); 1123 *pool = NULL; 1124 } 1125 1126 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1127 { 1128 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1129 && caps->max_video_width != 0 1130 && plane_state->src_rect.width > caps->max_video_width) 1131 return DC_FAIL_SURFACE_VALIDATE; 1132 1133 return DC_OK; 1134 } 1135 1136 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1137 { 1138 int i, j; 1139 bool video_down_scaled = false; 1140 bool video_large = false; 1141 bool desktop_large = false; 1142 bool dcc_disabled = false; 1143 1144 for (i = 0; i < context->stream_count; i++) { 1145 if (context->stream_status[i].plane_count == 0) 1146 continue; 1147 1148 if (context->stream_status[i].plane_count > 2) 1149 return false; 1150 1151 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1152 struct dc_plane_state *plane = 1153 context->stream_status[i].plane_states[j]; 1154 1155 1156 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1157 1158 if (plane->src_rect.width > plane->dst_rect.width || 1159 plane->src_rect.height > plane->dst_rect.height) 1160 video_down_scaled = true; 1161 1162 if (plane->src_rect.width >= 3840) 1163 video_large = true; 1164 1165 } else { 1166 if (plane->src_rect.width >= 3840) 1167 desktop_large = true; 1168 if (!plane->dcc.enable) 1169 dcc_disabled = true; 1170 } 1171 } 1172 } 1173 1174 /* 1175 * Workaround: On DCN10 there is UMC issue that causes underflow when 1176 * playing 4k video on 4k desktop with video downscaled and single channel 1177 * memory 1178 */ 1179 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1180 dc->dcn_soc->number_of_channels == 1) 1181 return DC_FAIL_SURFACE_VALIDATE; 1182 1183 return DC_OK; 1184 } 1185 1186 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1187 { 1188 enum dc_status result = DC_OK; 1189 1190 enum surface_pixel_format surf_pix_format = plane_state->format; 1191 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1192 1193 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1194 1195 if (bpp == 64) 1196 swizzle = DC_SW_64KB_D; 1197 else 1198 swizzle = DC_SW_64KB_S; 1199 1200 plane_state->tiling_info.gfx9.swizzle = swizzle; 1201 return result; 1202 } 1203 1204 static const struct dc_cap_funcs cap_funcs = { 1205 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1206 }; 1207 1208 static const struct resource_funcs dcn10_res_pool_funcs = { 1209 .destroy = dcn10_destroy_resource_pool, 1210 .link_enc_create = dcn10_link_encoder_create, 1211 .validate_bandwidth = dcn_validate_bandwidth, 1212 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1213 .validate_plane = dcn10_validate_plane, 1214 .validate_global = dcn10_validate_global, 1215 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1216 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode 1217 }; 1218 1219 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1220 { 1221 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1222 /* RV1 support max 4 pipes */ 1223 value = value & 0xf; 1224 return value; 1225 } 1226 1227 static bool construct( 1228 uint8_t num_virtual_links, 1229 struct dc *dc, 1230 struct dcn10_resource_pool *pool) 1231 { 1232 int i; 1233 int j; 1234 struct dc_context *ctx = dc->ctx; 1235 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1236 1237 ctx->dc_bios->regs = &bios_regs; 1238 1239 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1240 if (ctx->dce_version == DCN_VERSION_1_01) 1241 pool->base.res_cap = &rv2_res_cap; 1242 else 1243 #endif 1244 pool->base.res_cap = &res_cap; 1245 pool->base.funcs = &dcn10_res_pool_funcs; 1246 1247 /* 1248 * TODO fill in from actual raven resource when we create 1249 * more than virtual encoder 1250 */ 1251 1252 /************************************************* 1253 * Resource + asic cap harcoding * 1254 *************************************************/ 1255 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1256 1257 /* max pipe num for ASIC before check pipe fuses */ 1258 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1259 1260 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1261 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1262 pool->base.pipe_count = 3; 1263 #endif 1264 dc->caps.max_video_width = 3840; 1265 dc->caps.max_downscale_ratio = 200; 1266 dc->caps.i2c_speed_in_khz = 100; 1267 dc->caps.max_cursor_size = 256; 1268 dc->caps.max_slave_planes = 1; 1269 dc->caps.is_apu = true; 1270 dc->caps.post_blend_color_processing = false; 1271 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1272 dc->caps.force_dp_tps4_for_cp2520 = true; 1273 1274 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1275 dc->debug = debug_defaults_drv; 1276 else 1277 dc->debug = debug_defaults_diags; 1278 1279 /************************************************* 1280 * Create resources * 1281 *************************************************/ 1282 1283 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1284 dcn10_clock_source_create(ctx, ctx->dc_bios, 1285 CLOCK_SOURCE_COMBO_PHY_PLL0, 1286 &clk_src_regs[0], false); 1287 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1288 dcn10_clock_source_create(ctx, ctx->dc_bios, 1289 CLOCK_SOURCE_COMBO_PHY_PLL1, 1290 &clk_src_regs[1], false); 1291 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1292 dcn10_clock_source_create(ctx, ctx->dc_bios, 1293 CLOCK_SOURCE_COMBO_PHY_PLL2, 1294 &clk_src_regs[2], false); 1295 1296 #ifdef CONFIG_DRM_AMD_DC_DCN1_01 1297 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1298 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1299 dcn10_clock_source_create(ctx, ctx->dc_bios, 1300 CLOCK_SOURCE_COMBO_PHY_PLL3, 1301 &clk_src_regs[3], false); 1302 } 1303 #else 1304 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1305 dcn10_clock_source_create(ctx, ctx->dc_bios, 1306 CLOCK_SOURCE_COMBO_PHY_PLL3, 1307 &clk_src_regs[3], false); 1308 #endif 1309 1310 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1311 1312 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1313 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1314 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1315 #endif 1316 1317 pool->base.dp_clock_source = 1318 dcn10_clock_source_create(ctx, ctx->dc_bios, 1319 CLOCK_SOURCE_ID_DP_DTO, 1320 /* todo: not reuse phy_pll registers */ 1321 &clk_src_regs[0], true); 1322 1323 for (i = 0; i < pool->base.clk_src_count; i++) { 1324 if (pool->base.clock_sources[i] == NULL) { 1325 dm_error("DC: failed to create clock sources!\n"); 1326 BREAK_TO_DEBUGGER(); 1327 goto fail; 1328 } 1329 } 1330 pool->base.clk_mgr = dcn1_clk_mgr_create(ctx); 1331 if (pool->base.clk_mgr == NULL) { 1332 dm_error("DC: failed to create display clock!\n"); 1333 BREAK_TO_DEBUGGER(); 1334 goto fail; 1335 } 1336 1337 pool->base.dmcu = dcn10_dmcu_create(ctx, 1338 &dmcu_regs, 1339 &dmcu_shift, 1340 &dmcu_mask); 1341 if (pool->base.dmcu == NULL) { 1342 dm_error("DC: failed to create dmcu!\n"); 1343 BREAK_TO_DEBUGGER(); 1344 goto fail; 1345 } 1346 1347 pool->base.abm = dce_abm_create(ctx, 1348 &abm_regs, 1349 &abm_shift, 1350 &abm_mask); 1351 if (pool->base.abm == NULL) { 1352 dm_error("DC: failed to create abm!\n"); 1353 BREAK_TO_DEBUGGER(); 1354 goto fail; 1355 } 1356 1357 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1358 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1359 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1360 1361 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1362 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1363 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1364 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1365 struct display_mode_lib *dml = &dc->dml; 1366 1367 dml->ip.max_num_dpp = 3; 1368 /* TODO how to handle 23.84? */ 1369 dcn_soc->dram_clock_change_latency = 23; 1370 dcn_ip->max_num_dpp = 3; 1371 } 1372 #endif 1373 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1374 dc->dcn_soc->urgent_latency = 3; 1375 dc->debug.disable_dmcu = true; 1376 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1377 } 1378 1379 1380 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1381 ASSERT(dc->dcn_soc->number_of_channels < 3); 1382 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1383 dc->dcn_soc->number_of_channels = 2; 1384 1385 if (dc->dcn_soc->number_of_channels == 1) { 1386 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1387 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1388 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1389 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1390 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1391 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1392 } 1393 } 1394 1395 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1396 1397 if (!dc->debug.disable_pplib_clock_request) 1398 dcn_bw_update_from_pplib(dc); 1399 dcn_bw_sync_calcs_and_dml(dc); 1400 if (!dc->debug.disable_pplib_wm_range) { 1401 dc->res_pool = &pool->base; 1402 dcn_bw_notify_pplib_of_wm_ranges(dc); 1403 } 1404 1405 { 1406 struct irq_service_init_data init_data; 1407 init_data.ctx = dc->ctx; 1408 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1409 if (!pool->base.irqs) 1410 goto fail; 1411 } 1412 1413 /* index to valid pipe resource */ 1414 j = 0; 1415 /* mem input -> ipp -> dpp -> opp -> TG */ 1416 for (i = 0; i < pool->base.pipe_count; i++) { 1417 /* if pipe is disabled, skip instance of HW pipe, 1418 * i.e, skip ASIC register instance 1419 */ 1420 if ((pipe_fuses & (1 << i)) != 0) 1421 continue; 1422 1423 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1424 if (pool->base.hubps[j] == NULL) { 1425 BREAK_TO_DEBUGGER(); 1426 dm_error( 1427 "DC: failed to create memory input!\n"); 1428 goto fail; 1429 } 1430 1431 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1432 if (pool->base.ipps[j] == NULL) { 1433 BREAK_TO_DEBUGGER(); 1434 dm_error( 1435 "DC: failed to create input pixel processor!\n"); 1436 goto fail; 1437 } 1438 1439 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1440 if (pool->base.dpps[j] == NULL) { 1441 BREAK_TO_DEBUGGER(); 1442 dm_error( 1443 "DC: failed to create dpp!\n"); 1444 goto fail; 1445 } 1446 1447 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1448 if (pool->base.opps[j] == NULL) { 1449 BREAK_TO_DEBUGGER(); 1450 dm_error( 1451 "DC: failed to create output pixel processor!\n"); 1452 goto fail; 1453 } 1454 1455 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1456 ctx, i); 1457 if (pool->base.timing_generators[j] == NULL) { 1458 BREAK_TO_DEBUGGER(); 1459 dm_error("DC: failed to create tg!\n"); 1460 goto fail; 1461 } 1462 /* check next valid pipe */ 1463 j++; 1464 } 1465 1466 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1467 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1468 if (pool->base.engines[i] == NULL) { 1469 BREAK_TO_DEBUGGER(); 1470 dm_error( 1471 "DC:failed to create aux engine!!\n"); 1472 goto fail; 1473 } 1474 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1475 if (pool->base.hw_i2cs[i] == NULL) { 1476 BREAK_TO_DEBUGGER(); 1477 dm_error( 1478 "DC:failed to create hw i2c!!\n"); 1479 goto fail; 1480 } 1481 pool->base.sw_i2cs[i] = NULL; 1482 } 1483 1484 /* valid pipe num */ 1485 pool->base.pipe_count = j; 1486 pool->base.timing_generator_count = j; 1487 1488 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1489 * the value may be changed 1490 */ 1491 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1492 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1493 1494 pool->base.mpc = dcn10_mpc_create(ctx); 1495 if (pool->base.mpc == NULL) { 1496 BREAK_TO_DEBUGGER(); 1497 dm_error("DC: failed to create mpc!\n"); 1498 goto fail; 1499 } 1500 1501 pool->base.hubbub = dcn10_hubbub_create(ctx); 1502 if (pool->base.hubbub == NULL) { 1503 BREAK_TO_DEBUGGER(); 1504 dm_error("DC: failed to create hubbub!\n"); 1505 goto fail; 1506 } 1507 1508 if (!resource_construct(num_virtual_links, dc, &pool->base, 1509 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1510 &res_create_funcs : &res_create_maximus_funcs))) 1511 goto fail; 1512 1513 dcn10_hw_sequencer_construct(dc); 1514 dc->caps.max_planes = pool->base.pipe_count; 1515 1516 for (i = 0; i < dc->caps.max_planes; ++i) 1517 dc->caps.planes[i] = plane_cap; 1518 1519 dc->cap_funcs = cap_funcs; 1520 1521 return true; 1522 1523 fail: 1524 1525 destruct(pool); 1526 1527 return false; 1528 } 1529 1530 struct resource_pool *dcn10_create_resource_pool( 1531 const struct dc_init_data *init_data, 1532 struct dc *dc) 1533 { 1534 struct dcn10_resource_pool *pool = 1535 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1536 1537 if (!pool) 1538 return NULL; 1539 1540 if (construct(init_data->num_virtual_links, dc, pool)) 1541 return &pool->base; 1542 1543 BREAK_TO_DEBUGGER(); 1544 return NULL; 1545 } 1546