1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 31 #include "resource.h" 32 #include "include/irq_service_interface.h" 33 #include "dcn10_resource.h" 34 #include "dcn10_ipp.h" 35 #include "dcn10_mpc.h" 36 #include "irq/dcn10/irq_service_dcn10.h" 37 #include "dcn10_dpp.h" 38 #include "dcn10_optc.h" 39 #include "dcn10_hw_sequencer.h" 40 #include "dce110/dce110_hw_sequencer.h" 41 #include "dcn10_opp.h" 42 #include "dcn10_link_encoder.h" 43 #include "dcn10_stream_encoder.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs_luma = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 157 }; 158 159 /* begin ********************* 160 * macros to expend register list macro defined in HW object header file */ 161 162 /* DCN */ 163 #define BASE_INNER(seg) \ 164 DCE_BASE__INST0_SEG ## seg 165 166 #define BASE(seg) \ 167 BASE_INNER(seg) 168 169 #define SR(reg_name)\ 170 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 171 mm ## reg_name 172 173 #define SRI(reg_name, block, id)\ 174 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 mm ## block ## id ## _ ## reg_name 176 177 178 #define SRII(reg_name, block, id)\ 179 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 180 mm ## block ## id ## _ ## reg_name 181 182 /* NBIO */ 183 #define NBIO_BASE_INNER(seg) \ 184 NBIF_BASE__INST0_SEG ## seg 185 186 #define NBIO_BASE(seg) \ 187 NBIO_BASE_INNER(seg) 188 189 #define NBIO_SR(reg_name)\ 190 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 191 mm ## reg_name 192 193 /* MMHUB */ 194 #define MMHUB_BASE_INNER(seg) \ 195 MMHUB_BASE__INST0_SEG ## seg 196 197 #define MMHUB_BASE(seg) \ 198 MMHUB_BASE_INNER(seg) 199 200 #define MMHUB_SR(reg_name)\ 201 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 202 mm ## reg_name 203 204 /* macros to expend register list macro defined in HW object header file 205 * end *********************/ 206 207 208 static const struct dce_dmcu_registers dmcu_regs = { 209 DMCU_DCN10_REG_LIST() 210 }; 211 212 static const struct dce_dmcu_shift dmcu_shift = { 213 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 214 }; 215 216 static const struct dce_dmcu_mask dmcu_mask = { 217 DMCU_MASK_SH_LIST_DCN10(_MASK) 218 }; 219 220 static const struct dce_abm_registers abm_regs = { 221 ABM_DCN10_REG_LIST(0) 222 }; 223 224 static const struct dce_abm_shift abm_shift = { 225 ABM_MASK_SH_LIST_DCN10(__SHIFT) 226 }; 227 228 static const struct dce_abm_mask abm_mask = { 229 ABM_MASK_SH_LIST_DCN10(_MASK) 230 }; 231 232 #define stream_enc_regs(id)\ 233 [id] = {\ 234 SE_DCN_REG_LIST(id)\ 235 } 236 237 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 238 stream_enc_regs(0), 239 stream_enc_regs(1), 240 stream_enc_regs(2), 241 stream_enc_regs(3), 242 }; 243 244 static const struct dcn10_stream_encoder_shift se_shift = { 245 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 246 }; 247 248 static const struct dcn10_stream_encoder_mask se_mask = { 249 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 250 }; 251 252 #define audio_regs(id)\ 253 [id] = {\ 254 AUD_COMMON_REG_LIST(id)\ 255 } 256 257 static const struct dce_audio_registers audio_regs[] = { 258 audio_regs(0), 259 audio_regs(1), 260 audio_regs(2), 261 audio_regs(3), 262 }; 263 264 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 265 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 266 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 267 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 268 269 static const struct dce_audio_shift audio_shift = { 270 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 271 }; 272 273 static const struct dce_audio_mask audio_mask = { 274 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 275 }; 276 277 #define aux_regs(id)\ 278 [id] = {\ 279 AUX_REG_LIST(id)\ 280 } 281 282 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 283 aux_regs(0), 284 aux_regs(1), 285 aux_regs(2), 286 aux_regs(3) 287 }; 288 289 #define hpd_regs(id)\ 290 [id] = {\ 291 HPD_REG_LIST(id)\ 292 } 293 294 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 295 hpd_regs(0), 296 hpd_regs(1), 297 hpd_regs(2), 298 hpd_regs(3) 299 }; 300 301 #define link_regs(id)\ 302 [id] = {\ 303 LE_DCN10_REG_LIST(id), \ 304 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 305 } 306 307 static const struct dcn10_link_enc_registers link_enc_regs[] = { 308 link_regs(0), 309 link_regs(1), 310 link_regs(2), 311 link_regs(3) 312 }; 313 314 static const struct dcn10_link_enc_shift le_shift = { 315 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 316 }; 317 318 static const struct dcn10_link_enc_mask le_mask = { 319 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 320 }; 321 322 static const struct dce110_aux_registers_shift aux_shift = { 323 DCN10_AUX_MASK_SH_LIST(__SHIFT) 324 }; 325 326 static const struct dce110_aux_registers_mask aux_mask = { 327 DCN10_AUX_MASK_SH_LIST(_MASK) 328 }; 329 330 #define ipp_regs(id)\ 331 [id] = {\ 332 IPP_REG_LIST_DCN10(id),\ 333 } 334 335 static const struct dcn10_ipp_registers ipp_regs[] = { 336 ipp_regs(0), 337 ipp_regs(1), 338 ipp_regs(2), 339 ipp_regs(3), 340 }; 341 342 static const struct dcn10_ipp_shift ipp_shift = { 343 IPP_MASK_SH_LIST_DCN10(__SHIFT) 344 }; 345 346 static const struct dcn10_ipp_mask ipp_mask = { 347 IPP_MASK_SH_LIST_DCN10(_MASK), 348 }; 349 350 #define opp_regs(id)\ 351 [id] = {\ 352 OPP_REG_LIST_DCN10(id),\ 353 } 354 355 static const struct dcn10_opp_registers opp_regs[] = { 356 opp_regs(0), 357 opp_regs(1), 358 opp_regs(2), 359 opp_regs(3), 360 }; 361 362 static const struct dcn10_opp_shift opp_shift = { 363 OPP_MASK_SH_LIST_DCN10(__SHIFT) 364 }; 365 366 static const struct dcn10_opp_mask opp_mask = { 367 OPP_MASK_SH_LIST_DCN10(_MASK), 368 }; 369 370 #define aux_engine_regs(id)\ 371 [id] = {\ 372 AUX_COMMON_REG_LIST(id), \ 373 .AUX_RESET_MASK = 0 \ 374 } 375 376 static const struct dce110_aux_registers aux_engine_regs[] = { 377 aux_engine_regs(0), 378 aux_engine_regs(1), 379 aux_engine_regs(2), 380 aux_engine_regs(3), 381 aux_engine_regs(4), 382 aux_engine_regs(5) 383 }; 384 385 #define tf_regs(id)\ 386 [id] = {\ 387 TF_REG_LIST_DCN10(id),\ 388 } 389 390 static const struct dcn_dpp_registers tf_regs[] = { 391 tf_regs(0), 392 tf_regs(1), 393 tf_regs(2), 394 tf_regs(3), 395 }; 396 397 static const struct dcn_dpp_shift tf_shift = { 398 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 399 TF_DEBUG_REG_LIST_SH_DCN10 400 401 }; 402 403 static const struct dcn_dpp_mask tf_mask = { 404 TF_REG_LIST_SH_MASK_DCN10(_MASK), 405 TF_DEBUG_REG_LIST_MASK_DCN10 406 }; 407 408 static const struct dcn_mpc_registers mpc_regs = { 409 MPC_COMMON_REG_LIST_DCN1_0(0), 410 MPC_COMMON_REG_LIST_DCN1_0(1), 411 MPC_COMMON_REG_LIST_DCN1_0(2), 412 MPC_COMMON_REG_LIST_DCN1_0(3), 413 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 414 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 415 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 416 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 417 }; 418 419 static const struct dcn_mpc_shift mpc_shift = { 420 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 421 }; 422 423 static const struct dcn_mpc_mask mpc_mask = { 424 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 425 }; 426 427 #define tg_regs(id)\ 428 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 429 430 static const struct dcn_optc_registers tg_regs[] = { 431 tg_regs(0), 432 tg_regs(1), 433 tg_regs(2), 434 tg_regs(3), 435 }; 436 437 static const struct dcn_optc_shift tg_shift = { 438 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 439 }; 440 441 static const struct dcn_optc_mask tg_mask = { 442 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 443 }; 444 445 static const struct bios_registers bios_regs = { 446 NBIO_SR(BIOS_SCRATCH_3), 447 NBIO_SR(BIOS_SCRATCH_6) 448 }; 449 450 #define hubp_regs(id)\ 451 [id] = {\ 452 HUBP_REG_LIST_DCN10(id)\ 453 } 454 455 static const struct dcn_mi_registers hubp_regs[] = { 456 hubp_regs(0), 457 hubp_regs(1), 458 hubp_regs(2), 459 hubp_regs(3), 460 }; 461 462 static const struct dcn_mi_shift hubp_shift = { 463 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 464 }; 465 466 static const struct dcn_mi_mask hubp_mask = { 467 HUBP_MASK_SH_LIST_DCN10(_MASK) 468 }; 469 470 static const struct dcn_hubbub_registers hubbub_reg = { 471 HUBBUB_REG_LIST_DCN10(0) 472 }; 473 474 static const struct dcn_hubbub_shift hubbub_shift = { 475 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 476 }; 477 478 static const struct dcn_hubbub_mask hubbub_mask = { 479 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 480 }; 481 482 #define clk_src_regs(index, pllid)\ 483 [index] = {\ 484 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 485 } 486 487 static const struct dce110_clk_src_regs clk_src_regs[] = { 488 clk_src_regs(0, A), 489 clk_src_regs(1, B), 490 clk_src_regs(2, C), 491 clk_src_regs(3, D) 492 }; 493 494 static const struct dce110_clk_src_shift cs_shift = { 495 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 496 }; 497 498 static const struct dce110_clk_src_mask cs_mask = { 499 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 500 }; 501 502 static const struct resource_caps res_cap = { 503 .num_timing_generator = 4, 504 .num_opp = 4, 505 .num_video_plane = 4, 506 .num_audio = 4, 507 .num_stream_encoder = 4, 508 .num_pll = 4, 509 .num_ddc = 4, 510 }; 511 512 static const struct resource_caps rv2_res_cap = { 513 .num_timing_generator = 3, 514 .num_opp = 3, 515 .num_video_plane = 3, 516 .num_audio = 3, 517 .num_stream_encoder = 3, 518 .num_pll = 3, 519 .num_ddc = 4, 520 }; 521 522 static const struct dc_plane_cap plane_cap = { 523 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 524 .blends_with_above = true, 525 .blends_with_below = true, 526 .per_pixel_alpha = true, 527 528 .pixel_format_support = { 529 .argb8888 = true, 530 .nv12 = true, 531 .fp16 = true 532 }, 533 534 .max_upscale_factor = { 535 .argb8888 = 16000, 536 .nv12 = 16000, 537 .fp16 = 1 538 }, 539 540 .max_downscale_factor = { 541 .argb8888 = 250, 542 .nv12 = 250, 543 .fp16 = 1 544 } 545 }; 546 547 static const struct dc_debug_options debug_defaults_drv = { 548 .sanity_checks = true, 549 .disable_dmcu = true, 550 .force_abm_enable = false, 551 .timing_trace = false, 552 .clock_trace = true, 553 554 /* raven smu dones't allow 0 disp clk, 555 * smu min disp clk limit is 50Mhz 556 * keep min disp clk 100Mhz avoid smu hang 557 */ 558 .min_disp_clk_khz = 100000, 559 560 .disable_pplib_clock_request = false, 561 .disable_pplib_wm_range = false, 562 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 563 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 564 .force_single_disp_pipe_split = true, 565 .disable_dcc = DCC_ENABLE, 566 .voltage_align_fclk = true, 567 .disable_stereo_support = true, 568 .vsr_support = true, 569 .performance_trace = false, 570 .az_endpoint_mute_only = true, 571 .recovery_enabled = false, /*enable this by default after testing.*/ 572 .max_downscale_src_width = 3840, 573 .underflow_assert_delay_us = 0xFFFFFFFF, 574 }; 575 576 static const struct dc_debug_options debug_defaults_diags = { 577 .disable_dmcu = true, 578 .force_abm_enable = false, 579 .timing_trace = true, 580 .clock_trace = true, 581 .disable_stutter = true, 582 .disable_pplib_clock_request = true, 583 .disable_pplib_wm_range = true, 584 .underflow_assert_delay_us = 0xFFFFFFFF, 585 }; 586 587 static void dcn10_dpp_destroy(struct dpp **dpp) 588 { 589 kfree(TO_DCN10_DPP(*dpp)); 590 *dpp = NULL; 591 } 592 593 static struct dpp *dcn10_dpp_create( 594 struct dc_context *ctx, 595 uint32_t inst) 596 { 597 struct dcn10_dpp *dpp = 598 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 599 600 if (!dpp) 601 return NULL; 602 603 dpp1_construct(dpp, ctx, inst, 604 &tf_regs[inst], &tf_shift, &tf_mask); 605 return &dpp->base; 606 } 607 608 static struct input_pixel_processor *dcn10_ipp_create( 609 struct dc_context *ctx, uint32_t inst) 610 { 611 struct dcn10_ipp *ipp = 612 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 613 614 if (!ipp) { 615 BREAK_TO_DEBUGGER(); 616 return NULL; 617 } 618 619 dcn10_ipp_construct(ipp, ctx, inst, 620 &ipp_regs[inst], &ipp_shift, &ipp_mask); 621 return &ipp->base; 622 } 623 624 625 static struct output_pixel_processor *dcn10_opp_create( 626 struct dc_context *ctx, uint32_t inst) 627 { 628 struct dcn10_opp *opp = 629 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 630 631 if (!opp) { 632 BREAK_TO_DEBUGGER(); 633 return NULL; 634 } 635 636 dcn10_opp_construct(opp, ctx, inst, 637 &opp_regs[inst], &opp_shift, &opp_mask); 638 return &opp->base; 639 } 640 641 struct dce_aux *dcn10_aux_engine_create( 642 struct dc_context *ctx, 643 uint32_t inst) 644 { 645 struct aux_engine_dce110 *aux_engine = 646 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 647 648 if (!aux_engine) 649 return NULL; 650 651 dce110_aux_engine_construct(aux_engine, ctx, inst, 652 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 653 &aux_engine_regs[inst], 654 &aux_mask, 655 &aux_shift, 656 ctx->dc->caps.extended_aux_timeout_support); 657 658 return &aux_engine->base; 659 } 660 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 661 662 static const struct dce_i2c_registers i2c_hw_regs[] = { 663 i2c_inst_regs(1), 664 i2c_inst_regs(2), 665 i2c_inst_regs(3), 666 i2c_inst_regs(4), 667 i2c_inst_regs(5), 668 i2c_inst_regs(6), 669 }; 670 671 static const struct dce_i2c_shift i2c_shifts = { 672 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 673 }; 674 675 static const struct dce_i2c_mask i2c_masks = { 676 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 677 }; 678 679 struct dce_i2c_hw *dcn10_i2c_hw_create( 680 struct dc_context *ctx, 681 uint32_t inst) 682 { 683 struct dce_i2c_hw *dce_i2c_hw = 684 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 685 686 if (!dce_i2c_hw) 687 return NULL; 688 689 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 690 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 691 692 return dce_i2c_hw; 693 } 694 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 695 { 696 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 697 GFP_KERNEL); 698 699 if (!mpc10) 700 return NULL; 701 702 dcn10_mpc_construct(mpc10, ctx, 703 &mpc_regs, 704 &mpc_shift, 705 &mpc_mask, 706 4); 707 708 return &mpc10->base; 709 } 710 711 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 712 { 713 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 714 GFP_KERNEL); 715 716 if (!dcn10_hubbub) 717 return NULL; 718 719 hubbub1_construct(&dcn10_hubbub->base, ctx, 720 &hubbub_reg, 721 &hubbub_shift, 722 &hubbub_mask); 723 724 return &dcn10_hubbub->base; 725 } 726 727 static struct timing_generator *dcn10_timing_generator_create( 728 struct dc_context *ctx, 729 uint32_t instance) 730 { 731 struct optc *tgn10 = 732 kzalloc(sizeof(struct optc), GFP_KERNEL); 733 734 if (!tgn10) 735 return NULL; 736 737 tgn10->base.inst = instance; 738 tgn10->base.ctx = ctx; 739 740 tgn10->tg_regs = &tg_regs[instance]; 741 tgn10->tg_shift = &tg_shift; 742 tgn10->tg_mask = &tg_mask; 743 744 dcn10_timing_generator_init(tgn10); 745 746 return &tgn10->base; 747 } 748 749 static const struct encoder_feature_support link_enc_feature = { 750 .max_hdmi_deep_color = COLOR_DEPTH_121212, 751 .max_hdmi_pixel_clock = 600000, 752 .hdmi_ycbcr420_supported = true, 753 .dp_ycbcr420_supported = false, 754 .flags.bits.IS_HBR2_CAPABLE = true, 755 .flags.bits.IS_HBR3_CAPABLE = true, 756 .flags.bits.IS_TPS3_CAPABLE = true, 757 .flags.bits.IS_TPS4_CAPABLE = true 758 }; 759 760 struct link_encoder *dcn10_link_encoder_create( 761 const struct encoder_init_data *enc_init_data) 762 { 763 struct dcn10_link_encoder *enc10 = 764 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 765 766 if (!enc10) 767 return NULL; 768 769 dcn10_link_encoder_construct(enc10, 770 enc_init_data, 771 &link_enc_feature, 772 &link_enc_regs[enc_init_data->transmitter], 773 &link_enc_aux_regs[enc_init_data->channel - 1], 774 &link_enc_hpd_regs[enc_init_data->hpd_source], 775 &le_shift, 776 &le_mask); 777 778 return &enc10->base; 779 } 780 781 struct clock_source *dcn10_clock_source_create( 782 struct dc_context *ctx, 783 struct dc_bios *bios, 784 enum clock_source_id id, 785 const struct dce110_clk_src_regs *regs, 786 bool dp_clk_src) 787 { 788 struct dce110_clk_src *clk_src = 789 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 790 791 if (!clk_src) 792 return NULL; 793 794 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 795 regs, &cs_shift, &cs_mask)) { 796 clk_src->base.dp_clk_src = dp_clk_src; 797 return &clk_src->base; 798 } 799 800 kfree(clk_src); 801 BREAK_TO_DEBUGGER(); 802 return NULL; 803 } 804 805 static void read_dce_straps( 806 struct dc_context *ctx, 807 struct resource_straps *straps) 808 { 809 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 810 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 811 } 812 813 static struct audio *create_audio( 814 struct dc_context *ctx, unsigned int inst) 815 { 816 return dce_audio_create(ctx, inst, 817 &audio_regs[inst], &audio_shift, &audio_mask); 818 } 819 820 static struct stream_encoder *dcn10_stream_encoder_create( 821 enum engine_id eng_id, 822 struct dc_context *ctx) 823 { 824 struct dcn10_stream_encoder *enc1 = 825 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 826 827 if (!enc1) 828 return NULL; 829 830 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 831 &stream_enc_regs[eng_id], 832 &se_shift, &se_mask); 833 return &enc1->base; 834 } 835 836 static const struct dce_hwseq_registers hwseq_reg = { 837 HWSEQ_DCN1_REG_LIST() 838 }; 839 840 static const struct dce_hwseq_shift hwseq_shift = { 841 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 842 }; 843 844 static const struct dce_hwseq_mask hwseq_mask = { 845 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 846 }; 847 848 static struct dce_hwseq *dcn10_hwseq_create( 849 struct dc_context *ctx) 850 { 851 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 852 853 if (hws) { 854 hws->ctx = ctx; 855 hws->regs = &hwseq_reg; 856 hws->shifts = &hwseq_shift; 857 hws->masks = &hwseq_mask; 858 hws->wa.DEGVIDCN10_253 = true; 859 hws->wa.false_optc_underflow = true; 860 hws->wa.DEGVIDCN10_254 = true; 861 } 862 return hws; 863 } 864 865 static const struct resource_create_funcs res_create_funcs = { 866 .read_dce_straps = read_dce_straps, 867 .create_audio = create_audio, 868 .create_stream_encoder = dcn10_stream_encoder_create, 869 .create_hwseq = dcn10_hwseq_create, 870 }; 871 872 static const struct resource_create_funcs res_create_maximus_funcs = { 873 .read_dce_straps = NULL, 874 .create_audio = NULL, 875 .create_stream_encoder = NULL, 876 .create_hwseq = dcn10_hwseq_create, 877 }; 878 879 void dcn10_clock_source_destroy(struct clock_source **clk_src) 880 { 881 kfree(TO_DCE110_CLK_SRC(*clk_src)); 882 *clk_src = NULL; 883 } 884 885 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 886 { 887 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 888 889 if (!pp_smu) 890 return pp_smu; 891 892 dm_pp_get_funcs(ctx, pp_smu); 893 return pp_smu; 894 } 895 896 static void destruct(struct dcn10_resource_pool *pool) 897 { 898 unsigned int i; 899 900 for (i = 0; i < pool->base.stream_enc_count; i++) { 901 if (pool->base.stream_enc[i] != NULL) { 902 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 903 pool->base.stream_enc[i] = NULL; 904 } 905 } 906 907 if (pool->base.mpc != NULL) { 908 kfree(TO_DCN10_MPC(pool->base.mpc)); 909 pool->base.mpc = NULL; 910 } 911 912 if (pool->base.hubbub != NULL) { 913 kfree(pool->base.hubbub); 914 pool->base.hubbub = NULL; 915 } 916 917 for (i = 0; i < pool->base.pipe_count; i++) { 918 if (pool->base.opps[i] != NULL) 919 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 920 921 if (pool->base.dpps[i] != NULL) 922 dcn10_dpp_destroy(&pool->base.dpps[i]); 923 924 if (pool->base.ipps[i] != NULL) 925 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 926 927 if (pool->base.hubps[i] != NULL) { 928 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 929 pool->base.hubps[i] = NULL; 930 } 931 932 if (pool->base.irqs != NULL) { 933 dal_irq_service_destroy(&pool->base.irqs); 934 } 935 936 if (pool->base.timing_generators[i] != NULL) { 937 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 938 pool->base.timing_generators[i] = NULL; 939 } 940 } 941 942 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 943 if (pool->base.engines[i] != NULL) 944 dce110_engine_destroy(&pool->base.engines[i]); 945 if (pool->base.hw_i2cs[i] != NULL) { 946 kfree(pool->base.hw_i2cs[i]); 947 pool->base.hw_i2cs[i] = NULL; 948 } 949 if (pool->base.sw_i2cs[i] != NULL) { 950 kfree(pool->base.sw_i2cs[i]); 951 pool->base.sw_i2cs[i] = NULL; 952 } 953 } 954 955 for (i = 0; i < pool->base.audio_count; i++) { 956 if (pool->base.audios[i]) 957 dce_aud_destroy(&pool->base.audios[i]); 958 } 959 960 for (i = 0; i < pool->base.clk_src_count; i++) { 961 if (pool->base.clock_sources[i] != NULL) { 962 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 963 pool->base.clock_sources[i] = NULL; 964 } 965 } 966 967 if (pool->base.dp_clock_source != NULL) { 968 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 969 pool->base.dp_clock_source = NULL; 970 } 971 972 if (pool->base.abm != NULL) 973 dce_abm_destroy(&pool->base.abm); 974 975 if (pool->base.dmcu != NULL) 976 dce_dmcu_destroy(&pool->base.dmcu); 977 978 kfree(pool->base.pp_smu); 979 } 980 981 static struct hubp *dcn10_hubp_create( 982 struct dc_context *ctx, 983 uint32_t inst) 984 { 985 struct dcn10_hubp *hubp1 = 986 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 987 988 if (!hubp1) 989 return NULL; 990 991 dcn10_hubp_construct(hubp1, ctx, inst, 992 &hubp_regs[inst], &hubp_shift, &hubp_mask); 993 return &hubp1->base; 994 } 995 996 static void get_pixel_clock_parameters( 997 const struct pipe_ctx *pipe_ctx, 998 struct pixel_clk_params *pixel_clk_params) 999 { 1000 const struct dc_stream_state *stream = pipe_ctx->stream; 1001 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1002 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 1003 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1004 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1005 /* TODO: un-hardcode*/ 1006 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1007 LINK_RATE_REF_FREQ_IN_KHZ; 1008 pixel_clk_params->flags.ENABLE_SS = 0; 1009 pixel_clk_params->color_depth = 1010 stream->timing.display_color_depth; 1011 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1012 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1013 1014 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1015 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1016 1017 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1018 pixel_clk_params->requested_pix_clk_100hz /= 2; 1019 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1020 pixel_clk_params->requested_pix_clk_100hz *= 2; 1021 1022 } 1023 1024 static void build_clamping_params(struct dc_stream_state *stream) 1025 { 1026 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1027 stream->clamping.c_depth = stream->timing.display_color_depth; 1028 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1029 } 1030 1031 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1032 { 1033 1034 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1035 1036 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1037 pipe_ctx->clock_source, 1038 &pipe_ctx->stream_res.pix_clk_params, 1039 &pipe_ctx->pll_settings); 1040 1041 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1042 1043 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1044 &pipe_ctx->stream->bit_depth_params); 1045 build_clamping_params(pipe_ctx->stream); 1046 } 1047 1048 static enum dc_status build_mapped_resource( 1049 const struct dc *dc, 1050 struct dc_state *context, 1051 struct dc_stream_state *stream) 1052 { 1053 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1054 1055 /*TODO Seems unneeded anymore */ 1056 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1057 if (stream != NULL && old_context->streams[i] != NULL) { 1058 todo: shouldn't have to copy missing parameter here 1059 resource_build_bit_depth_reduction_params(stream, 1060 &stream->bit_depth_params); 1061 stream->clamping.pixel_encoding = 1062 stream->timing.pixel_encoding; 1063 1064 resource_build_bit_depth_reduction_params(stream, 1065 &stream->bit_depth_params); 1066 build_clamping_params(stream); 1067 1068 continue; 1069 } 1070 } 1071 */ 1072 1073 if (!pipe_ctx) 1074 return DC_ERROR_UNEXPECTED; 1075 1076 build_pipe_hw_param(pipe_ctx); 1077 return DC_OK; 1078 } 1079 1080 enum dc_status dcn10_add_stream_to_ctx( 1081 struct dc *dc, 1082 struct dc_state *new_ctx, 1083 struct dc_stream_state *dc_stream) 1084 { 1085 enum dc_status result = DC_ERROR_UNEXPECTED; 1086 1087 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1088 1089 if (result == DC_OK) 1090 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1091 1092 1093 if (result == DC_OK) 1094 result = build_mapped_resource(dc, new_ctx, dc_stream); 1095 1096 return result; 1097 } 1098 1099 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1100 struct dc_state *context, 1101 const struct resource_pool *pool, 1102 struct dc_stream_state *stream) 1103 { 1104 struct resource_context *res_ctx = &context->res_ctx; 1105 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1106 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 1107 1108 if (!head_pipe) { 1109 ASSERT(0); 1110 return NULL; 1111 } 1112 1113 if (!idle_pipe) 1114 return NULL; 1115 1116 idle_pipe->stream = head_pipe->stream; 1117 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1118 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1119 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1120 1121 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1122 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1123 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1124 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1125 1126 return idle_pipe; 1127 } 1128 1129 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1130 const struct dc_dcc_surface_param *input, 1131 struct dc_surface_dcc_cap *output) 1132 { 1133 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1134 dc->res_pool->hubbub, 1135 input, 1136 output); 1137 } 1138 1139 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1140 { 1141 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1142 1143 destruct(dcn10_pool); 1144 kfree(dcn10_pool); 1145 *pool = NULL; 1146 } 1147 1148 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1149 { 1150 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1151 && caps->max_video_width != 0 1152 && plane_state->src_rect.width > caps->max_video_width) 1153 return DC_FAIL_SURFACE_VALIDATE; 1154 1155 return DC_OK; 1156 } 1157 1158 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1159 { 1160 int i, j; 1161 bool video_down_scaled = false; 1162 bool video_large = false; 1163 bool desktop_large = false; 1164 bool dcc_disabled = false; 1165 1166 for (i = 0; i < context->stream_count; i++) { 1167 if (context->stream_status[i].plane_count == 0) 1168 continue; 1169 1170 if (context->stream_status[i].plane_count > 2) 1171 return DC_FAIL_UNSUPPORTED_1; 1172 1173 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1174 struct dc_plane_state *plane = 1175 context->stream_status[i].plane_states[j]; 1176 1177 1178 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1179 1180 if (plane->src_rect.width > plane->dst_rect.width || 1181 plane->src_rect.height > plane->dst_rect.height) 1182 video_down_scaled = true; 1183 1184 if (plane->src_rect.width >= 3840) 1185 video_large = true; 1186 1187 } else { 1188 if (plane->src_rect.width >= 3840) 1189 desktop_large = true; 1190 if (!plane->dcc.enable) 1191 dcc_disabled = true; 1192 } 1193 } 1194 } 1195 1196 /* 1197 * Workaround: On DCN10 there is UMC issue that causes underflow when 1198 * playing 4k video on 4k desktop with video downscaled and single channel 1199 * memory 1200 */ 1201 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1202 dc->dcn_soc->number_of_channels == 1) 1203 return DC_FAIL_SURFACE_VALIDATE; 1204 1205 return DC_OK; 1206 } 1207 1208 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1209 { 1210 enum dc_status result = DC_OK; 1211 1212 enum surface_pixel_format surf_pix_format = plane_state->format; 1213 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1214 1215 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1216 1217 if (bpp == 64) 1218 swizzle = DC_SW_64KB_D; 1219 else 1220 swizzle = DC_SW_64KB_S; 1221 1222 plane_state->tiling_info.gfx9.swizzle = swizzle; 1223 return result; 1224 } 1225 1226 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( 1227 struct resource_context *res_ctx, 1228 const struct resource_pool *pool, 1229 struct dc_stream_state *stream) 1230 { 1231 int i; 1232 int j = -1; 1233 struct dc_link *link = stream->link; 1234 1235 for (i = 0; i < pool->stream_enc_count; i++) { 1236 if (!res_ctx->is_stream_enc_acquired[i] && 1237 pool->stream_enc[i]) { 1238 /* Store first available for MST second display 1239 * in daisy chain use case 1240 */ 1241 j = i; 1242 if (pool->stream_enc[i]->id == 1243 link->link_enc->preferred_engine) 1244 return pool->stream_enc[i]; 1245 } 1246 } 1247 1248 /* 1249 * For CZ and later, we can allow DIG FE and BE to differ for all display types 1250 */ 1251 1252 if (j >= 0) 1253 return pool->stream_enc[j]; 1254 1255 return NULL; 1256 } 1257 1258 static const struct dc_cap_funcs cap_funcs = { 1259 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1260 }; 1261 1262 static const struct resource_funcs dcn10_res_pool_funcs = { 1263 .destroy = dcn10_destroy_resource_pool, 1264 .link_enc_create = dcn10_link_encoder_create, 1265 .validate_bandwidth = dcn_validate_bandwidth, 1266 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1267 .validate_plane = dcn10_validate_plane, 1268 .validate_global = dcn10_validate_global, 1269 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1270 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode, 1271 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 1272 }; 1273 1274 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1275 { 1276 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1277 /* RV1 support max 4 pipes */ 1278 value = value & 0xf; 1279 return value; 1280 } 1281 1282 static bool construct( 1283 uint8_t num_virtual_links, 1284 struct dc *dc, 1285 struct dcn10_resource_pool *pool) 1286 { 1287 int i; 1288 int j; 1289 struct dc_context *ctx = dc->ctx; 1290 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1291 1292 ctx->dc_bios->regs = &bios_regs; 1293 1294 if (ctx->dce_version == DCN_VERSION_1_01) 1295 pool->base.res_cap = &rv2_res_cap; 1296 else 1297 pool->base.res_cap = &res_cap; 1298 pool->base.funcs = &dcn10_res_pool_funcs; 1299 1300 /* 1301 * TODO fill in from actual raven resource when we create 1302 * more than virtual encoder 1303 */ 1304 1305 /************************************************* 1306 * Resource + asic cap harcoding * 1307 *************************************************/ 1308 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1309 1310 /* max pipe num for ASIC before check pipe fuses */ 1311 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1312 1313 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1314 pool->base.pipe_count = 3; 1315 dc->caps.max_video_width = 3840; 1316 dc->caps.max_downscale_ratio = 200; 1317 dc->caps.i2c_speed_in_khz = 100; 1318 dc->caps.max_cursor_size = 256; 1319 dc->caps.max_slave_planes = 1; 1320 dc->caps.is_apu = true; 1321 dc->caps.post_blend_color_processing = false; 1322 dc->caps.extended_aux_timeout_support = false; 1323 1324 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1325 dc->caps.force_dp_tps4_for_cp2520 = true; 1326 1327 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1328 dc->debug = debug_defaults_drv; 1329 else 1330 dc->debug = debug_defaults_diags; 1331 1332 /************************************************* 1333 * Create resources * 1334 *************************************************/ 1335 1336 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1337 dcn10_clock_source_create(ctx, ctx->dc_bios, 1338 CLOCK_SOURCE_COMBO_PHY_PLL0, 1339 &clk_src_regs[0], false); 1340 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1341 dcn10_clock_source_create(ctx, ctx->dc_bios, 1342 CLOCK_SOURCE_COMBO_PHY_PLL1, 1343 &clk_src_regs[1], false); 1344 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1345 dcn10_clock_source_create(ctx, ctx->dc_bios, 1346 CLOCK_SOURCE_COMBO_PHY_PLL2, 1347 &clk_src_regs[2], false); 1348 1349 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1350 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1351 dcn10_clock_source_create(ctx, ctx->dc_bios, 1352 CLOCK_SOURCE_COMBO_PHY_PLL3, 1353 &clk_src_regs[3], false); 1354 } 1355 1356 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1357 1358 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1359 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1360 1361 pool->base.dp_clock_source = 1362 dcn10_clock_source_create(ctx, ctx->dc_bios, 1363 CLOCK_SOURCE_ID_DP_DTO, 1364 /* todo: not reuse phy_pll registers */ 1365 &clk_src_regs[0], true); 1366 1367 for (i = 0; i < pool->base.clk_src_count; i++) { 1368 if (pool->base.clock_sources[i] == NULL) { 1369 dm_error("DC: failed to create clock sources!\n"); 1370 BREAK_TO_DEBUGGER(); 1371 goto fail; 1372 } 1373 } 1374 1375 pool->base.dmcu = dcn10_dmcu_create(ctx, 1376 &dmcu_regs, 1377 &dmcu_shift, 1378 &dmcu_mask); 1379 if (pool->base.dmcu == NULL) { 1380 dm_error("DC: failed to create dmcu!\n"); 1381 BREAK_TO_DEBUGGER(); 1382 goto fail; 1383 } 1384 1385 pool->base.abm = dce_abm_create(ctx, 1386 &abm_regs, 1387 &abm_shift, 1388 &abm_mask); 1389 if (pool->base.abm == NULL) { 1390 dm_error("DC: failed to create abm!\n"); 1391 BREAK_TO_DEBUGGER(); 1392 goto fail; 1393 } 1394 1395 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1396 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1397 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1398 1399 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1400 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1401 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1402 struct display_mode_lib *dml = &dc->dml; 1403 1404 dml->ip.max_num_dpp = 3; 1405 /* TODO how to handle 23.84? */ 1406 dcn_soc->dram_clock_change_latency = 23; 1407 dcn_ip->max_num_dpp = 3; 1408 } 1409 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1410 dc->dcn_soc->urgent_latency = 3; 1411 dc->debug.disable_dmcu = true; 1412 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1413 } 1414 1415 1416 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1417 ASSERT(dc->dcn_soc->number_of_channels < 3); 1418 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1419 dc->dcn_soc->number_of_channels = 2; 1420 1421 if (dc->dcn_soc->number_of_channels == 1) { 1422 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1423 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1424 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1425 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1426 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1427 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1428 } 1429 } 1430 1431 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1432 1433 /* 1434 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * 1435 * implemented. So AZ D3 should work.For issue 197007. * 1436 */ 1437 if (pool->base.pp_smu != NULL 1438 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) 1439 dc->debug.az_endpoint_mute_only = false; 1440 1441 if (!dc->debug.disable_pplib_clock_request) 1442 dcn_bw_update_from_pplib(dc); 1443 dcn_bw_sync_calcs_and_dml(dc); 1444 if (!dc->debug.disable_pplib_wm_range) { 1445 dc->res_pool = &pool->base; 1446 dcn_bw_notify_pplib_of_wm_ranges(dc); 1447 } 1448 1449 { 1450 struct irq_service_init_data init_data; 1451 init_data.ctx = dc->ctx; 1452 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1453 if (!pool->base.irqs) 1454 goto fail; 1455 } 1456 1457 /* index to valid pipe resource */ 1458 j = 0; 1459 /* mem input -> ipp -> dpp -> opp -> TG */ 1460 for (i = 0; i < pool->base.pipe_count; i++) { 1461 /* if pipe is disabled, skip instance of HW pipe, 1462 * i.e, skip ASIC register instance 1463 */ 1464 if ((pipe_fuses & (1 << i)) != 0) 1465 continue; 1466 1467 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1468 if (pool->base.hubps[j] == NULL) { 1469 BREAK_TO_DEBUGGER(); 1470 dm_error( 1471 "DC: failed to create memory input!\n"); 1472 goto fail; 1473 } 1474 1475 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1476 if (pool->base.ipps[j] == NULL) { 1477 BREAK_TO_DEBUGGER(); 1478 dm_error( 1479 "DC: failed to create input pixel processor!\n"); 1480 goto fail; 1481 } 1482 1483 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1484 if (pool->base.dpps[j] == NULL) { 1485 BREAK_TO_DEBUGGER(); 1486 dm_error( 1487 "DC: failed to create dpp!\n"); 1488 goto fail; 1489 } 1490 1491 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1492 if (pool->base.opps[j] == NULL) { 1493 BREAK_TO_DEBUGGER(); 1494 dm_error( 1495 "DC: failed to create output pixel processor!\n"); 1496 goto fail; 1497 } 1498 1499 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1500 ctx, i); 1501 if (pool->base.timing_generators[j] == NULL) { 1502 BREAK_TO_DEBUGGER(); 1503 dm_error("DC: failed to create tg!\n"); 1504 goto fail; 1505 } 1506 /* check next valid pipe */ 1507 j++; 1508 } 1509 1510 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1511 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1512 if (pool->base.engines[i] == NULL) { 1513 BREAK_TO_DEBUGGER(); 1514 dm_error( 1515 "DC:failed to create aux engine!!\n"); 1516 goto fail; 1517 } 1518 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1519 if (pool->base.hw_i2cs[i] == NULL) { 1520 BREAK_TO_DEBUGGER(); 1521 dm_error( 1522 "DC:failed to create hw i2c!!\n"); 1523 goto fail; 1524 } 1525 pool->base.sw_i2cs[i] = NULL; 1526 } 1527 1528 /* valid pipe num */ 1529 pool->base.pipe_count = j; 1530 pool->base.timing_generator_count = j; 1531 1532 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1533 * the value may be changed 1534 */ 1535 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1536 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1537 1538 pool->base.mpc = dcn10_mpc_create(ctx); 1539 if (pool->base.mpc == NULL) { 1540 BREAK_TO_DEBUGGER(); 1541 dm_error("DC: failed to create mpc!\n"); 1542 goto fail; 1543 } 1544 1545 pool->base.hubbub = dcn10_hubbub_create(ctx); 1546 if (pool->base.hubbub == NULL) { 1547 BREAK_TO_DEBUGGER(); 1548 dm_error("DC: failed to create hubbub!\n"); 1549 goto fail; 1550 } 1551 1552 if (!resource_construct(num_virtual_links, dc, &pool->base, 1553 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1554 &res_create_funcs : &res_create_maximus_funcs))) 1555 goto fail; 1556 1557 dcn10_hw_sequencer_construct(dc); 1558 dc->caps.max_planes = pool->base.pipe_count; 1559 1560 for (i = 0; i < dc->caps.max_planes; ++i) 1561 dc->caps.planes[i] = plane_cap; 1562 1563 dc->cap_funcs = cap_funcs; 1564 1565 return true; 1566 1567 fail: 1568 1569 destruct(pool); 1570 1571 return false; 1572 } 1573 1574 struct resource_pool *dcn10_create_resource_pool( 1575 const struct dc_init_data *init_data, 1576 struct dc *dc) 1577 { 1578 struct dcn10_resource_pool *pool = 1579 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1580 1581 if (!pool) 1582 return NULL; 1583 1584 if (construct(init_data->num_virtual_links, dc, pool)) 1585 return &pool->base; 1586 1587 kfree(pool); 1588 BREAK_TO_DEBUGGER(); 1589 return NULL; 1590 } 1591