1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 29 #include "resource.h" 30 #include "include/irq_service_interface.h" 31 #include "dcn10_resource.h" 32 33 #include "dcn10_ipp.h" 34 #include "dcn10_mpc.h" 35 #include "irq/dcn10/irq_service_dcn10.h" 36 #include "dcn10_dpp.h" 37 #include "dcn10_optc.h" 38 #include "dcn10_hw_sequencer.h" 39 #include "dce110/dce110_hw_sequencer.h" 40 #include "dcn10_opp.h" 41 #include "dcn10_link_encoder.h" 42 #include "dcn10_stream_encoder.h" 43 #include "dcn10_clk_mgr.h" 44 #include "dce/dce_clock_source.h" 45 #include "dce/dce_audio.h" 46 #include "dce/dce_hwseq.h" 47 #include "virtual/virtual_stream_encoder.h" 48 #include "dce110/dce110_resource.h" 49 #include "dce112/dce112_resource.h" 50 #include "dcn10_hubp.h" 51 #include "dcn10_hubbub.h" 52 53 #include "soc15_hw_ip.h" 54 #include "vega10_ip_offset.h" 55 56 #include "dcn/dcn_1_0_offset.h" 57 #include "dcn/dcn_1_0_sh_mask.h" 58 59 #include "nbio/nbio_7_0_offset.h" 60 61 #include "mmhub/mmhub_9_1_offset.h" 62 #include "mmhub/mmhub_9_1_sh_mask.h" 63 64 #include "reg_helper.h" 65 #include "dce/dce_abm.h" 66 #include "dce/dce_dmcu.h" 67 #include "dce/dce_aux.h" 68 #include "dce/dce_i2c.h" 69 70 const struct _vcs_dpi_ip_params_st dcn1_0_ip = { 71 .rob_buffer_size_kbytes = 64, 72 .det_buffer_size_kbytes = 164, 73 .dpte_buffer_size_in_pte_reqs_luma = 42, 74 .dpp_output_buffer_pixels = 2560, 75 .opp_output_buffer_lines = 1, 76 .pixel_chunk_size_kbytes = 8, 77 .pte_enable = 1, 78 .pte_chunk_size_kbytes = 2, 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 2, 81 .line_buffer_size_bits = 589824, 82 .max_line_buffer_lines = 12, 83 .IsLineBufferBppFixed = 0, 84 .LineBufferFixedBpp = -1, 85 .writeback_luma_buffer_size_kbytes = 12, 86 .writeback_chroma_buffer_size_kbytes = 8, 87 .max_num_dpp = 4, 88 .max_num_wb = 2, 89 .max_dchub_pscl_bw_pix_per_clk = 4, 90 .max_pscl_lb_bw_pix_per_clk = 2, 91 .max_lb_vscl_bw_pix_per_clk = 4, 92 .max_vscl_hscl_bw_pix_per_clk = 4, 93 .max_hscl_ratio = 4, 94 .max_vscl_ratio = 4, 95 .hscl_mults = 4, 96 .vscl_mults = 4, 97 .max_hscl_taps = 8, 98 .max_vscl_taps = 8, 99 .dispclk_ramp_margin_percent = 1, 100 .underscan_factor = 1.10, 101 .min_vblank_lines = 14, 102 .dppclk_delay_subtotal = 90, 103 .dispclk_delay_subtotal = 42, 104 .dcfclk_cstate_latency = 10, 105 .max_inter_dcn_tile_repeaters = 8, 106 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, 107 .bug_forcing_LC_req_same_size_fixed = 0, 108 }; 109 110 const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { 111 .sr_exit_time_us = 9.0, 112 .sr_enter_plus_exit_time_us = 11.0, 113 .urgent_latency_us = 4.0, 114 .writeback_latency_us = 12.0, 115 .ideal_dram_bw_after_urgent_percent = 80.0, 116 .max_request_size_bytes = 256, 117 .downspread_percent = 0.5, 118 .dram_page_open_time_ns = 50.0, 119 .dram_rw_turnaround_time_ns = 17.5, 120 .dram_return_buffer_per_channel_bytes = 8192, 121 .round_trip_ping_latency_dcfclk_cycles = 128, 122 .urgent_out_of_order_return_per_channel_bytes = 256, 123 .channel_interleave_bytes = 256, 124 .num_banks = 8, 125 .num_chans = 2, 126 .vmm_page_size_bytes = 4096, 127 .dram_clock_change_latency_us = 17.0, 128 .writeback_dram_clock_change_latency_us = 23.0, 129 .return_bus_width_bytes = 64, 130 }; 131 132 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 133 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 134 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 135 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 136 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 137 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 138 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 139 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 140 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 141 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 142 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 143 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 144 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 145 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 146 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 147 #endif 148 149 150 enum dcn10_clk_src_array_id { 151 DCN10_CLK_SRC_PLL0, 152 DCN10_CLK_SRC_PLL1, 153 DCN10_CLK_SRC_PLL2, 154 DCN10_CLK_SRC_PLL3, 155 DCN10_CLK_SRC_TOTAL, 156 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 157 DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 158 #endif 159 }; 160 161 /* begin ********************* 162 * macros to expend register list macro defined in HW object header file */ 163 164 /* DCN */ 165 #define BASE_INNER(seg) \ 166 DCE_BASE__INST0_SEG ## seg 167 168 #define BASE(seg) \ 169 BASE_INNER(seg) 170 171 #define SR(reg_name)\ 172 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 173 mm ## reg_name 174 175 #define SRI(reg_name, block, id)\ 176 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 177 mm ## block ## id ## _ ## reg_name 178 179 180 #define SRII(reg_name, block, id)\ 181 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 mm ## block ## id ## _ ## reg_name 183 184 /* NBIO */ 185 #define NBIO_BASE_INNER(seg) \ 186 NBIF_BASE__INST0_SEG ## seg 187 188 #define NBIO_BASE(seg) \ 189 NBIO_BASE_INNER(seg) 190 191 #define NBIO_SR(reg_name)\ 192 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 193 mm ## reg_name 194 195 /* MMHUB */ 196 #define MMHUB_BASE_INNER(seg) \ 197 MMHUB_BASE__INST0_SEG ## seg 198 199 #define MMHUB_BASE(seg) \ 200 MMHUB_BASE_INNER(seg) 201 202 #define MMHUB_SR(reg_name)\ 203 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ 204 mm ## reg_name 205 /* macros to expend register list macro defined in HW object header file 206 * end *********************/ 207 208 209 static const struct dce_dmcu_registers dmcu_regs = { 210 DMCU_DCN10_REG_LIST() 211 }; 212 213 static const struct dce_dmcu_shift dmcu_shift = { 214 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 215 }; 216 217 static const struct dce_dmcu_mask dmcu_mask = { 218 DMCU_MASK_SH_LIST_DCN10(_MASK) 219 }; 220 221 static const struct dce_abm_registers abm_regs = { 222 ABM_DCN10_REG_LIST(0) 223 }; 224 225 static const struct dce_abm_shift abm_shift = { 226 ABM_MASK_SH_LIST_DCN10(__SHIFT) 227 }; 228 229 static const struct dce_abm_mask abm_mask = { 230 ABM_MASK_SH_LIST_DCN10(_MASK) 231 }; 232 233 #define stream_enc_regs(id)\ 234 [id] = {\ 235 SE_DCN_REG_LIST(id)\ 236 } 237 238 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 239 stream_enc_regs(0), 240 stream_enc_regs(1), 241 stream_enc_regs(2), 242 stream_enc_regs(3), 243 }; 244 245 static const struct dcn10_stream_encoder_shift se_shift = { 246 SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) 247 }; 248 249 static const struct dcn10_stream_encoder_mask se_mask = { 250 SE_COMMON_MASK_SH_LIST_DCN10(_MASK) 251 }; 252 253 #define audio_regs(id)\ 254 [id] = {\ 255 AUD_COMMON_REG_LIST(id)\ 256 } 257 258 static const struct dce_audio_registers audio_regs[] = { 259 audio_regs(0), 260 audio_regs(1), 261 audio_regs(2), 262 audio_regs(3), 263 }; 264 265 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 266 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 267 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 268 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 269 270 static const struct dce_audio_shift audio_shift = { 271 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dce_aduio_mask audio_mask = { 275 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 276 }; 277 278 #define aux_regs(id)\ 279 [id] = {\ 280 AUX_REG_LIST(id)\ 281 } 282 283 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 284 aux_regs(0), 285 aux_regs(1), 286 aux_regs(2), 287 aux_regs(3) 288 }; 289 290 #define hpd_regs(id)\ 291 [id] = {\ 292 HPD_REG_LIST(id)\ 293 } 294 295 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 296 hpd_regs(0), 297 hpd_regs(1), 298 hpd_regs(2), 299 hpd_regs(3) 300 }; 301 302 #define link_regs(id)\ 303 [id] = {\ 304 LE_DCN10_REG_LIST(id), \ 305 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 306 } 307 308 static const struct dcn10_link_enc_registers link_enc_regs[] = { 309 link_regs(0), 310 link_regs(1), 311 link_regs(2), 312 link_regs(3) 313 }; 314 315 static const struct dcn10_link_enc_shift le_shift = { 316 LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) 317 }; 318 319 static const struct dcn10_link_enc_mask le_mask = { 320 LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) 321 }; 322 323 #define ipp_regs(id)\ 324 [id] = {\ 325 IPP_REG_LIST_DCN10(id),\ 326 } 327 328 static const struct dcn10_ipp_registers ipp_regs[] = { 329 ipp_regs(0), 330 ipp_regs(1), 331 ipp_regs(2), 332 ipp_regs(3), 333 }; 334 335 static const struct dcn10_ipp_shift ipp_shift = { 336 IPP_MASK_SH_LIST_DCN10(__SHIFT) 337 }; 338 339 static const struct dcn10_ipp_mask ipp_mask = { 340 IPP_MASK_SH_LIST_DCN10(_MASK), 341 }; 342 343 #define opp_regs(id)\ 344 [id] = {\ 345 OPP_REG_LIST_DCN10(id),\ 346 } 347 348 static const struct dcn10_opp_registers opp_regs[] = { 349 opp_regs(0), 350 opp_regs(1), 351 opp_regs(2), 352 opp_regs(3), 353 }; 354 355 static const struct dcn10_opp_shift opp_shift = { 356 OPP_MASK_SH_LIST_DCN10(__SHIFT) 357 }; 358 359 static const struct dcn10_opp_mask opp_mask = { 360 OPP_MASK_SH_LIST_DCN10(_MASK), 361 }; 362 363 #define aux_engine_regs(id)\ 364 [id] = {\ 365 AUX_COMMON_REG_LIST(id), \ 366 .AUX_RESET_MASK = 0 \ 367 } 368 369 static const struct dce110_aux_registers aux_engine_regs[] = { 370 aux_engine_regs(0), 371 aux_engine_regs(1), 372 aux_engine_regs(2), 373 aux_engine_regs(3), 374 aux_engine_regs(4), 375 aux_engine_regs(5) 376 }; 377 378 #define tf_regs(id)\ 379 [id] = {\ 380 TF_REG_LIST_DCN10(id),\ 381 } 382 383 static const struct dcn_dpp_registers tf_regs[] = { 384 tf_regs(0), 385 tf_regs(1), 386 tf_regs(2), 387 tf_regs(3), 388 }; 389 390 static const struct dcn_dpp_shift tf_shift = { 391 TF_REG_LIST_SH_MASK_DCN10(__SHIFT), 392 TF_DEBUG_REG_LIST_SH_DCN10 393 394 }; 395 396 static const struct dcn_dpp_mask tf_mask = { 397 TF_REG_LIST_SH_MASK_DCN10(_MASK), 398 TF_DEBUG_REG_LIST_MASK_DCN10 399 }; 400 401 static const struct dcn_mpc_registers mpc_regs = { 402 MPC_COMMON_REG_LIST_DCN1_0(0), 403 MPC_COMMON_REG_LIST_DCN1_0(1), 404 MPC_COMMON_REG_LIST_DCN1_0(2), 405 MPC_COMMON_REG_LIST_DCN1_0(3), 406 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), 407 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), 408 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), 409 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) 410 }; 411 412 static const struct dcn_mpc_shift mpc_shift = { 413 MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 414 }; 415 416 static const struct dcn_mpc_mask mpc_mask = { 417 MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), 418 }; 419 420 #define tg_regs(id)\ 421 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} 422 423 static const struct dcn_optc_registers tg_regs[] = { 424 tg_regs(0), 425 tg_regs(1), 426 tg_regs(2), 427 tg_regs(3), 428 }; 429 430 static const struct dcn_optc_shift tg_shift = { 431 TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 432 }; 433 434 static const struct dcn_optc_mask tg_mask = { 435 TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 436 }; 437 438 static const struct bios_registers bios_regs = { 439 NBIO_SR(BIOS_SCRATCH_3), 440 NBIO_SR(BIOS_SCRATCH_6) 441 }; 442 443 #define hubp_regs(id)\ 444 [id] = {\ 445 HUBP_REG_LIST_DCN10(id)\ 446 } 447 448 449 static const struct dcn_mi_registers hubp_regs[] = { 450 hubp_regs(0), 451 hubp_regs(1), 452 hubp_regs(2), 453 hubp_regs(3), 454 }; 455 456 static const struct dcn_mi_shift hubp_shift = { 457 HUBP_MASK_SH_LIST_DCN10(__SHIFT) 458 }; 459 460 static const struct dcn_mi_mask hubp_mask = { 461 HUBP_MASK_SH_LIST_DCN10(_MASK) 462 }; 463 464 465 static const struct dcn_hubbub_registers hubbub_reg = { 466 HUBBUB_REG_LIST_DCN10(0) 467 }; 468 469 static const struct dcn_hubbub_shift hubbub_shift = { 470 HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) 471 }; 472 473 static const struct dcn_hubbub_mask hubbub_mask = { 474 HUBBUB_MASK_SH_LIST_DCN10(_MASK) 475 }; 476 477 #define clk_src_regs(index, pllid)\ 478 [index] = {\ 479 CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ 480 } 481 482 static const struct dce110_clk_src_regs clk_src_regs[] = { 483 clk_src_regs(0, A), 484 clk_src_regs(1, B), 485 clk_src_regs(2, C), 486 clk_src_regs(3, D) 487 }; 488 489 static const struct dce110_clk_src_shift cs_shift = { 490 CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) 491 }; 492 493 static const struct dce110_clk_src_mask cs_mask = { 494 CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) 495 }; 496 497 static const struct resource_caps res_cap = { 498 .num_timing_generator = 4, 499 .num_opp = 4, 500 .num_video_plane = 4, 501 .num_audio = 4, 502 .num_stream_encoder = 4, 503 .num_pll = 4, 504 .num_ddc = 4, 505 }; 506 507 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 508 static const struct resource_caps rv2_res_cap = { 509 .num_timing_generator = 3, 510 .num_opp = 3, 511 .num_video_plane = 3, 512 .num_audio = 3, 513 .num_stream_encoder = 3, 514 .num_pll = 3, 515 .num_ddc = 3, 516 }; 517 #endif 518 519 static const struct dc_plane_cap plane_cap = { 520 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 521 .blends_with_above = true, 522 .blends_with_below = true, 523 .per_pixel_alpha = true, 524 525 .pixel_format_support = { 526 .argb8888 = true, 527 .nv12 = true, 528 .fp16 = true 529 }, 530 531 .max_upscale_factor = { 532 .argb8888 = 16000, 533 .nv12 = 16000, 534 .fp16 = 1 535 }, 536 537 .max_downscale_factor = { 538 .argb8888 = 250, 539 .nv12 = 250, 540 .fp16 = 1 541 } 542 }; 543 544 static const struct dc_debug_options debug_defaults_drv = { 545 .sanity_checks = true, 546 .disable_dmcu = true, 547 .force_abm_enable = false, 548 .timing_trace = false, 549 .clock_trace = true, 550 551 /* raven smu dones't allow 0 disp clk, 552 * smu min disp clk limit is 50Mhz 553 * keep min disp clk 100Mhz avoid smu hang 554 */ 555 .min_disp_clk_khz = 100000, 556 557 .disable_pplib_clock_request = false, 558 .disable_pplib_wm_range = false, 559 .pplib_wm_report_mode = WM_REPORT_DEFAULT, 560 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 561 .force_single_disp_pipe_split = true, 562 .disable_dcc = DCC_ENABLE, 563 .voltage_align_fclk = true, 564 .disable_stereo_support = true, 565 .vsr_support = true, 566 .performance_trace = false, 567 .az_endpoint_mute_only = true, 568 .recovery_enabled = false, /*enable this by default after testing.*/ 569 .max_downscale_src_width = 3840, 570 }; 571 572 static const struct dc_debug_options debug_defaults_diags = { 573 .disable_dmcu = true, 574 .force_abm_enable = false, 575 .timing_trace = true, 576 .clock_trace = true, 577 .disable_stutter = true, 578 .disable_pplib_clock_request = true, 579 .disable_pplib_wm_range = true 580 }; 581 582 static void dcn10_dpp_destroy(struct dpp **dpp) 583 { 584 kfree(TO_DCN10_DPP(*dpp)); 585 *dpp = NULL; 586 } 587 588 static struct dpp *dcn10_dpp_create( 589 struct dc_context *ctx, 590 uint32_t inst) 591 { 592 struct dcn10_dpp *dpp = 593 kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); 594 595 if (!dpp) 596 return NULL; 597 598 dpp1_construct(dpp, ctx, inst, 599 &tf_regs[inst], &tf_shift, &tf_mask); 600 return &dpp->base; 601 } 602 603 static struct input_pixel_processor *dcn10_ipp_create( 604 struct dc_context *ctx, uint32_t inst) 605 { 606 struct dcn10_ipp *ipp = 607 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); 608 609 if (!ipp) { 610 BREAK_TO_DEBUGGER(); 611 return NULL; 612 } 613 614 dcn10_ipp_construct(ipp, ctx, inst, 615 &ipp_regs[inst], &ipp_shift, &ipp_mask); 616 return &ipp->base; 617 } 618 619 620 static struct output_pixel_processor *dcn10_opp_create( 621 struct dc_context *ctx, uint32_t inst) 622 { 623 struct dcn10_opp *opp = 624 kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); 625 626 if (!opp) { 627 BREAK_TO_DEBUGGER(); 628 return NULL; 629 } 630 631 dcn10_opp_construct(opp, ctx, inst, 632 &opp_regs[inst], &opp_shift, &opp_mask); 633 return &opp->base; 634 } 635 636 struct dce_aux *dcn10_aux_engine_create( 637 struct dc_context *ctx, 638 uint32_t inst) 639 { 640 struct aux_engine_dce110 *aux_engine = 641 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 642 643 if (!aux_engine) 644 return NULL; 645 646 dce110_aux_engine_construct(aux_engine, ctx, inst, 647 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 648 &aux_engine_regs[inst]); 649 650 return &aux_engine->base; 651 } 652 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 653 654 static const struct dce_i2c_registers i2c_hw_regs[] = { 655 i2c_inst_regs(1), 656 i2c_inst_regs(2), 657 i2c_inst_regs(3), 658 i2c_inst_regs(4), 659 i2c_inst_regs(5), 660 i2c_inst_regs(6), 661 }; 662 663 static const struct dce_i2c_shift i2c_shifts = { 664 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 665 }; 666 667 static const struct dce_i2c_mask i2c_masks = { 668 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 669 }; 670 671 struct dce_i2c_hw *dcn10_i2c_hw_create( 672 struct dc_context *ctx, 673 uint32_t inst) 674 { 675 struct dce_i2c_hw *dce_i2c_hw = 676 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 677 678 if (!dce_i2c_hw) 679 return NULL; 680 681 dcn1_i2c_hw_construct(dce_i2c_hw, ctx, inst, 682 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 683 684 return dce_i2c_hw; 685 } 686 static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 687 { 688 struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), 689 GFP_KERNEL); 690 691 if (!mpc10) 692 return NULL; 693 694 dcn10_mpc_construct(mpc10, ctx, 695 &mpc_regs, 696 &mpc_shift, 697 &mpc_mask, 698 4); 699 700 return &mpc10->base; 701 } 702 703 static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) 704 { 705 struct dcn10_hubbub *dcn10_hubbub = kzalloc(sizeof(struct dcn10_hubbub), 706 GFP_KERNEL); 707 708 if (!dcn10_hubbub) 709 return NULL; 710 711 hubbub1_construct(&dcn10_hubbub->base, ctx, 712 &hubbub_reg, 713 &hubbub_shift, 714 &hubbub_mask); 715 716 return &dcn10_hubbub->base; 717 } 718 719 static struct timing_generator *dcn10_timing_generator_create( 720 struct dc_context *ctx, 721 uint32_t instance) 722 { 723 struct optc *tgn10 = 724 kzalloc(sizeof(struct optc), GFP_KERNEL); 725 726 if (!tgn10) 727 return NULL; 728 729 tgn10->base.inst = instance; 730 tgn10->base.ctx = ctx; 731 732 tgn10->tg_regs = &tg_regs[instance]; 733 tgn10->tg_shift = &tg_shift; 734 tgn10->tg_mask = &tg_mask; 735 736 dcn10_timing_generator_init(tgn10); 737 738 return &tgn10->base; 739 } 740 741 static const struct encoder_feature_support link_enc_feature = { 742 .max_hdmi_deep_color = COLOR_DEPTH_121212, 743 .max_hdmi_pixel_clock = 600000, 744 .hdmi_ycbcr420_supported = true, 745 .dp_ycbcr420_supported = false, 746 .flags.bits.IS_HBR2_CAPABLE = true, 747 .flags.bits.IS_HBR3_CAPABLE = true, 748 .flags.bits.IS_TPS3_CAPABLE = true, 749 .flags.bits.IS_TPS4_CAPABLE = true 750 }; 751 752 struct link_encoder *dcn10_link_encoder_create( 753 const struct encoder_init_data *enc_init_data) 754 { 755 struct dcn10_link_encoder *enc10 = 756 kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL); 757 758 if (!enc10) 759 return NULL; 760 761 dcn10_link_encoder_construct(enc10, 762 enc_init_data, 763 &link_enc_feature, 764 &link_enc_regs[enc_init_data->transmitter], 765 &link_enc_aux_regs[enc_init_data->channel - 1], 766 &link_enc_hpd_regs[enc_init_data->hpd_source], 767 &le_shift, 768 &le_mask); 769 770 return &enc10->base; 771 } 772 773 struct clock_source *dcn10_clock_source_create( 774 struct dc_context *ctx, 775 struct dc_bios *bios, 776 enum clock_source_id id, 777 const struct dce110_clk_src_regs *regs, 778 bool dp_clk_src) 779 { 780 struct dce110_clk_src *clk_src = 781 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 782 783 if (!clk_src) 784 return NULL; 785 786 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 787 regs, &cs_shift, &cs_mask)) { 788 clk_src->base.dp_clk_src = dp_clk_src; 789 return &clk_src->base; 790 } 791 792 BREAK_TO_DEBUGGER(); 793 return NULL; 794 } 795 796 static void read_dce_straps( 797 struct dc_context *ctx, 798 struct resource_straps *straps) 799 { 800 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 801 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 802 } 803 804 static struct audio *create_audio( 805 struct dc_context *ctx, unsigned int inst) 806 { 807 return dce_audio_create(ctx, inst, 808 &audio_regs[inst], &audio_shift, &audio_mask); 809 } 810 811 static struct stream_encoder *dcn10_stream_encoder_create( 812 enum engine_id eng_id, 813 struct dc_context *ctx) 814 { 815 struct dcn10_stream_encoder *enc1 = 816 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 817 818 if (!enc1) 819 return NULL; 820 821 dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 822 &stream_enc_regs[eng_id], 823 &se_shift, &se_mask); 824 return &enc1->base; 825 } 826 827 static const struct dce_hwseq_registers hwseq_reg = { 828 HWSEQ_DCN1_REG_LIST() 829 }; 830 831 static const struct dce_hwseq_shift hwseq_shift = { 832 HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) 833 }; 834 835 static const struct dce_hwseq_mask hwseq_mask = { 836 HWSEQ_DCN1_MASK_SH_LIST(_MASK) 837 }; 838 839 static struct dce_hwseq *dcn10_hwseq_create( 840 struct dc_context *ctx) 841 { 842 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 843 844 if (hws) { 845 hws->ctx = ctx; 846 hws->regs = &hwseq_reg; 847 hws->shifts = &hwseq_shift; 848 hws->masks = &hwseq_mask; 849 hws->wa.DEGVIDCN10_253 = true; 850 hws->wa.false_optc_underflow = true; 851 hws->wa.DEGVIDCN10_254 = true; 852 } 853 return hws; 854 } 855 856 static const struct resource_create_funcs res_create_funcs = { 857 .read_dce_straps = read_dce_straps, 858 .create_audio = create_audio, 859 .create_stream_encoder = dcn10_stream_encoder_create, 860 .create_hwseq = dcn10_hwseq_create, 861 }; 862 863 static const struct resource_create_funcs res_create_maximus_funcs = { 864 .read_dce_straps = NULL, 865 .create_audio = NULL, 866 .create_stream_encoder = NULL, 867 .create_hwseq = dcn10_hwseq_create, 868 }; 869 870 void dcn10_clock_source_destroy(struct clock_source **clk_src) 871 { 872 kfree(TO_DCE110_CLK_SRC(*clk_src)); 873 *clk_src = NULL; 874 } 875 876 static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) 877 { 878 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); 879 880 if (!pp_smu) 881 return pp_smu; 882 883 dm_pp_get_funcs(ctx, pp_smu); 884 return pp_smu; 885 } 886 887 static void destruct(struct dcn10_resource_pool *pool) 888 { 889 unsigned int i; 890 891 for (i = 0; i < pool->base.stream_enc_count; i++) { 892 if (pool->base.stream_enc[i] != NULL) { 893 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 894 pool->base.stream_enc[i] = NULL; 895 } 896 } 897 898 if (pool->base.mpc != NULL) { 899 kfree(TO_DCN10_MPC(pool->base.mpc)); 900 pool->base.mpc = NULL; 901 } 902 903 if (pool->base.hubbub != NULL) { 904 kfree(pool->base.hubbub); 905 pool->base.hubbub = NULL; 906 } 907 908 for (i = 0; i < pool->base.pipe_count; i++) { 909 if (pool->base.opps[i] != NULL) 910 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 911 912 if (pool->base.dpps[i] != NULL) 913 dcn10_dpp_destroy(&pool->base.dpps[i]); 914 915 if (pool->base.ipps[i] != NULL) 916 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 917 918 if (pool->base.hubps[i] != NULL) { 919 kfree(TO_DCN10_HUBP(pool->base.hubps[i])); 920 pool->base.hubps[i] = NULL; 921 } 922 923 if (pool->base.irqs != NULL) { 924 dal_irq_service_destroy(&pool->base.irqs); 925 } 926 927 if (pool->base.timing_generators[i] != NULL) { 928 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 929 pool->base.timing_generators[i] = NULL; 930 } 931 } 932 933 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 934 if (pool->base.engines[i] != NULL) 935 dce110_engine_destroy(&pool->base.engines[i]); 936 if (pool->base.hw_i2cs[i] != NULL) { 937 kfree(pool->base.hw_i2cs[i]); 938 pool->base.hw_i2cs[i] = NULL; 939 } 940 if (pool->base.sw_i2cs[i] != NULL) { 941 kfree(pool->base.sw_i2cs[i]); 942 pool->base.sw_i2cs[i] = NULL; 943 } 944 } 945 946 for (i = 0; i < pool->base.audio_count; i++) { 947 if (pool->base.audios[i]) 948 dce_aud_destroy(&pool->base.audios[i]); 949 } 950 951 for (i = 0; i < pool->base.clk_src_count; i++) { 952 if (pool->base.clock_sources[i] != NULL) { 953 dcn10_clock_source_destroy(&pool->base.clock_sources[i]); 954 pool->base.clock_sources[i] = NULL; 955 } 956 } 957 958 if (pool->base.dp_clock_source != NULL) { 959 dcn10_clock_source_destroy(&pool->base.dp_clock_source); 960 pool->base.dp_clock_source = NULL; 961 } 962 963 if (pool->base.abm != NULL) 964 dce_abm_destroy(&pool->base.abm); 965 966 if (pool->base.dmcu != NULL) 967 dce_dmcu_destroy(&pool->base.dmcu); 968 969 if (pool->base.clk_mgr != NULL) 970 dce_clk_mgr_destroy(&pool->base.clk_mgr); 971 972 kfree(pool->base.pp_smu); 973 } 974 975 static struct hubp *dcn10_hubp_create( 976 struct dc_context *ctx, 977 uint32_t inst) 978 { 979 struct dcn10_hubp *hubp1 = 980 kzalloc(sizeof(struct dcn10_hubp), GFP_KERNEL); 981 982 if (!hubp1) 983 return NULL; 984 985 dcn10_hubp_construct(hubp1, ctx, inst, 986 &hubp_regs[inst], &hubp_shift, &hubp_mask); 987 return &hubp1->base; 988 } 989 990 static void get_pixel_clock_parameters( 991 const struct pipe_ctx *pipe_ctx, 992 struct pixel_clk_params *pixel_clk_params) 993 { 994 const struct dc_stream_state *stream = pipe_ctx->stream; 995 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 996 pixel_clk_params->encoder_object_id = stream->link->link_enc->id; 997 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 998 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 999 /* TODO: un-hardcode*/ 1000 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1001 LINK_RATE_REF_FREQ_IN_KHZ; 1002 pixel_clk_params->flags.ENABLE_SS = 0; 1003 pixel_clk_params->color_depth = 1004 stream->timing.display_color_depth; 1005 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1006 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1007 1008 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1009 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1010 1011 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1012 pixel_clk_params->requested_pix_clk_100hz /= 2; 1013 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1014 pixel_clk_params->requested_pix_clk_100hz *= 2; 1015 1016 } 1017 1018 static void build_clamping_params(struct dc_stream_state *stream) 1019 { 1020 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1021 stream->clamping.c_depth = stream->timing.display_color_depth; 1022 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1023 } 1024 1025 static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1026 { 1027 1028 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1029 1030 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1031 pipe_ctx->clock_source, 1032 &pipe_ctx->stream_res.pix_clk_params, 1033 &pipe_ctx->pll_settings); 1034 1035 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1036 1037 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1038 &pipe_ctx->stream->bit_depth_params); 1039 build_clamping_params(pipe_ctx->stream); 1040 } 1041 1042 static enum dc_status build_mapped_resource( 1043 const struct dc *dc, 1044 struct dc_state *context, 1045 struct dc_stream_state *stream) 1046 { 1047 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 1048 1049 /*TODO Seems unneeded anymore */ 1050 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { 1051 if (stream != NULL && old_context->streams[i] != NULL) { 1052 todo: shouldn't have to copy missing parameter here 1053 resource_build_bit_depth_reduction_params(stream, 1054 &stream->bit_depth_params); 1055 stream->clamping.pixel_encoding = 1056 stream->timing.pixel_encoding; 1057 1058 resource_build_bit_depth_reduction_params(stream, 1059 &stream->bit_depth_params); 1060 build_clamping_params(stream); 1061 1062 continue; 1063 } 1064 } 1065 */ 1066 1067 if (!pipe_ctx) 1068 return DC_ERROR_UNEXPECTED; 1069 1070 build_pipe_hw_param(pipe_ctx); 1071 return DC_OK; 1072 } 1073 1074 enum dc_status dcn10_add_stream_to_ctx( 1075 struct dc *dc, 1076 struct dc_state *new_ctx, 1077 struct dc_stream_state *dc_stream) 1078 { 1079 enum dc_status result = DC_ERROR_UNEXPECTED; 1080 1081 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1082 1083 if (result == DC_OK) 1084 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1085 1086 1087 if (result == DC_OK) 1088 result = build_mapped_resource(dc, new_ctx, dc_stream); 1089 1090 return result; 1091 } 1092 1093 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( 1094 struct dc_state *context, 1095 const struct resource_pool *pool, 1096 struct dc_stream_state *stream) 1097 { 1098 struct resource_context *res_ctx = &context->res_ctx; 1099 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); 1100 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); 1101 1102 if (!head_pipe) { 1103 ASSERT(0); 1104 return NULL; 1105 } 1106 1107 if (!idle_pipe) 1108 return NULL; 1109 1110 idle_pipe->stream = head_pipe->stream; 1111 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; 1112 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; 1113 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; 1114 1115 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; 1116 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; 1117 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; 1118 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; 1119 1120 return idle_pipe; 1121 } 1122 1123 static bool dcn10_get_dcc_compression_cap(const struct dc *dc, 1124 const struct dc_dcc_surface_param *input, 1125 struct dc_surface_dcc_cap *output) 1126 { 1127 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 1128 dc->res_pool->hubbub, 1129 input, 1130 output); 1131 } 1132 1133 static void dcn10_destroy_resource_pool(struct resource_pool **pool) 1134 { 1135 struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); 1136 1137 destruct(dcn10_pool); 1138 kfree(dcn10_pool); 1139 *pool = NULL; 1140 } 1141 1142 static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) 1143 { 1144 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN 1145 && caps->max_video_width != 0 1146 && plane_state->src_rect.width > caps->max_video_width) 1147 return DC_FAIL_SURFACE_VALIDATE; 1148 1149 return DC_OK; 1150 } 1151 1152 static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) 1153 { 1154 int i, j; 1155 bool video_down_scaled = false; 1156 bool video_large = false; 1157 bool desktop_large = false; 1158 bool dcc_disabled = false; 1159 1160 for (i = 0; i < context->stream_count; i++) { 1161 if (context->stream_status[i].plane_count == 0) 1162 continue; 1163 1164 if (context->stream_status[i].plane_count > 2) 1165 return DC_FAIL_UNSUPPORTED_1; 1166 1167 for (j = 0; j < context->stream_status[i].plane_count; j++) { 1168 struct dc_plane_state *plane = 1169 context->stream_status[i].plane_states[j]; 1170 1171 1172 if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { 1173 1174 if (plane->src_rect.width > plane->dst_rect.width || 1175 plane->src_rect.height > plane->dst_rect.height) 1176 video_down_scaled = true; 1177 1178 if (plane->src_rect.width >= 3840) 1179 video_large = true; 1180 1181 } else { 1182 if (plane->src_rect.width >= 3840) 1183 desktop_large = true; 1184 if (!plane->dcc.enable) 1185 dcc_disabled = true; 1186 } 1187 } 1188 } 1189 1190 /* 1191 * Workaround: On DCN10 there is UMC issue that causes underflow when 1192 * playing 4k video on 4k desktop with video downscaled and single channel 1193 * memory 1194 */ 1195 if (video_large && desktop_large && video_down_scaled && dcc_disabled && 1196 dc->dcn_soc->number_of_channels == 1) 1197 return DC_FAIL_SURFACE_VALIDATE; 1198 1199 return DC_OK; 1200 } 1201 1202 static enum dc_status dcn10_get_default_swizzle_mode(struct dc_plane_state *plane_state) 1203 { 1204 enum dc_status result = DC_OK; 1205 1206 enum surface_pixel_format surf_pix_format = plane_state->format; 1207 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 1208 1209 enum swizzle_mode_values swizzle = DC_SW_LINEAR; 1210 1211 if (bpp == 64) 1212 swizzle = DC_SW_64KB_D; 1213 else 1214 swizzle = DC_SW_64KB_S; 1215 1216 plane_state->tiling_info.gfx9.swizzle = swizzle; 1217 return result; 1218 } 1219 1220 static const struct dc_cap_funcs cap_funcs = { 1221 .get_dcc_compression_cap = dcn10_get_dcc_compression_cap 1222 }; 1223 1224 static const struct resource_funcs dcn10_res_pool_funcs = { 1225 .destroy = dcn10_destroy_resource_pool, 1226 .link_enc_create = dcn10_link_encoder_create, 1227 .validate_bandwidth = dcn_validate_bandwidth, 1228 .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, 1229 .validate_plane = dcn10_validate_plane, 1230 .validate_global = dcn10_validate_global, 1231 .add_stream_to_ctx = dcn10_add_stream_to_ctx, 1232 .get_default_swizzle_mode = dcn10_get_default_swizzle_mode 1233 }; 1234 1235 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1236 { 1237 uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); 1238 /* RV1 support max 4 pipes */ 1239 value = value & 0xf; 1240 return value; 1241 } 1242 1243 static bool construct( 1244 uint8_t num_virtual_links, 1245 struct dc *dc, 1246 struct dcn10_resource_pool *pool) 1247 { 1248 int i; 1249 int j; 1250 struct dc_context *ctx = dc->ctx; 1251 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1252 1253 ctx->dc_bios->regs = &bios_regs; 1254 1255 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1256 if (ctx->dce_version == DCN_VERSION_1_01) 1257 pool->base.res_cap = &rv2_res_cap; 1258 else 1259 #endif 1260 pool->base.res_cap = &res_cap; 1261 pool->base.funcs = &dcn10_res_pool_funcs; 1262 1263 /* 1264 * TODO fill in from actual raven resource when we create 1265 * more than virtual encoder 1266 */ 1267 1268 /************************************************* 1269 * Resource + asic cap harcoding * 1270 *************************************************/ 1271 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1272 1273 /* max pipe num for ASIC before check pipe fuses */ 1274 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1275 1276 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1277 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1278 pool->base.pipe_count = 3; 1279 #endif 1280 dc->caps.max_video_width = 3840; 1281 dc->caps.max_downscale_ratio = 200; 1282 dc->caps.i2c_speed_in_khz = 100; 1283 dc->caps.max_cursor_size = 256; 1284 dc->caps.max_slave_planes = 1; 1285 dc->caps.is_apu = true; 1286 dc->caps.post_blend_color_processing = false; 1287 /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ 1288 dc->caps.force_dp_tps4_for_cp2520 = true; 1289 1290 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1291 dc->debug = debug_defaults_drv; 1292 else 1293 dc->debug = debug_defaults_diags; 1294 1295 /************************************************* 1296 * Create resources * 1297 *************************************************/ 1298 1299 pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = 1300 dcn10_clock_source_create(ctx, ctx->dc_bios, 1301 CLOCK_SOURCE_COMBO_PHY_PLL0, 1302 &clk_src_regs[0], false); 1303 pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = 1304 dcn10_clock_source_create(ctx, ctx->dc_bios, 1305 CLOCK_SOURCE_COMBO_PHY_PLL1, 1306 &clk_src_regs[1], false); 1307 pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = 1308 dcn10_clock_source_create(ctx, ctx->dc_bios, 1309 CLOCK_SOURCE_COMBO_PHY_PLL2, 1310 &clk_src_regs[2], false); 1311 1312 #ifdef CONFIG_DRM_AMD_DC_DCN1_01 1313 if (dc->ctx->dce_version == DCN_VERSION_1_0) { 1314 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1315 dcn10_clock_source_create(ctx, ctx->dc_bios, 1316 CLOCK_SOURCE_COMBO_PHY_PLL3, 1317 &clk_src_regs[3], false); 1318 } 1319 #else 1320 pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = 1321 dcn10_clock_source_create(ctx, ctx->dc_bios, 1322 CLOCK_SOURCE_COMBO_PHY_PLL3, 1323 &clk_src_regs[3], false); 1324 #endif 1325 1326 pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; 1327 1328 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1329 if (dc->ctx->dce_version == DCN_VERSION_1_01) 1330 pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; 1331 #endif 1332 1333 pool->base.dp_clock_source = 1334 dcn10_clock_source_create(ctx, ctx->dc_bios, 1335 CLOCK_SOURCE_ID_DP_DTO, 1336 /* todo: not reuse phy_pll registers */ 1337 &clk_src_regs[0], true); 1338 1339 for (i = 0; i < pool->base.clk_src_count; i++) { 1340 if (pool->base.clock_sources[i] == NULL) { 1341 dm_error("DC: failed to create clock sources!\n"); 1342 BREAK_TO_DEBUGGER(); 1343 goto fail; 1344 } 1345 } 1346 pool->base.clk_mgr = dcn1_clk_mgr_create(ctx); 1347 if (pool->base.clk_mgr == NULL) { 1348 dm_error("DC: failed to create display clock!\n"); 1349 BREAK_TO_DEBUGGER(); 1350 goto fail; 1351 } 1352 1353 pool->base.dmcu = dcn10_dmcu_create(ctx, 1354 &dmcu_regs, 1355 &dmcu_shift, 1356 &dmcu_mask); 1357 if (pool->base.dmcu == NULL) { 1358 dm_error("DC: failed to create dmcu!\n"); 1359 BREAK_TO_DEBUGGER(); 1360 goto fail; 1361 } 1362 1363 pool->base.abm = dce_abm_create(ctx, 1364 &abm_regs, 1365 &abm_shift, 1366 &abm_mask); 1367 if (pool->base.abm == NULL) { 1368 dm_error("DC: failed to create abm!\n"); 1369 BREAK_TO_DEBUGGER(); 1370 goto fail; 1371 } 1372 1373 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); 1374 memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); 1375 memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); 1376 1377 #if defined(CONFIG_DRM_AMD_DC_DCN1_01) 1378 if (dc->ctx->dce_version == DCN_VERSION_1_01) { 1379 struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; 1380 struct dcn_ip_params *dcn_ip = dc->dcn_ip; 1381 struct display_mode_lib *dml = &dc->dml; 1382 1383 dml->ip.max_num_dpp = 3; 1384 /* TODO how to handle 23.84? */ 1385 dcn_soc->dram_clock_change_latency = 23; 1386 dcn_ip->max_num_dpp = 3; 1387 } 1388 #endif 1389 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1390 dc->dcn_soc->urgent_latency = 3; 1391 dc->debug.disable_dmcu = true; 1392 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; 1393 } 1394 1395 1396 dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; 1397 ASSERT(dc->dcn_soc->number_of_channels < 3); 1398 if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ 1399 dc->dcn_soc->number_of_channels = 2; 1400 1401 if (dc->dcn_soc->number_of_channels == 1) { 1402 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; 1403 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; 1404 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; 1405 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; 1406 if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { 1407 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; 1408 } 1409 } 1410 1411 pool->base.pp_smu = dcn10_pp_smu_create(ctx); 1412 1413 if (!dc->debug.disable_pplib_clock_request) 1414 dcn_bw_update_from_pplib(dc); 1415 dcn_bw_sync_calcs_and_dml(dc); 1416 if (!dc->debug.disable_pplib_wm_range) { 1417 dc->res_pool = &pool->base; 1418 dcn_bw_notify_pplib_of_wm_ranges(dc); 1419 } 1420 1421 { 1422 struct irq_service_init_data init_data; 1423 init_data.ctx = dc->ctx; 1424 pool->base.irqs = dal_irq_service_dcn10_create(&init_data); 1425 if (!pool->base.irqs) 1426 goto fail; 1427 } 1428 1429 /* index to valid pipe resource */ 1430 j = 0; 1431 /* mem input -> ipp -> dpp -> opp -> TG */ 1432 for (i = 0; i < pool->base.pipe_count; i++) { 1433 /* if pipe is disabled, skip instance of HW pipe, 1434 * i.e, skip ASIC register instance 1435 */ 1436 if ((pipe_fuses & (1 << i)) != 0) 1437 continue; 1438 1439 pool->base.hubps[j] = dcn10_hubp_create(ctx, i); 1440 if (pool->base.hubps[j] == NULL) { 1441 BREAK_TO_DEBUGGER(); 1442 dm_error( 1443 "DC: failed to create memory input!\n"); 1444 goto fail; 1445 } 1446 1447 pool->base.ipps[j] = dcn10_ipp_create(ctx, i); 1448 if (pool->base.ipps[j] == NULL) { 1449 BREAK_TO_DEBUGGER(); 1450 dm_error( 1451 "DC: failed to create input pixel processor!\n"); 1452 goto fail; 1453 } 1454 1455 pool->base.dpps[j] = dcn10_dpp_create(ctx, i); 1456 if (pool->base.dpps[j] == NULL) { 1457 BREAK_TO_DEBUGGER(); 1458 dm_error( 1459 "DC: failed to create dpp!\n"); 1460 goto fail; 1461 } 1462 1463 pool->base.opps[j] = dcn10_opp_create(ctx, i); 1464 if (pool->base.opps[j] == NULL) { 1465 BREAK_TO_DEBUGGER(); 1466 dm_error( 1467 "DC: failed to create output pixel processor!\n"); 1468 goto fail; 1469 } 1470 1471 pool->base.timing_generators[j] = dcn10_timing_generator_create( 1472 ctx, i); 1473 if (pool->base.timing_generators[j] == NULL) { 1474 BREAK_TO_DEBUGGER(); 1475 dm_error("DC: failed to create tg!\n"); 1476 goto fail; 1477 } 1478 /* check next valid pipe */ 1479 j++; 1480 } 1481 1482 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1483 pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); 1484 if (pool->base.engines[i] == NULL) { 1485 BREAK_TO_DEBUGGER(); 1486 dm_error( 1487 "DC:failed to create aux engine!!\n"); 1488 goto fail; 1489 } 1490 pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, i); 1491 if (pool->base.hw_i2cs[i] == NULL) { 1492 BREAK_TO_DEBUGGER(); 1493 dm_error( 1494 "DC:failed to create hw i2c!!\n"); 1495 goto fail; 1496 } 1497 pool->base.sw_i2cs[i] = NULL; 1498 } 1499 1500 /* valid pipe num */ 1501 pool->base.pipe_count = j; 1502 pool->base.timing_generator_count = j; 1503 1504 /* within dml lib, it is hard code to 4. If ASIC pipe is fused, 1505 * the value may be changed 1506 */ 1507 dc->dml.ip.max_num_dpp = pool->base.pipe_count; 1508 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; 1509 1510 pool->base.mpc = dcn10_mpc_create(ctx); 1511 if (pool->base.mpc == NULL) { 1512 BREAK_TO_DEBUGGER(); 1513 dm_error("DC: failed to create mpc!\n"); 1514 goto fail; 1515 } 1516 1517 pool->base.hubbub = dcn10_hubbub_create(ctx); 1518 if (pool->base.hubbub == NULL) { 1519 BREAK_TO_DEBUGGER(); 1520 dm_error("DC: failed to create hubbub!\n"); 1521 goto fail; 1522 } 1523 1524 if (!resource_construct(num_virtual_links, dc, &pool->base, 1525 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1526 &res_create_funcs : &res_create_maximus_funcs))) 1527 goto fail; 1528 1529 dcn10_hw_sequencer_construct(dc); 1530 dc->caps.max_planes = pool->base.pipe_count; 1531 1532 for (i = 0; i < dc->caps.max_planes; ++i) 1533 dc->caps.planes[i] = plane_cap; 1534 1535 dc->cap_funcs = cap_funcs; 1536 1537 return true; 1538 1539 fail: 1540 1541 destruct(pool); 1542 1543 return false; 1544 } 1545 1546 struct resource_pool *dcn10_create_resource_pool( 1547 const struct dc_init_data *init_data, 1548 struct dc *dc) 1549 { 1550 struct dcn10_resource_pool *pool = 1551 kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); 1552 1553 if (!pool) 1554 return NULL; 1555 1556 if (construct(init_data->num_virtual_links, dc, pool)) 1557 return &pool->base; 1558 1559 BREAK_TO_DEBUGGER(); 1560 return NULL; 1561 } 1562