1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void optc1_apply_front_porch_workaround( 50 struct timing_generator *optc, 51 struct dc_crtc_timing *timing) 52 { 53 if (timing->flags.INTERLACE == 1) { 54 if (timing->v_front_porch < 2) 55 timing->v_front_porch = 2; 56 } else { 57 if (timing->v_front_porch < 1) 58 timing->v_front_porch = 1; 59 } 60 } 61 62 void optc1_program_global_sync( 63 struct timing_generator *optc) 64 { 65 struct optc *optc1 = DCN10TG_FROM_TG(optc); 66 67 if (optc->dlg_otg_param.vstartup_start == 0) { 68 BREAK_TO_DEBUGGER(); 69 return; 70 } 71 72 REG_SET(OTG_VSTARTUP_PARAM, 0, 73 VSTARTUP_START, optc->dlg_otg_param.vstartup_start); 74 75 REG_SET_2(OTG_VUPDATE_PARAM, 0, 76 VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset, 77 VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width); 78 79 REG_SET(OTG_VREADY_PARAM, 0, 80 VREADY_OFFSET, optc->dlg_otg_param.vready_offset); 81 } 82 83 static void optc1_disable_stereo(struct timing_generator *optc) 84 { 85 struct optc *optc1 = DCN10TG_FROM_TG(optc); 86 87 REG_SET(OTG_STEREO_CONTROL, 0, 88 OTG_STEREO_EN, 0); 89 90 REG_SET_3(OTG_3D_STRUCTURE_CONTROL, 0, 91 OTG_3D_STRUCTURE_EN, 0, 92 OTG_3D_STRUCTURE_V_UPDATE_MODE, 0, 93 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 94 } 95 96 static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) 97 { 98 struct dc_crtc_timing patched_crtc_timing; 99 int vesa_sync_start; 100 int asic_blank_end; 101 int vertical_line_start; 102 103 patched_crtc_timing = *dc_crtc_timing; 104 optc1_apply_front_porch_workaround(optc, &patched_crtc_timing); 105 106 vesa_sync_start = patched_crtc_timing.h_addressable + 107 patched_crtc_timing.h_border_right + 108 patched_crtc_timing.h_front_porch; 109 110 asic_blank_end = patched_crtc_timing.h_total - 111 vesa_sync_start - 112 patched_crtc_timing.h_border_left; 113 114 vesa_sync_start = patched_crtc_timing.v_addressable + 115 patched_crtc_timing.v_border_bottom + 116 patched_crtc_timing.v_front_porch; 117 118 asic_blank_end = (patched_crtc_timing.v_total - 119 vesa_sync_start - 120 patched_crtc_timing.v_border_top); 121 122 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1; 123 if (vertical_line_start < 0) { 124 ASSERT(0); 125 vertical_line_start = 0; 126 } 127 128 return vertical_line_start; 129 } 130 131 void optc1_program_vline_interrupt( 132 struct timing_generator *optc, 133 const struct dc_crtc_timing *dc_crtc_timing, 134 unsigned long long vsync_delta) 135 { 136 137 struct optc *optc1 = DCN10TG_FROM_TG(optc); 138 139 unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000); 140 unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100); 141 uint32_t req_delta_lines = (uint32_t) div64_u64( 142 (req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1), 143 dc_crtc_timing->h_total); 144 145 uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing); 146 uint32_t start_line = 0; 147 uint32_t endLine = 0; 148 149 if (req_delta_lines != 0) 150 req_delta_lines--; 151 152 if (req_delta_lines > vsync_line) 153 start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) + 2; 154 else 155 start_line = vsync_line - req_delta_lines; 156 157 endLine = start_line + 2; 158 159 if (endLine >= dc_crtc_timing->v_total) 160 endLine = 2; 161 162 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 163 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 164 OTG_VERTICAL_INTERRUPT0_LINE_END, endLine); 165 } 166 167 /** 168 * program_timing_generator used by mode timing set 169 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 170 * Including SYNC. Call BIOS command table to program Timings. 171 */ 172 void optc1_program_timing( 173 struct timing_generator *optc, 174 const struct dc_crtc_timing *dc_crtc_timing, 175 bool use_vbios) 176 { 177 struct dc_crtc_timing patched_crtc_timing; 178 uint32_t vesa_sync_start; 179 uint32_t asic_blank_end; 180 uint32_t asic_blank_start; 181 uint32_t v_total; 182 uint32_t v_sync_end; 183 uint32_t v_init, v_fp2; 184 uint32_t h_sync_polarity, v_sync_polarity; 185 uint32_t start_point = 0; 186 uint32_t field_num = 0; 187 uint32_t h_div_2; 188 int32_t vertical_line_start; 189 190 struct optc *optc1 = DCN10TG_FROM_TG(optc); 191 192 patched_crtc_timing = *dc_crtc_timing; 193 optc1_apply_front_porch_workaround(optc, &patched_crtc_timing); 194 195 /* Load horizontal timing */ 196 197 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 198 REG_SET(OTG_H_TOTAL, 0, 199 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 200 201 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 202 REG_UPDATE_2(OTG_H_SYNC_A, 203 OTG_H_SYNC_A_START, 0, 204 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 205 206 /* asic_h_blank_end = HsyncWidth + HbackPorch = 207 * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart - 208 * vesa.h_left_border 209 */ 210 vesa_sync_start = patched_crtc_timing.h_addressable + 211 patched_crtc_timing.h_border_right + 212 patched_crtc_timing.h_front_porch; 213 214 asic_blank_end = patched_crtc_timing.h_total - 215 vesa_sync_start - 216 patched_crtc_timing.h_border_left; 217 218 /* h_blank_start = v_blank_end + v_active */ 219 asic_blank_start = asic_blank_end + 220 patched_crtc_timing.h_border_left + 221 patched_crtc_timing.h_addressable + 222 patched_crtc_timing.h_border_right; 223 224 REG_UPDATE_2(OTG_H_BLANK_START_END, 225 OTG_H_BLANK_START, asic_blank_start, 226 OTG_H_BLANK_END, asic_blank_end); 227 228 /* h_sync polarity */ 229 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 230 0 : 1; 231 232 REG_UPDATE(OTG_H_SYNC_A_CNTL, 233 OTG_H_SYNC_A_POL, h_sync_polarity); 234 235 v_total = patched_crtc_timing.v_total - 1; 236 237 REG_SET(OTG_V_TOTAL, 0, 238 OTG_V_TOTAL, v_total); 239 240 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 241 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 242 */ 243 REG_SET(OTG_V_TOTAL_MAX, 0, 244 OTG_V_TOTAL_MAX, v_total); 245 REG_SET(OTG_V_TOTAL_MIN, 0, 246 OTG_V_TOTAL_MIN, v_total); 247 248 /* v_sync_start = 0, v_sync_end = v_sync_width */ 249 v_sync_end = patched_crtc_timing.v_sync_width; 250 251 REG_UPDATE_2(OTG_V_SYNC_A, 252 OTG_V_SYNC_A_START, 0, 253 OTG_V_SYNC_A_END, v_sync_end); 254 255 vesa_sync_start = patched_crtc_timing.v_addressable + 256 patched_crtc_timing.v_border_bottom + 257 patched_crtc_timing.v_front_porch; 258 259 asic_blank_end = (patched_crtc_timing.v_total - 260 vesa_sync_start - 261 patched_crtc_timing.v_border_top); 262 263 /* v_blank_start = v_blank_end + v_active */ 264 asic_blank_start = asic_blank_end + 265 (patched_crtc_timing.v_border_top + 266 patched_crtc_timing.v_addressable + 267 patched_crtc_timing.v_border_bottom); 268 269 REG_UPDATE_2(OTG_V_BLANK_START_END, 270 OTG_V_BLANK_START, asic_blank_start, 271 OTG_V_BLANK_END, asic_blank_end); 272 273 /* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt, 274 * program the reg for interrupt postition. 275 */ 276 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1; 277 if (vertical_line_start < 0) { 278 ASSERT(0); 279 vertical_line_start = 0; 280 } 281 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 282 OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start); 283 284 /* v_sync polarity */ 285 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 286 0 : 1; 287 288 REG_UPDATE(OTG_V_SYNC_A_CNTL, 289 OTG_V_SYNC_A_POL, v_sync_polarity); 290 291 v_init = asic_blank_start; 292 if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT || 293 optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 294 optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) { 295 start_point = 1; 296 if (patched_crtc_timing.flags.INTERLACE == 1) 297 field_num = 1; 298 } 299 v_fp2 = 0; 300 if (optc->dlg_otg_param.vstartup_start > asic_blank_end) 301 v_fp2 = optc->dlg_otg_param.vstartup_start > asic_blank_end; 302 303 /* Interlace */ 304 if (patched_crtc_timing.flags.INTERLACE == 1) { 305 REG_UPDATE(OTG_INTERLACE_CONTROL, 306 OTG_INTERLACE_ENABLE, 1); 307 v_init = v_init / 2; 308 if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end) 309 v_fp2 = v_fp2 / 2; 310 } else 311 REG_UPDATE(OTG_INTERLACE_CONTROL, 312 OTG_INTERLACE_ENABLE, 0); 313 314 315 /* VTG enable set to 0 first VInit */ 316 REG_UPDATE(CONTROL, 317 VTG0_ENABLE, 0); 318 319 REG_UPDATE_2(CONTROL, 320 VTG0_FP2, v_fp2, 321 VTG0_VCOUNT_INIT, v_init); 322 323 /* original code is using VTG offset to address OTG reg, seems wrong */ 324 REG_UPDATE_2(OTG_CONTROL, 325 OTG_START_POINT_CNTL, start_point, 326 OTG_FIELD_NUMBER_CNTL, field_num); 327 328 optc1_program_global_sync(optc); 329 330 /* TODO 331 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 332 * program_horz_count_by_2 333 * for DVI 30bpp mode, 0 otherwise 334 * program_horz_count_by_2(optc, &patched_crtc_timing); 335 */ 336 337 /* Enable stereo - only when we need to pack 3D frame. Other types 338 * of stereo handled in explicit call 339 */ 340 h_div_2 = (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ? 341 1 : 0; 342 343 REG_UPDATE(OTG_H_TIMING_CNTL, 344 OTG_H_TIMING_DIV_BY2, h_div_2); 345 346 } 347 348 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 349 { 350 struct optc *optc1 = DCN10TG_FROM_TG(optc); 351 352 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 353 354 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 355 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 356 } 357 358 /** 359 * unblank_crtc 360 * Call ASIC Control Object to UnBlank CRTC. 361 */ 362 static void optc1_unblank_crtc(struct timing_generator *optc) 363 { 364 struct optc *optc1 = DCN10TG_FROM_TG(optc); 365 uint32_t vertical_interrupt_enable = 0; 366 367 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 368 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &vertical_interrupt_enable); 369 370 /* temporary work around for vertical interrupt, once vertical interrupt enabled, 371 * this check will be removed. 372 */ 373 if (vertical_interrupt_enable) 374 optc1_set_blank_data_double_buffer(optc, true); 375 376 REG_UPDATE_2(OTG_BLANK_CONTROL, 377 OTG_BLANK_DATA_EN, 0, 378 OTG_BLANK_DE_MODE, 0); 379 } 380 381 /** 382 * blank_crtc 383 * Call ASIC Control Object to Blank CRTC. 384 */ 385 386 static void optc1_blank_crtc(struct timing_generator *optc) 387 { 388 struct optc *optc1 = DCN10TG_FROM_TG(optc); 389 390 REG_UPDATE_2(OTG_BLANK_CONTROL, 391 OTG_BLANK_DATA_EN, 1, 392 OTG_BLANK_DE_MODE, 0); 393 394 optc1_set_blank_data_double_buffer(optc, false); 395 } 396 397 void optc1_set_blank(struct timing_generator *optc, 398 bool enable_blanking) 399 { 400 if (enable_blanking) 401 optc1_blank_crtc(optc); 402 else 403 optc1_unblank_crtc(optc); 404 } 405 406 bool optc1_is_blanked(struct timing_generator *optc) 407 { 408 struct optc *optc1 = DCN10TG_FROM_TG(optc); 409 uint32_t blank_en; 410 uint32_t blank_state; 411 412 REG_GET_2(OTG_BLANK_CONTROL, 413 OTG_BLANK_DATA_EN, &blank_en, 414 OTG_CURRENT_BLANK_STATE, &blank_state); 415 416 return blank_en && blank_state; 417 } 418 419 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 420 { 421 struct optc *optc1 = DCN10TG_FROM_TG(optc); 422 423 if (enable) { 424 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 425 OPTC_INPUT_CLK_EN, 1, 426 OPTC_INPUT_CLK_GATE_DIS, 1); 427 428 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 429 OPTC_INPUT_CLK_ON, 1, 430 1, 1000); 431 432 /* Enable clock */ 433 REG_UPDATE_2(OTG_CLOCK_CONTROL, 434 OTG_CLOCK_EN, 1, 435 OTG_CLOCK_GATE_DIS, 1); 436 REG_WAIT(OTG_CLOCK_CONTROL, 437 OTG_CLOCK_ON, 1, 438 1, 1000); 439 } else { 440 REG_UPDATE_2(OTG_CLOCK_CONTROL, 441 OTG_CLOCK_GATE_DIS, 0, 442 OTG_CLOCK_EN, 0); 443 444 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 445 OPTC_INPUT_CLK_GATE_DIS, 0, 446 OPTC_INPUT_CLK_EN, 0); 447 } 448 } 449 450 /** 451 * Enable CRTC 452 * Enable CRTC - call ASIC Control Object to enable Timing generator. 453 */ 454 static bool optc1_enable_crtc(struct timing_generator *optc) 455 { 456 /* TODO FPGA wait for answer 457 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 458 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 459 */ 460 struct optc *optc1 = DCN10TG_FROM_TG(optc); 461 462 /* opp instance for OTG. For DCN1.0, ODM is remoed. 463 * OPP and OPTC should 1:1 mapping 464 */ 465 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 466 OPTC_SRC_SEL, optc->inst); 467 468 /* VTG enable first is for HW workaround */ 469 REG_UPDATE(CONTROL, 470 VTG0_ENABLE, 1); 471 472 /* Enable CRTC */ 473 REG_UPDATE_2(OTG_CONTROL, 474 OTG_DISABLE_POINT_CNTL, 3, 475 OTG_MASTER_EN, 1); 476 477 return true; 478 } 479 480 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 481 bool optc1_disable_crtc(struct timing_generator *optc) 482 { 483 struct optc *optc1 = DCN10TG_FROM_TG(optc); 484 485 /* disable otg request until end of the first line 486 * in the vertical blank region 487 */ 488 REG_UPDATE_2(OTG_CONTROL, 489 OTG_DISABLE_POINT_CNTL, 3, 490 OTG_MASTER_EN, 0); 491 492 REG_UPDATE(CONTROL, 493 VTG0_ENABLE, 0); 494 495 /* CRTC disabled, so disable clock. */ 496 REG_WAIT(OTG_CLOCK_CONTROL, 497 OTG_BUSY, 0, 498 1, 100000); 499 500 return true; 501 } 502 503 504 void optc1_program_blank_color( 505 struct timing_generator *optc, 506 const struct tg_color *black_color) 507 { 508 struct optc *optc1 = DCN10TG_FROM_TG(optc); 509 510 REG_SET_3(OTG_BLACK_COLOR, 0, 511 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 512 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 513 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 514 } 515 516 bool optc1_validate_timing( 517 struct timing_generator *optc, 518 const struct dc_crtc_timing *timing) 519 { 520 uint32_t v_blank; 521 uint32_t h_blank; 522 uint32_t min_v_blank; 523 struct optc *optc1 = DCN10TG_FROM_TG(optc); 524 525 ASSERT(timing != NULL); 526 527 v_blank = (timing->v_total - timing->v_addressable - 528 timing->v_border_top - timing->v_border_bottom); 529 530 h_blank = (timing->h_total - timing->h_addressable - 531 timing->h_border_right - 532 timing->h_border_left); 533 534 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 535 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 536 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 537 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 538 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 539 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 540 return false; 541 542 /* Temporarily blocking interlacing mode until it's supported */ 543 if (timing->flags.INTERLACE == 1) 544 return false; 545 546 /* Check maximum number of pixels supported by Timing Generator 547 * (Currently will never fail, in order to fail needs display which 548 * needs more than 8192 horizontal and 549 * more than 8192 vertical total pixels) 550 */ 551 if (timing->h_total > optc1->max_h_total || 552 timing->v_total > optc1->max_v_total) 553 return false; 554 555 556 if (h_blank < optc1->min_h_blank) 557 return false; 558 559 if (timing->h_sync_width < optc1->min_h_sync_width || 560 timing->v_sync_width < optc1->min_v_sync_width) 561 return false; 562 563 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 564 565 if (v_blank < min_v_blank) 566 return false; 567 568 return true; 569 570 } 571 572 /* 573 * get_vblank_counter 574 * 575 * @brief 576 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 577 * holds the counter of frames. 578 * 579 * @param 580 * struct timing_generator *optc - [in] timing generator which controls the 581 * desired CRTC 582 * 583 * @return 584 * Counter of frames, which should equal to number of vblanks. 585 */ 586 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 587 { 588 struct optc *optc1 = DCN10TG_FROM_TG(optc); 589 uint32_t frame_count; 590 591 REG_GET(OTG_STATUS_FRAME_COUNT, 592 OTG_FRAME_COUNT, &frame_count); 593 594 return frame_count; 595 } 596 597 void optc1_lock(struct timing_generator *optc) 598 { 599 struct optc *optc1 = DCN10TG_FROM_TG(optc); 600 601 REG_SET(OTG_GLOBAL_CONTROL0, 0, 602 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 603 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 604 OTG_MASTER_UPDATE_LOCK, 1); 605 606 /* Should be fast, status does not update on maximus */ 607 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 608 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 609 UPDATE_LOCK_STATUS, 1, 610 1, 10); 611 } 612 613 void optc1_unlock(struct timing_generator *optc) 614 { 615 struct optc *optc1 = DCN10TG_FROM_TG(optc); 616 617 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 618 OTG_MASTER_UPDATE_LOCK, 0); 619 } 620 621 void optc1_get_position(struct timing_generator *optc, 622 struct crtc_position *position) 623 { 624 struct optc *optc1 = DCN10TG_FROM_TG(optc); 625 626 REG_GET_2(OTG_STATUS_POSITION, 627 OTG_HORZ_COUNT, &position->horizontal_count, 628 OTG_VERT_COUNT, &position->vertical_count); 629 630 REG_GET(OTG_NOM_VERT_POSITION, 631 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 632 } 633 634 bool optc1_is_counter_moving(struct timing_generator *optc) 635 { 636 struct crtc_position position1, position2; 637 638 optc->funcs->get_position(optc, &position1); 639 optc->funcs->get_position(optc, &position2); 640 641 if (position1.horizontal_count == position2.horizontal_count && 642 position1.vertical_count == position2.vertical_count) 643 return false; 644 else 645 return true; 646 } 647 648 bool optc1_did_triggered_reset_occur( 649 struct timing_generator *optc) 650 { 651 struct optc *optc1 = DCN10TG_FROM_TG(optc); 652 uint32_t occurred_force, occurred_vsync; 653 654 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 655 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 656 657 REG_GET(OTG_VERT_SYNC_CONTROL, 658 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 659 660 return occurred_vsync != 0 || occurred_force != 0; 661 } 662 663 void optc1_disable_reset_trigger(struct timing_generator *optc) 664 { 665 struct optc *optc1 = DCN10TG_FROM_TG(optc); 666 667 REG_WRITE(OTG_TRIGA_CNTL, 0); 668 669 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 670 OTG_FORCE_COUNT_NOW_CLEAR, 1); 671 672 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 673 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 674 } 675 676 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 677 { 678 struct optc *optc1 = DCN10TG_FROM_TG(optc); 679 uint32_t falling_edge; 680 681 REG_GET(OTG_V_SYNC_A_CNTL, 682 OTG_V_SYNC_A_POL, &falling_edge); 683 684 if (falling_edge) 685 REG_SET_3(OTG_TRIGA_CNTL, 0, 686 /* vsync signal from selected OTG pipe based 687 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 688 */ 689 OTG_TRIGA_SOURCE_SELECT, 20, 690 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 691 /* always detect falling edge */ 692 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 693 else 694 REG_SET_3(OTG_TRIGA_CNTL, 0, 695 /* vsync signal from selected OTG pipe based 696 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 697 */ 698 OTG_TRIGA_SOURCE_SELECT, 20, 699 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 700 /* always detect rising edge */ 701 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 702 703 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 704 /* force H count to H_TOTAL and V count to V_TOTAL in 705 * progressive mode and V_TOTAL-1 in interlaced mode 706 */ 707 OTG_FORCE_COUNT_NOW_MODE, 2); 708 } 709 710 void optc1_enable_crtc_reset( 711 struct timing_generator *optc, 712 int source_tg_inst, 713 struct crtc_trigger_info *crtc_tp) 714 { 715 struct optc *optc1 = DCN10TG_FROM_TG(optc); 716 uint32_t falling_edge = 0; 717 uint32_t rising_edge = 0; 718 719 switch (crtc_tp->event) { 720 721 case CRTC_EVENT_VSYNC_RISING: 722 rising_edge = 1; 723 break; 724 725 case CRTC_EVENT_VSYNC_FALLING: 726 falling_edge = 1; 727 break; 728 } 729 730 REG_SET_4(OTG_TRIGA_CNTL, 0, 731 /* vsync signal from selected OTG pipe based 732 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 733 */ 734 OTG_TRIGA_SOURCE_SELECT, 20, 735 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 736 /* always detect falling edge */ 737 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 738 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 739 740 switch (crtc_tp->delay) { 741 case TRIGGER_DELAY_NEXT_LINE: 742 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 743 OTG_AUTO_FORCE_VSYNC_MODE, 1); 744 break; 745 case TRIGGER_DELAY_NEXT_PIXEL: 746 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 747 /* force H count to H_TOTAL and V count to V_TOTAL in 748 * progressive mode and V_TOTAL-1 in interlaced mode 749 */ 750 OTG_FORCE_COUNT_NOW_MODE, 2); 751 break; 752 } 753 } 754 755 void optc1_wait_for_state(struct timing_generator *optc, 756 enum crtc_state state) 757 { 758 struct optc *optc1 = DCN10TG_FROM_TG(optc); 759 760 switch (state) { 761 case CRTC_STATE_VBLANK: 762 REG_WAIT(OTG_STATUS, 763 OTG_V_BLANK, 1, 764 1, 100000); /* 1 vupdate at 10hz */ 765 break; 766 767 case CRTC_STATE_VACTIVE: 768 REG_WAIT(OTG_STATUS, 769 OTG_V_ACTIVE_DISP, 1, 770 1, 100000); /* 1 vupdate at 10hz */ 771 break; 772 773 default: 774 break; 775 } 776 } 777 778 void optc1_set_early_control( 779 struct timing_generator *optc, 780 uint32_t early_cntl) 781 { 782 /* asic design change, do not need this control 783 * empty for share caller logic 784 */ 785 } 786 787 788 void optc1_set_static_screen_control( 789 struct timing_generator *optc, 790 uint32_t value) 791 { 792 struct optc *optc1 = DCN10TG_FROM_TG(optc); 793 794 /* Bit 8 is no longer applicable in RV for PSR case, 795 * set bit 8 to 0 if given 796 */ 797 if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 798 != 0) 799 value = value & 800 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 801 802 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 803 OTG_STATIC_SCREEN_EVENT_MASK, value, 804 OTG_STATIC_SCREEN_FRAME_COUNT, 2); 805 } 806 807 808 /** 809 ***************************************************************************** 810 * Function: set_drr 811 * 812 * @brief 813 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 814 * 815 ***************************************************************************** 816 */ 817 void optc1_set_drr( 818 struct timing_generator *optc, 819 const struct drr_params *params) 820 { 821 struct optc *optc1 = DCN10TG_FROM_TG(optc); 822 823 if (params != NULL && 824 params->vertical_total_max > 0 && 825 params->vertical_total_min > 0) { 826 827 REG_SET(OTG_V_TOTAL_MAX, 0, 828 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 829 830 REG_SET(OTG_V_TOTAL_MIN, 0, 831 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 832 833 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 834 OTG_V_TOTAL_MIN_SEL, 1, 835 OTG_V_TOTAL_MAX_SEL, 1, 836 OTG_FORCE_LOCK_ON_EVENT, 0, 837 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 838 OTG_SET_V_TOTAL_MIN_MASK, 0); 839 } else { 840 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 841 OTG_SET_V_TOTAL_MIN_MASK, 0, 842 OTG_V_TOTAL_MIN_SEL, 0, 843 OTG_V_TOTAL_MAX_SEL, 0, 844 OTG_FORCE_LOCK_ON_EVENT, 0); 845 846 REG_SET(OTG_V_TOTAL_MIN, 0, 847 OTG_V_TOTAL_MIN, 0); 848 849 REG_SET(OTG_V_TOTAL_MAX, 0, 850 OTG_V_TOTAL_MAX, 0); 851 } 852 } 853 854 static void optc1_set_test_pattern( 855 struct timing_generator *optc, 856 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 857 * because this is not DP-specific (which is probably somewhere in DP 858 * encoder) */ 859 enum controller_dp_test_pattern test_pattern, 860 enum dc_color_depth color_depth) 861 { 862 struct optc *optc1 = DCN10TG_FROM_TG(optc); 863 enum test_pattern_color_format bit_depth; 864 enum test_pattern_dyn_range dyn_range; 865 enum test_pattern_mode mode; 866 uint32_t pattern_mask; 867 uint32_t pattern_data; 868 /* color ramp generator mixes 16-bits color */ 869 uint32_t src_bpc = 16; 870 /* requested bpc */ 871 uint32_t dst_bpc; 872 uint32_t index; 873 /* RGB values of the color bars. 874 * Produce two RGB colors: RGB0 - white (all Fs) 875 * and RGB1 - black (all 0s) 876 * (three RGB components for two colors) 877 */ 878 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 879 0x0000, 0x0000}; 880 /* dest color (converted to the specified color format) */ 881 uint16_t dst_color[6]; 882 uint32_t inc_base; 883 884 /* translate to bit depth */ 885 switch (color_depth) { 886 case COLOR_DEPTH_666: 887 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 888 break; 889 case COLOR_DEPTH_888: 890 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 891 break; 892 case COLOR_DEPTH_101010: 893 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 894 break; 895 case COLOR_DEPTH_121212: 896 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 897 break; 898 default: 899 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 900 break; 901 } 902 903 switch (test_pattern) { 904 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 905 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 906 { 907 dyn_range = (test_pattern == 908 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 909 TEST_PATTERN_DYN_RANGE_CEA : 910 TEST_PATTERN_DYN_RANGE_VESA); 911 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 912 913 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 914 OTG_TEST_PATTERN_VRES, 6, 915 OTG_TEST_PATTERN_HRES, 6); 916 917 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 918 OTG_TEST_PATTERN_EN, 1, 919 OTG_TEST_PATTERN_MODE, mode, 920 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 921 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 922 } 923 break; 924 925 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 926 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 927 { 928 mode = (test_pattern == 929 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 930 TEST_PATTERN_MODE_VERTICALBARS : 931 TEST_PATTERN_MODE_HORIZONTALBARS); 932 933 switch (bit_depth) { 934 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 935 dst_bpc = 6; 936 break; 937 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 938 dst_bpc = 8; 939 break; 940 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 941 dst_bpc = 10; 942 break; 943 default: 944 dst_bpc = 8; 945 break; 946 } 947 948 /* adjust color to the required colorFormat */ 949 for (index = 0; index < 6; index++) { 950 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 951 * (srcBpc - dstBpc); 952 */ 953 dst_color[index] = 954 src_color[index] >> (src_bpc - dst_bpc); 955 /* CRTC_TEST_PATTERN_DATA has 16 bits, 956 * lowest 6 are hardwired to ZERO 957 * color bits should be left aligned aligned to MSB 958 * XXXXXXXXXX000000 for 10 bit, 959 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 960 */ 961 dst_color[index] <<= (16 - dst_bpc); 962 } 963 964 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 965 966 /* We have to write the mask before data, similar to pipeline. 967 * For example, for 8 bpc, if we want RGB0 to be magenta, 968 * and RGB1 to be cyan, 969 * we need to make 7 writes: 970 * MASK DATA 971 * 000001 00000000 00000000 set mask to R0 972 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 973 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 974 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 975 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 976 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 977 * 100000 11111111 00000000 B1 255, 0xFF00 978 * 979 * we will make a loop of 6 in which we prepare the mask, 980 * then write, then prepare the color for next write. 981 * first iteration will write mask only, 982 * but each next iteration color prepared in 983 * previous iteration will be written within new mask, 984 * the last component will written separately, 985 * mask is not changing between 6th and 7th write 986 * and color will be prepared by last iteration 987 */ 988 989 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 990 * is B1, G1, R1, B0, G0, R0 991 */ 992 pattern_data = 0; 993 for (index = 0; index < 6; index++) { 994 /* prepare color mask, first write PATTERN_DATA 995 * will have all zeros 996 */ 997 pattern_mask = (1 << index); 998 999 /* write color component */ 1000 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1001 OTG_TEST_PATTERN_MASK, pattern_mask, 1002 OTG_TEST_PATTERN_DATA, pattern_data); 1003 1004 /* prepare next color component, 1005 * will be written in the next iteration 1006 */ 1007 pattern_data = dst_color[index]; 1008 } 1009 /* write last color component, 1010 * it's been already prepared in the loop 1011 */ 1012 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1013 OTG_TEST_PATTERN_MASK, pattern_mask, 1014 OTG_TEST_PATTERN_DATA, pattern_data); 1015 1016 /* enable test pattern */ 1017 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1018 OTG_TEST_PATTERN_EN, 1, 1019 OTG_TEST_PATTERN_MODE, mode, 1020 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1021 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1022 } 1023 break; 1024 1025 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1026 { 1027 mode = (bit_depth == 1028 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1029 TEST_PATTERN_MODE_DUALRAMP_RGB : 1030 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1031 1032 switch (bit_depth) { 1033 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1034 dst_bpc = 6; 1035 break; 1036 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1037 dst_bpc = 8; 1038 break; 1039 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1040 dst_bpc = 10; 1041 break; 1042 default: 1043 dst_bpc = 8; 1044 break; 1045 } 1046 1047 /* increment for the first ramp for one color gradation 1048 * 1 gradation for 6-bit color is 2^10 1049 * gradations in 16-bit color 1050 */ 1051 inc_base = (src_bpc - dst_bpc); 1052 1053 switch (bit_depth) { 1054 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1055 { 1056 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1057 OTG_TEST_PATTERN_INC0, inc_base, 1058 OTG_TEST_PATTERN_INC1, 0, 1059 OTG_TEST_PATTERN_HRES, 6, 1060 OTG_TEST_PATTERN_VRES, 6, 1061 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1062 } 1063 break; 1064 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1065 { 1066 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1067 OTG_TEST_PATTERN_INC0, inc_base, 1068 OTG_TEST_PATTERN_INC1, 0, 1069 OTG_TEST_PATTERN_HRES, 8, 1070 OTG_TEST_PATTERN_VRES, 6, 1071 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1072 } 1073 break; 1074 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1075 { 1076 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1077 OTG_TEST_PATTERN_INC0, inc_base, 1078 OTG_TEST_PATTERN_INC1, inc_base + 2, 1079 OTG_TEST_PATTERN_HRES, 8, 1080 OTG_TEST_PATTERN_VRES, 5, 1081 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1082 } 1083 break; 1084 default: 1085 break; 1086 } 1087 1088 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1089 1090 /* enable test pattern */ 1091 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1092 1093 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1094 OTG_TEST_PATTERN_EN, 1, 1095 OTG_TEST_PATTERN_MODE, mode, 1096 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1097 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1098 } 1099 break; 1100 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1101 { 1102 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1103 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1104 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1105 } 1106 break; 1107 default: 1108 break; 1109 1110 } 1111 } 1112 1113 void optc1_get_crtc_scanoutpos( 1114 struct timing_generator *optc, 1115 uint32_t *v_blank_start, 1116 uint32_t *v_blank_end, 1117 uint32_t *h_position, 1118 uint32_t *v_position) 1119 { 1120 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1121 struct crtc_position position; 1122 1123 REG_GET_2(OTG_V_BLANK_START_END, 1124 OTG_V_BLANK_START, v_blank_start, 1125 OTG_V_BLANK_END, v_blank_end); 1126 1127 optc1_get_position(optc, &position); 1128 1129 *h_position = position.horizontal_count; 1130 *v_position = position.vertical_count; 1131 } 1132 1133 static void optc1_enable_stereo(struct timing_generator *optc, 1134 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1135 { 1136 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1137 1138 if (flags) { 1139 uint32_t stereo_en; 1140 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1141 1142 if (flags->PROGRAM_STEREO) 1143 REG_UPDATE_3(OTG_STEREO_CONTROL, 1144 OTG_STEREO_EN, stereo_en, 1145 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1146 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0); 1147 1148 if (flags->PROGRAM_POLARITY) 1149 REG_UPDATE(OTG_STEREO_CONTROL, 1150 OTG_STEREO_EYE_FLAG_POLARITY, 1151 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1152 1153 if (flags->DISABLE_STEREO_DP_SYNC) 1154 REG_UPDATE(OTG_STEREO_CONTROL, 1155 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1156 1157 if (flags->PROGRAM_STEREO) 1158 REG_UPDATE_3(OTG_3D_STRUCTURE_CONTROL, 1159 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1160 OTG_3D_STRUCTURE_V_UPDATE_MODE, flags->FRAME_PACKED, 1161 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1162 1163 } 1164 } 1165 1166 void optc1_program_stereo(struct timing_generator *optc, 1167 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1168 { 1169 if (flags->PROGRAM_STEREO) 1170 optc1_enable_stereo(optc, timing, flags); 1171 else 1172 optc1_disable_stereo(optc); 1173 } 1174 1175 1176 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1177 { 1178 bool ret = false; 1179 uint32_t left_eye = 0; 1180 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1181 1182 REG_GET(OTG_STEREO_STATUS, 1183 OTG_STEREO_CURRENT_EYE, &left_eye); 1184 if (left_eye == 1) 1185 ret = true; 1186 else 1187 ret = false; 1188 1189 return ret; 1190 } 1191 1192 void optc1_read_otg_state(struct optc *optc1, 1193 struct dcn_otg_state *s) 1194 { 1195 REG_GET(OTG_CONTROL, 1196 OTG_MASTER_EN, &s->otg_enabled); 1197 1198 REG_GET_2(OTG_V_BLANK_START_END, 1199 OTG_V_BLANK_START, &s->v_blank_start, 1200 OTG_V_BLANK_END, &s->v_blank_end); 1201 1202 REG_GET(OTG_V_SYNC_A_CNTL, 1203 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1204 1205 REG_GET(OTG_V_TOTAL, 1206 OTG_V_TOTAL, &s->v_total); 1207 1208 REG_GET(OTG_V_TOTAL_MAX, 1209 OTG_V_TOTAL_MAX, &s->v_total_max); 1210 1211 REG_GET(OTG_V_TOTAL_MIN, 1212 OTG_V_TOTAL_MIN, &s->v_total_min); 1213 1214 REG_GET(OTG_V_TOTAL_CONTROL, 1215 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1216 1217 REG_GET(OTG_V_TOTAL_CONTROL, 1218 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1219 1220 REG_GET_2(OTG_V_SYNC_A, 1221 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1222 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1223 1224 REG_GET_2(OTG_H_BLANK_START_END, 1225 OTG_H_BLANK_START, &s->h_blank_start, 1226 OTG_H_BLANK_END, &s->h_blank_end); 1227 1228 REG_GET_2(OTG_H_SYNC_A, 1229 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1230 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1231 1232 REG_GET(OTG_H_SYNC_A_CNTL, 1233 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1234 1235 REG_GET(OTG_H_TOTAL, 1236 OTG_H_TOTAL, &s->h_total); 1237 1238 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1239 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1240 } 1241 1242 bool optc1_get_otg_active_size(struct timing_generator *optc, 1243 uint32_t *otg_active_width, 1244 uint32_t *otg_active_height) 1245 { 1246 uint32_t otg_enabled; 1247 uint32_t v_blank_start; 1248 uint32_t v_blank_end; 1249 uint32_t h_blank_start; 1250 uint32_t h_blank_end; 1251 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1252 1253 1254 REG_GET(OTG_CONTROL, 1255 OTG_MASTER_EN, &otg_enabled); 1256 1257 if (otg_enabled == 0) 1258 return false; 1259 1260 REG_GET_2(OTG_V_BLANK_START_END, 1261 OTG_V_BLANK_START, &v_blank_start, 1262 OTG_V_BLANK_END, &v_blank_end); 1263 1264 REG_GET_2(OTG_H_BLANK_START_END, 1265 OTG_H_BLANK_START, &h_blank_start, 1266 OTG_H_BLANK_END, &h_blank_end); 1267 1268 *otg_active_width = v_blank_start - v_blank_end; 1269 *otg_active_height = h_blank_start - h_blank_end; 1270 return true; 1271 } 1272 1273 void optc1_clear_optc_underflow(struct timing_generator *optc) 1274 { 1275 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1276 1277 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1278 } 1279 1280 void optc1_tg_init(struct timing_generator *optc) 1281 { 1282 optc1_set_blank_data_double_buffer(optc, true); 1283 optc1_clear_optc_underflow(optc); 1284 } 1285 1286 bool optc1_is_tg_enabled(struct timing_generator *optc) 1287 { 1288 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1289 uint32_t otg_enabled = 0; 1290 1291 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1292 1293 return (otg_enabled != 0); 1294 1295 } 1296 1297 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1298 { 1299 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1300 uint32_t underflow_occurred = 0; 1301 1302 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1303 OPTC_UNDERFLOW_OCCURRED_STATUS, 1304 &underflow_occurred); 1305 1306 return (underflow_occurred == 1); 1307 } 1308 1309 bool optc1_configure_crc(struct timing_generator *optc, 1310 const struct crc_params *params) 1311 { 1312 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1313 1314 /* Cannot configure crc on a CRTC that is disabled */ 1315 if (!optc1_is_tg_enabled(optc)) 1316 return false; 1317 1318 REG_WRITE(OTG_CRC_CNTL, 0); 1319 1320 if (!params->enable) 1321 return true; 1322 1323 /* Program frame boundaries */ 1324 /* Window A x axis start and end. */ 1325 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1326 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1327 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1328 1329 /* Window A y axis start and end. */ 1330 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1331 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1332 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1333 1334 /* Window B x axis start and end. */ 1335 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1336 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1337 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1338 1339 /* Window B y axis start and end. */ 1340 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1341 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1342 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1343 1344 /* Set crc mode and selection, and enable. Only using CRC0*/ 1345 REG_UPDATE_3(OTG_CRC_CNTL, 1346 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1347 OTG_CRC0_SELECT, params->selection, 1348 OTG_CRC_EN, 1); 1349 1350 return true; 1351 } 1352 1353 bool optc1_get_crc(struct timing_generator *optc, 1354 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1355 { 1356 uint32_t field = 0; 1357 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1358 1359 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1360 1361 /* Early return if CRC is not enabled for this CRTC */ 1362 if (!field) 1363 return false; 1364 1365 REG_GET_2(OTG_CRC0_DATA_RG, 1366 CRC0_R_CR, r_cr, 1367 CRC0_G_Y, g_y); 1368 1369 REG_GET(OTG_CRC0_DATA_B, 1370 CRC0_B_CB, b_cb); 1371 1372 return true; 1373 } 1374 1375 static const struct timing_generator_funcs dcn10_tg_funcs = { 1376 .validate_timing = optc1_validate_timing, 1377 .program_timing = optc1_program_timing, 1378 .program_vline_interrupt = optc1_program_vline_interrupt, 1379 .program_global_sync = optc1_program_global_sync, 1380 .enable_crtc = optc1_enable_crtc, 1381 .disable_crtc = optc1_disable_crtc, 1382 /* used by enable_timing_synchronization. Not need for FPGA */ 1383 .is_counter_moving = optc1_is_counter_moving, 1384 .get_position = optc1_get_position, 1385 .get_frame_count = optc1_get_vblank_counter, 1386 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1387 .get_otg_active_size = optc1_get_otg_active_size, 1388 .set_early_control = optc1_set_early_control, 1389 /* used by enable_timing_synchronization. Not need for FPGA */ 1390 .wait_for_state = optc1_wait_for_state, 1391 .set_blank = optc1_set_blank, 1392 .is_blanked = optc1_is_blanked, 1393 .set_blank_color = optc1_program_blank_color, 1394 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1395 .enable_reset_trigger = optc1_enable_reset_trigger, 1396 .enable_crtc_reset = optc1_enable_crtc_reset, 1397 .disable_reset_trigger = optc1_disable_reset_trigger, 1398 .lock = optc1_lock, 1399 .unlock = optc1_unlock, 1400 .enable_optc_clock = optc1_enable_optc_clock, 1401 .set_drr = optc1_set_drr, 1402 .set_static_screen_control = optc1_set_static_screen_control, 1403 .set_test_pattern = optc1_set_test_pattern, 1404 .program_stereo = optc1_program_stereo, 1405 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1406 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1407 .tg_init = optc1_tg_init, 1408 .is_tg_enabled = optc1_is_tg_enabled, 1409 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1410 .clear_optc_underflow = optc1_clear_optc_underflow, 1411 .get_crc = optc1_get_crc, 1412 .configure_crc = optc1_configure_crc, 1413 }; 1414 1415 void dcn10_timing_generator_init(struct optc *optc1) 1416 { 1417 optc1->base.funcs = &dcn10_tg_funcs; 1418 1419 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1420 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1421 1422 optc1->min_h_blank = 32; 1423 optc1->min_v_blank = 3; 1424 optc1->min_v_blank_interlace = 5; 1425 optc1->min_h_sync_width = 8; 1426 optc1->min_v_sync_width = 1; 1427 } 1428