1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 169 /* Load horizontal timing */ 170 171 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 172 REG_SET(OTG_H_TOTAL, 0, 173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 174 175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 176 REG_UPDATE_2(OTG_H_SYNC_A, 177 OTG_H_SYNC_A_START, 0, 178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 179 180 /* blank_start = line end - front porch */ 181 asic_blank_start = patched_crtc_timing.h_total - 182 patched_crtc_timing.h_front_porch; 183 184 /* blank_end = blank_start - active */ 185 asic_blank_end = asic_blank_start - 186 patched_crtc_timing.h_border_right - 187 patched_crtc_timing.h_addressable - 188 patched_crtc_timing.h_border_left; 189 190 REG_UPDATE_2(OTG_H_BLANK_START_END, 191 OTG_H_BLANK_START, asic_blank_start, 192 OTG_H_BLANK_END, asic_blank_end); 193 194 /* h_sync polarity */ 195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 196 0 : 1; 197 198 REG_UPDATE(OTG_H_SYNC_A_CNTL, 199 OTG_H_SYNC_A_POL, h_sync_polarity); 200 201 v_total = patched_crtc_timing.v_total - 1; 202 203 REG_SET(OTG_V_TOTAL, 0, 204 OTG_V_TOTAL, v_total); 205 206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 207 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 208 */ 209 REG_SET(OTG_V_TOTAL_MAX, 0, 210 OTG_V_TOTAL_MAX, v_total); 211 REG_SET(OTG_V_TOTAL_MIN, 0, 212 OTG_V_TOTAL_MIN, v_total); 213 214 /* v_sync_start = 0, v_sync_end = v_sync_width */ 215 v_sync_end = patched_crtc_timing.v_sync_width; 216 217 REG_UPDATE_2(OTG_V_SYNC_A, 218 OTG_V_SYNC_A_START, 0, 219 OTG_V_SYNC_A_END, v_sync_end); 220 221 /* blank_start = frame end - front porch */ 222 asic_blank_start = patched_crtc_timing.v_total - 223 patched_crtc_timing.v_front_porch; 224 225 /* blank_end = blank_start - active */ 226 asic_blank_end = asic_blank_start - 227 patched_crtc_timing.v_border_bottom - 228 patched_crtc_timing.v_addressable - 229 patched_crtc_timing.v_border_top; 230 231 REG_UPDATE_2(OTG_V_BLANK_START_END, 232 OTG_V_BLANK_START, asic_blank_start, 233 OTG_V_BLANK_END, asic_blank_end); 234 235 /* v_sync polarity */ 236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 237 0 : 1; 238 239 REG_UPDATE(OTG_V_SYNC_A_CNTL, 240 OTG_V_SYNC_A_POL, v_sync_polarity); 241 242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 244 optc1->signal == SIGNAL_TYPE_EDP) { 245 start_point = 1; 246 if (patched_crtc_timing.flags.INTERLACE == 1) 247 field_num = 1; 248 } 249 250 /* Interlace */ 251 if (REG(OTG_INTERLACE_CONTROL)) { 252 if (patched_crtc_timing.flags.INTERLACE == 1) 253 REG_UPDATE(OTG_INTERLACE_CONTROL, 254 OTG_INTERLACE_ENABLE, 1); 255 else 256 REG_UPDATE(OTG_INTERLACE_CONTROL, 257 OTG_INTERLACE_ENABLE, 0); 258 } 259 260 /* VTG enable set to 0 first VInit */ 261 REG_UPDATE(CONTROL, 262 VTG0_ENABLE, 0); 263 264 /* original code is using VTG offset to address OTG reg, seems wrong */ 265 REG_UPDATE_2(OTG_CONTROL, 266 OTG_START_POINT_CNTL, start_point, 267 OTG_FIELD_NUMBER_CNTL, field_num); 268 269 optc->funcs->program_global_sync(optc, 270 vready_offset, 271 vstartup_start, 272 vupdate_offset, 273 vupdate_width); 274 275 optc->funcs->set_vtg_params(optc, dc_crtc_timing); 276 277 /* TODO 278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 279 * program_horz_count_by_2 280 * for DVI 30bpp mode, 0 otherwise 281 * program_horz_count_by_2(optc, &patched_crtc_timing); 282 */ 283 284 /* Enable stereo - only when we need to pack 3D frame. Other types 285 * of stereo handled in explicit call 286 */ 287 288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) 289 h_div = H_TIMING_DIV_BY2; 290 291 if (REG(OPTC_DATA_FORMAT_CONTROL)) { 292 uint32_t data_fmt = 0; 293 294 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 295 data_fmt = 1; 296 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 297 data_fmt = 2; 298 299 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 300 } 301 302 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { 303 if (optc1->opp_count == 4) 304 h_div = H_TIMING_DIV_BY4; 305 306 REG_UPDATE(OTG_H_TIMING_CNTL, 307 OTG_H_TIMING_DIV_MODE, h_div); 308 } else { 309 REG_UPDATE(OTG_H_TIMING_CNTL, 310 OTG_H_TIMING_DIV_BY2, h_div); 311 } 312 } 313 314 void optc1_set_vtg_params(struct timing_generator *optc, 315 const struct dc_crtc_timing *dc_crtc_timing) 316 { 317 struct dc_crtc_timing patched_crtc_timing; 318 uint32_t asic_blank_end; 319 uint32_t v_init; 320 uint32_t v_fp2 = 0; 321 int32_t vertical_line_start; 322 323 struct optc *optc1 = DCN10TG_FROM_TG(optc); 324 325 patched_crtc_timing = *dc_crtc_timing; 326 apply_front_porch_workaround(&patched_crtc_timing); 327 328 /* VCOUNT_INIT is the start of blank */ 329 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 330 331 /* end of blank = v_init - active */ 332 asic_blank_end = v_init - 333 patched_crtc_timing.v_border_bottom - 334 patched_crtc_timing.v_addressable - 335 patched_crtc_timing.v_border_top; 336 337 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 338 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 339 if (vertical_line_start < 0) 340 v_fp2 = -vertical_line_start; 341 342 /* Interlace */ 343 if (REG(OTG_INTERLACE_CONTROL)) { 344 if (patched_crtc_timing.flags.INTERLACE == 1) { 345 v_init = v_init / 2; 346 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 347 v_fp2 = v_fp2 / 2; 348 } 349 } 350 351 REG_UPDATE_2(CONTROL, 352 VTG0_FP2, v_fp2, 353 VTG0_VCOUNT_INIT, v_init); 354 } 355 356 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 357 { 358 struct optc *optc1 = DCN10TG_FROM_TG(optc); 359 360 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 361 362 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 363 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 364 } 365 366 /** 367 * optc1_set_timing_double_buffer() - DRR double buffering control 368 * 369 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 370 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 371 * 372 * Options: any time, start of frame, dp start of frame (range timing) 373 */ 374 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 375 { 376 struct optc *optc1 = DCN10TG_FROM_TG(optc); 377 uint32_t mode = enable ? 2 : 0; 378 379 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 380 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode); 381 } 382 383 /** 384 * unblank_crtc 385 * Call ASIC Control Object to UnBlank CRTC. 386 */ 387 static void optc1_unblank_crtc(struct timing_generator *optc) 388 { 389 struct optc *optc1 = DCN10TG_FROM_TG(optc); 390 391 REG_UPDATE_2(OTG_BLANK_CONTROL, 392 OTG_BLANK_DATA_EN, 0, 393 OTG_BLANK_DE_MODE, 0); 394 395 /* W/A for automated testing 396 * Automated testing will fail underflow test as there 397 * sporadic underflows which occur during the optc blank 398 * sequence. As a w/a, clear underflow on unblank. 399 * This prevents the failure, but will not mask actual 400 * underflow that affect real use cases. 401 */ 402 optc1_clear_optc_underflow(optc); 403 } 404 405 /** 406 * blank_crtc 407 * Call ASIC Control Object to Blank CRTC. 408 */ 409 410 static void optc1_blank_crtc(struct timing_generator *optc) 411 { 412 struct optc *optc1 = DCN10TG_FROM_TG(optc); 413 414 REG_UPDATE_2(OTG_BLANK_CONTROL, 415 OTG_BLANK_DATA_EN, 1, 416 OTG_BLANK_DE_MODE, 0); 417 418 optc1_set_blank_data_double_buffer(optc, false); 419 } 420 421 void optc1_set_blank(struct timing_generator *optc, 422 bool enable_blanking) 423 { 424 if (enable_blanking) 425 optc1_blank_crtc(optc); 426 else 427 optc1_unblank_crtc(optc); 428 } 429 430 bool optc1_is_blanked(struct timing_generator *optc) 431 { 432 struct optc *optc1 = DCN10TG_FROM_TG(optc); 433 uint32_t blank_en; 434 uint32_t blank_state; 435 436 REG_GET_2(OTG_BLANK_CONTROL, 437 OTG_BLANK_DATA_EN, &blank_en, 438 OTG_CURRENT_BLANK_STATE, &blank_state); 439 440 return blank_en && blank_state; 441 } 442 443 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 444 { 445 struct optc *optc1 = DCN10TG_FROM_TG(optc); 446 447 if (enable) { 448 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 449 OPTC_INPUT_CLK_EN, 1, 450 OPTC_INPUT_CLK_GATE_DIS, 1); 451 452 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 453 OPTC_INPUT_CLK_ON, 1, 454 1, 1000); 455 456 /* Enable clock */ 457 REG_UPDATE_2(OTG_CLOCK_CONTROL, 458 OTG_CLOCK_EN, 1, 459 OTG_CLOCK_GATE_DIS, 1); 460 REG_WAIT(OTG_CLOCK_CONTROL, 461 OTG_CLOCK_ON, 1, 462 1, 1000); 463 } else { 464 REG_UPDATE_2(OTG_CLOCK_CONTROL, 465 OTG_CLOCK_GATE_DIS, 0, 466 OTG_CLOCK_EN, 0); 467 468 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 469 OPTC_INPUT_CLK_GATE_DIS, 0, 470 OPTC_INPUT_CLK_EN, 0); 471 } 472 } 473 474 /** 475 * Enable CRTC 476 * Enable CRTC - call ASIC Control Object to enable Timing generator. 477 */ 478 static bool optc1_enable_crtc(struct timing_generator *optc) 479 { 480 /* TODO FPGA wait for answer 481 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 482 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 483 */ 484 struct optc *optc1 = DCN10TG_FROM_TG(optc); 485 486 /* opp instance for OTG. For DCN1.0, ODM is remoed. 487 * OPP and OPTC should 1:1 mapping 488 */ 489 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 490 OPTC_SRC_SEL, optc->inst); 491 492 /* VTG enable first is for HW workaround */ 493 REG_UPDATE(CONTROL, 494 VTG0_ENABLE, 1); 495 496 REG_SEQ_START(); 497 498 /* Enable CRTC */ 499 REG_UPDATE_2(OTG_CONTROL, 500 OTG_DISABLE_POINT_CNTL, 3, 501 OTG_MASTER_EN, 1); 502 503 REG_SEQ_SUBMIT(); 504 REG_SEQ_WAIT_DONE(); 505 506 return true; 507 } 508 509 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 510 bool optc1_disable_crtc(struct timing_generator *optc) 511 { 512 struct optc *optc1 = DCN10TG_FROM_TG(optc); 513 514 /* disable otg request until end of the first line 515 * in the vertical blank region 516 */ 517 REG_UPDATE_2(OTG_CONTROL, 518 OTG_DISABLE_POINT_CNTL, 3, 519 OTG_MASTER_EN, 0); 520 521 REG_UPDATE(CONTROL, 522 VTG0_ENABLE, 0); 523 524 /* CRTC disabled, so disable clock. */ 525 REG_WAIT(OTG_CLOCK_CONTROL, 526 OTG_BUSY, 0, 527 1, 100000); 528 529 return true; 530 } 531 532 533 void optc1_program_blank_color( 534 struct timing_generator *optc, 535 const struct tg_color *black_color) 536 { 537 struct optc *optc1 = DCN10TG_FROM_TG(optc); 538 539 REG_SET_3(OTG_BLACK_COLOR, 0, 540 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 541 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 542 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 543 } 544 545 bool optc1_validate_timing( 546 struct timing_generator *optc, 547 const struct dc_crtc_timing *timing) 548 { 549 uint32_t v_blank; 550 uint32_t h_blank; 551 uint32_t min_v_blank; 552 struct optc *optc1 = DCN10TG_FROM_TG(optc); 553 554 ASSERT(timing != NULL); 555 556 v_blank = (timing->v_total - timing->v_addressable - 557 timing->v_border_top - timing->v_border_bottom); 558 559 h_blank = (timing->h_total - timing->h_addressable - 560 timing->h_border_right - 561 timing->h_border_left); 562 563 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 564 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 565 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 566 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 567 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 568 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 569 return false; 570 571 /* Temporarily blocking interlacing mode until it's supported */ 572 if (timing->flags.INTERLACE == 1) 573 return false; 574 575 /* Check maximum number of pixels supported by Timing Generator 576 * (Currently will never fail, in order to fail needs display which 577 * needs more than 8192 horizontal and 578 * more than 8192 vertical total pixels) 579 */ 580 if (timing->h_total > optc1->max_h_total || 581 timing->v_total > optc1->max_v_total) 582 return false; 583 584 585 if (h_blank < optc1->min_h_blank) 586 return false; 587 588 if (timing->h_sync_width < optc1->min_h_sync_width || 589 timing->v_sync_width < optc1->min_v_sync_width) 590 return false; 591 592 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 593 594 if (v_blank < min_v_blank) 595 return false; 596 597 return true; 598 599 } 600 601 /* 602 * get_vblank_counter 603 * 604 * @brief 605 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 606 * holds the counter of frames. 607 * 608 * @param 609 * struct timing_generator *optc - [in] timing generator which controls the 610 * desired CRTC 611 * 612 * @return 613 * Counter of frames, which should equal to number of vblanks. 614 */ 615 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 616 { 617 struct optc *optc1 = DCN10TG_FROM_TG(optc); 618 uint32_t frame_count; 619 620 REG_GET(OTG_STATUS_FRAME_COUNT, 621 OTG_FRAME_COUNT, &frame_count); 622 623 return frame_count; 624 } 625 626 void optc1_lock(struct timing_generator *optc) 627 { 628 struct optc *optc1 = DCN10TG_FROM_TG(optc); 629 uint32_t regval = 0; 630 631 regval = REG_READ(OTG_CONTROL); 632 633 /* otg is not running, do not need to be locked */ 634 if ((regval & 0x1) == 0x0) 635 return; 636 637 REG_SET(OTG_GLOBAL_CONTROL0, 0, 638 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 639 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 640 OTG_MASTER_UPDATE_LOCK, 1); 641 642 /* Should be fast, status does not update on maximus */ 643 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { 644 645 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 646 UPDATE_LOCK_STATUS, 1, 647 1, 10); 648 } 649 } 650 651 void optc1_unlock(struct timing_generator *optc) 652 { 653 struct optc *optc1 = DCN10TG_FROM_TG(optc); 654 655 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 656 OTG_MASTER_UPDATE_LOCK, 0); 657 } 658 659 void optc1_get_position(struct timing_generator *optc, 660 struct crtc_position *position) 661 { 662 struct optc *optc1 = DCN10TG_FROM_TG(optc); 663 664 REG_GET_2(OTG_STATUS_POSITION, 665 OTG_HORZ_COUNT, &position->horizontal_count, 666 OTG_VERT_COUNT, &position->vertical_count); 667 668 REG_GET(OTG_NOM_VERT_POSITION, 669 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 670 } 671 672 bool optc1_is_counter_moving(struct timing_generator *optc) 673 { 674 struct crtc_position position1, position2; 675 676 optc->funcs->get_position(optc, &position1); 677 optc->funcs->get_position(optc, &position2); 678 679 if (position1.horizontal_count == position2.horizontal_count && 680 position1.vertical_count == position2.vertical_count) 681 return false; 682 else 683 return true; 684 } 685 686 bool optc1_did_triggered_reset_occur( 687 struct timing_generator *optc) 688 { 689 struct optc *optc1 = DCN10TG_FROM_TG(optc); 690 uint32_t occurred_force, occurred_vsync; 691 692 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 693 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 694 695 REG_GET(OTG_VERT_SYNC_CONTROL, 696 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 697 698 return occurred_vsync != 0 || occurred_force != 0; 699 } 700 701 void optc1_disable_reset_trigger(struct timing_generator *optc) 702 { 703 struct optc *optc1 = DCN10TG_FROM_TG(optc); 704 705 REG_WRITE(OTG_TRIGA_CNTL, 0); 706 707 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 708 OTG_FORCE_COUNT_NOW_CLEAR, 1); 709 710 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 711 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 712 } 713 714 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 715 { 716 struct optc *optc1 = DCN10TG_FROM_TG(optc); 717 uint32_t falling_edge; 718 719 REG_GET(OTG_V_SYNC_A_CNTL, 720 OTG_V_SYNC_A_POL, &falling_edge); 721 722 if (falling_edge) 723 REG_SET_3(OTG_TRIGA_CNTL, 0, 724 /* vsync signal from selected OTG pipe based 725 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 726 */ 727 OTG_TRIGA_SOURCE_SELECT, 20, 728 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 729 /* always detect falling edge */ 730 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 731 else 732 REG_SET_3(OTG_TRIGA_CNTL, 0, 733 /* vsync signal from selected OTG pipe based 734 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 735 */ 736 OTG_TRIGA_SOURCE_SELECT, 20, 737 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 738 /* always detect rising edge */ 739 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 740 741 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 742 /* force H count to H_TOTAL and V count to V_TOTAL in 743 * progressive mode and V_TOTAL-1 in interlaced mode 744 */ 745 OTG_FORCE_COUNT_NOW_MODE, 2); 746 } 747 748 void optc1_enable_crtc_reset( 749 struct timing_generator *optc, 750 int source_tg_inst, 751 struct crtc_trigger_info *crtc_tp) 752 { 753 struct optc *optc1 = DCN10TG_FROM_TG(optc); 754 uint32_t falling_edge = 0; 755 uint32_t rising_edge = 0; 756 757 switch (crtc_tp->event) { 758 759 case CRTC_EVENT_VSYNC_RISING: 760 rising_edge = 1; 761 break; 762 763 case CRTC_EVENT_VSYNC_FALLING: 764 falling_edge = 1; 765 break; 766 } 767 768 REG_SET_4(OTG_TRIGA_CNTL, 0, 769 /* vsync signal from selected OTG pipe based 770 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 771 */ 772 OTG_TRIGA_SOURCE_SELECT, 20, 773 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 774 /* always detect falling edge */ 775 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 776 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 777 778 switch (crtc_tp->delay) { 779 case TRIGGER_DELAY_NEXT_LINE: 780 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 781 OTG_AUTO_FORCE_VSYNC_MODE, 1); 782 break; 783 case TRIGGER_DELAY_NEXT_PIXEL: 784 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 785 /* force H count to H_TOTAL and V count to V_TOTAL in 786 * progressive mode and V_TOTAL-1 in interlaced mode 787 */ 788 OTG_FORCE_COUNT_NOW_MODE, 2); 789 break; 790 } 791 } 792 793 void optc1_wait_for_state(struct timing_generator *optc, 794 enum crtc_state state) 795 { 796 struct optc *optc1 = DCN10TG_FROM_TG(optc); 797 798 switch (state) { 799 case CRTC_STATE_VBLANK: 800 REG_WAIT(OTG_STATUS, 801 OTG_V_BLANK, 1, 802 1, 100000); /* 1 vupdate at 10hz */ 803 break; 804 805 case CRTC_STATE_VACTIVE: 806 REG_WAIT(OTG_STATUS, 807 OTG_V_ACTIVE_DISP, 1, 808 1, 100000); /* 1 vupdate at 10hz */ 809 break; 810 811 default: 812 break; 813 } 814 } 815 816 void optc1_set_early_control( 817 struct timing_generator *optc, 818 uint32_t early_cntl) 819 { 820 /* asic design change, do not need this control 821 * empty for share caller logic 822 */ 823 } 824 825 826 void optc1_set_static_screen_control( 827 struct timing_generator *optc, 828 uint32_t event_triggers, 829 uint32_t num_frames) 830 { 831 struct optc *optc1 = DCN10TG_FROM_TG(optc); 832 833 // By register spec, it only takes 8 bit value 834 if (num_frames > 0xFF) 835 num_frames = 0xFF; 836 837 /* Bit 8 is no longer applicable in RV for PSR case, 838 * set bit 8 to 0 if given 839 */ 840 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 841 != 0) 842 event_triggers = event_triggers & 843 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 844 845 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 846 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 847 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 848 } 849 850 void optc1_setup_manual_trigger(struct timing_generator *optc) 851 { 852 struct optc *optc1 = DCN10TG_FROM_TG(optc); 853 854 REG_SET(OTG_GLOBAL_CONTROL2, 0, 855 MANUAL_FLOW_CONTROL_SEL, optc->inst); 856 857 REG_SET_8(OTG_TRIGA_CNTL, 0, 858 OTG_TRIGA_SOURCE_SELECT, 22, 859 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 860 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 861 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 862 OTG_TRIGA_POLARITY_SELECT, 0, 863 OTG_TRIGA_FREQUENCY_SELECT, 0, 864 OTG_TRIGA_DELAY, 0, 865 OTG_TRIGA_CLEAR, 1); 866 } 867 868 void optc1_program_manual_trigger(struct timing_generator *optc) 869 { 870 struct optc *optc1 = DCN10TG_FROM_TG(optc); 871 872 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 873 MANUAL_FLOW_CONTROL, 1); 874 875 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 876 MANUAL_FLOW_CONTROL, 0); 877 } 878 879 880 /** 881 ***************************************************************************** 882 * Function: set_drr 883 * 884 * @brief 885 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 886 * 887 ***************************************************************************** 888 */ 889 void optc1_set_drr( 890 struct timing_generator *optc, 891 const struct drr_params *params) 892 { 893 struct optc *optc1 = DCN10TG_FROM_TG(optc); 894 895 if (params != NULL && 896 params->vertical_total_max > 0 && 897 params->vertical_total_min > 0) { 898 899 if (params->vertical_total_mid != 0) { 900 901 REG_SET(OTG_V_TOTAL_MID, 0, 902 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 903 904 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 905 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 906 OTG_VTOTAL_MID_FRAME_NUM, 907 (uint8_t)params->vertical_total_mid_frame_num); 908 909 } 910 911 REG_SET(OTG_V_TOTAL_MAX, 0, 912 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 913 914 REG_SET(OTG_V_TOTAL_MIN, 0, 915 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 916 917 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 918 OTG_V_TOTAL_MIN_SEL, 1, 919 OTG_V_TOTAL_MAX_SEL, 1, 920 OTG_FORCE_LOCK_ON_EVENT, 0, 921 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 922 OTG_SET_V_TOTAL_MIN_MASK, 0); 923 924 // Setup manual flow control for EOF via TRIG_A 925 optc->funcs->setup_manual_trigger(optc); 926 927 } else { 928 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 929 OTG_SET_V_TOTAL_MIN_MASK, 0, 930 OTG_V_TOTAL_MIN_SEL, 0, 931 OTG_V_TOTAL_MAX_SEL, 0, 932 OTG_FORCE_LOCK_ON_EVENT, 0); 933 934 REG_SET(OTG_V_TOTAL_MIN, 0, 935 OTG_V_TOTAL_MIN, 0); 936 937 REG_SET(OTG_V_TOTAL_MAX, 0, 938 OTG_V_TOTAL_MAX, 0); 939 } 940 } 941 942 static void optc1_set_test_pattern( 943 struct timing_generator *optc, 944 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 945 * because this is not DP-specific (which is probably somewhere in DP 946 * encoder) */ 947 enum controller_dp_test_pattern test_pattern, 948 enum dc_color_depth color_depth) 949 { 950 struct optc *optc1 = DCN10TG_FROM_TG(optc); 951 enum test_pattern_color_format bit_depth; 952 enum test_pattern_dyn_range dyn_range; 953 enum test_pattern_mode mode; 954 uint32_t pattern_mask; 955 uint32_t pattern_data; 956 /* color ramp generator mixes 16-bits color */ 957 uint32_t src_bpc = 16; 958 /* requested bpc */ 959 uint32_t dst_bpc; 960 uint32_t index; 961 /* RGB values of the color bars. 962 * Produce two RGB colors: RGB0 - white (all Fs) 963 * and RGB1 - black (all 0s) 964 * (three RGB components for two colors) 965 */ 966 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 967 0x0000, 0x0000}; 968 /* dest color (converted to the specified color format) */ 969 uint16_t dst_color[6]; 970 uint32_t inc_base; 971 972 /* translate to bit depth */ 973 switch (color_depth) { 974 case COLOR_DEPTH_666: 975 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 976 break; 977 case COLOR_DEPTH_888: 978 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 979 break; 980 case COLOR_DEPTH_101010: 981 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 982 break; 983 case COLOR_DEPTH_121212: 984 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 985 break; 986 default: 987 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 988 break; 989 } 990 991 switch (test_pattern) { 992 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 993 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 994 { 995 dyn_range = (test_pattern == 996 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 997 TEST_PATTERN_DYN_RANGE_CEA : 998 TEST_PATTERN_DYN_RANGE_VESA); 999 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 1000 1001 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 1002 OTG_TEST_PATTERN_VRES, 6, 1003 OTG_TEST_PATTERN_HRES, 6); 1004 1005 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1006 OTG_TEST_PATTERN_EN, 1, 1007 OTG_TEST_PATTERN_MODE, mode, 1008 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 1009 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1010 } 1011 break; 1012 1013 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 1014 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 1015 { 1016 mode = (test_pattern == 1017 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 1018 TEST_PATTERN_MODE_VERTICALBARS : 1019 TEST_PATTERN_MODE_HORIZONTALBARS); 1020 1021 switch (bit_depth) { 1022 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1023 dst_bpc = 6; 1024 break; 1025 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1026 dst_bpc = 8; 1027 break; 1028 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1029 dst_bpc = 10; 1030 break; 1031 default: 1032 dst_bpc = 8; 1033 break; 1034 } 1035 1036 /* adjust color to the required colorFormat */ 1037 for (index = 0; index < 6; index++) { 1038 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1039 * (srcBpc - dstBpc); 1040 */ 1041 dst_color[index] = 1042 src_color[index] >> (src_bpc - dst_bpc); 1043 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1044 * lowest 6 are hardwired to ZERO 1045 * color bits should be left aligned aligned to MSB 1046 * XXXXXXXXXX000000 for 10 bit, 1047 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1048 */ 1049 dst_color[index] <<= (16 - dst_bpc); 1050 } 1051 1052 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1053 1054 /* We have to write the mask before data, similar to pipeline. 1055 * For example, for 8 bpc, if we want RGB0 to be magenta, 1056 * and RGB1 to be cyan, 1057 * we need to make 7 writes: 1058 * MASK DATA 1059 * 000001 00000000 00000000 set mask to R0 1060 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1061 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1062 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1063 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1064 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1065 * 100000 11111111 00000000 B1 255, 0xFF00 1066 * 1067 * we will make a loop of 6 in which we prepare the mask, 1068 * then write, then prepare the color for next write. 1069 * first iteration will write mask only, 1070 * but each next iteration color prepared in 1071 * previous iteration will be written within new mask, 1072 * the last component will written separately, 1073 * mask is not changing between 6th and 7th write 1074 * and color will be prepared by last iteration 1075 */ 1076 1077 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1078 * is B1, G1, R1, B0, G0, R0 1079 */ 1080 pattern_data = 0; 1081 for (index = 0; index < 6; index++) { 1082 /* prepare color mask, first write PATTERN_DATA 1083 * will have all zeros 1084 */ 1085 pattern_mask = (1 << index); 1086 1087 /* write color component */ 1088 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1089 OTG_TEST_PATTERN_MASK, pattern_mask, 1090 OTG_TEST_PATTERN_DATA, pattern_data); 1091 1092 /* prepare next color component, 1093 * will be written in the next iteration 1094 */ 1095 pattern_data = dst_color[index]; 1096 } 1097 /* write last color component, 1098 * it's been already prepared in the loop 1099 */ 1100 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1101 OTG_TEST_PATTERN_MASK, pattern_mask, 1102 OTG_TEST_PATTERN_DATA, pattern_data); 1103 1104 /* enable test pattern */ 1105 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1106 OTG_TEST_PATTERN_EN, 1, 1107 OTG_TEST_PATTERN_MODE, mode, 1108 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1109 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1110 } 1111 break; 1112 1113 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1114 { 1115 mode = (bit_depth == 1116 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1117 TEST_PATTERN_MODE_DUALRAMP_RGB : 1118 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1119 1120 switch (bit_depth) { 1121 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1122 dst_bpc = 6; 1123 break; 1124 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1125 dst_bpc = 8; 1126 break; 1127 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1128 dst_bpc = 10; 1129 break; 1130 default: 1131 dst_bpc = 8; 1132 break; 1133 } 1134 1135 /* increment for the first ramp for one color gradation 1136 * 1 gradation for 6-bit color is 2^10 1137 * gradations in 16-bit color 1138 */ 1139 inc_base = (src_bpc - dst_bpc); 1140 1141 switch (bit_depth) { 1142 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1143 { 1144 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1145 OTG_TEST_PATTERN_INC0, inc_base, 1146 OTG_TEST_PATTERN_INC1, 0, 1147 OTG_TEST_PATTERN_HRES, 6, 1148 OTG_TEST_PATTERN_VRES, 6, 1149 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1150 } 1151 break; 1152 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1153 { 1154 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1155 OTG_TEST_PATTERN_INC0, inc_base, 1156 OTG_TEST_PATTERN_INC1, 0, 1157 OTG_TEST_PATTERN_HRES, 8, 1158 OTG_TEST_PATTERN_VRES, 6, 1159 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1160 } 1161 break; 1162 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1163 { 1164 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1165 OTG_TEST_PATTERN_INC0, inc_base, 1166 OTG_TEST_PATTERN_INC1, inc_base + 2, 1167 OTG_TEST_PATTERN_HRES, 8, 1168 OTG_TEST_PATTERN_VRES, 5, 1169 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1170 } 1171 break; 1172 default: 1173 break; 1174 } 1175 1176 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1177 1178 /* enable test pattern */ 1179 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1180 1181 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1182 OTG_TEST_PATTERN_EN, 1, 1183 OTG_TEST_PATTERN_MODE, mode, 1184 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1185 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1186 } 1187 break; 1188 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1189 { 1190 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1191 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1192 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1193 } 1194 break; 1195 default: 1196 break; 1197 1198 } 1199 } 1200 1201 void optc1_get_crtc_scanoutpos( 1202 struct timing_generator *optc, 1203 uint32_t *v_blank_start, 1204 uint32_t *v_blank_end, 1205 uint32_t *h_position, 1206 uint32_t *v_position) 1207 { 1208 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1209 struct crtc_position position; 1210 1211 REG_GET_2(OTG_V_BLANK_START_END, 1212 OTG_V_BLANK_START, v_blank_start, 1213 OTG_V_BLANK_END, v_blank_end); 1214 1215 optc1_get_position(optc, &position); 1216 1217 *h_position = position.horizontal_count; 1218 *v_position = position.vertical_count; 1219 } 1220 1221 static void optc1_enable_stereo(struct timing_generator *optc, 1222 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1223 { 1224 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1225 1226 if (flags) { 1227 uint32_t stereo_en; 1228 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1229 1230 if (flags->PROGRAM_STEREO) 1231 REG_UPDATE_3(OTG_STEREO_CONTROL, 1232 OTG_STEREO_EN, stereo_en, 1233 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1234 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1235 1236 if (flags->PROGRAM_POLARITY) 1237 REG_UPDATE(OTG_STEREO_CONTROL, 1238 OTG_STEREO_EYE_FLAG_POLARITY, 1239 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1240 1241 if (flags->DISABLE_STEREO_DP_SYNC) 1242 REG_UPDATE(OTG_STEREO_CONTROL, 1243 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1244 1245 if (flags->PROGRAM_STEREO) 1246 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1247 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1248 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1249 1250 } 1251 } 1252 1253 void optc1_program_stereo(struct timing_generator *optc, 1254 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1255 { 1256 if (flags->PROGRAM_STEREO) 1257 optc1_enable_stereo(optc, timing, flags); 1258 else 1259 optc1_disable_stereo(optc); 1260 } 1261 1262 1263 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1264 { 1265 bool ret = false; 1266 uint32_t left_eye = 0; 1267 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1268 1269 REG_GET(OTG_STEREO_STATUS, 1270 OTG_STEREO_CURRENT_EYE, &left_eye); 1271 if (left_eye == 1) 1272 ret = true; 1273 else 1274 ret = false; 1275 1276 return ret; 1277 } 1278 1279 bool optc1_get_hw_timing(struct timing_generator *tg, 1280 struct dc_crtc_timing *hw_crtc_timing) 1281 { 1282 struct dcn_otg_state s = {0}; 1283 1284 if (tg == NULL || hw_crtc_timing == NULL) 1285 return false; 1286 1287 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1288 1289 hw_crtc_timing->h_total = s.h_total + 1; 1290 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1291 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1292 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1293 1294 hw_crtc_timing->v_total = s.v_total + 1; 1295 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1296 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1297 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1298 1299 return true; 1300 } 1301 1302 1303 void optc1_read_otg_state(struct optc *optc1, 1304 struct dcn_otg_state *s) 1305 { 1306 REG_GET(OTG_CONTROL, 1307 OTG_MASTER_EN, &s->otg_enabled); 1308 1309 REG_GET_2(OTG_V_BLANK_START_END, 1310 OTG_V_BLANK_START, &s->v_blank_start, 1311 OTG_V_BLANK_END, &s->v_blank_end); 1312 1313 REG_GET(OTG_V_SYNC_A_CNTL, 1314 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1315 1316 REG_GET(OTG_V_TOTAL, 1317 OTG_V_TOTAL, &s->v_total); 1318 1319 REG_GET(OTG_V_TOTAL_MAX, 1320 OTG_V_TOTAL_MAX, &s->v_total_max); 1321 1322 REG_GET(OTG_V_TOTAL_MIN, 1323 OTG_V_TOTAL_MIN, &s->v_total_min); 1324 1325 REG_GET(OTG_V_TOTAL_CONTROL, 1326 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1327 1328 REG_GET(OTG_V_TOTAL_CONTROL, 1329 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1330 1331 REG_GET_2(OTG_V_SYNC_A, 1332 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1333 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1334 1335 REG_GET_2(OTG_H_BLANK_START_END, 1336 OTG_H_BLANK_START, &s->h_blank_start, 1337 OTG_H_BLANK_END, &s->h_blank_end); 1338 1339 REG_GET_2(OTG_H_SYNC_A, 1340 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1341 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1342 1343 REG_GET(OTG_H_SYNC_A_CNTL, 1344 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1345 1346 REG_GET(OTG_H_TOTAL, 1347 OTG_H_TOTAL, &s->h_total); 1348 1349 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1350 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1351 } 1352 1353 bool optc1_get_otg_active_size(struct timing_generator *optc, 1354 uint32_t *otg_active_width, 1355 uint32_t *otg_active_height) 1356 { 1357 uint32_t otg_enabled; 1358 uint32_t v_blank_start; 1359 uint32_t v_blank_end; 1360 uint32_t h_blank_start; 1361 uint32_t h_blank_end; 1362 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1363 1364 1365 REG_GET(OTG_CONTROL, 1366 OTG_MASTER_EN, &otg_enabled); 1367 1368 if (otg_enabled == 0) 1369 return false; 1370 1371 REG_GET_2(OTG_V_BLANK_START_END, 1372 OTG_V_BLANK_START, &v_blank_start, 1373 OTG_V_BLANK_END, &v_blank_end); 1374 1375 REG_GET_2(OTG_H_BLANK_START_END, 1376 OTG_H_BLANK_START, &h_blank_start, 1377 OTG_H_BLANK_END, &h_blank_end); 1378 1379 *otg_active_width = v_blank_start - v_blank_end; 1380 *otg_active_height = h_blank_start - h_blank_end; 1381 return true; 1382 } 1383 1384 void optc1_clear_optc_underflow(struct timing_generator *optc) 1385 { 1386 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1387 1388 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1389 } 1390 1391 void optc1_tg_init(struct timing_generator *optc) 1392 { 1393 optc1_set_blank_data_double_buffer(optc, true); 1394 optc1_set_timing_double_buffer(optc, true); 1395 optc1_clear_optc_underflow(optc); 1396 } 1397 1398 bool optc1_is_tg_enabled(struct timing_generator *optc) 1399 { 1400 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1401 uint32_t otg_enabled = 0; 1402 1403 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1404 1405 return (otg_enabled != 0); 1406 1407 } 1408 1409 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1410 { 1411 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1412 uint32_t underflow_occurred = 0; 1413 1414 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1415 OPTC_UNDERFLOW_OCCURRED_STATUS, 1416 &underflow_occurred); 1417 1418 return (underflow_occurred == 1); 1419 } 1420 1421 bool optc1_configure_crc(struct timing_generator *optc, 1422 const struct crc_params *params) 1423 { 1424 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1425 1426 /* Cannot configure crc on a CRTC that is disabled */ 1427 if (!optc1_is_tg_enabled(optc)) 1428 return false; 1429 1430 REG_WRITE(OTG_CRC_CNTL, 0); 1431 1432 if (!params->enable) 1433 return true; 1434 1435 /* Program frame boundaries */ 1436 /* Window A x axis start and end. */ 1437 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1438 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1439 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1440 1441 /* Window A y axis start and end. */ 1442 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1443 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1444 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1445 1446 /* Window B x axis start and end. */ 1447 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1448 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1449 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1450 1451 /* Window B y axis start and end. */ 1452 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1453 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1454 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1455 1456 /* Set crc mode and selection, and enable. Only using CRC0*/ 1457 REG_UPDATE_3(OTG_CRC_CNTL, 1458 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1459 OTG_CRC0_SELECT, params->selection, 1460 OTG_CRC_EN, 1); 1461 1462 return true; 1463 } 1464 1465 bool optc1_get_crc(struct timing_generator *optc, 1466 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1467 { 1468 uint32_t field = 0; 1469 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1470 1471 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1472 1473 /* Early return if CRC is not enabled for this CRTC */ 1474 if (!field) 1475 return false; 1476 1477 REG_GET_2(OTG_CRC0_DATA_RG, 1478 CRC0_R_CR, r_cr, 1479 CRC0_G_Y, g_y); 1480 1481 REG_GET(OTG_CRC0_DATA_B, 1482 CRC0_B_CB, b_cb); 1483 1484 return true; 1485 } 1486 1487 static const struct timing_generator_funcs dcn10_tg_funcs = { 1488 .validate_timing = optc1_validate_timing, 1489 .program_timing = optc1_program_timing, 1490 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1491 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1492 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1493 .program_global_sync = optc1_program_global_sync, 1494 .enable_crtc = optc1_enable_crtc, 1495 .disable_crtc = optc1_disable_crtc, 1496 /* used by enable_timing_synchronization. Not need for FPGA */ 1497 .is_counter_moving = optc1_is_counter_moving, 1498 .get_position = optc1_get_position, 1499 .get_frame_count = optc1_get_vblank_counter, 1500 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1501 .get_otg_active_size = optc1_get_otg_active_size, 1502 .set_early_control = optc1_set_early_control, 1503 /* used by enable_timing_synchronization. Not need for FPGA */ 1504 .wait_for_state = optc1_wait_for_state, 1505 .set_blank = optc1_set_blank, 1506 .is_blanked = optc1_is_blanked, 1507 .set_blank_color = optc1_program_blank_color, 1508 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1509 .enable_reset_trigger = optc1_enable_reset_trigger, 1510 .enable_crtc_reset = optc1_enable_crtc_reset, 1511 .disable_reset_trigger = optc1_disable_reset_trigger, 1512 .lock = optc1_lock, 1513 .unlock = optc1_unlock, 1514 .enable_optc_clock = optc1_enable_optc_clock, 1515 .set_drr = optc1_set_drr, 1516 .set_static_screen_control = optc1_set_static_screen_control, 1517 .set_test_pattern = optc1_set_test_pattern, 1518 .program_stereo = optc1_program_stereo, 1519 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1520 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1521 .tg_init = optc1_tg_init, 1522 .is_tg_enabled = optc1_is_tg_enabled, 1523 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1524 .clear_optc_underflow = optc1_clear_optc_underflow, 1525 .get_crc = optc1_get_crc, 1526 .configure_crc = optc1_configure_crc, 1527 .set_vtg_params = optc1_set_vtg_params, 1528 .program_manual_trigger = optc1_program_manual_trigger, 1529 .setup_manual_trigger = optc1_setup_manual_trigger, 1530 .get_hw_timing = optc1_get_hw_timing, 1531 }; 1532 1533 void dcn10_timing_generator_init(struct optc *optc1) 1534 { 1535 optc1->base.funcs = &dcn10_tg_funcs; 1536 1537 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1538 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1539 1540 optc1->min_h_blank = 32; 1541 optc1->min_v_blank = 3; 1542 optc1->min_v_blank_interlace = 5; 1543 optc1->min_h_sync_width = 8; 1544 optc1->min_v_sync_width = 1; 1545 } 1546 1547 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1548 * 1549 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1550 * containter rate. 1551 * 1552 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1553 * halved to maintain the correct pixel rate. 1554 * 1555 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1556 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1557 * 1558 */ 1559 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1560 { 1561 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1562 1563 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1564 && !timing->dsc_cfg.ycbcr422_simple); 1565 return two_pix; 1566 } 1567 1568