1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 uint32_t h_div_2; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 169 /* Load horizontal timing */ 170 171 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 172 REG_SET(OTG_H_TOTAL, 0, 173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 174 175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 176 REG_UPDATE_2(OTG_H_SYNC_A, 177 OTG_H_SYNC_A_START, 0, 178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 179 180 /* blank_start = line end - front porch */ 181 asic_blank_start = patched_crtc_timing.h_total - 182 patched_crtc_timing.h_front_porch; 183 184 /* blank_end = blank_start - active */ 185 asic_blank_end = asic_blank_start - 186 patched_crtc_timing.h_border_right - 187 patched_crtc_timing.h_addressable - 188 patched_crtc_timing.h_border_left; 189 190 REG_UPDATE_2(OTG_H_BLANK_START_END, 191 OTG_H_BLANK_START, asic_blank_start, 192 OTG_H_BLANK_END, asic_blank_end); 193 194 /* h_sync polarity */ 195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 196 0 : 1; 197 198 REG_UPDATE(OTG_H_SYNC_A_CNTL, 199 OTG_H_SYNC_A_POL, h_sync_polarity); 200 201 v_total = patched_crtc_timing.v_total - 1; 202 203 REG_SET(OTG_V_TOTAL, 0, 204 OTG_V_TOTAL, v_total); 205 206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 207 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 208 */ 209 REG_SET(OTG_V_TOTAL_MAX, 0, 210 OTG_V_TOTAL_MAX, v_total); 211 REG_SET(OTG_V_TOTAL_MIN, 0, 212 OTG_V_TOTAL_MIN, v_total); 213 214 /* v_sync_start = 0, v_sync_end = v_sync_width */ 215 v_sync_end = patched_crtc_timing.v_sync_width; 216 217 REG_UPDATE_2(OTG_V_SYNC_A, 218 OTG_V_SYNC_A_START, 0, 219 OTG_V_SYNC_A_END, v_sync_end); 220 221 /* blank_start = frame end - front porch */ 222 asic_blank_start = patched_crtc_timing.v_total - 223 patched_crtc_timing.v_front_porch; 224 225 /* blank_end = blank_start - active */ 226 asic_blank_end = asic_blank_start - 227 patched_crtc_timing.v_border_bottom - 228 patched_crtc_timing.v_addressable - 229 patched_crtc_timing.v_border_top; 230 231 REG_UPDATE_2(OTG_V_BLANK_START_END, 232 OTG_V_BLANK_START, asic_blank_start, 233 OTG_V_BLANK_END, asic_blank_end); 234 235 /* v_sync polarity */ 236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 237 0 : 1; 238 239 REG_UPDATE(OTG_V_SYNC_A_CNTL, 240 OTG_V_SYNC_A_POL, v_sync_polarity); 241 242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 244 optc1->signal == SIGNAL_TYPE_EDP) { 245 start_point = 1; 246 if (patched_crtc_timing.flags.INTERLACE == 1) 247 field_num = 1; 248 } 249 250 /* Interlace */ 251 if (REG(OTG_INTERLACE_CONTROL)) { 252 if (patched_crtc_timing.flags.INTERLACE == 1) 253 REG_UPDATE(OTG_INTERLACE_CONTROL, 254 OTG_INTERLACE_ENABLE, 1); 255 else 256 REG_UPDATE(OTG_INTERLACE_CONTROL, 257 OTG_INTERLACE_ENABLE, 0); 258 } 259 260 /* VTG enable set to 0 first VInit */ 261 REG_UPDATE(CONTROL, 262 VTG0_ENABLE, 0); 263 264 /* original code is using VTG offset to address OTG reg, seems wrong */ 265 REG_UPDATE_2(OTG_CONTROL, 266 OTG_START_POINT_CNTL, start_point, 267 OTG_FIELD_NUMBER_CNTL, field_num); 268 269 optc->funcs->program_global_sync(optc, 270 vready_offset, 271 vstartup_start, 272 vupdate_offset, 273 vupdate_width); 274 275 optc->funcs->set_vtg_params(optc, dc_crtc_timing); 276 277 /* TODO 278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 279 * program_horz_count_by_2 280 * for DVI 30bpp mode, 0 otherwise 281 * program_horz_count_by_2(optc, &patched_crtc_timing); 282 */ 283 284 /* Enable stereo - only when we need to pack 3D frame. Other types 285 * of stereo handled in explicit call 286 */ 287 288 h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing); 289 REG_UPDATE(OTG_H_TIMING_CNTL, 290 OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf); 291 292 } 293 294 void optc1_set_vtg_params(struct timing_generator *optc, 295 const struct dc_crtc_timing *dc_crtc_timing) 296 { 297 struct dc_crtc_timing patched_crtc_timing; 298 uint32_t asic_blank_end; 299 uint32_t v_init; 300 uint32_t v_fp2 = 0; 301 int32_t vertical_line_start; 302 303 struct optc *optc1 = DCN10TG_FROM_TG(optc); 304 305 patched_crtc_timing = *dc_crtc_timing; 306 apply_front_porch_workaround(&patched_crtc_timing); 307 308 /* VCOUNT_INIT is the start of blank */ 309 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 310 311 /* end of blank = v_init - active */ 312 asic_blank_end = v_init - 313 patched_crtc_timing.v_border_bottom - 314 patched_crtc_timing.v_addressable - 315 patched_crtc_timing.v_border_top; 316 317 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 318 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 319 if (vertical_line_start < 0) 320 v_fp2 = -vertical_line_start; 321 322 /* Interlace */ 323 if (REG(OTG_INTERLACE_CONTROL)) { 324 if (patched_crtc_timing.flags.INTERLACE == 1) { 325 v_init = v_init / 2; 326 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 327 v_fp2 = v_fp2 / 2; 328 } 329 } 330 331 REG_UPDATE_2(CONTROL, 332 VTG0_FP2, v_fp2, 333 VTG0_VCOUNT_INIT, v_init); 334 } 335 336 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 337 { 338 struct optc *optc1 = DCN10TG_FROM_TG(optc); 339 340 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 341 342 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 343 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 344 } 345 346 /** 347 * unblank_crtc 348 * Call ASIC Control Object to UnBlank CRTC. 349 */ 350 static void optc1_unblank_crtc(struct timing_generator *optc) 351 { 352 struct optc *optc1 = DCN10TG_FROM_TG(optc); 353 354 REG_UPDATE_2(OTG_BLANK_CONTROL, 355 OTG_BLANK_DATA_EN, 0, 356 OTG_BLANK_DE_MODE, 0); 357 358 /* W/A for automated testing 359 * Automated testing will fail underflow test as there 360 * sporadic underflows which occur during the optc blank 361 * sequence. As a w/a, clear underflow on unblank. 362 * This prevents the failure, but will not mask actual 363 * underflow that affect real use cases. 364 */ 365 optc1_clear_optc_underflow(optc); 366 } 367 368 /** 369 * blank_crtc 370 * Call ASIC Control Object to Blank CRTC. 371 */ 372 373 static void optc1_blank_crtc(struct timing_generator *optc) 374 { 375 struct optc *optc1 = DCN10TG_FROM_TG(optc); 376 377 REG_UPDATE_2(OTG_BLANK_CONTROL, 378 OTG_BLANK_DATA_EN, 1, 379 OTG_BLANK_DE_MODE, 0); 380 381 optc1_set_blank_data_double_buffer(optc, false); 382 } 383 384 void optc1_set_blank(struct timing_generator *optc, 385 bool enable_blanking) 386 { 387 if (enable_blanking) 388 optc1_blank_crtc(optc); 389 else 390 optc1_unblank_crtc(optc); 391 } 392 393 bool optc1_is_blanked(struct timing_generator *optc) 394 { 395 struct optc *optc1 = DCN10TG_FROM_TG(optc); 396 uint32_t blank_en; 397 uint32_t blank_state; 398 399 REG_GET_2(OTG_BLANK_CONTROL, 400 OTG_BLANK_DATA_EN, &blank_en, 401 OTG_CURRENT_BLANK_STATE, &blank_state); 402 403 return blank_en && blank_state; 404 } 405 406 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 407 { 408 struct optc *optc1 = DCN10TG_FROM_TG(optc); 409 410 if (enable) { 411 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 412 OPTC_INPUT_CLK_EN, 1, 413 OPTC_INPUT_CLK_GATE_DIS, 1); 414 415 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 416 OPTC_INPUT_CLK_ON, 1, 417 1, 1000); 418 419 /* Enable clock */ 420 REG_UPDATE_2(OTG_CLOCK_CONTROL, 421 OTG_CLOCK_EN, 1, 422 OTG_CLOCK_GATE_DIS, 1); 423 REG_WAIT(OTG_CLOCK_CONTROL, 424 OTG_CLOCK_ON, 1, 425 1, 1000); 426 } else { 427 REG_UPDATE_2(OTG_CLOCK_CONTROL, 428 OTG_CLOCK_GATE_DIS, 0, 429 OTG_CLOCK_EN, 0); 430 431 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 432 OPTC_INPUT_CLK_GATE_DIS, 0, 433 OPTC_INPUT_CLK_EN, 0); 434 } 435 } 436 437 /** 438 * Enable CRTC 439 * Enable CRTC - call ASIC Control Object to enable Timing generator. 440 */ 441 static bool optc1_enable_crtc(struct timing_generator *optc) 442 { 443 /* TODO FPGA wait for answer 444 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 445 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 446 */ 447 struct optc *optc1 = DCN10TG_FROM_TG(optc); 448 449 /* opp instance for OTG. For DCN1.0, ODM is remoed. 450 * OPP and OPTC should 1:1 mapping 451 */ 452 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 453 OPTC_SRC_SEL, optc->inst); 454 455 /* VTG enable first is for HW workaround */ 456 REG_UPDATE(CONTROL, 457 VTG0_ENABLE, 1); 458 459 /* Enable CRTC */ 460 REG_UPDATE_2(OTG_CONTROL, 461 OTG_DISABLE_POINT_CNTL, 3, 462 OTG_MASTER_EN, 1); 463 464 return true; 465 } 466 467 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 468 bool optc1_disable_crtc(struct timing_generator *optc) 469 { 470 struct optc *optc1 = DCN10TG_FROM_TG(optc); 471 472 /* disable otg request until end of the first line 473 * in the vertical blank region 474 */ 475 REG_UPDATE_2(OTG_CONTROL, 476 OTG_DISABLE_POINT_CNTL, 3, 477 OTG_MASTER_EN, 0); 478 479 REG_UPDATE(CONTROL, 480 VTG0_ENABLE, 0); 481 482 /* CRTC disabled, so disable clock. */ 483 REG_WAIT(OTG_CLOCK_CONTROL, 484 OTG_BUSY, 0, 485 1, 100000); 486 487 return true; 488 } 489 490 491 void optc1_program_blank_color( 492 struct timing_generator *optc, 493 const struct tg_color *black_color) 494 { 495 struct optc *optc1 = DCN10TG_FROM_TG(optc); 496 497 REG_SET_3(OTG_BLACK_COLOR, 0, 498 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 499 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 500 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 501 } 502 503 bool optc1_validate_timing( 504 struct timing_generator *optc, 505 const struct dc_crtc_timing *timing) 506 { 507 uint32_t v_blank; 508 uint32_t h_blank; 509 uint32_t min_v_blank; 510 struct optc *optc1 = DCN10TG_FROM_TG(optc); 511 512 ASSERT(timing != NULL); 513 514 v_blank = (timing->v_total - timing->v_addressable - 515 timing->v_border_top - timing->v_border_bottom); 516 517 h_blank = (timing->h_total - timing->h_addressable - 518 timing->h_border_right - 519 timing->h_border_left); 520 521 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 522 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 523 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 524 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 525 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 526 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 527 return false; 528 529 /* Temporarily blocking interlacing mode until it's supported */ 530 if (timing->flags.INTERLACE == 1) 531 return false; 532 533 /* Check maximum number of pixels supported by Timing Generator 534 * (Currently will never fail, in order to fail needs display which 535 * needs more than 8192 horizontal and 536 * more than 8192 vertical total pixels) 537 */ 538 if (timing->h_total > optc1->max_h_total || 539 timing->v_total > optc1->max_v_total) 540 return false; 541 542 543 if (h_blank < optc1->min_h_blank) 544 return false; 545 546 if (timing->h_sync_width < optc1->min_h_sync_width || 547 timing->v_sync_width < optc1->min_v_sync_width) 548 return false; 549 550 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 551 552 if (v_blank < min_v_blank) 553 return false; 554 555 return true; 556 557 } 558 559 /* 560 * get_vblank_counter 561 * 562 * @brief 563 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 564 * holds the counter of frames. 565 * 566 * @param 567 * struct timing_generator *optc - [in] timing generator which controls the 568 * desired CRTC 569 * 570 * @return 571 * Counter of frames, which should equal to number of vblanks. 572 */ 573 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 574 { 575 struct optc *optc1 = DCN10TG_FROM_TG(optc); 576 uint32_t frame_count; 577 578 REG_GET(OTG_STATUS_FRAME_COUNT, 579 OTG_FRAME_COUNT, &frame_count); 580 581 return frame_count; 582 } 583 584 void optc1_lock(struct timing_generator *optc) 585 { 586 struct optc *optc1 = DCN10TG_FROM_TG(optc); 587 588 REG_SET(OTG_GLOBAL_CONTROL0, 0, 589 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 590 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 591 OTG_MASTER_UPDATE_LOCK, 1); 592 593 /* Should be fast, status does not update on maximus */ 594 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 595 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 596 UPDATE_LOCK_STATUS, 1, 597 1, 10); 598 } 599 600 void optc1_unlock(struct timing_generator *optc) 601 { 602 struct optc *optc1 = DCN10TG_FROM_TG(optc); 603 604 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 605 OTG_MASTER_UPDATE_LOCK, 0); 606 } 607 608 void optc1_get_position(struct timing_generator *optc, 609 struct crtc_position *position) 610 { 611 struct optc *optc1 = DCN10TG_FROM_TG(optc); 612 613 REG_GET_2(OTG_STATUS_POSITION, 614 OTG_HORZ_COUNT, &position->horizontal_count, 615 OTG_VERT_COUNT, &position->vertical_count); 616 617 REG_GET(OTG_NOM_VERT_POSITION, 618 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 619 } 620 621 bool optc1_is_counter_moving(struct timing_generator *optc) 622 { 623 struct crtc_position position1, position2; 624 625 optc->funcs->get_position(optc, &position1); 626 optc->funcs->get_position(optc, &position2); 627 628 if (position1.horizontal_count == position2.horizontal_count && 629 position1.vertical_count == position2.vertical_count) 630 return false; 631 else 632 return true; 633 } 634 635 bool optc1_did_triggered_reset_occur( 636 struct timing_generator *optc) 637 { 638 struct optc *optc1 = DCN10TG_FROM_TG(optc); 639 uint32_t occurred_force, occurred_vsync; 640 641 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 642 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 643 644 REG_GET(OTG_VERT_SYNC_CONTROL, 645 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 646 647 return occurred_vsync != 0 || occurred_force != 0; 648 } 649 650 void optc1_disable_reset_trigger(struct timing_generator *optc) 651 { 652 struct optc *optc1 = DCN10TG_FROM_TG(optc); 653 654 REG_WRITE(OTG_TRIGA_CNTL, 0); 655 656 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 657 OTG_FORCE_COUNT_NOW_CLEAR, 1); 658 659 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 660 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 661 } 662 663 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 664 { 665 struct optc *optc1 = DCN10TG_FROM_TG(optc); 666 uint32_t falling_edge; 667 668 REG_GET(OTG_V_SYNC_A_CNTL, 669 OTG_V_SYNC_A_POL, &falling_edge); 670 671 if (falling_edge) 672 REG_SET_3(OTG_TRIGA_CNTL, 0, 673 /* vsync signal from selected OTG pipe based 674 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 675 */ 676 OTG_TRIGA_SOURCE_SELECT, 20, 677 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 678 /* always detect falling edge */ 679 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 680 else 681 REG_SET_3(OTG_TRIGA_CNTL, 0, 682 /* vsync signal from selected OTG pipe based 683 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 684 */ 685 OTG_TRIGA_SOURCE_SELECT, 20, 686 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 687 /* always detect rising edge */ 688 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 689 690 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 691 /* force H count to H_TOTAL and V count to V_TOTAL in 692 * progressive mode and V_TOTAL-1 in interlaced mode 693 */ 694 OTG_FORCE_COUNT_NOW_MODE, 2); 695 } 696 697 void optc1_enable_crtc_reset( 698 struct timing_generator *optc, 699 int source_tg_inst, 700 struct crtc_trigger_info *crtc_tp) 701 { 702 struct optc *optc1 = DCN10TG_FROM_TG(optc); 703 uint32_t falling_edge = 0; 704 uint32_t rising_edge = 0; 705 706 switch (crtc_tp->event) { 707 708 case CRTC_EVENT_VSYNC_RISING: 709 rising_edge = 1; 710 break; 711 712 case CRTC_EVENT_VSYNC_FALLING: 713 falling_edge = 1; 714 break; 715 } 716 717 REG_SET_4(OTG_TRIGA_CNTL, 0, 718 /* vsync signal from selected OTG pipe based 719 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 720 */ 721 OTG_TRIGA_SOURCE_SELECT, 20, 722 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 723 /* always detect falling edge */ 724 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 725 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 726 727 switch (crtc_tp->delay) { 728 case TRIGGER_DELAY_NEXT_LINE: 729 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 730 OTG_AUTO_FORCE_VSYNC_MODE, 1); 731 break; 732 case TRIGGER_DELAY_NEXT_PIXEL: 733 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 734 /* force H count to H_TOTAL and V count to V_TOTAL in 735 * progressive mode and V_TOTAL-1 in interlaced mode 736 */ 737 OTG_FORCE_COUNT_NOW_MODE, 2); 738 break; 739 } 740 } 741 742 void optc1_wait_for_state(struct timing_generator *optc, 743 enum crtc_state state) 744 { 745 struct optc *optc1 = DCN10TG_FROM_TG(optc); 746 747 switch (state) { 748 case CRTC_STATE_VBLANK: 749 REG_WAIT(OTG_STATUS, 750 OTG_V_BLANK, 1, 751 1, 100000); /* 1 vupdate at 10hz */ 752 break; 753 754 case CRTC_STATE_VACTIVE: 755 REG_WAIT(OTG_STATUS, 756 OTG_V_ACTIVE_DISP, 1, 757 1, 100000); /* 1 vupdate at 10hz */ 758 break; 759 760 default: 761 break; 762 } 763 } 764 765 void optc1_set_early_control( 766 struct timing_generator *optc, 767 uint32_t early_cntl) 768 { 769 /* asic design change, do not need this control 770 * empty for share caller logic 771 */ 772 } 773 774 775 void optc1_set_static_screen_control( 776 struct timing_generator *optc, 777 uint32_t value) 778 { 779 struct optc *optc1 = DCN10TG_FROM_TG(optc); 780 781 /* Bit 8 is no longer applicable in RV for PSR case, 782 * set bit 8 to 0 if given 783 */ 784 if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 785 != 0) 786 value = value & 787 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 788 789 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 790 OTG_STATIC_SCREEN_EVENT_MASK, value, 791 OTG_STATIC_SCREEN_FRAME_COUNT, 2); 792 } 793 794 void optc1_setup_manual_trigger(struct timing_generator *optc) 795 { 796 struct optc *optc1 = DCN10TG_FROM_TG(optc); 797 798 REG_SET(OTG_GLOBAL_CONTROL2, 0, 799 MANUAL_FLOW_CONTROL_SEL, optc->inst); 800 801 REG_SET_8(OTG_TRIGA_CNTL, 0, 802 OTG_TRIGA_SOURCE_SELECT, 22, 803 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 804 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 805 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 806 OTG_TRIGA_POLARITY_SELECT, 0, 807 OTG_TRIGA_FREQUENCY_SELECT, 0, 808 OTG_TRIGA_DELAY, 0, 809 OTG_TRIGA_CLEAR, 1); 810 } 811 812 void optc1_program_manual_trigger(struct timing_generator *optc) 813 { 814 struct optc *optc1 = DCN10TG_FROM_TG(optc); 815 816 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 817 MANUAL_FLOW_CONTROL, 1); 818 } 819 820 821 /** 822 ***************************************************************************** 823 * Function: set_drr 824 * 825 * @brief 826 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 827 * 828 ***************************************************************************** 829 */ 830 void optc1_set_drr( 831 struct timing_generator *optc, 832 const struct drr_params *params) 833 { 834 struct optc *optc1 = DCN10TG_FROM_TG(optc); 835 836 if (params != NULL && 837 params->vertical_total_max > 0 && 838 params->vertical_total_min > 0) { 839 840 REG_SET(OTG_V_TOTAL_MAX, 0, 841 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 842 843 REG_SET(OTG_V_TOTAL_MIN, 0, 844 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 845 846 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 847 OTG_V_TOTAL_MIN_SEL, 1, 848 OTG_V_TOTAL_MAX_SEL, 1, 849 OTG_FORCE_LOCK_ON_EVENT, 0, 850 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 851 OTG_SET_V_TOTAL_MIN_MASK, 0); 852 853 // Setup manual flow control for EOF via TRIG_A 854 optc->funcs->setup_manual_trigger(optc); 855 856 } else { 857 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 858 OTG_SET_V_TOTAL_MIN_MASK, 0, 859 OTG_V_TOTAL_MIN_SEL, 0, 860 OTG_V_TOTAL_MAX_SEL, 0, 861 OTG_FORCE_LOCK_ON_EVENT, 0); 862 863 REG_SET(OTG_V_TOTAL_MIN, 0, 864 OTG_V_TOTAL_MIN, 0); 865 866 REG_SET(OTG_V_TOTAL_MAX, 0, 867 OTG_V_TOTAL_MAX, 0); 868 } 869 } 870 871 static void optc1_set_test_pattern( 872 struct timing_generator *optc, 873 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 874 * because this is not DP-specific (which is probably somewhere in DP 875 * encoder) */ 876 enum controller_dp_test_pattern test_pattern, 877 enum dc_color_depth color_depth) 878 { 879 struct optc *optc1 = DCN10TG_FROM_TG(optc); 880 enum test_pattern_color_format bit_depth; 881 enum test_pattern_dyn_range dyn_range; 882 enum test_pattern_mode mode; 883 uint32_t pattern_mask; 884 uint32_t pattern_data; 885 /* color ramp generator mixes 16-bits color */ 886 uint32_t src_bpc = 16; 887 /* requested bpc */ 888 uint32_t dst_bpc; 889 uint32_t index; 890 /* RGB values of the color bars. 891 * Produce two RGB colors: RGB0 - white (all Fs) 892 * and RGB1 - black (all 0s) 893 * (three RGB components for two colors) 894 */ 895 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 896 0x0000, 0x0000}; 897 /* dest color (converted to the specified color format) */ 898 uint16_t dst_color[6]; 899 uint32_t inc_base; 900 901 /* translate to bit depth */ 902 switch (color_depth) { 903 case COLOR_DEPTH_666: 904 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 905 break; 906 case COLOR_DEPTH_888: 907 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 908 break; 909 case COLOR_DEPTH_101010: 910 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 911 break; 912 case COLOR_DEPTH_121212: 913 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 914 break; 915 default: 916 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 917 break; 918 } 919 920 switch (test_pattern) { 921 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 922 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 923 { 924 dyn_range = (test_pattern == 925 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 926 TEST_PATTERN_DYN_RANGE_CEA : 927 TEST_PATTERN_DYN_RANGE_VESA); 928 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 929 930 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 931 OTG_TEST_PATTERN_VRES, 6, 932 OTG_TEST_PATTERN_HRES, 6); 933 934 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 935 OTG_TEST_PATTERN_EN, 1, 936 OTG_TEST_PATTERN_MODE, mode, 937 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 938 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 939 } 940 break; 941 942 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 943 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 944 { 945 mode = (test_pattern == 946 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 947 TEST_PATTERN_MODE_VERTICALBARS : 948 TEST_PATTERN_MODE_HORIZONTALBARS); 949 950 switch (bit_depth) { 951 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 952 dst_bpc = 6; 953 break; 954 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 955 dst_bpc = 8; 956 break; 957 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 958 dst_bpc = 10; 959 break; 960 default: 961 dst_bpc = 8; 962 break; 963 } 964 965 /* adjust color to the required colorFormat */ 966 for (index = 0; index < 6; index++) { 967 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 968 * (srcBpc - dstBpc); 969 */ 970 dst_color[index] = 971 src_color[index] >> (src_bpc - dst_bpc); 972 /* CRTC_TEST_PATTERN_DATA has 16 bits, 973 * lowest 6 are hardwired to ZERO 974 * color bits should be left aligned aligned to MSB 975 * XXXXXXXXXX000000 for 10 bit, 976 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 977 */ 978 dst_color[index] <<= (16 - dst_bpc); 979 } 980 981 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 982 983 /* We have to write the mask before data, similar to pipeline. 984 * For example, for 8 bpc, if we want RGB0 to be magenta, 985 * and RGB1 to be cyan, 986 * we need to make 7 writes: 987 * MASK DATA 988 * 000001 00000000 00000000 set mask to R0 989 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 990 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 991 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 992 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 993 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 994 * 100000 11111111 00000000 B1 255, 0xFF00 995 * 996 * we will make a loop of 6 in which we prepare the mask, 997 * then write, then prepare the color for next write. 998 * first iteration will write mask only, 999 * but each next iteration color prepared in 1000 * previous iteration will be written within new mask, 1001 * the last component will written separately, 1002 * mask is not changing between 6th and 7th write 1003 * and color will be prepared by last iteration 1004 */ 1005 1006 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1007 * is B1, G1, R1, B0, G0, R0 1008 */ 1009 pattern_data = 0; 1010 for (index = 0; index < 6; index++) { 1011 /* prepare color mask, first write PATTERN_DATA 1012 * will have all zeros 1013 */ 1014 pattern_mask = (1 << index); 1015 1016 /* write color component */ 1017 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1018 OTG_TEST_PATTERN_MASK, pattern_mask, 1019 OTG_TEST_PATTERN_DATA, pattern_data); 1020 1021 /* prepare next color component, 1022 * will be written in the next iteration 1023 */ 1024 pattern_data = dst_color[index]; 1025 } 1026 /* write last color component, 1027 * it's been already prepared in the loop 1028 */ 1029 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1030 OTG_TEST_PATTERN_MASK, pattern_mask, 1031 OTG_TEST_PATTERN_DATA, pattern_data); 1032 1033 /* enable test pattern */ 1034 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1035 OTG_TEST_PATTERN_EN, 1, 1036 OTG_TEST_PATTERN_MODE, mode, 1037 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1038 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1039 } 1040 break; 1041 1042 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1043 { 1044 mode = (bit_depth == 1045 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1046 TEST_PATTERN_MODE_DUALRAMP_RGB : 1047 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1048 1049 switch (bit_depth) { 1050 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1051 dst_bpc = 6; 1052 break; 1053 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1054 dst_bpc = 8; 1055 break; 1056 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1057 dst_bpc = 10; 1058 break; 1059 default: 1060 dst_bpc = 8; 1061 break; 1062 } 1063 1064 /* increment for the first ramp for one color gradation 1065 * 1 gradation for 6-bit color is 2^10 1066 * gradations in 16-bit color 1067 */ 1068 inc_base = (src_bpc - dst_bpc); 1069 1070 switch (bit_depth) { 1071 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1072 { 1073 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1074 OTG_TEST_PATTERN_INC0, inc_base, 1075 OTG_TEST_PATTERN_INC1, 0, 1076 OTG_TEST_PATTERN_HRES, 6, 1077 OTG_TEST_PATTERN_VRES, 6, 1078 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1079 } 1080 break; 1081 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1082 { 1083 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1084 OTG_TEST_PATTERN_INC0, inc_base, 1085 OTG_TEST_PATTERN_INC1, 0, 1086 OTG_TEST_PATTERN_HRES, 8, 1087 OTG_TEST_PATTERN_VRES, 6, 1088 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1089 } 1090 break; 1091 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1092 { 1093 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1094 OTG_TEST_PATTERN_INC0, inc_base, 1095 OTG_TEST_PATTERN_INC1, inc_base + 2, 1096 OTG_TEST_PATTERN_HRES, 8, 1097 OTG_TEST_PATTERN_VRES, 5, 1098 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1099 } 1100 break; 1101 default: 1102 break; 1103 } 1104 1105 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1106 1107 /* enable test pattern */ 1108 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1109 1110 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1111 OTG_TEST_PATTERN_EN, 1, 1112 OTG_TEST_PATTERN_MODE, mode, 1113 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1114 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1115 } 1116 break; 1117 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1118 { 1119 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1120 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1121 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1122 } 1123 break; 1124 default: 1125 break; 1126 1127 } 1128 } 1129 1130 void optc1_get_crtc_scanoutpos( 1131 struct timing_generator *optc, 1132 uint32_t *v_blank_start, 1133 uint32_t *v_blank_end, 1134 uint32_t *h_position, 1135 uint32_t *v_position) 1136 { 1137 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1138 struct crtc_position position; 1139 1140 REG_GET_2(OTG_V_BLANK_START_END, 1141 OTG_V_BLANK_START, v_blank_start, 1142 OTG_V_BLANK_END, v_blank_end); 1143 1144 optc1_get_position(optc, &position); 1145 1146 *h_position = position.horizontal_count; 1147 *v_position = position.vertical_count; 1148 } 1149 1150 static void optc1_enable_stereo(struct timing_generator *optc, 1151 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1152 { 1153 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1154 1155 if (flags) { 1156 uint32_t stereo_en; 1157 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1158 1159 if (flags->PROGRAM_STEREO) 1160 REG_UPDATE_3(OTG_STEREO_CONTROL, 1161 OTG_STEREO_EN, stereo_en, 1162 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1163 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0); 1164 1165 if (flags->PROGRAM_POLARITY) 1166 REG_UPDATE(OTG_STEREO_CONTROL, 1167 OTG_STEREO_EYE_FLAG_POLARITY, 1168 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1169 1170 if (flags->DISABLE_STEREO_DP_SYNC) 1171 REG_UPDATE(OTG_STEREO_CONTROL, 1172 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1173 1174 if (flags->PROGRAM_STEREO) 1175 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1176 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1177 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1178 1179 } 1180 } 1181 1182 void optc1_program_stereo(struct timing_generator *optc, 1183 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1184 { 1185 if (flags->PROGRAM_STEREO) 1186 optc1_enable_stereo(optc, timing, flags); 1187 else 1188 optc1_disable_stereo(optc); 1189 } 1190 1191 1192 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1193 { 1194 bool ret = false; 1195 uint32_t left_eye = 0; 1196 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1197 1198 REG_GET(OTG_STEREO_STATUS, 1199 OTG_STEREO_CURRENT_EYE, &left_eye); 1200 if (left_eye == 1) 1201 ret = true; 1202 else 1203 ret = false; 1204 1205 return ret; 1206 } 1207 1208 bool optc1_is_matching_timing(struct timing_generator *tg, 1209 const struct dc_crtc_timing *otg_timing) 1210 { 1211 struct dc_crtc_timing hw_crtc_timing = {0}; 1212 struct dcn_otg_state s = {0}; 1213 1214 if (tg == NULL || otg_timing == NULL) 1215 return false; 1216 1217 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1218 1219 hw_crtc_timing.h_total = s.h_total + 1; 1220 hw_crtc_timing.h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1221 hw_crtc_timing.h_front_porch = s.h_total + 1 - s.h_blank_start; 1222 hw_crtc_timing.h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1223 1224 hw_crtc_timing.v_total = s.v_total + 1; 1225 hw_crtc_timing.v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1226 hw_crtc_timing.v_front_porch = s.v_total + 1 - s.v_blank_start; 1227 hw_crtc_timing.v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1228 1229 if (otg_timing->h_total != hw_crtc_timing.h_total) 1230 return false; 1231 1232 if (otg_timing->h_border_left != hw_crtc_timing.h_border_left) 1233 return false; 1234 1235 if (otg_timing->h_addressable != hw_crtc_timing.h_addressable) 1236 return false; 1237 1238 if (otg_timing->h_border_right != hw_crtc_timing.h_border_right) 1239 return false; 1240 1241 if (otg_timing->h_front_porch != hw_crtc_timing.h_front_porch) 1242 return false; 1243 1244 if (otg_timing->h_sync_width != hw_crtc_timing.h_sync_width) 1245 return false; 1246 1247 if (otg_timing->v_total != hw_crtc_timing.v_total) 1248 return false; 1249 1250 if (otg_timing->v_border_top != hw_crtc_timing.v_border_top) 1251 return false; 1252 1253 if (otg_timing->v_addressable != hw_crtc_timing.v_addressable) 1254 return false; 1255 1256 if (otg_timing->v_border_bottom != hw_crtc_timing.v_border_bottom) 1257 return false; 1258 1259 if (otg_timing->v_sync_width != hw_crtc_timing.v_sync_width) 1260 return false; 1261 1262 return true; 1263 } 1264 1265 1266 void optc1_read_otg_state(struct optc *optc1, 1267 struct dcn_otg_state *s) 1268 { 1269 REG_GET(OTG_CONTROL, 1270 OTG_MASTER_EN, &s->otg_enabled); 1271 1272 REG_GET_2(OTG_V_BLANK_START_END, 1273 OTG_V_BLANK_START, &s->v_blank_start, 1274 OTG_V_BLANK_END, &s->v_blank_end); 1275 1276 REG_GET(OTG_V_SYNC_A_CNTL, 1277 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1278 1279 REG_GET(OTG_V_TOTAL, 1280 OTG_V_TOTAL, &s->v_total); 1281 1282 REG_GET(OTG_V_TOTAL_MAX, 1283 OTG_V_TOTAL_MAX, &s->v_total_max); 1284 1285 REG_GET(OTG_V_TOTAL_MIN, 1286 OTG_V_TOTAL_MIN, &s->v_total_min); 1287 1288 REG_GET(OTG_V_TOTAL_CONTROL, 1289 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1290 1291 REG_GET(OTG_V_TOTAL_CONTROL, 1292 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1293 1294 REG_GET_2(OTG_V_SYNC_A, 1295 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1296 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1297 1298 REG_GET_2(OTG_H_BLANK_START_END, 1299 OTG_H_BLANK_START, &s->h_blank_start, 1300 OTG_H_BLANK_END, &s->h_blank_end); 1301 1302 REG_GET_2(OTG_H_SYNC_A, 1303 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1304 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1305 1306 REG_GET(OTG_H_SYNC_A_CNTL, 1307 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1308 1309 REG_GET(OTG_H_TOTAL, 1310 OTG_H_TOTAL, &s->h_total); 1311 1312 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1313 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1314 } 1315 1316 bool optc1_get_otg_active_size(struct timing_generator *optc, 1317 uint32_t *otg_active_width, 1318 uint32_t *otg_active_height) 1319 { 1320 uint32_t otg_enabled; 1321 uint32_t v_blank_start; 1322 uint32_t v_blank_end; 1323 uint32_t h_blank_start; 1324 uint32_t h_blank_end; 1325 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1326 1327 1328 REG_GET(OTG_CONTROL, 1329 OTG_MASTER_EN, &otg_enabled); 1330 1331 if (otg_enabled == 0) 1332 return false; 1333 1334 REG_GET_2(OTG_V_BLANK_START_END, 1335 OTG_V_BLANK_START, &v_blank_start, 1336 OTG_V_BLANK_END, &v_blank_end); 1337 1338 REG_GET_2(OTG_H_BLANK_START_END, 1339 OTG_H_BLANK_START, &h_blank_start, 1340 OTG_H_BLANK_END, &h_blank_end); 1341 1342 *otg_active_width = v_blank_start - v_blank_end; 1343 *otg_active_height = h_blank_start - h_blank_end; 1344 return true; 1345 } 1346 1347 void optc1_clear_optc_underflow(struct timing_generator *optc) 1348 { 1349 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1350 1351 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1352 } 1353 1354 void optc1_tg_init(struct timing_generator *optc) 1355 { 1356 optc1_set_blank_data_double_buffer(optc, true); 1357 optc1_clear_optc_underflow(optc); 1358 } 1359 1360 bool optc1_is_tg_enabled(struct timing_generator *optc) 1361 { 1362 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1363 uint32_t otg_enabled = 0; 1364 1365 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1366 1367 return (otg_enabled != 0); 1368 1369 } 1370 1371 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1372 { 1373 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1374 uint32_t underflow_occurred = 0; 1375 1376 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1377 OPTC_UNDERFLOW_OCCURRED_STATUS, 1378 &underflow_occurred); 1379 1380 return (underflow_occurred == 1); 1381 } 1382 1383 bool optc1_configure_crc(struct timing_generator *optc, 1384 const struct crc_params *params) 1385 { 1386 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1387 1388 /* Cannot configure crc on a CRTC that is disabled */ 1389 if (!optc1_is_tg_enabled(optc)) 1390 return false; 1391 1392 REG_WRITE(OTG_CRC_CNTL, 0); 1393 1394 if (!params->enable) 1395 return true; 1396 1397 /* Program frame boundaries */ 1398 /* Window A x axis start and end. */ 1399 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1400 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1401 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1402 1403 /* Window A y axis start and end. */ 1404 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1405 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1406 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1407 1408 /* Window B x axis start and end. */ 1409 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1410 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1411 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1412 1413 /* Window B y axis start and end. */ 1414 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1415 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1416 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1417 1418 /* Set crc mode and selection, and enable. Only using CRC0*/ 1419 REG_UPDATE_3(OTG_CRC_CNTL, 1420 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1421 OTG_CRC0_SELECT, params->selection, 1422 OTG_CRC_EN, 1); 1423 1424 return true; 1425 } 1426 1427 bool optc1_get_crc(struct timing_generator *optc, 1428 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1429 { 1430 uint32_t field = 0; 1431 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1432 1433 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1434 1435 /* Early return if CRC is not enabled for this CRTC */ 1436 if (!field) 1437 return false; 1438 1439 REG_GET_2(OTG_CRC0_DATA_RG, 1440 CRC0_R_CR, r_cr, 1441 CRC0_G_Y, g_y); 1442 1443 REG_GET(OTG_CRC0_DATA_B, 1444 CRC0_B_CB, b_cb); 1445 1446 return true; 1447 } 1448 1449 static const struct timing_generator_funcs dcn10_tg_funcs = { 1450 .validate_timing = optc1_validate_timing, 1451 .program_timing = optc1_program_timing, 1452 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1453 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1454 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1455 .program_global_sync = optc1_program_global_sync, 1456 .enable_crtc = optc1_enable_crtc, 1457 .disable_crtc = optc1_disable_crtc, 1458 /* used by enable_timing_synchronization. Not need for FPGA */ 1459 .is_counter_moving = optc1_is_counter_moving, 1460 .get_position = optc1_get_position, 1461 .get_frame_count = optc1_get_vblank_counter, 1462 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1463 .get_otg_active_size = optc1_get_otg_active_size, 1464 .is_matching_timing = optc1_is_matching_timing, 1465 .set_early_control = optc1_set_early_control, 1466 /* used by enable_timing_synchronization. Not need for FPGA */ 1467 .wait_for_state = optc1_wait_for_state, 1468 .set_blank = optc1_set_blank, 1469 .is_blanked = optc1_is_blanked, 1470 .set_blank_color = optc1_program_blank_color, 1471 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1472 .enable_reset_trigger = optc1_enable_reset_trigger, 1473 .enable_crtc_reset = optc1_enable_crtc_reset, 1474 .disable_reset_trigger = optc1_disable_reset_trigger, 1475 .lock = optc1_lock, 1476 .unlock = optc1_unlock, 1477 .enable_optc_clock = optc1_enable_optc_clock, 1478 .set_drr = optc1_set_drr, 1479 .set_static_screen_control = optc1_set_static_screen_control, 1480 .set_test_pattern = optc1_set_test_pattern, 1481 .program_stereo = optc1_program_stereo, 1482 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1483 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1484 .tg_init = optc1_tg_init, 1485 .is_tg_enabled = optc1_is_tg_enabled, 1486 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1487 .clear_optc_underflow = optc1_clear_optc_underflow, 1488 .get_crc = optc1_get_crc, 1489 .configure_crc = optc1_configure_crc, 1490 .set_vtg_params = optc1_set_vtg_params, 1491 .program_manual_trigger = optc1_program_manual_trigger, 1492 .setup_manual_trigger = optc1_setup_manual_trigger 1493 }; 1494 1495 void dcn10_timing_generator_init(struct optc *optc1) 1496 { 1497 optc1->base.funcs = &dcn10_tg_funcs; 1498 1499 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1500 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1501 1502 optc1->min_h_blank = 32; 1503 optc1->min_v_blank = 3; 1504 optc1->min_v_blank_interlace = 5; 1505 optc1->min_h_sync_width = 8; 1506 optc1->min_v_sync_width = 1; 1507 optc1->comb_opp_id = 0xf; 1508 } 1509 1510 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1511 { 1512 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1513 1514 return two_pix; 1515 } 1516 1517