1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 169 /* Load horizontal timing */ 170 171 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 172 REG_SET(OTG_H_TOTAL, 0, 173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 174 175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 176 REG_UPDATE_2(OTG_H_SYNC_A, 177 OTG_H_SYNC_A_START, 0, 178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 179 180 /* blank_start = line end - front porch */ 181 asic_blank_start = patched_crtc_timing.h_total - 182 patched_crtc_timing.h_front_porch; 183 184 /* blank_end = blank_start - active */ 185 asic_blank_end = asic_blank_start - 186 patched_crtc_timing.h_border_right - 187 patched_crtc_timing.h_addressable - 188 patched_crtc_timing.h_border_left; 189 190 REG_UPDATE_2(OTG_H_BLANK_START_END, 191 OTG_H_BLANK_START, asic_blank_start, 192 OTG_H_BLANK_END, asic_blank_end); 193 194 /* h_sync polarity */ 195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 196 0 : 1; 197 198 REG_UPDATE(OTG_H_SYNC_A_CNTL, 199 OTG_H_SYNC_A_POL, h_sync_polarity); 200 201 v_total = patched_crtc_timing.v_total - 1; 202 203 REG_SET(OTG_V_TOTAL, 0, 204 OTG_V_TOTAL, v_total); 205 206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 207 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 208 */ 209 REG_SET(OTG_V_TOTAL_MAX, 0, 210 OTG_V_TOTAL_MAX, v_total); 211 REG_SET(OTG_V_TOTAL_MIN, 0, 212 OTG_V_TOTAL_MIN, v_total); 213 214 /* v_sync_start = 0, v_sync_end = v_sync_width */ 215 v_sync_end = patched_crtc_timing.v_sync_width; 216 217 REG_UPDATE_2(OTG_V_SYNC_A, 218 OTG_V_SYNC_A_START, 0, 219 OTG_V_SYNC_A_END, v_sync_end); 220 221 /* blank_start = frame end - front porch */ 222 asic_blank_start = patched_crtc_timing.v_total - 223 patched_crtc_timing.v_front_porch; 224 225 /* blank_end = blank_start - active */ 226 asic_blank_end = asic_blank_start - 227 patched_crtc_timing.v_border_bottom - 228 patched_crtc_timing.v_addressable - 229 patched_crtc_timing.v_border_top; 230 231 REG_UPDATE_2(OTG_V_BLANK_START_END, 232 OTG_V_BLANK_START, asic_blank_start, 233 OTG_V_BLANK_END, asic_blank_end); 234 235 /* v_sync polarity */ 236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 237 0 : 1; 238 239 REG_UPDATE(OTG_V_SYNC_A_CNTL, 240 OTG_V_SYNC_A_POL, v_sync_polarity); 241 242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 244 optc1->signal == SIGNAL_TYPE_EDP) { 245 start_point = 1; 246 if (patched_crtc_timing.flags.INTERLACE == 1) 247 field_num = 1; 248 } 249 250 /* Interlace */ 251 if (REG(OTG_INTERLACE_CONTROL)) { 252 if (patched_crtc_timing.flags.INTERLACE == 1) 253 REG_UPDATE(OTG_INTERLACE_CONTROL, 254 OTG_INTERLACE_ENABLE, 1); 255 else 256 REG_UPDATE(OTG_INTERLACE_CONTROL, 257 OTG_INTERLACE_ENABLE, 0); 258 } 259 260 /* VTG enable set to 0 first VInit */ 261 REG_UPDATE(CONTROL, 262 VTG0_ENABLE, 0); 263 264 /* original code is using VTG offset to address OTG reg, seems wrong */ 265 REG_UPDATE_2(OTG_CONTROL, 266 OTG_START_POINT_CNTL, start_point, 267 OTG_FIELD_NUMBER_CNTL, field_num); 268 269 optc->funcs->program_global_sync(optc, 270 vready_offset, 271 vstartup_start, 272 vupdate_offset, 273 vupdate_width); 274 275 optc->funcs->set_vtg_params(optc, dc_crtc_timing); 276 277 /* TODO 278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 279 * program_horz_count_by_2 280 * for DVI 30bpp mode, 0 otherwise 281 * program_horz_count_by_2(optc, &patched_crtc_timing); 282 */ 283 284 /* Enable stereo - only when we need to pack 3D frame. Other types 285 * of stereo handled in explicit call 286 */ 287 288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) 289 h_div = H_TIMING_DIV_BY2; 290 291 REG_UPDATE(OTG_H_TIMING_CNTL, 292 OTG_H_TIMING_DIV_BY2, h_div); 293 } 294 295 void optc1_set_vtg_params(struct timing_generator *optc, 296 const struct dc_crtc_timing *dc_crtc_timing) 297 { 298 struct dc_crtc_timing patched_crtc_timing; 299 uint32_t asic_blank_end; 300 uint32_t v_init; 301 uint32_t v_fp2 = 0; 302 303 struct optc *optc1 = DCN10TG_FROM_TG(optc); 304 305 patched_crtc_timing = *dc_crtc_timing; 306 apply_front_porch_workaround(&patched_crtc_timing); 307 308 /* VCOUNT_INIT is the start of blank */ 309 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 310 311 /* end of blank = v_init - active */ 312 asic_blank_end = v_init - 313 patched_crtc_timing.v_border_bottom - 314 patched_crtc_timing.v_addressable - 315 patched_crtc_timing.v_border_top; 316 317 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 318 if (optc1->vstartup_start > asic_blank_end) 319 v_fp2 = optc1->vstartup_start - asic_blank_end; 320 321 /* Interlace */ 322 if (REG(OTG_INTERLACE_CONTROL)) { 323 if (patched_crtc_timing.flags.INTERLACE == 1) { 324 v_init = v_init / 2; 325 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 326 v_fp2 = v_fp2 / 2; 327 } 328 } 329 330 REG_UPDATE_2(CONTROL, 331 VTG0_FP2, v_fp2, 332 VTG0_VCOUNT_INIT, v_init); 333 } 334 335 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 336 { 337 struct optc *optc1 = DCN10TG_FROM_TG(optc); 338 339 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 340 341 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 342 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 343 } 344 345 /** 346 * optc1_set_timing_double_buffer() - DRR double buffering control 347 * 348 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 349 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 350 * 351 * Options: any time, start of frame, dp start of frame (range timing) 352 */ 353 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 354 { 355 struct optc *optc1 = DCN10TG_FROM_TG(optc); 356 uint32_t mode = enable ? 2 : 0; 357 358 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 359 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode); 360 } 361 362 /** 363 * unblank_crtc 364 * Call ASIC Control Object to UnBlank CRTC. 365 */ 366 static void optc1_unblank_crtc(struct timing_generator *optc) 367 { 368 struct optc *optc1 = DCN10TG_FROM_TG(optc); 369 370 REG_UPDATE_2(OTG_BLANK_CONTROL, 371 OTG_BLANK_DATA_EN, 0, 372 OTG_BLANK_DE_MODE, 0); 373 374 /* W/A for automated testing 375 * Automated testing will fail underflow test as there 376 * sporadic underflows which occur during the optc blank 377 * sequence. As a w/a, clear underflow on unblank. 378 * This prevents the failure, but will not mask actual 379 * underflow that affect real use cases. 380 */ 381 optc1_clear_optc_underflow(optc); 382 } 383 384 /** 385 * blank_crtc 386 * Call ASIC Control Object to Blank CRTC. 387 */ 388 389 static void optc1_blank_crtc(struct timing_generator *optc) 390 { 391 struct optc *optc1 = DCN10TG_FROM_TG(optc); 392 393 REG_UPDATE_2(OTG_BLANK_CONTROL, 394 OTG_BLANK_DATA_EN, 1, 395 OTG_BLANK_DE_MODE, 0); 396 397 optc1_set_blank_data_double_buffer(optc, false); 398 } 399 400 void optc1_set_blank(struct timing_generator *optc, 401 bool enable_blanking) 402 { 403 if (enable_blanking) 404 optc1_blank_crtc(optc); 405 else 406 optc1_unblank_crtc(optc); 407 } 408 409 bool optc1_is_blanked(struct timing_generator *optc) 410 { 411 struct optc *optc1 = DCN10TG_FROM_TG(optc); 412 uint32_t blank_en; 413 uint32_t blank_state; 414 415 REG_GET_2(OTG_BLANK_CONTROL, 416 OTG_BLANK_DATA_EN, &blank_en, 417 OTG_CURRENT_BLANK_STATE, &blank_state); 418 419 return blank_en && blank_state; 420 } 421 422 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 423 { 424 struct optc *optc1 = DCN10TG_FROM_TG(optc); 425 426 if (enable) { 427 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 428 OPTC_INPUT_CLK_EN, 1, 429 OPTC_INPUT_CLK_GATE_DIS, 1); 430 431 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 432 OPTC_INPUT_CLK_ON, 1, 433 1, 1000); 434 435 /* Enable clock */ 436 REG_UPDATE_2(OTG_CLOCK_CONTROL, 437 OTG_CLOCK_EN, 1, 438 OTG_CLOCK_GATE_DIS, 1); 439 REG_WAIT(OTG_CLOCK_CONTROL, 440 OTG_CLOCK_ON, 1, 441 1, 1000); 442 } else { 443 REG_UPDATE_2(OTG_CLOCK_CONTROL, 444 OTG_CLOCK_GATE_DIS, 0, 445 OTG_CLOCK_EN, 0); 446 447 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 448 OPTC_INPUT_CLK_GATE_DIS, 0, 449 OPTC_INPUT_CLK_EN, 0); 450 } 451 } 452 453 /** 454 * Enable CRTC 455 * Enable CRTC - call ASIC Control Object to enable Timing generator. 456 */ 457 static bool optc1_enable_crtc(struct timing_generator *optc) 458 { 459 /* TODO FPGA wait for answer 460 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 461 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 462 */ 463 struct optc *optc1 = DCN10TG_FROM_TG(optc); 464 465 /* opp instance for OTG. For DCN1.0, ODM is remoed. 466 * OPP and OPTC should 1:1 mapping 467 */ 468 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 469 OPTC_SRC_SEL, optc->inst); 470 471 /* VTG enable first is for HW workaround */ 472 REG_UPDATE(CONTROL, 473 VTG0_ENABLE, 1); 474 475 REG_SEQ_START(); 476 477 /* Enable CRTC */ 478 REG_UPDATE_2(OTG_CONTROL, 479 OTG_DISABLE_POINT_CNTL, 3, 480 OTG_MASTER_EN, 1); 481 482 REG_SEQ_SUBMIT(); 483 REG_SEQ_WAIT_DONE(); 484 485 return true; 486 } 487 488 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 489 bool optc1_disable_crtc(struct timing_generator *optc) 490 { 491 struct optc *optc1 = DCN10TG_FROM_TG(optc); 492 493 /* disable otg request until end of the first line 494 * in the vertical blank region 495 */ 496 REG_UPDATE_2(OTG_CONTROL, 497 OTG_DISABLE_POINT_CNTL, 3, 498 OTG_MASTER_EN, 0); 499 500 REG_UPDATE(CONTROL, 501 VTG0_ENABLE, 0); 502 503 /* CRTC disabled, so disable clock. */ 504 REG_WAIT(OTG_CLOCK_CONTROL, 505 OTG_BUSY, 0, 506 1, 100000); 507 508 return true; 509 } 510 511 512 void optc1_program_blank_color( 513 struct timing_generator *optc, 514 const struct tg_color *black_color) 515 { 516 struct optc *optc1 = DCN10TG_FROM_TG(optc); 517 518 REG_SET_3(OTG_BLACK_COLOR, 0, 519 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 520 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 521 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 522 } 523 524 bool optc1_validate_timing( 525 struct timing_generator *optc, 526 const struct dc_crtc_timing *timing) 527 { 528 uint32_t v_blank; 529 uint32_t h_blank; 530 uint32_t min_v_blank; 531 struct optc *optc1 = DCN10TG_FROM_TG(optc); 532 533 ASSERT(timing != NULL); 534 535 v_blank = (timing->v_total - timing->v_addressable - 536 timing->v_border_top - timing->v_border_bottom); 537 538 h_blank = (timing->h_total - timing->h_addressable - 539 timing->h_border_right - 540 timing->h_border_left); 541 542 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 543 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 544 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 545 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 546 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 547 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 548 return false; 549 550 /* Temporarily blocking interlacing mode until it's supported */ 551 if (timing->flags.INTERLACE == 1) 552 return false; 553 554 /* Check maximum number of pixels supported by Timing Generator 555 * (Currently will never fail, in order to fail needs display which 556 * needs more than 8192 horizontal and 557 * more than 8192 vertical total pixels) 558 */ 559 if (timing->h_total > optc1->max_h_total || 560 timing->v_total > optc1->max_v_total) 561 return false; 562 563 564 if (h_blank < optc1->min_h_blank) 565 return false; 566 567 if (timing->h_sync_width < optc1->min_h_sync_width || 568 timing->v_sync_width < optc1->min_v_sync_width) 569 return false; 570 571 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 572 573 if (v_blank < min_v_blank) 574 return false; 575 576 return true; 577 578 } 579 580 /* 581 * get_vblank_counter 582 * 583 * @brief 584 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 585 * holds the counter of frames. 586 * 587 * @param 588 * struct timing_generator *optc - [in] timing generator which controls the 589 * desired CRTC 590 * 591 * @return 592 * Counter of frames, which should equal to number of vblanks. 593 */ 594 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 595 { 596 struct optc *optc1 = DCN10TG_FROM_TG(optc); 597 uint32_t frame_count; 598 599 REG_GET(OTG_STATUS_FRAME_COUNT, 600 OTG_FRAME_COUNT, &frame_count); 601 602 return frame_count; 603 } 604 605 void optc1_lock(struct timing_generator *optc) 606 { 607 struct optc *optc1 = DCN10TG_FROM_TG(optc); 608 uint32_t regval = 0; 609 610 regval = REG_READ(OTG_CONTROL); 611 612 /* otg is not running, do not need to be locked */ 613 if ((regval & 0x1) == 0x0) 614 return; 615 616 REG_SET(OTG_GLOBAL_CONTROL0, 0, 617 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 618 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 619 OTG_MASTER_UPDATE_LOCK, 1); 620 621 /* Should be fast, status does not update on maximus */ 622 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { 623 624 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 625 UPDATE_LOCK_STATUS, 1, 626 1, 10); 627 } 628 } 629 630 void optc1_unlock(struct timing_generator *optc) 631 { 632 struct optc *optc1 = DCN10TG_FROM_TG(optc); 633 634 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 635 OTG_MASTER_UPDATE_LOCK, 0); 636 } 637 638 void optc1_get_position(struct timing_generator *optc, 639 struct crtc_position *position) 640 { 641 struct optc *optc1 = DCN10TG_FROM_TG(optc); 642 643 REG_GET_2(OTG_STATUS_POSITION, 644 OTG_HORZ_COUNT, &position->horizontal_count, 645 OTG_VERT_COUNT, &position->vertical_count); 646 647 REG_GET(OTG_NOM_VERT_POSITION, 648 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 649 } 650 651 bool optc1_is_counter_moving(struct timing_generator *optc) 652 { 653 struct crtc_position position1, position2; 654 655 optc->funcs->get_position(optc, &position1); 656 optc->funcs->get_position(optc, &position2); 657 658 if (position1.horizontal_count == position2.horizontal_count && 659 position1.vertical_count == position2.vertical_count) 660 return false; 661 else 662 return true; 663 } 664 665 bool optc1_did_triggered_reset_occur( 666 struct timing_generator *optc) 667 { 668 struct optc *optc1 = DCN10TG_FROM_TG(optc); 669 uint32_t occurred_force, occurred_vsync; 670 671 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 672 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 673 674 REG_GET(OTG_VERT_SYNC_CONTROL, 675 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 676 677 return occurred_vsync != 0 || occurred_force != 0; 678 } 679 680 void optc1_disable_reset_trigger(struct timing_generator *optc) 681 { 682 struct optc *optc1 = DCN10TG_FROM_TG(optc); 683 684 REG_WRITE(OTG_TRIGA_CNTL, 0); 685 686 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 687 OTG_FORCE_COUNT_NOW_CLEAR, 1); 688 689 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 690 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 691 } 692 693 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 694 { 695 struct optc *optc1 = DCN10TG_FROM_TG(optc); 696 uint32_t falling_edge; 697 698 REG_GET(OTG_V_SYNC_A_CNTL, 699 OTG_V_SYNC_A_POL, &falling_edge); 700 701 if (falling_edge) 702 REG_SET_3(OTG_TRIGA_CNTL, 0, 703 /* vsync signal from selected OTG pipe based 704 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 705 */ 706 OTG_TRIGA_SOURCE_SELECT, 20, 707 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 708 /* always detect falling edge */ 709 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 710 else 711 REG_SET_3(OTG_TRIGA_CNTL, 0, 712 /* vsync signal from selected OTG pipe based 713 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 714 */ 715 OTG_TRIGA_SOURCE_SELECT, 20, 716 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 717 /* always detect rising edge */ 718 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 719 720 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 721 /* force H count to H_TOTAL and V count to V_TOTAL in 722 * progressive mode and V_TOTAL-1 in interlaced mode 723 */ 724 OTG_FORCE_COUNT_NOW_MODE, 2); 725 } 726 727 void optc1_enable_crtc_reset( 728 struct timing_generator *optc, 729 int source_tg_inst, 730 struct crtc_trigger_info *crtc_tp) 731 { 732 struct optc *optc1 = DCN10TG_FROM_TG(optc); 733 uint32_t falling_edge = 0; 734 uint32_t rising_edge = 0; 735 736 switch (crtc_tp->event) { 737 738 case CRTC_EVENT_VSYNC_RISING: 739 rising_edge = 1; 740 break; 741 742 case CRTC_EVENT_VSYNC_FALLING: 743 falling_edge = 1; 744 break; 745 } 746 747 REG_SET_4(OTG_TRIGA_CNTL, 0, 748 /* vsync signal from selected OTG pipe based 749 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 750 */ 751 OTG_TRIGA_SOURCE_SELECT, 20, 752 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 753 /* always detect falling edge */ 754 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 755 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 756 757 switch (crtc_tp->delay) { 758 case TRIGGER_DELAY_NEXT_LINE: 759 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 760 OTG_AUTO_FORCE_VSYNC_MODE, 1); 761 break; 762 case TRIGGER_DELAY_NEXT_PIXEL: 763 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 764 /* force H count to H_TOTAL and V count to V_TOTAL in 765 * progressive mode and V_TOTAL-1 in interlaced mode 766 */ 767 OTG_FORCE_COUNT_NOW_MODE, 2); 768 break; 769 } 770 } 771 772 void optc1_wait_for_state(struct timing_generator *optc, 773 enum crtc_state state) 774 { 775 struct optc *optc1 = DCN10TG_FROM_TG(optc); 776 777 switch (state) { 778 case CRTC_STATE_VBLANK: 779 REG_WAIT(OTG_STATUS, 780 OTG_V_BLANK, 1, 781 1, 100000); /* 1 vupdate at 10hz */ 782 break; 783 784 case CRTC_STATE_VACTIVE: 785 REG_WAIT(OTG_STATUS, 786 OTG_V_ACTIVE_DISP, 1, 787 1, 100000); /* 1 vupdate at 10hz */ 788 break; 789 790 default: 791 break; 792 } 793 } 794 795 void optc1_set_early_control( 796 struct timing_generator *optc, 797 uint32_t early_cntl) 798 { 799 /* asic design change, do not need this control 800 * empty for share caller logic 801 */ 802 } 803 804 805 void optc1_set_static_screen_control( 806 struct timing_generator *optc, 807 uint32_t event_triggers, 808 uint32_t num_frames) 809 { 810 struct optc *optc1 = DCN10TG_FROM_TG(optc); 811 812 // By register spec, it only takes 8 bit value 813 if (num_frames > 0xFF) 814 num_frames = 0xFF; 815 816 /* Bit 8 is no longer applicable in RV for PSR case, 817 * set bit 8 to 0 if given 818 */ 819 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 820 != 0) 821 event_triggers = event_triggers & 822 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 823 824 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 825 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 826 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 827 } 828 829 void optc1_setup_manual_trigger(struct timing_generator *optc) 830 { 831 struct optc *optc1 = DCN10TG_FROM_TG(optc); 832 833 REG_SET(OTG_GLOBAL_CONTROL2, 0, 834 MANUAL_FLOW_CONTROL_SEL, optc->inst); 835 836 REG_SET_8(OTG_TRIGA_CNTL, 0, 837 OTG_TRIGA_SOURCE_SELECT, 22, 838 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 839 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 840 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 841 OTG_TRIGA_POLARITY_SELECT, 0, 842 OTG_TRIGA_FREQUENCY_SELECT, 0, 843 OTG_TRIGA_DELAY, 0, 844 OTG_TRIGA_CLEAR, 1); 845 } 846 847 void optc1_program_manual_trigger(struct timing_generator *optc) 848 { 849 struct optc *optc1 = DCN10TG_FROM_TG(optc); 850 851 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 852 MANUAL_FLOW_CONTROL, 1); 853 854 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 855 MANUAL_FLOW_CONTROL, 0); 856 } 857 858 859 /** 860 ***************************************************************************** 861 * Function: set_drr 862 * 863 * @brief 864 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 865 * 866 ***************************************************************************** 867 */ 868 void optc1_set_drr( 869 struct timing_generator *optc, 870 const struct drr_params *params) 871 { 872 struct optc *optc1 = DCN10TG_FROM_TG(optc); 873 874 if (params != NULL && 875 params->vertical_total_max > 0 && 876 params->vertical_total_min > 0) { 877 878 if (params->vertical_total_mid != 0) { 879 880 REG_SET(OTG_V_TOTAL_MID, 0, 881 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 882 883 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 884 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 885 OTG_VTOTAL_MID_FRAME_NUM, 886 (uint8_t)params->vertical_total_mid_frame_num); 887 888 } 889 890 REG_SET(OTG_V_TOTAL_MAX, 0, 891 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 892 893 REG_SET(OTG_V_TOTAL_MIN, 0, 894 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 895 896 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 897 OTG_V_TOTAL_MIN_SEL, 1, 898 OTG_V_TOTAL_MAX_SEL, 1, 899 OTG_FORCE_LOCK_ON_EVENT, 0, 900 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 901 OTG_SET_V_TOTAL_MIN_MASK, 0); 902 903 // Setup manual flow control for EOF via TRIG_A 904 optc->funcs->setup_manual_trigger(optc); 905 906 } else { 907 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 908 OTG_SET_V_TOTAL_MIN_MASK, 0, 909 OTG_V_TOTAL_MIN_SEL, 0, 910 OTG_V_TOTAL_MAX_SEL, 0, 911 OTG_FORCE_LOCK_ON_EVENT, 0); 912 913 REG_SET(OTG_V_TOTAL_MIN, 0, 914 OTG_V_TOTAL_MIN, 0); 915 916 REG_SET(OTG_V_TOTAL_MAX, 0, 917 OTG_V_TOTAL_MAX, 0); 918 } 919 } 920 921 static void optc1_set_test_pattern( 922 struct timing_generator *optc, 923 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 924 * because this is not DP-specific (which is probably somewhere in DP 925 * encoder) */ 926 enum controller_dp_test_pattern test_pattern, 927 enum dc_color_depth color_depth) 928 { 929 struct optc *optc1 = DCN10TG_FROM_TG(optc); 930 enum test_pattern_color_format bit_depth; 931 enum test_pattern_dyn_range dyn_range; 932 enum test_pattern_mode mode; 933 uint32_t pattern_mask; 934 uint32_t pattern_data; 935 /* color ramp generator mixes 16-bits color */ 936 uint32_t src_bpc = 16; 937 /* requested bpc */ 938 uint32_t dst_bpc; 939 uint32_t index; 940 /* RGB values of the color bars. 941 * Produce two RGB colors: RGB0 - white (all Fs) 942 * and RGB1 - black (all 0s) 943 * (three RGB components for two colors) 944 */ 945 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 946 0x0000, 0x0000}; 947 /* dest color (converted to the specified color format) */ 948 uint16_t dst_color[6]; 949 uint32_t inc_base; 950 951 /* translate to bit depth */ 952 switch (color_depth) { 953 case COLOR_DEPTH_666: 954 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 955 break; 956 case COLOR_DEPTH_888: 957 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 958 break; 959 case COLOR_DEPTH_101010: 960 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 961 break; 962 case COLOR_DEPTH_121212: 963 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 964 break; 965 default: 966 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 967 break; 968 } 969 970 switch (test_pattern) { 971 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 972 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 973 { 974 dyn_range = (test_pattern == 975 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 976 TEST_PATTERN_DYN_RANGE_CEA : 977 TEST_PATTERN_DYN_RANGE_VESA); 978 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 979 980 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 981 OTG_TEST_PATTERN_VRES, 6, 982 OTG_TEST_PATTERN_HRES, 6); 983 984 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 985 OTG_TEST_PATTERN_EN, 1, 986 OTG_TEST_PATTERN_MODE, mode, 987 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 988 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 989 } 990 break; 991 992 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 993 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 994 { 995 mode = (test_pattern == 996 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 997 TEST_PATTERN_MODE_VERTICALBARS : 998 TEST_PATTERN_MODE_HORIZONTALBARS); 999 1000 switch (bit_depth) { 1001 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1002 dst_bpc = 6; 1003 break; 1004 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1005 dst_bpc = 8; 1006 break; 1007 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1008 dst_bpc = 10; 1009 break; 1010 default: 1011 dst_bpc = 8; 1012 break; 1013 } 1014 1015 /* adjust color to the required colorFormat */ 1016 for (index = 0; index < 6; index++) { 1017 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1018 * (srcBpc - dstBpc); 1019 */ 1020 dst_color[index] = 1021 src_color[index] >> (src_bpc - dst_bpc); 1022 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1023 * lowest 6 are hardwired to ZERO 1024 * color bits should be left aligned aligned to MSB 1025 * XXXXXXXXXX000000 for 10 bit, 1026 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1027 */ 1028 dst_color[index] <<= (16 - dst_bpc); 1029 } 1030 1031 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1032 1033 /* We have to write the mask before data, similar to pipeline. 1034 * For example, for 8 bpc, if we want RGB0 to be magenta, 1035 * and RGB1 to be cyan, 1036 * we need to make 7 writes: 1037 * MASK DATA 1038 * 000001 00000000 00000000 set mask to R0 1039 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1040 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1041 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1042 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1043 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1044 * 100000 11111111 00000000 B1 255, 0xFF00 1045 * 1046 * we will make a loop of 6 in which we prepare the mask, 1047 * then write, then prepare the color for next write. 1048 * first iteration will write mask only, 1049 * but each next iteration color prepared in 1050 * previous iteration will be written within new mask, 1051 * the last component will written separately, 1052 * mask is not changing between 6th and 7th write 1053 * and color will be prepared by last iteration 1054 */ 1055 1056 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1057 * is B1, G1, R1, B0, G0, R0 1058 */ 1059 pattern_data = 0; 1060 for (index = 0; index < 6; index++) { 1061 /* prepare color mask, first write PATTERN_DATA 1062 * will have all zeros 1063 */ 1064 pattern_mask = (1 << index); 1065 1066 /* write color component */ 1067 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1068 OTG_TEST_PATTERN_MASK, pattern_mask, 1069 OTG_TEST_PATTERN_DATA, pattern_data); 1070 1071 /* prepare next color component, 1072 * will be written in the next iteration 1073 */ 1074 pattern_data = dst_color[index]; 1075 } 1076 /* write last color component, 1077 * it's been already prepared in the loop 1078 */ 1079 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1080 OTG_TEST_PATTERN_MASK, pattern_mask, 1081 OTG_TEST_PATTERN_DATA, pattern_data); 1082 1083 /* enable test pattern */ 1084 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1085 OTG_TEST_PATTERN_EN, 1, 1086 OTG_TEST_PATTERN_MODE, mode, 1087 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1088 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1089 } 1090 break; 1091 1092 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1093 { 1094 mode = (bit_depth == 1095 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1096 TEST_PATTERN_MODE_DUALRAMP_RGB : 1097 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1098 1099 switch (bit_depth) { 1100 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1101 dst_bpc = 6; 1102 break; 1103 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1104 dst_bpc = 8; 1105 break; 1106 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1107 dst_bpc = 10; 1108 break; 1109 default: 1110 dst_bpc = 8; 1111 break; 1112 } 1113 1114 /* increment for the first ramp for one color gradation 1115 * 1 gradation for 6-bit color is 2^10 1116 * gradations in 16-bit color 1117 */ 1118 inc_base = (src_bpc - dst_bpc); 1119 1120 switch (bit_depth) { 1121 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1122 { 1123 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1124 OTG_TEST_PATTERN_INC0, inc_base, 1125 OTG_TEST_PATTERN_INC1, 0, 1126 OTG_TEST_PATTERN_HRES, 6, 1127 OTG_TEST_PATTERN_VRES, 6, 1128 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1129 } 1130 break; 1131 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1132 { 1133 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1134 OTG_TEST_PATTERN_INC0, inc_base, 1135 OTG_TEST_PATTERN_INC1, 0, 1136 OTG_TEST_PATTERN_HRES, 8, 1137 OTG_TEST_PATTERN_VRES, 6, 1138 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1139 } 1140 break; 1141 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1142 { 1143 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1144 OTG_TEST_PATTERN_INC0, inc_base, 1145 OTG_TEST_PATTERN_INC1, inc_base + 2, 1146 OTG_TEST_PATTERN_HRES, 8, 1147 OTG_TEST_PATTERN_VRES, 5, 1148 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1149 } 1150 break; 1151 default: 1152 break; 1153 } 1154 1155 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1156 1157 /* enable test pattern */ 1158 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1159 1160 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1161 OTG_TEST_PATTERN_EN, 1, 1162 OTG_TEST_PATTERN_MODE, mode, 1163 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1164 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1165 } 1166 break; 1167 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1168 { 1169 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1170 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1171 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1172 } 1173 break; 1174 default: 1175 break; 1176 1177 } 1178 } 1179 1180 void optc1_get_crtc_scanoutpos( 1181 struct timing_generator *optc, 1182 uint32_t *v_blank_start, 1183 uint32_t *v_blank_end, 1184 uint32_t *h_position, 1185 uint32_t *v_position) 1186 { 1187 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1188 struct crtc_position position; 1189 1190 REG_GET_2(OTG_V_BLANK_START_END, 1191 OTG_V_BLANK_START, v_blank_start, 1192 OTG_V_BLANK_END, v_blank_end); 1193 1194 optc1_get_position(optc, &position); 1195 1196 *h_position = position.horizontal_count; 1197 *v_position = position.vertical_count; 1198 } 1199 1200 static void optc1_enable_stereo(struct timing_generator *optc, 1201 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1202 { 1203 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1204 1205 if (flags) { 1206 uint32_t stereo_en; 1207 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1208 1209 if (flags->PROGRAM_STEREO) 1210 REG_UPDATE_3(OTG_STEREO_CONTROL, 1211 OTG_STEREO_EN, stereo_en, 1212 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1213 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1214 1215 if (flags->PROGRAM_POLARITY) 1216 REG_UPDATE(OTG_STEREO_CONTROL, 1217 OTG_STEREO_EYE_FLAG_POLARITY, 1218 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1219 1220 if (flags->DISABLE_STEREO_DP_SYNC) 1221 REG_UPDATE(OTG_STEREO_CONTROL, 1222 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1223 1224 if (flags->PROGRAM_STEREO) 1225 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1226 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1227 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1228 1229 } 1230 } 1231 1232 void optc1_program_stereo(struct timing_generator *optc, 1233 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1234 { 1235 if (flags->PROGRAM_STEREO) 1236 optc1_enable_stereo(optc, timing, flags); 1237 else 1238 optc1_disable_stereo(optc); 1239 } 1240 1241 1242 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1243 { 1244 bool ret = false; 1245 uint32_t left_eye = 0; 1246 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1247 1248 REG_GET(OTG_STEREO_STATUS, 1249 OTG_STEREO_CURRENT_EYE, &left_eye); 1250 if (left_eye == 1) 1251 ret = true; 1252 else 1253 ret = false; 1254 1255 return ret; 1256 } 1257 1258 bool optc1_get_hw_timing(struct timing_generator *tg, 1259 struct dc_crtc_timing *hw_crtc_timing) 1260 { 1261 struct dcn_otg_state s = {0}; 1262 1263 if (tg == NULL || hw_crtc_timing == NULL) 1264 return false; 1265 1266 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1267 1268 hw_crtc_timing->h_total = s.h_total + 1; 1269 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1270 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1271 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1272 1273 hw_crtc_timing->v_total = s.v_total + 1; 1274 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1275 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1276 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1277 1278 return true; 1279 } 1280 1281 1282 void optc1_read_otg_state(struct optc *optc1, 1283 struct dcn_otg_state *s) 1284 { 1285 REG_GET(OTG_CONTROL, 1286 OTG_MASTER_EN, &s->otg_enabled); 1287 1288 REG_GET_2(OTG_V_BLANK_START_END, 1289 OTG_V_BLANK_START, &s->v_blank_start, 1290 OTG_V_BLANK_END, &s->v_blank_end); 1291 1292 REG_GET(OTG_V_SYNC_A_CNTL, 1293 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1294 1295 REG_GET(OTG_V_TOTAL, 1296 OTG_V_TOTAL, &s->v_total); 1297 1298 REG_GET(OTG_V_TOTAL_MAX, 1299 OTG_V_TOTAL_MAX, &s->v_total_max); 1300 1301 REG_GET(OTG_V_TOTAL_MIN, 1302 OTG_V_TOTAL_MIN, &s->v_total_min); 1303 1304 REG_GET(OTG_V_TOTAL_CONTROL, 1305 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1306 1307 REG_GET(OTG_V_TOTAL_CONTROL, 1308 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1309 1310 REG_GET_2(OTG_V_SYNC_A, 1311 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1312 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1313 1314 REG_GET_2(OTG_H_BLANK_START_END, 1315 OTG_H_BLANK_START, &s->h_blank_start, 1316 OTG_H_BLANK_END, &s->h_blank_end); 1317 1318 REG_GET_2(OTG_H_SYNC_A, 1319 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1320 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1321 1322 REG_GET(OTG_H_SYNC_A_CNTL, 1323 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1324 1325 REG_GET(OTG_H_TOTAL, 1326 OTG_H_TOTAL, &s->h_total); 1327 1328 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1329 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1330 } 1331 1332 bool optc1_get_otg_active_size(struct timing_generator *optc, 1333 uint32_t *otg_active_width, 1334 uint32_t *otg_active_height) 1335 { 1336 uint32_t otg_enabled; 1337 uint32_t v_blank_start; 1338 uint32_t v_blank_end; 1339 uint32_t h_blank_start; 1340 uint32_t h_blank_end; 1341 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1342 1343 1344 REG_GET(OTG_CONTROL, 1345 OTG_MASTER_EN, &otg_enabled); 1346 1347 if (otg_enabled == 0) 1348 return false; 1349 1350 REG_GET_2(OTG_V_BLANK_START_END, 1351 OTG_V_BLANK_START, &v_blank_start, 1352 OTG_V_BLANK_END, &v_blank_end); 1353 1354 REG_GET_2(OTG_H_BLANK_START_END, 1355 OTG_H_BLANK_START, &h_blank_start, 1356 OTG_H_BLANK_END, &h_blank_end); 1357 1358 *otg_active_width = v_blank_start - v_blank_end; 1359 *otg_active_height = h_blank_start - h_blank_end; 1360 return true; 1361 } 1362 1363 void optc1_clear_optc_underflow(struct timing_generator *optc) 1364 { 1365 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1366 1367 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1368 } 1369 1370 void optc1_tg_init(struct timing_generator *optc) 1371 { 1372 optc1_set_blank_data_double_buffer(optc, true); 1373 optc1_set_timing_double_buffer(optc, true); 1374 optc1_clear_optc_underflow(optc); 1375 } 1376 1377 bool optc1_is_tg_enabled(struct timing_generator *optc) 1378 { 1379 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1380 uint32_t otg_enabled = 0; 1381 1382 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1383 1384 return (otg_enabled != 0); 1385 1386 } 1387 1388 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1389 { 1390 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1391 uint32_t underflow_occurred = 0; 1392 1393 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1394 OPTC_UNDERFLOW_OCCURRED_STATUS, 1395 &underflow_occurred); 1396 1397 return (underflow_occurred == 1); 1398 } 1399 1400 bool optc1_configure_crc(struct timing_generator *optc, 1401 const struct crc_params *params) 1402 { 1403 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1404 1405 /* Cannot configure crc on a CRTC that is disabled */ 1406 if (!optc1_is_tg_enabled(optc)) 1407 return false; 1408 1409 REG_WRITE(OTG_CRC_CNTL, 0); 1410 1411 if (!params->enable) 1412 return true; 1413 1414 /* Program frame boundaries */ 1415 /* Window A x axis start and end. */ 1416 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1417 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1418 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1419 1420 /* Window A y axis start and end. */ 1421 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1422 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1423 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1424 1425 /* Window B x axis start and end. */ 1426 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1427 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1428 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1429 1430 /* Window B y axis start and end. */ 1431 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1432 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1433 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1434 1435 /* Set crc mode and selection, and enable. Only using CRC0*/ 1436 REG_UPDATE_3(OTG_CRC_CNTL, 1437 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1438 OTG_CRC0_SELECT, params->selection, 1439 OTG_CRC_EN, 1); 1440 1441 return true; 1442 } 1443 1444 bool optc1_get_crc(struct timing_generator *optc, 1445 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1446 { 1447 uint32_t field = 0; 1448 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1449 1450 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1451 1452 /* Early return if CRC is not enabled for this CRTC */ 1453 if (!field) 1454 return false; 1455 1456 REG_GET_2(OTG_CRC0_DATA_RG, 1457 CRC0_R_CR, r_cr, 1458 CRC0_G_Y, g_y); 1459 1460 REG_GET(OTG_CRC0_DATA_B, 1461 CRC0_B_CB, b_cb); 1462 1463 return true; 1464 } 1465 1466 static const struct timing_generator_funcs dcn10_tg_funcs = { 1467 .validate_timing = optc1_validate_timing, 1468 .program_timing = optc1_program_timing, 1469 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1470 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1471 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1472 .program_global_sync = optc1_program_global_sync, 1473 .enable_crtc = optc1_enable_crtc, 1474 .disable_crtc = optc1_disable_crtc, 1475 /* used by enable_timing_synchronization. Not need for FPGA */ 1476 .is_counter_moving = optc1_is_counter_moving, 1477 .get_position = optc1_get_position, 1478 .get_frame_count = optc1_get_vblank_counter, 1479 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1480 .get_otg_active_size = optc1_get_otg_active_size, 1481 .set_early_control = optc1_set_early_control, 1482 /* used by enable_timing_synchronization. Not need for FPGA */ 1483 .wait_for_state = optc1_wait_for_state, 1484 .set_blank = optc1_set_blank, 1485 .is_blanked = optc1_is_blanked, 1486 .set_blank_color = optc1_program_blank_color, 1487 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1488 .enable_reset_trigger = optc1_enable_reset_trigger, 1489 .enable_crtc_reset = optc1_enable_crtc_reset, 1490 .disable_reset_trigger = optc1_disable_reset_trigger, 1491 .lock = optc1_lock, 1492 .unlock = optc1_unlock, 1493 .enable_optc_clock = optc1_enable_optc_clock, 1494 .set_drr = optc1_set_drr, 1495 .set_static_screen_control = optc1_set_static_screen_control, 1496 .set_test_pattern = optc1_set_test_pattern, 1497 .program_stereo = optc1_program_stereo, 1498 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1499 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1500 .tg_init = optc1_tg_init, 1501 .is_tg_enabled = optc1_is_tg_enabled, 1502 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1503 .clear_optc_underflow = optc1_clear_optc_underflow, 1504 .get_crc = optc1_get_crc, 1505 .configure_crc = optc1_configure_crc, 1506 .set_vtg_params = optc1_set_vtg_params, 1507 .program_manual_trigger = optc1_program_manual_trigger, 1508 .setup_manual_trigger = optc1_setup_manual_trigger, 1509 .get_hw_timing = optc1_get_hw_timing, 1510 }; 1511 1512 void dcn10_timing_generator_init(struct optc *optc1) 1513 { 1514 optc1->base.funcs = &dcn10_tg_funcs; 1515 1516 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1517 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1518 1519 optc1->min_h_blank = 32; 1520 optc1->min_v_blank = 3; 1521 optc1->min_v_blank_interlace = 5; 1522 optc1->min_h_sync_width = 8; 1523 optc1->min_v_sync_width = 1; 1524 } 1525 1526 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1527 * 1528 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1529 * containter rate. 1530 * 1531 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1532 * halved to maintain the correct pixel rate. 1533 * 1534 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1535 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1536 * 1537 */ 1538 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1539 { 1540 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1541 1542 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1543 && !timing->dsc_cfg.ycbcr422_simple); 1544 return two_pix; 1545 } 1546 1547