1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 uint32_t h_div_2; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 169 /* Load horizontal timing */ 170 171 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 172 REG_SET(OTG_H_TOTAL, 0, 173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 174 175 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 176 REG_UPDATE_2(OTG_H_SYNC_A, 177 OTG_H_SYNC_A_START, 0, 178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 179 180 /* blank_start = line end - front porch */ 181 asic_blank_start = patched_crtc_timing.h_total - 182 patched_crtc_timing.h_front_porch; 183 184 /* blank_end = blank_start - active */ 185 asic_blank_end = asic_blank_start - 186 patched_crtc_timing.h_border_right - 187 patched_crtc_timing.h_addressable - 188 patched_crtc_timing.h_border_left; 189 190 REG_UPDATE_2(OTG_H_BLANK_START_END, 191 OTG_H_BLANK_START, asic_blank_start, 192 OTG_H_BLANK_END, asic_blank_end); 193 194 /* h_sync polarity */ 195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 196 0 : 1; 197 198 REG_UPDATE(OTG_H_SYNC_A_CNTL, 199 OTG_H_SYNC_A_POL, h_sync_polarity); 200 201 v_total = patched_crtc_timing.v_total - 1; 202 203 REG_SET(OTG_V_TOTAL, 0, 204 OTG_V_TOTAL, v_total); 205 206 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 207 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 208 */ 209 REG_SET(OTG_V_TOTAL_MAX, 0, 210 OTG_V_TOTAL_MAX, v_total); 211 REG_SET(OTG_V_TOTAL_MIN, 0, 212 OTG_V_TOTAL_MIN, v_total); 213 214 /* v_sync_start = 0, v_sync_end = v_sync_width */ 215 v_sync_end = patched_crtc_timing.v_sync_width; 216 217 REG_UPDATE_2(OTG_V_SYNC_A, 218 OTG_V_SYNC_A_START, 0, 219 OTG_V_SYNC_A_END, v_sync_end); 220 221 /* blank_start = frame end - front porch */ 222 asic_blank_start = patched_crtc_timing.v_total - 223 patched_crtc_timing.v_front_porch; 224 225 /* blank_end = blank_start - active */ 226 asic_blank_end = asic_blank_start - 227 patched_crtc_timing.v_border_bottom - 228 patched_crtc_timing.v_addressable - 229 patched_crtc_timing.v_border_top; 230 231 REG_UPDATE_2(OTG_V_BLANK_START_END, 232 OTG_V_BLANK_START, asic_blank_start, 233 OTG_V_BLANK_END, asic_blank_end); 234 235 /* v_sync polarity */ 236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 237 0 : 1; 238 239 REG_UPDATE(OTG_V_SYNC_A_CNTL, 240 OTG_V_SYNC_A_POL, v_sync_polarity); 241 242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 244 optc1->signal == SIGNAL_TYPE_EDP) { 245 start_point = 1; 246 if (patched_crtc_timing.flags.INTERLACE == 1) 247 field_num = 1; 248 } 249 250 /* Interlace */ 251 if (REG(OTG_INTERLACE_CONTROL)) { 252 if (patched_crtc_timing.flags.INTERLACE == 1) 253 REG_UPDATE(OTG_INTERLACE_CONTROL, 254 OTG_INTERLACE_ENABLE, 1); 255 else 256 REG_UPDATE(OTG_INTERLACE_CONTROL, 257 OTG_INTERLACE_ENABLE, 0); 258 } 259 260 /* VTG enable set to 0 first VInit */ 261 REG_UPDATE(CONTROL, 262 VTG0_ENABLE, 0); 263 264 /* original code is using VTG offset to address OTG reg, seems wrong */ 265 REG_UPDATE_2(OTG_CONTROL, 266 OTG_START_POINT_CNTL, start_point, 267 OTG_FIELD_NUMBER_CNTL, field_num); 268 269 optc->funcs->program_global_sync(optc, 270 vready_offset, 271 vstartup_start, 272 vupdate_offset, 273 vupdate_width); 274 275 optc->funcs->set_vtg_params(optc, dc_crtc_timing); 276 277 /* TODO 278 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 279 * program_horz_count_by_2 280 * for DVI 30bpp mode, 0 otherwise 281 * program_horz_count_by_2(optc, &patched_crtc_timing); 282 */ 283 284 /* Enable stereo - only when we need to pack 3D frame. Other types 285 * of stereo handled in explicit call 286 */ 287 288 h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing); 289 REG_UPDATE(OTG_H_TIMING_CNTL, 290 OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf); 291 292 } 293 294 void optc1_set_vtg_params(struct timing_generator *optc, 295 const struct dc_crtc_timing *dc_crtc_timing) 296 { 297 struct dc_crtc_timing patched_crtc_timing; 298 uint32_t asic_blank_end; 299 uint32_t v_init; 300 uint32_t v_fp2 = 0; 301 int32_t vertical_line_start; 302 303 struct optc *optc1 = DCN10TG_FROM_TG(optc); 304 305 patched_crtc_timing = *dc_crtc_timing; 306 apply_front_porch_workaround(&patched_crtc_timing); 307 308 /* VCOUNT_INIT is the start of blank */ 309 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 310 311 /* end of blank = v_init - active */ 312 asic_blank_end = v_init - 313 patched_crtc_timing.v_border_bottom - 314 patched_crtc_timing.v_addressable - 315 patched_crtc_timing.v_border_top; 316 317 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 318 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 319 if (vertical_line_start < 0) 320 v_fp2 = -vertical_line_start; 321 322 /* Interlace */ 323 if (REG(OTG_INTERLACE_CONTROL)) { 324 if (patched_crtc_timing.flags.INTERLACE == 1) { 325 v_init = v_init / 2; 326 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 327 v_fp2 = v_fp2 / 2; 328 } 329 } 330 331 REG_UPDATE_2(CONTROL, 332 VTG0_FP2, v_fp2, 333 VTG0_VCOUNT_INIT, v_init); 334 } 335 336 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 337 { 338 struct optc *optc1 = DCN10TG_FROM_TG(optc); 339 340 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 341 342 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 343 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 344 } 345 346 /** 347 * unblank_crtc 348 * Call ASIC Control Object to UnBlank CRTC. 349 */ 350 static void optc1_unblank_crtc(struct timing_generator *optc) 351 { 352 struct optc *optc1 = DCN10TG_FROM_TG(optc); 353 354 REG_UPDATE_2(OTG_BLANK_CONTROL, 355 OTG_BLANK_DATA_EN, 0, 356 OTG_BLANK_DE_MODE, 0); 357 358 /* W/A for automated testing 359 * Automated testing will fail underflow test as there 360 * sporadic underflows which occur during the optc blank 361 * sequence. As a w/a, clear underflow on unblank. 362 * This prevents the failure, but will not mask actual 363 * underflow that affect real use cases. 364 */ 365 optc1_clear_optc_underflow(optc); 366 } 367 368 /** 369 * blank_crtc 370 * Call ASIC Control Object to Blank CRTC. 371 */ 372 373 static void optc1_blank_crtc(struct timing_generator *optc) 374 { 375 struct optc *optc1 = DCN10TG_FROM_TG(optc); 376 377 REG_UPDATE_2(OTG_BLANK_CONTROL, 378 OTG_BLANK_DATA_EN, 1, 379 OTG_BLANK_DE_MODE, 0); 380 381 optc1_set_blank_data_double_buffer(optc, false); 382 } 383 384 void optc1_set_blank(struct timing_generator *optc, 385 bool enable_blanking) 386 { 387 if (enable_blanking) 388 optc1_blank_crtc(optc); 389 else 390 optc1_unblank_crtc(optc); 391 } 392 393 bool optc1_is_blanked(struct timing_generator *optc) 394 { 395 struct optc *optc1 = DCN10TG_FROM_TG(optc); 396 uint32_t blank_en; 397 uint32_t blank_state; 398 399 REG_GET_2(OTG_BLANK_CONTROL, 400 OTG_BLANK_DATA_EN, &blank_en, 401 OTG_CURRENT_BLANK_STATE, &blank_state); 402 403 return blank_en && blank_state; 404 } 405 406 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 407 { 408 struct optc *optc1 = DCN10TG_FROM_TG(optc); 409 410 if (enable) { 411 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 412 OPTC_INPUT_CLK_EN, 1, 413 OPTC_INPUT_CLK_GATE_DIS, 1); 414 415 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 416 OPTC_INPUT_CLK_ON, 1, 417 1, 1000); 418 419 /* Enable clock */ 420 REG_UPDATE_2(OTG_CLOCK_CONTROL, 421 OTG_CLOCK_EN, 1, 422 OTG_CLOCK_GATE_DIS, 1); 423 REG_WAIT(OTG_CLOCK_CONTROL, 424 OTG_CLOCK_ON, 1, 425 1, 1000); 426 } else { 427 REG_UPDATE_2(OTG_CLOCK_CONTROL, 428 OTG_CLOCK_GATE_DIS, 0, 429 OTG_CLOCK_EN, 0); 430 431 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 432 OPTC_INPUT_CLK_GATE_DIS, 0, 433 OPTC_INPUT_CLK_EN, 0); 434 } 435 } 436 437 /** 438 * Enable CRTC 439 * Enable CRTC - call ASIC Control Object to enable Timing generator. 440 */ 441 static bool optc1_enable_crtc(struct timing_generator *optc) 442 { 443 /* TODO FPGA wait for answer 444 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 445 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 446 */ 447 struct optc *optc1 = DCN10TG_FROM_TG(optc); 448 449 /* opp instance for OTG. For DCN1.0, ODM is remoed. 450 * OPP and OPTC should 1:1 mapping 451 */ 452 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 453 OPTC_SRC_SEL, optc->inst); 454 455 /* VTG enable first is for HW workaround */ 456 REG_UPDATE(CONTROL, 457 VTG0_ENABLE, 1); 458 459 /* Enable CRTC */ 460 REG_UPDATE_2(OTG_CONTROL, 461 OTG_DISABLE_POINT_CNTL, 3, 462 OTG_MASTER_EN, 1); 463 464 return true; 465 } 466 467 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 468 bool optc1_disable_crtc(struct timing_generator *optc) 469 { 470 struct optc *optc1 = DCN10TG_FROM_TG(optc); 471 472 /* disable otg request until end of the first line 473 * in the vertical blank region 474 */ 475 REG_UPDATE_2(OTG_CONTROL, 476 OTG_DISABLE_POINT_CNTL, 3, 477 OTG_MASTER_EN, 0); 478 479 REG_UPDATE(CONTROL, 480 VTG0_ENABLE, 0); 481 482 /* CRTC disabled, so disable clock. */ 483 REG_WAIT(OTG_CLOCK_CONTROL, 484 OTG_BUSY, 0, 485 1, 100000); 486 487 return true; 488 } 489 490 491 void optc1_program_blank_color( 492 struct timing_generator *optc, 493 const struct tg_color *black_color) 494 { 495 struct optc *optc1 = DCN10TG_FROM_TG(optc); 496 497 REG_SET_3(OTG_BLACK_COLOR, 0, 498 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 499 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 500 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 501 } 502 503 bool optc1_validate_timing( 504 struct timing_generator *optc, 505 const struct dc_crtc_timing *timing) 506 { 507 uint32_t v_blank; 508 uint32_t h_blank; 509 uint32_t min_v_blank; 510 struct optc *optc1 = DCN10TG_FROM_TG(optc); 511 512 ASSERT(timing != NULL); 513 514 v_blank = (timing->v_total - timing->v_addressable - 515 timing->v_border_top - timing->v_border_bottom); 516 517 h_blank = (timing->h_total - timing->h_addressable - 518 timing->h_border_right - 519 timing->h_border_left); 520 521 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 522 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 523 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 524 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 525 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 526 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 527 return false; 528 529 /* Temporarily blocking interlacing mode until it's supported */ 530 if (timing->flags.INTERLACE == 1) 531 return false; 532 533 /* Check maximum number of pixels supported by Timing Generator 534 * (Currently will never fail, in order to fail needs display which 535 * needs more than 8192 horizontal and 536 * more than 8192 vertical total pixels) 537 */ 538 if (timing->h_total > optc1->max_h_total || 539 timing->v_total > optc1->max_v_total) 540 return false; 541 542 543 if (h_blank < optc1->min_h_blank) 544 return false; 545 546 if (timing->h_sync_width < optc1->min_h_sync_width || 547 timing->v_sync_width < optc1->min_v_sync_width) 548 return false; 549 550 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 551 552 if (v_blank < min_v_blank) 553 return false; 554 555 return true; 556 557 } 558 559 /* 560 * get_vblank_counter 561 * 562 * @brief 563 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 564 * holds the counter of frames. 565 * 566 * @param 567 * struct timing_generator *optc - [in] timing generator which controls the 568 * desired CRTC 569 * 570 * @return 571 * Counter of frames, which should equal to number of vblanks. 572 */ 573 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 574 { 575 struct optc *optc1 = DCN10TG_FROM_TG(optc); 576 uint32_t frame_count; 577 578 REG_GET(OTG_STATUS_FRAME_COUNT, 579 OTG_FRAME_COUNT, &frame_count); 580 581 return frame_count; 582 } 583 584 void optc1_lock(struct timing_generator *optc) 585 { 586 struct optc *optc1 = DCN10TG_FROM_TG(optc); 587 uint32_t regval = 0; 588 589 regval = REG_READ(OTG_CONTROL); 590 591 /* otg is not running, do not need to be locked */ 592 if ((regval & 0x1) == 0x0) 593 return; 594 595 REG_SET(OTG_GLOBAL_CONTROL0, 0, 596 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 597 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 598 OTG_MASTER_UPDATE_LOCK, 1); 599 600 /* Should be fast, status does not update on maximus */ 601 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { 602 603 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 604 UPDATE_LOCK_STATUS, 1, 605 1, 10); 606 } 607 } 608 609 void optc1_unlock(struct timing_generator *optc) 610 { 611 struct optc *optc1 = DCN10TG_FROM_TG(optc); 612 613 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 614 OTG_MASTER_UPDATE_LOCK, 0); 615 } 616 617 void optc1_get_position(struct timing_generator *optc, 618 struct crtc_position *position) 619 { 620 struct optc *optc1 = DCN10TG_FROM_TG(optc); 621 622 REG_GET_2(OTG_STATUS_POSITION, 623 OTG_HORZ_COUNT, &position->horizontal_count, 624 OTG_VERT_COUNT, &position->vertical_count); 625 626 REG_GET(OTG_NOM_VERT_POSITION, 627 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 628 } 629 630 bool optc1_is_counter_moving(struct timing_generator *optc) 631 { 632 struct crtc_position position1, position2; 633 634 optc->funcs->get_position(optc, &position1); 635 optc->funcs->get_position(optc, &position2); 636 637 if (position1.horizontal_count == position2.horizontal_count && 638 position1.vertical_count == position2.vertical_count) 639 return false; 640 else 641 return true; 642 } 643 644 bool optc1_did_triggered_reset_occur( 645 struct timing_generator *optc) 646 { 647 struct optc *optc1 = DCN10TG_FROM_TG(optc); 648 uint32_t occurred_force, occurred_vsync; 649 650 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 651 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 652 653 REG_GET(OTG_VERT_SYNC_CONTROL, 654 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 655 656 return occurred_vsync != 0 || occurred_force != 0; 657 } 658 659 void optc1_disable_reset_trigger(struct timing_generator *optc) 660 { 661 struct optc *optc1 = DCN10TG_FROM_TG(optc); 662 663 REG_WRITE(OTG_TRIGA_CNTL, 0); 664 665 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 666 OTG_FORCE_COUNT_NOW_CLEAR, 1); 667 668 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 669 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 670 } 671 672 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 673 { 674 struct optc *optc1 = DCN10TG_FROM_TG(optc); 675 uint32_t falling_edge; 676 677 REG_GET(OTG_V_SYNC_A_CNTL, 678 OTG_V_SYNC_A_POL, &falling_edge); 679 680 if (falling_edge) 681 REG_SET_3(OTG_TRIGA_CNTL, 0, 682 /* vsync signal from selected OTG pipe based 683 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 684 */ 685 OTG_TRIGA_SOURCE_SELECT, 20, 686 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 687 /* always detect falling edge */ 688 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 689 else 690 REG_SET_3(OTG_TRIGA_CNTL, 0, 691 /* vsync signal from selected OTG pipe based 692 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 693 */ 694 OTG_TRIGA_SOURCE_SELECT, 20, 695 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 696 /* always detect rising edge */ 697 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 698 699 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 700 /* force H count to H_TOTAL and V count to V_TOTAL in 701 * progressive mode and V_TOTAL-1 in interlaced mode 702 */ 703 OTG_FORCE_COUNT_NOW_MODE, 2); 704 } 705 706 void optc1_enable_crtc_reset( 707 struct timing_generator *optc, 708 int source_tg_inst, 709 struct crtc_trigger_info *crtc_tp) 710 { 711 struct optc *optc1 = DCN10TG_FROM_TG(optc); 712 uint32_t falling_edge = 0; 713 uint32_t rising_edge = 0; 714 715 switch (crtc_tp->event) { 716 717 case CRTC_EVENT_VSYNC_RISING: 718 rising_edge = 1; 719 break; 720 721 case CRTC_EVENT_VSYNC_FALLING: 722 falling_edge = 1; 723 break; 724 } 725 726 REG_SET_4(OTG_TRIGA_CNTL, 0, 727 /* vsync signal from selected OTG pipe based 728 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 729 */ 730 OTG_TRIGA_SOURCE_SELECT, 20, 731 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 732 /* always detect falling edge */ 733 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 734 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 735 736 switch (crtc_tp->delay) { 737 case TRIGGER_DELAY_NEXT_LINE: 738 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 739 OTG_AUTO_FORCE_VSYNC_MODE, 1); 740 break; 741 case TRIGGER_DELAY_NEXT_PIXEL: 742 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 743 /* force H count to H_TOTAL and V count to V_TOTAL in 744 * progressive mode and V_TOTAL-1 in interlaced mode 745 */ 746 OTG_FORCE_COUNT_NOW_MODE, 2); 747 break; 748 } 749 } 750 751 void optc1_wait_for_state(struct timing_generator *optc, 752 enum crtc_state state) 753 { 754 struct optc *optc1 = DCN10TG_FROM_TG(optc); 755 756 switch (state) { 757 case CRTC_STATE_VBLANK: 758 REG_WAIT(OTG_STATUS, 759 OTG_V_BLANK, 1, 760 1, 100000); /* 1 vupdate at 10hz */ 761 break; 762 763 case CRTC_STATE_VACTIVE: 764 REG_WAIT(OTG_STATUS, 765 OTG_V_ACTIVE_DISP, 1, 766 1, 100000); /* 1 vupdate at 10hz */ 767 break; 768 769 default: 770 break; 771 } 772 } 773 774 void optc1_set_early_control( 775 struct timing_generator *optc, 776 uint32_t early_cntl) 777 { 778 /* asic design change, do not need this control 779 * empty for share caller logic 780 */ 781 } 782 783 784 void optc1_set_static_screen_control( 785 struct timing_generator *optc, 786 uint32_t value) 787 { 788 struct optc *optc1 = DCN10TG_FROM_TG(optc); 789 790 /* Bit 8 is no longer applicable in RV for PSR case, 791 * set bit 8 to 0 if given 792 */ 793 if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 794 != 0) 795 value = value & 796 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 797 798 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 799 OTG_STATIC_SCREEN_EVENT_MASK, value, 800 OTG_STATIC_SCREEN_FRAME_COUNT, 2); 801 } 802 803 void optc1_setup_manual_trigger(struct timing_generator *optc) 804 { 805 struct optc *optc1 = DCN10TG_FROM_TG(optc); 806 807 REG_SET(OTG_GLOBAL_CONTROL2, 0, 808 MANUAL_FLOW_CONTROL_SEL, optc->inst); 809 810 REG_SET_8(OTG_TRIGA_CNTL, 0, 811 OTG_TRIGA_SOURCE_SELECT, 22, 812 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 813 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 814 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 815 OTG_TRIGA_POLARITY_SELECT, 0, 816 OTG_TRIGA_FREQUENCY_SELECT, 0, 817 OTG_TRIGA_DELAY, 0, 818 OTG_TRIGA_CLEAR, 1); 819 } 820 821 void optc1_program_manual_trigger(struct timing_generator *optc) 822 { 823 struct optc *optc1 = DCN10TG_FROM_TG(optc); 824 825 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 826 MANUAL_FLOW_CONTROL, 1); 827 } 828 829 830 /** 831 ***************************************************************************** 832 * Function: set_drr 833 * 834 * @brief 835 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 836 * 837 ***************************************************************************** 838 */ 839 void optc1_set_drr( 840 struct timing_generator *optc, 841 const struct drr_params *params) 842 { 843 struct optc *optc1 = DCN10TG_FROM_TG(optc); 844 845 if (params != NULL && 846 params->vertical_total_max > 0 && 847 params->vertical_total_min > 0) { 848 849 REG_SET(OTG_V_TOTAL_MAX, 0, 850 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 851 852 REG_SET(OTG_V_TOTAL_MIN, 0, 853 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 854 855 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 856 OTG_V_TOTAL_MIN_SEL, 1, 857 OTG_V_TOTAL_MAX_SEL, 1, 858 OTG_FORCE_LOCK_ON_EVENT, 0, 859 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 860 OTG_SET_V_TOTAL_MIN_MASK, 0); 861 862 // Setup manual flow control for EOF via TRIG_A 863 optc->funcs->setup_manual_trigger(optc); 864 865 } else { 866 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 867 OTG_SET_V_TOTAL_MIN_MASK, 0, 868 OTG_V_TOTAL_MIN_SEL, 0, 869 OTG_V_TOTAL_MAX_SEL, 0, 870 OTG_FORCE_LOCK_ON_EVENT, 0); 871 872 REG_SET(OTG_V_TOTAL_MIN, 0, 873 OTG_V_TOTAL_MIN, 0); 874 875 REG_SET(OTG_V_TOTAL_MAX, 0, 876 OTG_V_TOTAL_MAX, 0); 877 } 878 } 879 880 static void optc1_set_test_pattern( 881 struct timing_generator *optc, 882 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 883 * because this is not DP-specific (which is probably somewhere in DP 884 * encoder) */ 885 enum controller_dp_test_pattern test_pattern, 886 enum dc_color_depth color_depth) 887 { 888 struct optc *optc1 = DCN10TG_FROM_TG(optc); 889 enum test_pattern_color_format bit_depth; 890 enum test_pattern_dyn_range dyn_range; 891 enum test_pattern_mode mode; 892 uint32_t pattern_mask; 893 uint32_t pattern_data; 894 /* color ramp generator mixes 16-bits color */ 895 uint32_t src_bpc = 16; 896 /* requested bpc */ 897 uint32_t dst_bpc; 898 uint32_t index; 899 /* RGB values of the color bars. 900 * Produce two RGB colors: RGB0 - white (all Fs) 901 * and RGB1 - black (all 0s) 902 * (three RGB components for two colors) 903 */ 904 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 905 0x0000, 0x0000}; 906 /* dest color (converted to the specified color format) */ 907 uint16_t dst_color[6]; 908 uint32_t inc_base; 909 910 /* translate to bit depth */ 911 switch (color_depth) { 912 case COLOR_DEPTH_666: 913 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 914 break; 915 case COLOR_DEPTH_888: 916 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 917 break; 918 case COLOR_DEPTH_101010: 919 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 920 break; 921 case COLOR_DEPTH_121212: 922 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 923 break; 924 default: 925 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 926 break; 927 } 928 929 switch (test_pattern) { 930 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 931 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 932 { 933 dyn_range = (test_pattern == 934 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 935 TEST_PATTERN_DYN_RANGE_CEA : 936 TEST_PATTERN_DYN_RANGE_VESA); 937 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 938 939 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 940 OTG_TEST_PATTERN_VRES, 6, 941 OTG_TEST_PATTERN_HRES, 6); 942 943 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 944 OTG_TEST_PATTERN_EN, 1, 945 OTG_TEST_PATTERN_MODE, mode, 946 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 947 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 948 } 949 break; 950 951 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 952 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 953 { 954 mode = (test_pattern == 955 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 956 TEST_PATTERN_MODE_VERTICALBARS : 957 TEST_PATTERN_MODE_HORIZONTALBARS); 958 959 switch (bit_depth) { 960 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 961 dst_bpc = 6; 962 break; 963 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 964 dst_bpc = 8; 965 break; 966 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 967 dst_bpc = 10; 968 break; 969 default: 970 dst_bpc = 8; 971 break; 972 } 973 974 /* adjust color to the required colorFormat */ 975 for (index = 0; index < 6; index++) { 976 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 977 * (srcBpc - dstBpc); 978 */ 979 dst_color[index] = 980 src_color[index] >> (src_bpc - dst_bpc); 981 /* CRTC_TEST_PATTERN_DATA has 16 bits, 982 * lowest 6 are hardwired to ZERO 983 * color bits should be left aligned aligned to MSB 984 * XXXXXXXXXX000000 for 10 bit, 985 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 986 */ 987 dst_color[index] <<= (16 - dst_bpc); 988 } 989 990 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 991 992 /* We have to write the mask before data, similar to pipeline. 993 * For example, for 8 bpc, if we want RGB0 to be magenta, 994 * and RGB1 to be cyan, 995 * we need to make 7 writes: 996 * MASK DATA 997 * 000001 00000000 00000000 set mask to R0 998 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 999 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1000 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1001 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1002 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1003 * 100000 11111111 00000000 B1 255, 0xFF00 1004 * 1005 * we will make a loop of 6 in which we prepare the mask, 1006 * then write, then prepare the color for next write. 1007 * first iteration will write mask only, 1008 * but each next iteration color prepared in 1009 * previous iteration will be written within new mask, 1010 * the last component will written separately, 1011 * mask is not changing between 6th and 7th write 1012 * and color will be prepared by last iteration 1013 */ 1014 1015 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1016 * is B1, G1, R1, B0, G0, R0 1017 */ 1018 pattern_data = 0; 1019 for (index = 0; index < 6; index++) { 1020 /* prepare color mask, first write PATTERN_DATA 1021 * will have all zeros 1022 */ 1023 pattern_mask = (1 << index); 1024 1025 /* write color component */ 1026 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1027 OTG_TEST_PATTERN_MASK, pattern_mask, 1028 OTG_TEST_PATTERN_DATA, pattern_data); 1029 1030 /* prepare next color component, 1031 * will be written in the next iteration 1032 */ 1033 pattern_data = dst_color[index]; 1034 } 1035 /* write last color component, 1036 * it's been already prepared in the loop 1037 */ 1038 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1039 OTG_TEST_PATTERN_MASK, pattern_mask, 1040 OTG_TEST_PATTERN_DATA, pattern_data); 1041 1042 /* enable test pattern */ 1043 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1044 OTG_TEST_PATTERN_EN, 1, 1045 OTG_TEST_PATTERN_MODE, mode, 1046 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1047 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1048 } 1049 break; 1050 1051 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1052 { 1053 mode = (bit_depth == 1054 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1055 TEST_PATTERN_MODE_DUALRAMP_RGB : 1056 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1057 1058 switch (bit_depth) { 1059 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1060 dst_bpc = 6; 1061 break; 1062 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1063 dst_bpc = 8; 1064 break; 1065 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1066 dst_bpc = 10; 1067 break; 1068 default: 1069 dst_bpc = 8; 1070 break; 1071 } 1072 1073 /* increment for the first ramp for one color gradation 1074 * 1 gradation for 6-bit color is 2^10 1075 * gradations in 16-bit color 1076 */ 1077 inc_base = (src_bpc - dst_bpc); 1078 1079 switch (bit_depth) { 1080 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1081 { 1082 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1083 OTG_TEST_PATTERN_INC0, inc_base, 1084 OTG_TEST_PATTERN_INC1, 0, 1085 OTG_TEST_PATTERN_HRES, 6, 1086 OTG_TEST_PATTERN_VRES, 6, 1087 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1088 } 1089 break; 1090 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1091 { 1092 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1093 OTG_TEST_PATTERN_INC0, inc_base, 1094 OTG_TEST_PATTERN_INC1, 0, 1095 OTG_TEST_PATTERN_HRES, 8, 1096 OTG_TEST_PATTERN_VRES, 6, 1097 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1098 } 1099 break; 1100 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1101 { 1102 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1103 OTG_TEST_PATTERN_INC0, inc_base, 1104 OTG_TEST_PATTERN_INC1, inc_base + 2, 1105 OTG_TEST_PATTERN_HRES, 8, 1106 OTG_TEST_PATTERN_VRES, 5, 1107 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1108 } 1109 break; 1110 default: 1111 break; 1112 } 1113 1114 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1115 1116 /* enable test pattern */ 1117 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1118 1119 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1120 OTG_TEST_PATTERN_EN, 1, 1121 OTG_TEST_PATTERN_MODE, mode, 1122 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1123 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1124 } 1125 break; 1126 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1127 { 1128 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1129 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1130 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1131 } 1132 break; 1133 default: 1134 break; 1135 1136 } 1137 } 1138 1139 void optc1_get_crtc_scanoutpos( 1140 struct timing_generator *optc, 1141 uint32_t *v_blank_start, 1142 uint32_t *v_blank_end, 1143 uint32_t *h_position, 1144 uint32_t *v_position) 1145 { 1146 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1147 struct crtc_position position; 1148 1149 REG_GET_2(OTG_V_BLANK_START_END, 1150 OTG_V_BLANK_START, v_blank_start, 1151 OTG_V_BLANK_END, v_blank_end); 1152 1153 optc1_get_position(optc, &position); 1154 1155 *h_position = position.horizontal_count; 1156 *v_position = position.vertical_count; 1157 } 1158 1159 static void optc1_enable_stereo(struct timing_generator *optc, 1160 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1161 { 1162 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1163 1164 if (flags) { 1165 uint32_t stereo_en; 1166 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1167 1168 if (flags->PROGRAM_STEREO) 1169 REG_UPDATE_3(OTG_STEREO_CONTROL, 1170 OTG_STEREO_EN, stereo_en, 1171 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1172 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0); 1173 1174 if (flags->PROGRAM_POLARITY) 1175 REG_UPDATE(OTG_STEREO_CONTROL, 1176 OTG_STEREO_EYE_FLAG_POLARITY, 1177 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1178 1179 if (flags->DISABLE_STEREO_DP_SYNC) 1180 REG_UPDATE(OTG_STEREO_CONTROL, 1181 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1182 1183 if (flags->PROGRAM_STEREO) 1184 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1185 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1186 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1187 1188 } 1189 } 1190 1191 void optc1_program_stereo(struct timing_generator *optc, 1192 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1193 { 1194 if (flags->PROGRAM_STEREO) 1195 optc1_enable_stereo(optc, timing, flags); 1196 else 1197 optc1_disable_stereo(optc); 1198 } 1199 1200 1201 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1202 { 1203 bool ret = false; 1204 uint32_t left_eye = 0; 1205 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1206 1207 REG_GET(OTG_STEREO_STATUS, 1208 OTG_STEREO_CURRENT_EYE, &left_eye); 1209 if (left_eye == 1) 1210 ret = true; 1211 else 1212 ret = false; 1213 1214 return ret; 1215 } 1216 1217 bool optc1_is_matching_timing(struct timing_generator *tg, 1218 const struct dc_crtc_timing *otg_timing) 1219 { 1220 struct dc_crtc_timing hw_crtc_timing = {0}; 1221 struct dcn_otg_state s = {0}; 1222 1223 if (tg == NULL || otg_timing == NULL) 1224 return false; 1225 1226 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1227 1228 hw_crtc_timing.h_total = s.h_total + 1; 1229 hw_crtc_timing.h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1230 hw_crtc_timing.h_front_porch = s.h_total + 1 - s.h_blank_start; 1231 hw_crtc_timing.h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1232 1233 hw_crtc_timing.v_total = s.v_total + 1; 1234 hw_crtc_timing.v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1235 hw_crtc_timing.v_front_porch = s.v_total + 1 - s.v_blank_start; 1236 hw_crtc_timing.v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1237 1238 if (otg_timing->h_total != hw_crtc_timing.h_total) 1239 return false; 1240 1241 if (otg_timing->h_border_left != hw_crtc_timing.h_border_left) 1242 return false; 1243 1244 if (otg_timing->h_addressable != hw_crtc_timing.h_addressable) 1245 return false; 1246 1247 if (otg_timing->h_border_right != hw_crtc_timing.h_border_right) 1248 return false; 1249 1250 if (otg_timing->h_front_porch != hw_crtc_timing.h_front_porch) 1251 return false; 1252 1253 if (otg_timing->h_sync_width != hw_crtc_timing.h_sync_width) 1254 return false; 1255 1256 if (otg_timing->v_total != hw_crtc_timing.v_total) 1257 return false; 1258 1259 if (otg_timing->v_border_top != hw_crtc_timing.v_border_top) 1260 return false; 1261 1262 if (otg_timing->v_addressable != hw_crtc_timing.v_addressable) 1263 return false; 1264 1265 if (otg_timing->v_border_bottom != hw_crtc_timing.v_border_bottom) 1266 return false; 1267 1268 if (otg_timing->v_sync_width != hw_crtc_timing.v_sync_width) 1269 return false; 1270 1271 return true; 1272 } 1273 1274 1275 void optc1_read_otg_state(struct optc *optc1, 1276 struct dcn_otg_state *s) 1277 { 1278 REG_GET(OTG_CONTROL, 1279 OTG_MASTER_EN, &s->otg_enabled); 1280 1281 REG_GET_2(OTG_V_BLANK_START_END, 1282 OTG_V_BLANK_START, &s->v_blank_start, 1283 OTG_V_BLANK_END, &s->v_blank_end); 1284 1285 REG_GET(OTG_V_SYNC_A_CNTL, 1286 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1287 1288 REG_GET(OTG_V_TOTAL, 1289 OTG_V_TOTAL, &s->v_total); 1290 1291 REG_GET(OTG_V_TOTAL_MAX, 1292 OTG_V_TOTAL_MAX, &s->v_total_max); 1293 1294 REG_GET(OTG_V_TOTAL_MIN, 1295 OTG_V_TOTAL_MIN, &s->v_total_min); 1296 1297 REG_GET(OTG_V_TOTAL_CONTROL, 1298 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1299 1300 REG_GET(OTG_V_TOTAL_CONTROL, 1301 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1302 1303 REG_GET_2(OTG_V_SYNC_A, 1304 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1305 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1306 1307 REG_GET_2(OTG_H_BLANK_START_END, 1308 OTG_H_BLANK_START, &s->h_blank_start, 1309 OTG_H_BLANK_END, &s->h_blank_end); 1310 1311 REG_GET_2(OTG_H_SYNC_A, 1312 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1313 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1314 1315 REG_GET(OTG_H_SYNC_A_CNTL, 1316 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1317 1318 REG_GET(OTG_H_TOTAL, 1319 OTG_H_TOTAL, &s->h_total); 1320 1321 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1322 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1323 } 1324 1325 bool optc1_get_otg_active_size(struct timing_generator *optc, 1326 uint32_t *otg_active_width, 1327 uint32_t *otg_active_height) 1328 { 1329 uint32_t otg_enabled; 1330 uint32_t v_blank_start; 1331 uint32_t v_blank_end; 1332 uint32_t h_blank_start; 1333 uint32_t h_blank_end; 1334 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1335 1336 1337 REG_GET(OTG_CONTROL, 1338 OTG_MASTER_EN, &otg_enabled); 1339 1340 if (otg_enabled == 0) 1341 return false; 1342 1343 REG_GET_2(OTG_V_BLANK_START_END, 1344 OTG_V_BLANK_START, &v_blank_start, 1345 OTG_V_BLANK_END, &v_blank_end); 1346 1347 REG_GET_2(OTG_H_BLANK_START_END, 1348 OTG_H_BLANK_START, &h_blank_start, 1349 OTG_H_BLANK_END, &h_blank_end); 1350 1351 *otg_active_width = v_blank_start - v_blank_end; 1352 *otg_active_height = h_blank_start - h_blank_end; 1353 return true; 1354 } 1355 1356 void optc1_clear_optc_underflow(struct timing_generator *optc) 1357 { 1358 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1359 1360 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1361 } 1362 1363 void optc1_tg_init(struct timing_generator *optc) 1364 { 1365 optc1_set_blank_data_double_buffer(optc, true); 1366 optc1_clear_optc_underflow(optc); 1367 } 1368 1369 bool optc1_is_tg_enabled(struct timing_generator *optc) 1370 { 1371 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1372 uint32_t otg_enabled = 0; 1373 1374 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1375 1376 return (otg_enabled != 0); 1377 1378 } 1379 1380 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1381 { 1382 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1383 uint32_t underflow_occurred = 0; 1384 1385 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1386 OPTC_UNDERFLOW_OCCURRED_STATUS, 1387 &underflow_occurred); 1388 1389 return (underflow_occurred == 1); 1390 } 1391 1392 bool optc1_configure_crc(struct timing_generator *optc, 1393 const struct crc_params *params) 1394 { 1395 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1396 1397 /* Cannot configure crc on a CRTC that is disabled */ 1398 if (!optc1_is_tg_enabled(optc)) 1399 return false; 1400 1401 REG_WRITE(OTG_CRC_CNTL, 0); 1402 1403 if (!params->enable) 1404 return true; 1405 1406 /* Program frame boundaries */ 1407 /* Window A x axis start and end. */ 1408 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1409 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1410 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1411 1412 /* Window A y axis start and end. */ 1413 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1414 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1415 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1416 1417 /* Window B x axis start and end. */ 1418 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1419 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1420 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1421 1422 /* Window B y axis start and end. */ 1423 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1424 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1425 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1426 1427 /* Set crc mode and selection, and enable. Only using CRC0*/ 1428 REG_UPDATE_3(OTG_CRC_CNTL, 1429 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1430 OTG_CRC0_SELECT, params->selection, 1431 OTG_CRC_EN, 1); 1432 1433 return true; 1434 } 1435 1436 bool optc1_get_crc(struct timing_generator *optc, 1437 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1438 { 1439 uint32_t field = 0; 1440 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1441 1442 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1443 1444 /* Early return if CRC is not enabled for this CRTC */ 1445 if (!field) 1446 return false; 1447 1448 REG_GET_2(OTG_CRC0_DATA_RG, 1449 CRC0_R_CR, r_cr, 1450 CRC0_G_Y, g_y); 1451 1452 REG_GET(OTG_CRC0_DATA_B, 1453 CRC0_B_CB, b_cb); 1454 1455 return true; 1456 } 1457 1458 static const struct timing_generator_funcs dcn10_tg_funcs = { 1459 .validate_timing = optc1_validate_timing, 1460 .program_timing = optc1_program_timing, 1461 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1462 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1463 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1464 .program_global_sync = optc1_program_global_sync, 1465 .enable_crtc = optc1_enable_crtc, 1466 .disable_crtc = optc1_disable_crtc, 1467 /* used by enable_timing_synchronization. Not need for FPGA */ 1468 .is_counter_moving = optc1_is_counter_moving, 1469 .get_position = optc1_get_position, 1470 .get_frame_count = optc1_get_vblank_counter, 1471 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1472 .get_otg_active_size = optc1_get_otg_active_size, 1473 .is_matching_timing = optc1_is_matching_timing, 1474 .set_early_control = optc1_set_early_control, 1475 /* used by enable_timing_synchronization. Not need for FPGA */ 1476 .wait_for_state = optc1_wait_for_state, 1477 .set_blank = optc1_set_blank, 1478 .is_blanked = optc1_is_blanked, 1479 .set_blank_color = optc1_program_blank_color, 1480 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1481 .enable_reset_trigger = optc1_enable_reset_trigger, 1482 .enable_crtc_reset = optc1_enable_crtc_reset, 1483 .disable_reset_trigger = optc1_disable_reset_trigger, 1484 .lock = optc1_lock, 1485 .unlock = optc1_unlock, 1486 .enable_optc_clock = optc1_enable_optc_clock, 1487 .set_drr = optc1_set_drr, 1488 .set_static_screen_control = optc1_set_static_screen_control, 1489 .set_test_pattern = optc1_set_test_pattern, 1490 .program_stereo = optc1_program_stereo, 1491 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1492 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1493 .tg_init = optc1_tg_init, 1494 .is_tg_enabled = optc1_is_tg_enabled, 1495 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1496 .clear_optc_underflow = optc1_clear_optc_underflow, 1497 .get_crc = optc1_get_crc, 1498 .configure_crc = optc1_configure_crc, 1499 .set_vtg_params = optc1_set_vtg_params, 1500 .program_manual_trigger = optc1_program_manual_trigger, 1501 .setup_manual_trigger = optc1_setup_manual_trigger 1502 }; 1503 1504 void dcn10_timing_generator_init(struct optc *optc1) 1505 { 1506 optc1->base.funcs = &dcn10_tg_funcs; 1507 1508 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1509 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1510 1511 optc1->min_h_blank = 32; 1512 optc1->min_v_blank = 3; 1513 optc1->min_v_blank_interlace = 5; 1514 optc1->min_h_sync_width = 8; 1515 optc1->min_v_sync_width = 1; 1516 optc1->comb_opp_id = 0xf; 1517 } 1518 1519 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1520 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1521 * 1522 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1523 * containter rate. 1524 * 1525 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1526 * halved to maintain the correct pixel rate. 1527 * 1528 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1529 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1530 * 1531 */ 1532 #endif 1533 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1534 { 1535 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1536 1537 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1538 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1539 && !timing->dsc_cfg.ycbcr422_simple); 1540 #endif 1541 return two_pix; 1542 } 1543 1544