1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void optc1_apply_front_porch_workaround( 50 struct timing_generator *optc, 51 struct dc_crtc_timing *timing) 52 { 53 if (timing->flags.INTERLACE == 1) { 54 if (timing->v_front_porch < 2) 55 timing->v_front_porch = 2; 56 } else { 57 if (timing->v_front_porch < 1) 58 timing->v_front_porch = 1; 59 } 60 } 61 62 void optc1_program_global_sync( 63 struct timing_generator *optc) 64 { 65 struct optc *optc1 = DCN10TG_FROM_TG(optc); 66 67 if (optc->dlg_otg_param.vstartup_start == 0) { 68 BREAK_TO_DEBUGGER(); 69 return; 70 } 71 72 REG_SET(OTG_VSTARTUP_PARAM, 0, 73 VSTARTUP_START, optc->dlg_otg_param.vstartup_start); 74 75 REG_SET_2(OTG_VUPDATE_PARAM, 0, 76 VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset, 77 VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width); 78 79 REG_SET(OTG_VREADY_PARAM, 0, 80 VREADY_OFFSET, optc->dlg_otg_param.vready_offset); 81 } 82 83 static void optc1_disable_stereo(struct timing_generator *optc) 84 { 85 struct optc *optc1 = DCN10TG_FROM_TG(optc); 86 87 REG_SET(OTG_STEREO_CONTROL, 0, 88 OTG_STEREO_EN, 0); 89 90 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 91 OTG_3D_STRUCTURE_EN, 0, 92 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 93 } 94 95 static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) 96 { 97 struct dc_crtc_timing patched_crtc_timing; 98 int vesa_sync_start; 99 int asic_blank_end; 100 int vertical_line_start; 101 102 patched_crtc_timing = *dc_crtc_timing; 103 optc1_apply_front_porch_workaround(optc, &patched_crtc_timing); 104 105 vesa_sync_start = patched_crtc_timing.h_addressable + 106 patched_crtc_timing.h_border_right + 107 patched_crtc_timing.h_front_porch; 108 109 asic_blank_end = patched_crtc_timing.h_total - 110 vesa_sync_start - 111 patched_crtc_timing.h_border_left; 112 113 vesa_sync_start = patched_crtc_timing.v_addressable + 114 patched_crtc_timing.v_border_bottom + 115 patched_crtc_timing.v_front_porch; 116 117 asic_blank_end = (patched_crtc_timing.v_total - 118 vesa_sync_start - 119 patched_crtc_timing.v_border_top); 120 121 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1; 122 if (vertical_line_start < 0) { 123 ASSERT(0); 124 vertical_line_start = 0; 125 } 126 127 return vertical_line_start; 128 } 129 130 void optc1_program_vline_interrupt( 131 struct timing_generator *optc, 132 const struct dc_crtc_timing *dc_crtc_timing, 133 unsigned long long vsync_delta) 134 { 135 136 struct optc *optc1 = DCN10TG_FROM_TG(optc); 137 138 unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000); 139 unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100); 140 uint32_t req_delta_lines = (uint32_t) div64_u64( 141 (req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1), 142 dc_crtc_timing->h_total); 143 144 uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing); 145 uint32_t start_line = 0; 146 uint32_t endLine = 0; 147 148 if (req_delta_lines != 0) 149 req_delta_lines--; 150 151 if (req_delta_lines > vsync_line) 152 start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) + 2; 153 else 154 start_line = vsync_line - req_delta_lines; 155 156 endLine = start_line + 2; 157 158 if (endLine >= dc_crtc_timing->v_total) 159 endLine = 2; 160 161 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 162 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 163 OTG_VERTICAL_INTERRUPT0_LINE_END, endLine); 164 } 165 166 /** 167 * program_timing_generator used by mode timing set 168 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 169 * Including SYNC. Call BIOS command table to program Timings. 170 */ 171 void optc1_program_timing( 172 struct timing_generator *optc, 173 const struct dc_crtc_timing *dc_crtc_timing, 174 bool use_vbios) 175 { 176 struct dc_crtc_timing patched_crtc_timing; 177 uint32_t vesa_sync_start; 178 uint32_t asic_blank_end; 179 uint32_t asic_blank_start; 180 uint32_t v_total; 181 uint32_t v_sync_end; 182 uint32_t v_init, v_fp2; 183 uint32_t h_sync_polarity, v_sync_polarity; 184 uint32_t start_point = 0; 185 uint32_t field_num = 0; 186 uint32_t h_div_2; 187 int32_t vertical_line_start; 188 189 struct optc *optc1 = DCN10TG_FROM_TG(optc); 190 191 patched_crtc_timing = *dc_crtc_timing; 192 optc1_apply_front_porch_workaround(optc, &patched_crtc_timing); 193 194 /* Load horizontal timing */ 195 196 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 197 REG_SET(OTG_H_TOTAL, 0, 198 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 199 200 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 201 REG_UPDATE_2(OTG_H_SYNC_A, 202 OTG_H_SYNC_A_START, 0, 203 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 204 205 /* asic_h_blank_end = HsyncWidth + HbackPorch = 206 * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart - 207 * vesa.h_left_border 208 */ 209 vesa_sync_start = patched_crtc_timing.h_addressable + 210 patched_crtc_timing.h_border_right + 211 patched_crtc_timing.h_front_porch; 212 213 asic_blank_end = patched_crtc_timing.h_total - 214 vesa_sync_start - 215 patched_crtc_timing.h_border_left; 216 217 /* h_blank_start = v_blank_end + v_active */ 218 asic_blank_start = asic_blank_end + 219 patched_crtc_timing.h_border_left + 220 patched_crtc_timing.h_addressable + 221 patched_crtc_timing.h_border_right; 222 223 REG_UPDATE_2(OTG_H_BLANK_START_END, 224 OTG_H_BLANK_START, asic_blank_start, 225 OTG_H_BLANK_END, asic_blank_end); 226 227 /* h_sync polarity */ 228 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 229 0 : 1; 230 231 REG_UPDATE(OTG_H_SYNC_A_CNTL, 232 OTG_H_SYNC_A_POL, h_sync_polarity); 233 234 v_total = patched_crtc_timing.v_total - 1; 235 236 REG_SET(OTG_V_TOTAL, 0, 237 OTG_V_TOTAL, v_total); 238 239 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 240 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 241 */ 242 REG_SET(OTG_V_TOTAL_MAX, 0, 243 OTG_V_TOTAL_MAX, v_total); 244 REG_SET(OTG_V_TOTAL_MIN, 0, 245 OTG_V_TOTAL_MIN, v_total); 246 247 /* v_sync_start = 0, v_sync_end = v_sync_width */ 248 v_sync_end = patched_crtc_timing.v_sync_width; 249 250 REG_UPDATE_2(OTG_V_SYNC_A, 251 OTG_V_SYNC_A_START, 0, 252 OTG_V_SYNC_A_END, v_sync_end); 253 254 vesa_sync_start = patched_crtc_timing.v_addressable + 255 patched_crtc_timing.v_border_bottom + 256 patched_crtc_timing.v_front_porch; 257 258 asic_blank_end = (patched_crtc_timing.v_total - 259 vesa_sync_start - 260 patched_crtc_timing.v_border_top); 261 262 /* v_blank_start = v_blank_end + v_active */ 263 asic_blank_start = asic_blank_end + 264 (patched_crtc_timing.v_border_top + 265 patched_crtc_timing.v_addressable + 266 patched_crtc_timing.v_border_bottom); 267 268 REG_UPDATE_2(OTG_V_BLANK_START_END, 269 OTG_V_BLANK_START, asic_blank_start, 270 OTG_V_BLANK_END, asic_blank_end); 271 272 /* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt, 273 * program the reg for interrupt postition. 274 */ 275 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1; 276 v_fp2 = 0; 277 if (vertical_line_start < 0) 278 v_fp2 = -vertical_line_start; 279 if (vertical_line_start < 0) 280 vertical_line_start = 0; 281 282 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 283 OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start); 284 285 /* v_sync polarity */ 286 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 287 0 : 1; 288 289 REG_UPDATE(OTG_V_SYNC_A_CNTL, 290 OTG_V_SYNC_A_POL, v_sync_polarity); 291 292 v_init = asic_blank_start; 293 if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT || 294 optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 295 optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) { 296 start_point = 1; 297 if (patched_crtc_timing.flags.INTERLACE == 1) 298 field_num = 1; 299 } 300 301 /* Interlace */ 302 if (patched_crtc_timing.flags.INTERLACE == 1) { 303 REG_UPDATE(OTG_INTERLACE_CONTROL, 304 OTG_INTERLACE_ENABLE, 1); 305 v_init = v_init / 2; 306 if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end) 307 v_fp2 = v_fp2 / 2; 308 } else 309 REG_UPDATE(OTG_INTERLACE_CONTROL, 310 OTG_INTERLACE_ENABLE, 0); 311 312 313 /* VTG enable set to 0 first VInit */ 314 REG_UPDATE(CONTROL, 315 VTG0_ENABLE, 0); 316 317 REG_UPDATE_2(CONTROL, 318 VTG0_FP2, v_fp2, 319 VTG0_VCOUNT_INIT, v_init); 320 321 /* original code is using VTG offset to address OTG reg, seems wrong */ 322 REG_UPDATE_2(OTG_CONTROL, 323 OTG_START_POINT_CNTL, start_point, 324 OTG_FIELD_NUMBER_CNTL, field_num); 325 326 optc1_program_global_sync(optc); 327 328 /* TODO 329 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 330 * program_horz_count_by_2 331 * for DVI 30bpp mode, 0 otherwise 332 * program_horz_count_by_2(optc, &patched_crtc_timing); 333 */ 334 335 /* Enable stereo - only when we need to pack 3D frame. Other types 336 * of stereo handled in explicit call 337 */ 338 339 h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing); 340 REG_UPDATE(OTG_H_TIMING_CNTL, 341 OTG_H_TIMING_DIV_BY2, h_div_2); 342 343 } 344 345 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 346 { 347 struct optc *optc1 = DCN10TG_FROM_TG(optc); 348 349 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 350 351 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 352 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 353 } 354 355 /** 356 * unblank_crtc 357 * Call ASIC Control Object to UnBlank CRTC. 358 */ 359 static void optc1_unblank_crtc(struct timing_generator *optc) 360 { 361 struct optc *optc1 = DCN10TG_FROM_TG(optc); 362 363 REG_UPDATE_2(OTG_BLANK_CONTROL, 364 OTG_BLANK_DATA_EN, 0, 365 OTG_BLANK_DE_MODE, 0); 366 367 /* W/A for automated testing 368 * Automated testing will fail underflow test as there 369 * sporadic underflows which occur during the optc blank 370 * sequence. As a w/a, clear underflow on unblank. 371 * This prevents the failure, but will not mask actual 372 * underflow that affect real use cases. 373 */ 374 optc1_clear_optc_underflow(optc); 375 } 376 377 /** 378 * blank_crtc 379 * Call ASIC Control Object to Blank CRTC. 380 */ 381 382 static void optc1_blank_crtc(struct timing_generator *optc) 383 { 384 struct optc *optc1 = DCN10TG_FROM_TG(optc); 385 386 REG_UPDATE_2(OTG_BLANK_CONTROL, 387 OTG_BLANK_DATA_EN, 1, 388 OTG_BLANK_DE_MODE, 0); 389 390 optc1_set_blank_data_double_buffer(optc, false); 391 } 392 393 void optc1_set_blank(struct timing_generator *optc, 394 bool enable_blanking) 395 { 396 if (enable_blanking) 397 optc1_blank_crtc(optc); 398 else 399 optc1_unblank_crtc(optc); 400 } 401 402 bool optc1_is_blanked(struct timing_generator *optc) 403 { 404 struct optc *optc1 = DCN10TG_FROM_TG(optc); 405 uint32_t blank_en; 406 uint32_t blank_state; 407 408 REG_GET_2(OTG_BLANK_CONTROL, 409 OTG_BLANK_DATA_EN, &blank_en, 410 OTG_CURRENT_BLANK_STATE, &blank_state); 411 412 return blank_en && blank_state; 413 } 414 415 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 416 { 417 struct optc *optc1 = DCN10TG_FROM_TG(optc); 418 419 if (enable) { 420 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 421 OPTC_INPUT_CLK_EN, 1, 422 OPTC_INPUT_CLK_GATE_DIS, 1); 423 424 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 425 OPTC_INPUT_CLK_ON, 1, 426 1, 1000); 427 428 /* Enable clock */ 429 REG_UPDATE_2(OTG_CLOCK_CONTROL, 430 OTG_CLOCK_EN, 1, 431 OTG_CLOCK_GATE_DIS, 1); 432 REG_WAIT(OTG_CLOCK_CONTROL, 433 OTG_CLOCK_ON, 1, 434 1, 1000); 435 } else { 436 REG_UPDATE_2(OTG_CLOCK_CONTROL, 437 OTG_CLOCK_GATE_DIS, 0, 438 OTG_CLOCK_EN, 0); 439 440 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 441 OPTC_INPUT_CLK_GATE_DIS, 0, 442 OPTC_INPUT_CLK_EN, 0); 443 } 444 } 445 446 /** 447 * Enable CRTC 448 * Enable CRTC - call ASIC Control Object to enable Timing generator. 449 */ 450 static bool optc1_enable_crtc(struct timing_generator *optc) 451 { 452 /* TODO FPGA wait for answer 453 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 454 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 455 */ 456 struct optc *optc1 = DCN10TG_FROM_TG(optc); 457 458 /* opp instance for OTG. For DCN1.0, ODM is remoed. 459 * OPP and OPTC should 1:1 mapping 460 */ 461 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 462 OPTC_SRC_SEL, optc->inst); 463 464 /* VTG enable first is for HW workaround */ 465 REG_UPDATE(CONTROL, 466 VTG0_ENABLE, 1); 467 468 /* Enable CRTC */ 469 REG_UPDATE_2(OTG_CONTROL, 470 OTG_DISABLE_POINT_CNTL, 3, 471 OTG_MASTER_EN, 1); 472 473 return true; 474 } 475 476 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 477 bool optc1_disable_crtc(struct timing_generator *optc) 478 { 479 struct optc *optc1 = DCN10TG_FROM_TG(optc); 480 481 /* disable otg request until end of the first line 482 * in the vertical blank region 483 */ 484 REG_UPDATE_2(OTG_CONTROL, 485 OTG_DISABLE_POINT_CNTL, 3, 486 OTG_MASTER_EN, 0); 487 488 REG_UPDATE(CONTROL, 489 VTG0_ENABLE, 0); 490 491 /* CRTC disabled, so disable clock. */ 492 REG_WAIT(OTG_CLOCK_CONTROL, 493 OTG_BUSY, 0, 494 1, 100000); 495 496 return true; 497 } 498 499 500 void optc1_program_blank_color( 501 struct timing_generator *optc, 502 const struct tg_color *black_color) 503 { 504 struct optc *optc1 = DCN10TG_FROM_TG(optc); 505 506 REG_SET_3(OTG_BLACK_COLOR, 0, 507 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 508 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 509 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 510 } 511 512 bool optc1_validate_timing( 513 struct timing_generator *optc, 514 const struct dc_crtc_timing *timing) 515 { 516 uint32_t v_blank; 517 uint32_t h_blank; 518 uint32_t min_v_blank; 519 struct optc *optc1 = DCN10TG_FROM_TG(optc); 520 521 ASSERT(timing != NULL); 522 523 v_blank = (timing->v_total - timing->v_addressable - 524 timing->v_border_top - timing->v_border_bottom); 525 526 h_blank = (timing->h_total - timing->h_addressable - 527 timing->h_border_right - 528 timing->h_border_left); 529 530 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 531 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 532 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 533 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 534 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 535 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 536 return false; 537 538 /* Temporarily blocking interlacing mode until it's supported */ 539 if (timing->flags.INTERLACE == 1) 540 return false; 541 542 /* Check maximum number of pixels supported by Timing Generator 543 * (Currently will never fail, in order to fail needs display which 544 * needs more than 8192 horizontal and 545 * more than 8192 vertical total pixels) 546 */ 547 if (timing->h_total > optc1->max_h_total || 548 timing->v_total > optc1->max_v_total) 549 return false; 550 551 552 if (h_blank < optc1->min_h_blank) 553 return false; 554 555 if (timing->h_sync_width < optc1->min_h_sync_width || 556 timing->v_sync_width < optc1->min_v_sync_width) 557 return false; 558 559 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 560 561 if (v_blank < min_v_blank) 562 return false; 563 564 return true; 565 566 } 567 568 /* 569 * get_vblank_counter 570 * 571 * @brief 572 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 573 * holds the counter of frames. 574 * 575 * @param 576 * struct timing_generator *optc - [in] timing generator which controls the 577 * desired CRTC 578 * 579 * @return 580 * Counter of frames, which should equal to number of vblanks. 581 */ 582 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 583 { 584 struct optc *optc1 = DCN10TG_FROM_TG(optc); 585 uint32_t frame_count; 586 587 REG_GET(OTG_STATUS_FRAME_COUNT, 588 OTG_FRAME_COUNT, &frame_count); 589 590 return frame_count; 591 } 592 593 void optc1_lock(struct timing_generator *optc) 594 { 595 struct optc *optc1 = DCN10TG_FROM_TG(optc); 596 597 REG_SET(OTG_GLOBAL_CONTROL0, 0, 598 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 599 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 600 OTG_MASTER_UPDATE_LOCK, 1); 601 602 /* Should be fast, status does not update on maximus */ 603 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 604 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 605 UPDATE_LOCK_STATUS, 1, 606 1, 10); 607 } 608 609 void optc1_unlock(struct timing_generator *optc) 610 { 611 struct optc *optc1 = DCN10TG_FROM_TG(optc); 612 613 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 614 OTG_MASTER_UPDATE_LOCK, 0); 615 } 616 617 void optc1_get_position(struct timing_generator *optc, 618 struct crtc_position *position) 619 { 620 struct optc *optc1 = DCN10TG_FROM_TG(optc); 621 622 REG_GET_2(OTG_STATUS_POSITION, 623 OTG_HORZ_COUNT, &position->horizontal_count, 624 OTG_VERT_COUNT, &position->vertical_count); 625 626 REG_GET(OTG_NOM_VERT_POSITION, 627 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 628 } 629 630 bool optc1_is_counter_moving(struct timing_generator *optc) 631 { 632 struct crtc_position position1, position2; 633 634 optc->funcs->get_position(optc, &position1); 635 optc->funcs->get_position(optc, &position2); 636 637 if (position1.horizontal_count == position2.horizontal_count && 638 position1.vertical_count == position2.vertical_count) 639 return false; 640 else 641 return true; 642 } 643 644 bool optc1_did_triggered_reset_occur( 645 struct timing_generator *optc) 646 { 647 struct optc *optc1 = DCN10TG_FROM_TG(optc); 648 uint32_t occurred_force, occurred_vsync; 649 650 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 651 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 652 653 REG_GET(OTG_VERT_SYNC_CONTROL, 654 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 655 656 return occurred_vsync != 0 || occurred_force != 0; 657 } 658 659 void optc1_disable_reset_trigger(struct timing_generator *optc) 660 { 661 struct optc *optc1 = DCN10TG_FROM_TG(optc); 662 663 REG_WRITE(OTG_TRIGA_CNTL, 0); 664 665 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 666 OTG_FORCE_COUNT_NOW_CLEAR, 1); 667 668 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 669 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 670 } 671 672 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 673 { 674 struct optc *optc1 = DCN10TG_FROM_TG(optc); 675 uint32_t falling_edge; 676 677 REG_GET(OTG_V_SYNC_A_CNTL, 678 OTG_V_SYNC_A_POL, &falling_edge); 679 680 if (falling_edge) 681 REG_SET_3(OTG_TRIGA_CNTL, 0, 682 /* vsync signal from selected OTG pipe based 683 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 684 */ 685 OTG_TRIGA_SOURCE_SELECT, 20, 686 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 687 /* always detect falling edge */ 688 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 689 else 690 REG_SET_3(OTG_TRIGA_CNTL, 0, 691 /* vsync signal from selected OTG pipe based 692 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 693 */ 694 OTG_TRIGA_SOURCE_SELECT, 20, 695 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 696 /* always detect rising edge */ 697 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 698 699 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 700 /* force H count to H_TOTAL and V count to V_TOTAL in 701 * progressive mode and V_TOTAL-1 in interlaced mode 702 */ 703 OTG_FORCE_COUNT_NOW_MODE, 2); 704 } 705 706 void optc1_enable_crtc_reset( 707 struct timing_generator *optc, 708 int source_tg_inst, 709 struct crtc_trigger_info *crtc_tp) 710 { 711 struct optc *optc1 = DCN10TG_FROM_TG(optc); 712 uint32_t falling_edge = 0; 713 uint32_t rising_edge = 0; 714 715 switch (crtc_tp->event) { 716 717 case CRTC_EVENT_VSYNC_RISING: 718 rising_edge = 1; 719 break; 720 721 case CRTC_EVENT_VSYNC_FALLING: 722 falling_edge = 1; 723 break; 724 } 725 726 REG_SET_4(OTG_TRIGA_CNTL, 0, 727 /* vsync signal from selected OTG pipe based 728 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 729 */ 730 OTG_TRIGA_SOURCE_SELECT, 20, 731 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 732 /* always detect falling edge */ 733 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 734 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 735 736 switch (crtc_tp->delay) { 737 case TRIGGER_DELAY_NEXT_LINE: 738 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 739 OTG_AUTO_FORCE_VSYNC_MODE, 1); 740 break; 741 case TRIGGER_DELAY_NEXT_PIXEL: 742 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 743 /* force H count to H_TOTAL and V count to V_TOTAL in 744 * progressive mode and V_TOTAL-1 in interlaced mode 745 */ 746 OTG_FORCE_COUNT_NOW_MODE, 2); 747 break; 748 } 749 } 750 751 void optc1_wait_for_state(struct timing_generator *optc, 752 enum crtc_state state) 753 { 754 struct optc *optc1 = DCN10TG_FROM_TG(optc); 755 756 switch (state) { 757 case CRTC_STATE_VBLANK: 758 REG_WAIT(OTG_STATUS, 759 OTG_V_BLANK, 1, 760 1, 100000); /* 1 vupdate at 10hz */ 761 break; 762 763 case CRTC_STATE_VACTIVE: 764 REG_WAIT(OTG_STATUS, 765 OTG_V_ACTIVE_DISP, 1, 766 1, 100000); /* 1 vupdate at 10hz */ 767 break; 768 769 default: 770 break; 771 } 772 } 773 774 void optc1_set_early_control( 775 struct timing_generator *optc, 776 uint32_t early_cntl) 777 { 778 /* asic design change, do not need this control 779 * empty for share caller logic 780 */ 781 } 782 783 784 void optc1_set_static_screen_control( 785 struct timing_generator *optc, 786 uint32_t value) 787 { 788 struct optc *optc1 = DCN10TG_FROM_TG(optc); 789 790 /* Bit 8 is no longer applicable in RV for PSR case, 791 * set bit 8 to 0 if given 792 */ 793 if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 794 != 0) 795 value = value & 796 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 797 798 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 799 OTG_STATIC_SCREEN_EVENT_MASK, value, 800 OTG_STATIC_SCREEN_FRAME_COUNT, 2); 801 } 802 803 804 /** 805 ***************************************************************************** 806 * Function: set_drr 807 * 808 * @brief 809 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 810 * 811 ***************************************************************************** 812 */ 813 void optc1_set_drr( 814 struct timing_generator *optc, 815 const struct drr_params *params) 816 { 817 struct optc *optc1 = DCN10TG_FROM_TG(optc); 818 819 if (params != NULL && 820 params->vertical_total_max > 0 && 821 params->vertical_total_min > 0) { 822 823 REG_SET(OTG_V_TOTAL_MAX, 0, 824 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 825 826 REG_SET(OTG_V_TOTAL_MIN, 0, 827 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 828 829 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 830 OTG_V_TOTAL_MIN_SEL, 1, 831 OTG_V_TOTAL_MAX_SEL, 1, 832 OTG_FORCE_LOCK_ON_EVENT, 0, 833 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 834 OTG_SET_V_TOTAL_MIN_MASK, 0); 835 } else { 836 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 837 OTG_SET_V_TOTAL_MIN_MASK, 0, 838 OTG_V_TOTAL_MIN_SEL, 0, 839 OTG_V_TOTAL_MAX_SEL, 0, 840 OTG_FORCE_LOCK_ON_EVENT, 0); 841 842 REG_SET(OTG_V_TOTAL_MIN, 0, 843 OTG_V_TOTAL_MIN, 0); 844 845 REG_SET(OTG_V_TOTAL_MAX, 0, 846 OTG_V_TOTAL_MAX, 0); 847 } 848 } 849 850 static void optc1_set_test_pattern( 851 struct timing_generator *optc, 852 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 853 * because this is not DP-specific (which is probably somewhere in DP 854 * encoder) */ 855 enum controller_dp_test_pattern test_pattern, 856 enum dc_color_depth color_depth) 857 { 858 struct optc *optc1 = DCN10TG_FROM_TG(optc); 859 enum test_pattern_color_format bit_depth; 860 enum test_pattern_dyn_range dyn_range; 861 enum test_pattern_mode mode; 862 uint32_t pattern_mask; 863 uint32_t pattern_data; 864 /* color ramp generator mixes 16-bits color */ 865 uint32_t src_bpc = 16; 866 /* requested bpc */ 867 uint32_t dst_bpc; 868 uint32_t index; 869 /* RGB values of the color bars. 870 * Produce two RGB colors: RGB0 - white (all Fs) 871 * and RGB1 - black (all 0s) 872 * (three RGB components for two colors) 873 */ 874 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 875 0x0000, 0x0000}; 876 /* dest color (converted to the specified color format) */ 877 uint16_t dst_color[6]; 878 uint32_t inc_base; 879 880 /* translate to bit depth */ 881 switch (color_depth) { 882 case COLOR_DEPTH_666: 883 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 884 break; 885 case COLOR_DEPTH_888: 886 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 887 break; 888 case COLOR_DEPTH_101010: 889 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 890 break; 891 case COLOR_DEPTH_121212: 892 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 893 break; 894 default: 895 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 896 break; 897 } 898 899 switch (test_pattern) { 900 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 901 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 902 { 903 dyn_range = (test_pattern == 904 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 905 TEST_PATTERN_DYN_RANGE_CEA : 906 TEST_PATTERN_DYN_RANGE_VESA); 907 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 908 909 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 910 OTG_TEST_PATTERN_VRES, 6, 911 OTG_TEST_PATTERN_HRES, 6); 912 913 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 914 OTG_TEST_PATTERN_EN, 1, 915 OTG_TEST_PATTERN_MODE, mode, 916 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 917 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 918 } 919 break; 920 921 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 922 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 923 { 924 mode = (test_pattern == 925 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 926 TEST_PATTERN_MODE_VERTICALBARS : 927 TEST_PATTERN_MODE_HORIZONTALBARS); 928 929 switch (bit_depth) { 930 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 931 dst_bpc = 6; 932 break; 933 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 934 dst_bpc = 8; 935 break; 936 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 937 dst_bpc = 10; 938 break; 939 default: 940 dst_bpc = 8; 941 break; 942 } 943 944 /* adjust color to the required colorFormat */ 945 for (index = 0; index < 6; index++) { 946 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 947 * (srcBpc - dstBpc); 948 */ 949 dst_color[index] = 950 src_color[index] >> (src_bpc - dst_bpc); 951 /* CRTC_TEST_PATTERN_DATA has 16 bits, 952 * lowest 6 are hardwired to ZERO 953 * color bits should be left aligned aligned to MSB 954 * XXXXXXXXXX000000 for 10 bit, 955 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 956 */ 957 dst_color[index] <<= (16 - dst_bpc); 958 } 959 960 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 961 962 /* We have to write the mask before data, similar to pipeline. 963 * For example, for 8 bpc, if we want RGB0 to be magenta, 964 * and RGB1 to be cyan, 965 * we need to make 7 writes: 966 * MASK DATA 967 * 000001 00000000 00000000 set mask to R0 968 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 969 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 970 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 971 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 972 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 973 * 100000 11111111 00000000 B1 255, 0xFF00 974 * 975 * we will make a loop of 6 in which we prepare the mask, 976 * then write, then prepare the color for next write. 977 * first iteration will write mask only, 978 * but each next iteration color prepared in 979 * previous iteration will be written within new mask, 980 * the last component will written separately, 981 * mask is not changing between 6th and 7th write 982 * and color will be prepared by last iteration 983 */ 984 985 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 986 * is B1, G1, R1, B0, G0, R0 987 */ 988 pattern_data = 0; 989 for (index = 0; index < 6; index++) { 990 /* prepare color mask, first write PATTERN_DATA 991 * will have all zeros 992 */ 993 pattern_mask = (1 << index); 994 995 /* write color component */ 996 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 997 OTG_TEST_PATTERN_MASK, pattern_mask, 998 OTG_TEST_PATTERN_DATA, pattern_data); 999 1000 /* prepare next color component, 1001 * will be written in the next iteration 1002 */ 1003 pattern_data = dst_color[index]; 1004 } 1005 /* write last color component, 1006 * it's been already prepared in the loop 1007 */ 1008 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1009 OTG_TEST_PATTERN_MASK, pattern_mask, 1010 OTG_TEST_PATTERN_DATA, pattern_data); 1011 1012 /* enable test pattern */ 1013 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1014 OTG_TEST_PATTERN_EN, 1, 1015 OTG_TEST_PATTERN_MODE, mode, 1016 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1017 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1018 } 1019 break; 1020 1021 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1022 { 1023 mode = (bit_depth == 1024 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1025 TEST_PATTERN_MODE_DUALRAMP_RGB : 1026 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1027 1028 switch (bit_depth) { 1029 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1030 dst_bpc = 6; 1031 break; 1032 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1033 dst_bpc = 8; 1034 break; 1035 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1036 dst_bpc = 10; 1037 break; 1038 default: 1039 dst_bpc = 8; 1040 break; 1041 } 1042 1043 /* increment for the first ramp for one color gradation 1044 * 1 gradation for 6-bit color is 2^10 1045 * gradations in 16-bit color 1046 */ 1047 inc_base = (src_bpc - dst_bpc); 1048 1049 switch (bit_depth) { 1050 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1051 { 1052 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1053 OTG_TEST_PATTERN_INC0, inc_base, 1054 OTG_TEST_PATTERN_INC1, 0, 1055 OTG_TEST_PATTERN_HRES, 6, 1056 OTG_TEST_PATTERN_VRES, 6, 1057 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1058 } 1059 break; 1060 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1061 { 1062 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1063 OTG_TEST_PATTERN_INC0, inc_base, 1064 OTG_TEST_PATTERN_INC1, 0, 1065 OTG_TEST_PATTERN_HRES, 8, 1066 OTG_TEST_PATTERN_VRES, 6, 1067 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1068 } 1069 break; 1070 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1071 { 1072 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1073 OTG_TEST_PATTERN_INC0, inc_base, 1074 OTG_TEST_PATTERN_INC1, inc_base + 2, 1075 OTG_TEST_PATTERN_HRES, 8, 1076 OTG_TEST_PATTERN_VRES, 5, 1077 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1078 } 1079 break; 1080 default: 1081 break; 1082 } 1083 1084 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1085 1086 /* enable test pattern */ 1087 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1088 1089 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1090 OTG_TEST_PATTERN_EN, 1, 1091 OTG_TEST_PATTERN_MODE, mode, 1092 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1093 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1094 } 1095 break; 1096 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1097 { 1098 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1099 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1100 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1101 } 1102 break; 1103 default: 1104 break; 1105 1106 } 1107 } 1108 1109 void optc1_get_crtc_scanoutpos( 1110 struct timing_generator *optc, 1111 uint32_t *v_blank_start, 1112 uint32_t *v_blank_end, 1113 uint32_t *h_position, 1114 uint32_t *v_position) 1115 { 1116 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1117 struct crtc_position position; 1118 1119 REG_GET_2(OTG_V_BLANK_START_END, 1120 OTG_V_BLANK_START, v_blank_start, 1121 OTG_V_BLANK_END, v_blank_end); 1122 1123 optc1_get_position(optc, &position); 1124 1125 *h_position = position.horizontal_count; 1126 *v_position = position.vertical_count; 1127 } 1128 1129 static void optc1_enable_stereo(struct timing_generator *optc, 1130 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1131 { 1132 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1133 1134 if (flags) { 1135 uint32_t stereo_en; 1136 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1137 1138 if (flags->PROGRAM_STEREO) 1139 REG_UPDATE_3(OTG_STEREO_CONTROL, 1140 OTG_STEREO_EN, stereo_en, 1141 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1142 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0); 1143 1144 if (flags->PROGRAM_POLARITY) 1145 REG_UPDATE(OTG_STEREO_CONTROL, 1146 OTG_STEREO_EYE_FLAG_POLARITY, 1147 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1148 1149 if (flags->DISABLE_STEREO_DP_SYNC) 1150 REG_UPDATE(OTG_STEREO_CONTROL, 1151 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1152 1153 if (flags->PROGRAM_STEREO) 1154 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1155 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1156 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1157 1158 } 1159 } 1160 1161 void optc1_program_stereo(struct timing_generator *optc, 1162 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1163 { 1164 if (flags->PROGRAM_STEREO) 1165 optc1_enable_stereo(optc, timing, flags); 1166 else 1167 optc1_disable_stereo(optc); 1168 } 1169 1170 1171 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1172 { 1173 bool ret = false; 1174 uint32_t left_eye = 0; 1175 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1176 1177 REG_GET(OTG_STEREO_STATUS, 1178 OTG_STEREO_CURRENT_EYE, &left_eye); 1179 if (left_eye == 1) 1180 ret = true; 1181 else 1182 ret = false; 1183 1184 return ret; 1185 } 1186 1187 void optc1_read_otg_state(struct optc *optc1, 1188 struct dcn_otg_state *s) 1189 { 1190 REG_GET(OTG_CONTROL, 1191 OTG_MASTER_EN, &s->otg_enabled); 1192 1193 REG_GET_2(OTG_V_BLANK_START_END, 1194 OTG_V_BLANK_START, &s->v_blank_start, 1195 OTG_V_BLANK_END, &s->v_blank_end); 1196 1197 REG_GET(OTG_V_SYNC_A_CNTL, 1198 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1199 1200 REG_GET(OTG_V_TOTAL, 1201 OTG_V_TOTAL, &s->v_total); 1202 1203 REG_GET(OTG_V_TOTAL_MAX, 1204 OTG_V_TOTAL_MAX, &s->v_total_max); 1205 1206 REG_GET(OTG_V_TOTAL_MIN, 1207 OTG_V_TOTAL_MIN, &s->v_total_min); 1208 1209 REG_GET(OTG_V_TOTAL_CONTROL, 1210 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1211 1212 REG_GET(OTG_V_TOTAL_CONTROL, 1213 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1214 1215 REG_GET_2(OTG_V_SYNC_A, 1216 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1217 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1218 1219 REG_GET_2(OTG_H_BLANK_START_END, 1220 OTG_H_BLANK_START, &s->h_blank_start, 1221 OTG_H_BLANK_END, &s->h_blank_end); 1222 1223 REG_GET_2(OTG_H_SYNC_A, 1224 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1225 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1226 1227 REG_GET(OTG_H_SYNC_A_CNTL, 1228 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1229 1230 REG_GET(OTG_H_TOTAL, 1231 OTG_H_TOTAL, &s->h_total); 1232 1233 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1234 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1235 } 1236 1237 bool optc1_get_otg_active_size(struct timing_generator *optc, 1238 uint32_t *otg_active_width, 1239 uint32_t *otg_active_height) 1240 { 1241 uint32_t otg_enabled; 1242 uint32_t v_blank_start; 1243 uint32_t v_blank_end; 1244 uint32_t h_blank_start; 1245 uint32_t h_blank_end; 1246 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1247 1248 1249 REG_GET(OTG_CONTROL, 1250 OTG_MASTER_EN, &otg_enabled); 1251 1252 if (otg_enabled == 0) 1253 return false; 1254 1255 REG_GET_2(OTG_V_BLANK_START_END, 1256 OTG_V_BLANK_START, &v_blank_start, 1257 OTG_V_BLANK_END, &v_blank_end); 1258 1259 REG_GET_2(OTG_H_BLANK_START_END, 1260 OTG_H_BLANK_START, &h_blank_start, 1261 OTG_H_BLANK_END, &h_blank_end); 1262 1263 *otg_active_width = v_blank_start - v_blank_end; 1264 *otg_active_height = h_blank_start - h_blank_end; 1265 return true; 1266 } 1267 1268 void optc1_clear_optc_underflow(struct timing_generator *optc) 1269 { 1270 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1271 1272 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1273 } 1274 1275 void optc1_tg_init(struct timing_generator *optc) 1276 { 1277 optc1_set_blank_data_double_buffer(optc, true); 1278 optc1_clear_optc_underflow(optc); 1279 } 1280 1281 bool optc1_is_tg_enabled(struct timing_generator *optc) 1282 { 1283 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1284 uint32_t otg_enabled = 0; 1285 1286 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1287 1288 return (otg_enabled != 0); 1289 1290 } 1291 1292 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1293 { 1294 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1295 uint32_t underflow_occurred = 0; 1296 1297 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1298 OPTC_UNDERFLOW_OCCURRED_STATUS, 1299 &underflow_occurred); 1300 1301 return (underflow_occurred == 1); 1302 } 1303 1304 bool optc1_configure_crc(struct timing_generator *optc, 1305 const struct crc_params *params) 1306 { 1307 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1308 1309 /* Cannot configure crc on a CRTC that is disabled */ 1310 if (!optc1_is_tg_enabled(optc)) 1311 return false; 1312 1313 REG_WRITE(OTG_CRC_CNTL, 0); 1314 1315 if (!params->enable) 1316 return true; 1317 1318 /* Program frame boundaries */ 1319 /* Window A x axis start and end. */ 1320 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1321 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1322 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1323 1324 /* Window A y axis start and end. */ 1325 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1326 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1327 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1328 1329 /* Window B x axis start and end. */ 1330 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1331 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1332 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1333 1334 /* Window B y axis start and end. */ 1335 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1336 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1337 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1338 1339 /* Set crc mode and selection, and enable. Only using CRC0*/ 1340 REG_UPDATE_3(OTG_CRC_CNTL, 1341 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1342 OTG_CRC0_SELECT, params->selection, 1343 OTG_CRC_EN, 1); 1344 1345 return true; 1346 } 1347 1348 bool optc1_get_crc(struct timing_generator *optc, 1349 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1350 { 1351 uint32_t field = 0; 1352 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1353 1354 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1355 1356 /* Early return if CRC is not enabled for this CRTC */ 1357 if (!field) 1358 return false; 1359 1360 REG_GET_2(OTG_CRC0_DATA_RG, 1361 CRC0_R_CR, r_cr, 1362 CRC0_G_Y, g_y); 1363 1364 REG_GET(OTG_CRC0_DATA_B, 1365 CRC0_B_CB, b_cb); 1366 1367 return true; 1368 } 1369 1370 static const struct timing_generator_funcs dcn10_tg_funcs = { 1371 .validate_timing = optc1_validate_timing, 1372 .program_timing = optc1_program_timing, 1373 .program_vline_interrupt = optc1_program_vline_interrupt, 1374 .program_global_sync = optc1_program_global_sync, 1375 .enable_crtc = optc1_enable_crtc, 1376 .disable_crtc = optc1_disable_crtc, 1377 /* used by enable_timing_synchronization. Not need for FPGA */ 1378 .is_counter_moving = optc1_is_counter_moving, 1379 .get_position = optc1_get_position, 1380 .get_frame_count = optc1_get_vblank_counter, 1381 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1382 .get_otg_active_size = optc1_get_otg_active_size, 1383 .set_early_control = optc1_set_early_control, 1384 /* used by enable_timing_synchronization. Not need for FPGA */ 1385 .wait_for_state = optc1_wait_for_state, 1386 .set_blank = optc1_set_blank, 1387 .is_blanked = optc1_is_blanked, 1388 .set_blank_color = optc1_program_blank_color, 1389 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1390 .enable_reset_trigger = optc1_enable_reset_trigger, 1391 .enable_crtc_reset = optc1_enable_crtc_reset, 1392 .disable_reset_trigger = optc1_disable_reset_trigger, 1393 .lock = optc1_lock, 1394 .unlock = optc1_unlock, 1395 .enable_optc_clock = optc1_enable_optc_clock, 1396 .set_drr = optc1_set_drr, 1397 .set_static_screen_control = optc1_set_static_screen_control, 1398 .set_test_pattern = optc1_set_test_pattern, 1399 .program_stereo = optc1_program_stereo, 1400 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1401 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1402 .tg_init = optc1_tg_init, 1403 .is_tg_enabled = optc1_is_tg_enabled, 1404 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1405 .clear_optc_underflow = optc1_clear_optc_underflow, 1406 .get_crc = optc1_get_crc, 1407 .configure_crc = optc1_configure_crc, 1408 }; 1409 1410 void dcn10_timing_generator_init(struct optc *optc1) 1411 { 1412 optc1->base.funcs = &dcn10_tg_funcs; 1413 1414 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1415 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1416 1417 optc1->min_h_blank = 32; 1418 optc1->min_v_blank = 3; 1419 optc1->min_v_blank_interlace = 5; 1420 optc1->min_h_sync_width = 8; 1421 optc1->min_v_sync_width = 1; 1422 } 1423 1424 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1425 { 1426 return timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1427 } 1428 1429