1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void optc1_apply_front_porch_workaround( 50 struct timing_generator *optc, 51 struct dc_crtc_timing *timing) 52 { 53 if (timing->flags.INTERLACE == 1) { 54 if (timing->v_front_porch < 2) 55 timing->v_front_porch = 2; 56 } else { 57 if (timing->v_front_porch < 1) 58 timing->v_front_porch = 1; 59 } 60 } 61 62 void optc1_program_global_sync( 63 struct timing_generator *optc) 64 { 65 struct optc *optc1 = DCN10TG_FROM_TG(optc); 66 67 if (optc->dlg_otg_param.vstartup_start == 0) { 68 BREAK_TO_DEBUGGER(); 69 return; 70 } 71 72 REG_SET(OTG_VSTARTUP_PARAM, 0, 73 VSTARTUP_START, optc->dlg_otg_param.vstartup_start); 74 75 REG_SET_2(OTG_VUPDATE_PARAM, 0, 76 VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset, 77 VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width); 78 79 REG_SET(OTG_VREADY_PARAM, 0, 80 VREADY_OFFSET, optc->dlg_otg_param.vready_offset); 81 } 82 83 static void optc1_disable_stereo(struct timing_generator *optc) 84 { 85 struct optc *optc1 = DCN10TG_FROM_TG(optc); 86 87 REG_SET(OTG_STEREO_CONTROL, 0, 88 OTG_STEREO_EN, 0); 89 90 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 91 OTG_3D_STRUCTURE_EN, 0, 92 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 93 } 94 95 static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) 96 { 97 struct dc_crtc_timing patched_crtc_timing; 98 int vesa_sync_start; 99 int asic_blank_end; 100 int vertical_line_start; 101 102 patched_crtc_timing = *dc_crtc_timing; 103 optc1_apply_front_porch_workaround(optc, &patched_crtc_timing); 104 105 vesa_sync_start = patched_crtc_timing.h_addressable + 106 patched_crtc_timing.h_border_right + 107 patched_crtc_timing.h_front_porch; 108 109 asic_blank_end = patched_crtc_timing.h_total - 110 vesa_sync_start - 111 patched_crtc_timing.h_border_left; 112 113 vesa_sync_start = patched_crtc_timing.v_addressable + 114 patched_crtc_timing.v_border_bottom + 115 patched_crtc_timing.v_front_porch; 116 117 asic_blank_end = (patched_crtc_timing.v_total - 118 vesa_sync_start - 119 patched_crtc_timing.v_border_top); 120 121 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1; 122 if (vertical_line_start < 0) { 123 ASSERT(0); 124 vertical_line_start = 0; 125 } 126 127 return vertical_line_start; 128 } 129 130 void optc1_program_vline_interrupt( 131 struct timing_generator *optc, 132 const struct dc_crtc_timing *dc_crtc_timing, 133 unsigned long long vsync_delta) 134 { 135 136 struct optc *optc1 = DCN10TG_FROM_TG(optc); 137 138 unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000); 139 unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100); 140 uint32_t req_delta_lines = (uint32_t) div64_u64( 141 (req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1), 142 dc_crtc_timing->h_total); 143 144 uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing); 145 uint32_t start_line = 0; 146 uint32_t endLine = 0; 147 148 if (req_delta_lines != 0) 149 req_delta_lines--; 150 151 if (req_delta_lines > vsync_line) 152 start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) + 2; 153 else 154 start_line = vsync_line - req_delta_lines; 155 156 endLine = start_line + 2; 157 158 if (endLine >= dc_crtc_timing->v_total) 159 endLine = 2; 160 161 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 162 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 163 OTG_VERTICAL_INTERRUPT0_LINE_END, endLine); 164 } 165 166 /** 167 * program_timing_generator used by mode timing set 168 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 169 * Including SYNC. Call BIOS command table to program Timings. 170 */ 171 void optc1_program_timing( 172 struct timing_generator *optc, 173 const struct dc_crtc_timing *dc_crtc_timing, 174 bool use_vbios) 175 { 176 struct dc_crtc_timing patched_crtc_timing; 177 uint32_t vesa_sync_start; 178 uint32_t asic_blank_end; 179 uint32_t asic_blank_start; 180 uint32_t v_total; 181 uint32_t v_sync_end; 182 uint32_t v_init, v_fp2; 183 uint32_t h_sync_polarity, v_sync_polarity; 184 uint32_t start_point = 0; 185 uint32_t field_num = 0; 186 uint32_t h_div_2; 187 int32_t vertical_line_start; 188 189 struct optc *optc1 = DCN10TG_FROM_TG(optc); 190 191 patched_crtc_timing = *dc_crtc_timing; 192 optc1_apply_front_porch_workaround(optc, &patched_crtc_timing); 193 194 /* Load horizontal timing */ 195 196 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 197 REG_SET(OTG_H_TOTAL, 0, 198 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 199 200 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 201 REG_UPDATE_2(OTG_H_SYNC_A, 202 OTG_H_SYNC_A_START, 0, 203 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 204 205 /* asic_h_blank_end = HsyncWidth + HbackPorch = 206 * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart - 207 * vesa.h_left_border 208 */ 209 vesa_sync_start = patched_crtc_timing.h_addressable + 210 patched_crtc_timing.h_border_right + 211 patched_crtc_timing.h_front_porch; 212 213 asic_blank_end = patched_crtc_timing.h_total - 214 vesa_sync_start - 215 patched_crtc_timing.h_border_left; 216 217 /* h_blank_start = v_blank_end + v_active */ 218 asic_blank_start = asic_blank_end + 219 patched_crtc_timing.h_border_left + 220 patched_crtc_timing.h_addressable + 221 patched_crtc_timing.h_border_right; 222 223 REG_UPDATE_2(OTG_H_BLANK_START_END, 224 OTG_H_BLANK_START, asic_blank_start, 225 OTG_H_BLANK_END, asic_blank_end); 226 227 /* h_sync polarity */ 228 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 229 0 : 1; 230 231 REG_UPDATE(OTG_H_SYNC_A_CNTL, 232 OTG_H_SYNC_A_POL, h_sync_polarity); 233 234 v_total = patched_crtc_timing.v_total - 1; 235 236 REG_SET(OTG_V_TOTAL, 0, 237 OTG_V_TOTAL, v_total); 238 239 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 240 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 241 */ 242 REG_SET(OTG_V_TOTAL_MAX, 0, 243 OTG_V_TOTAL_MAX, v_total); 244 REG_SET(OTG_V_TOTAL_MIN, 0, 245 OTG_V_TOTAL_MIN, v_total); 246 247 /* v_sync_start = 0, v_sync_end = v_sync_width */ 248 v_sync_end = patched_crtc_timing.v_sync_width; 249 250 REG_UPDATE_2(OTG_V_SYNC_A, 251 OTG_V_SYNC_A_START, 0, 252 OTG_V_SYNC_A_END, v_sync_end); 253 254 vesa_sync_start = patched_crtc_timing.v_addressable + 255 patched_crtc_timing.v_border_bottom + 256 patched_crtc_timing.v_front_porch; 257 258 asic_blank_end = (patched_crtc_timing.v_total - 259 vesa_sync_start - 260 patched_crtc_timing.v_border_top); 261 262 /* v_blank_start = v_blank_end + v_active */ 263 asic_blank_start = asic_blank_end + 264 (patched_crtc_timing.v_border_top + 265 patched_crtc_timing.v_addressable + 266 patched_crtc_timing.v_border_bottom); 267 268 REG_UPDATE_2(OTG_V_BLANK_START_END, 269 OTG_V_BLANK_START, asic_blank_start, 270 OTG_V_BLANK_END, asic_blank_end); 271 272 /* Use OTG_VERTICAL_INTERRUPT2 replace VUPDATE interrupt, 273 * program the reg for interrupt postition. 274 */ 275 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1; 276 v_fp2 = 0; 277 if (vertical_line_start < 0) 278 v_fp2 = -vertical_line_start; 279 if (vertical_line_start < 0) 280 vertical_line_start = 0; 281 282 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 283 OTG_VERTICAL_INTERRUPT2_LINE_START, vertical_line_start); 284 285 /* v_sync polarity */ 286 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 287 0 : 1; 288 289 REG_UPDATE(OTG_V_SYNC_A_CNTL, 290 OTG_V_SYNC_A_POL, v_sync_polarity); 291 292 v_init = asic_blank_start; 293 if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT || 294 optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 295 optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) { 296 start_point = 1; 297 if (patched_crtc_timing.flags.INTERLACE == 1) 298 field_num = 1; 299 } 300 301 /* Interlace */ 302 if (patched_crtc_timing.flags.INTERLACE == 1) { 303 REG_UPDATE(OTG_INTERLACE_CONTROL, 304 OTG_INTERLACE_ENABLE, 1); 305 v_init = v_init / 2; 306 if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end) 307 v_fp2 = v_fp2 / 2; 308 } else 309 REG_UPDATE(OTG_INTERLACE_CONTROL, 310 OTG_INTERLACE_ENABLE, 0); 311 312 313 /* VTG enable set to 0 first VInit */ 314 REG_UPDATE(CONTROL, 315 VTG0_ENABLE, 0); 316 317 REG_UPDATE_2(CONTROL, 318 VTG0_FP2, v_fp2, 319 VTG0_VCOUNT_INIT, v_init); 320 321 /* original code is using VTG offset to address OTG reg, seems wrong */ 322 REG_UPDATE_2(OTG_CONTROL, 323 OTG_START_POINT_CNTL, start_point, 324 OTG_FIELD_NUMBER_CNTL, field_num); 325 326 optc1_program_global_sync(optc); 327 328 /* TODO 329 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 330 * program_horz_count_by_2 331 * for DVI 30bpp mode, 0 otherwise 332 * program_horz_count_by_2(optc, &patched_crtc_timing); 333 */ 334 335 /* Enable stereo - only when we need to pack 3D frame. Other types 336 * of stereo handled in explicit call 337 */ 338 h_div_2 = (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ? 339 1 : 0; 340 341 REG_UPDATE(OTG_H_TIMING_CNTL, 342 OTG_H_TIMING_DIV_BY2, h_div_2); 343 344 } 345 346 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 347 { 348 struct optc *optc1 = DCN10TG_FROM_TG(optc); 349 350 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 351 352 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 353 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 354 } 355 356 /** 357 * unblank_crtc 358 * Call ASIC Control Object to UnBlank CRTC. 359 */ 360 static void optc1_unblank_crtc(struct timing_generator *optc) 361 { 362 struct optc *optc1 = DCN10TG_FROM_TG(optc); 363 uint32_t vertical_interrupt_enable = 0; 364 365 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 366 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &vertical_interrupt_enable); 367 368 /* temporary work around for vertical interrupt, once vertical interrupt enabled, 369 * this check will be removed. 370 */ 371 if (vertical_interrupt_enable) 372 optc1_set_blank_data_double_buffer(optc, true); 373 374 REG_UPDATE_2(OTG_BLANK_CONTROL, 375 OTG_BLANK_DATA_EN, 0, 376 OTG_BLANK_DE_MODE, 0); 377 } 378 379 /** 380 * blank_crtc 381 * Call ASIC Control Object to Blank CRTC. 382 */ 383 384 static void optc1_blank_crtc(struct timing_generator *optc) 385 { 386 struct optc *optc1 = DCN10TG_FROM_TG(optc); 387 388 REG_UPDATE_2(OTG_BLANK_CONTROL, 389 OTG_BLANK_DATA_EN, 1, 390 OTG_BLANK_DE_MODE, 0); 391 392 optc1_set_blank_data_double_buffer(optc, false); 393 } 394 395 void optc1_set_blank(struct timing_generator *optc, 396 bool enable_blanking) 397 { 398 if (enable_blanking) 399 optc1_blank_crtc(optc); 400 else 401 optc1_unblank_crtc(optc); 402 } 403 404 bool optc1_is_blanked(struct timing_generator *optc) 405 { 406 struct optc *optc1 = DCN10TG_FROM_TG(optc); 407 uint32_t blank_en; 408 uint32_t blank_state; 409 410 REG_GET_2(OTG_BLANK_CONTROL, 411 OTG_BLANK_DATA_EN, &blank_en, 412 OTG_CURRENT_BLANK_STATE, &blank_state); 413 414 return blank_en && blank_state; 415 } 416 417 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 418 { 419 struct optc *optc1 = DCN10TG_FROM_TG(optc); 420 421 if (enable) { 422 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 423 OPTC_INPUT_CLK_EN, 1, 424 OPTC_INPUT_CLK_GATE_DIS, 1); 425 426 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 427 OPTC_INPUT_CLK_ON, 1, 428 1, 1000); 429 430 /* Enable clock */ 431 REG_UPDATE_2(OTG_CLOCK_CONTROL, 432 OTG_CLOCK_EN, 1, 433 OTG_CLOCK_GATE_DIS, 1); 434 REG_WAIT(OTG_CLOCK_CONTROL, 435 OTG_CLOCK_ON, 1, 436 1, 1000); 437 } else { 438 REG_UPDATE_2(OTG_CLOCK_CONTROL, 439 OTG_CLOCK_GATE_DIS, 0, 440 OTG_CLOCK_EN, 0); 441 442 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 443 OPTC_INPUT_CLK_GATE_DIS, 0, 444 OPTC_INPUT_CLK_EN, 0); 445 } 446 } 447 448 /** 449 * Enable CRTC 450 * Enable CRTC - call ASIC Control Object to enable Timing generator. 451 */ 452 static bool optc1_enable_crtc(struct timing_generator *optc) 453 { 454 /* TODO FPGA wait for answer 455 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 456 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 457 */ 458 struct optc *optc1 = DCN10TG_FROM_TG(optc); 459 460 /* opp instance for OTG. For DCN1.0, ODM is remoed. 461 * OPP and OPTC should 1:1 mapping 462 */ 463 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 464 OPTC_SRC_SEL, optc->inst); 465 466 /* VTG enable first is for HW workaround */ 467 REG_UPDATE(CONTROL, 468 VTG0_ENABLE, 1); 469 470 /* Enable CRTC */ 471 REG_UPDATE_2(OTG_CONTROL, 472 OTG_DISABLE_POINT_CNTL, 3, 473 OTG_MASTER_EN, 1); 474 475 return true; 476 } 477 478 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 479 bool optc1_disable_crtc(struct timing_generator *optc) 480 { 481 struct optc *optc1 = DCN10TG_FROM_TG(optc); 482 483 /* disable otg request until end of the first line 484 * in the vertical blank region 485 */ 486 REG_UPDATE_2(OTG_CONTROL, 487 OTG_DISABLE_POINT_CNTL, 3, 488 OTG_MASTER_EN, 0); 489 490 REG_UPDATE(CONTROL, 491 VTG0_ENABLE, 0); 492 493 /* CRTC disabled, so disable clock. */ 494 REG_WAIT(OTG_CLOCK_CONTROL, 495 OTG_BUSY, 0, 496 1, 100000); 497 498 return true; 499 } 500 501 502 void optc1_program_blank_color( 503 struct timing_generator *optc, 504 const struct tg_color *black_color) 505 { 506 struct optc *optc1 = DCN10TG_FROM_TG(optc); 507 508 REG_SET_3(OTG_BLACK_COLOR, 0, 509 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 510 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 511 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 512 } 513 514 bool optc1_validate_timing( 515 struct timing_generator *optc, 516 const struct dc_crtc_timing *timing) 517 { 518 uint32_t v_blank; 519 uint32_t h_blank; 520 uint32_t min_v_blank; 521 struct optc *optc1 = DCN10TG_FROM_TG(optc); 522 523 ASSERT(timing != NULL); 524 525 v_blank = (timing->v_total - timing->v_addressable - 526 timing->v_border_top - timing->v_border_bottom); 527 528 h_blank = (timing->h_total - timing->h_addressable - 529 timing->h_border_right - 530 timing->h_border_left); 531 532 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 533 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 534 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 535 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 536 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 537 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 538 return false; 539 540 /* Temporarily blocking interlacing mode until it's supported */ 541 if (timing->flags.INTERLACE == 1) 542 return false; 543 544 /* Check maximum number of pixels supported by Timing Generator 545 * (Currently will never fail, in order to fail needs display which 546 * needs more than 8192 horizontal and 547 * more than 8192 vertical total pixels) 548 */ 549 if (timing->h_total > optc1->max_h_total || 550 timing->v_total > optc1->max_v_total) 551 return false; 552 553 554 if (h_blank < optc1->min_h_blank) 555 return false; 556 557 if (timing->h_sync_width < optc1->min_h_sync_width || 558 timing->v_sync_width < optc1->min_v_sync_width) 559 return false; 560 561 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 562 563 if (v_blank < min_v_blank) 564 return false; 565 566 return true; 567 568 } 569 570 /* 571 * get_vblank_counter 572 * 573 * @brief 574 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 575 * holds the counter of frames. 576 * 577 * @param 578 * struct timing_generator *optc - [in] timing generator which controls the 579 * desired CRTC 580 * 581 * @return 582 * Counter of frames, which should equal to number of vblanks. 583 */ 584 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 585 { 586 struct optc *optc1 = DCN10TG_FROM_TG(optc); 587 uint32_t frame_count; 588 589 REG_GET(OTG_STATUS_FRAME_COUNT, 590 OTG_FRAME_COUNT, &frame_count); 591 592 return frame_count; 593 } 594 595 void optc1_lock(struct timing_generator *optc) 596 { 597 struct optc *optc1 = DCN10TG_FROM_TG(optc); 598 599 REG_SET(OTG_GLOBAL_CONTROL0, 0, 600 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 601 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 602 OTG_MASTER_UPDATE_LOCK, 1); 603 604 /* Should be fast, status does not update on maximus */ 605 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 606 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 607 UPDATE_LOCK_STATUS, 1, 608 1, 10); 609 } 610 611 void optc1_unlock(struct timing_generator *optc) 612 { 613 struct optc *optc1 = DCN10TG_FROM_TG(optc); 614 615 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 616 OTG_MASTER_UPDATE_LOCK, 0); 617 } 618 619 void optc1_get_position(struct timing_generator *optc, 620 struct crtc_position *position) 621 { 622 struct optc *optc1 = DCN10TG_FROM_TG(optc); 623 624 REG_GET_2(OTG_STATUS_POSITION, 625 OTG_HORZ_COUNT, &position->horizontal_count, 626 OTG_VERT_COUNT, &position->vertical_count); 627 628 REG_GET(OTG_NOM_VERT_POSITION, 629 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 630 } 631 632 bool optc1_is_counter_moving(struct timing_generator *optc) 633 { 634 struct crtc_position position1, position2; 635 636 optc->funcs->get_position(optc, &position1); 637 optc->funcs->get_position(optc, &position2); 638 639 if (position1.horizontal_count == position2.horizontal_count && 640 position1.vertical_count == position2.vertical_count) 641 return false; 642 else 643 return true; 644 } 645 646 bool optc1_did_triggered_reset_occur( 647 struct timing_generator *optc) 648 { 649 struct optc *optc1 = DCN10TG_FROM_TG(optc); 650 uint32_t occurred_force, occurred_vsync; 651 652 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 653 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 654 655 REG_GET(OTG_VERT_SYNC_CONTROL, 656 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 657 658 return occurred_vsync != 0 || occurred_force != 0; 659 } 660 661 void optc1_disable_reset_trigger(struct timing_generator *optc) 662 { 663 struct optc *optc1 = DCN10TG_FROM_TG(optc); 664 665 REG_WRITE(OTG_TRIGA_CNTL, 0); 666 667 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 668 OTG_FORCE_COUNT_NOW_CLEAR, 1); 669 670 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 671 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 672 } 673 674 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 675 { 676 struct optc *optc1 = DCN10TG_FROM_TG(optc); 677 uint32_t falling_edge; 678 679 REG_GET(OTG_V_SYNC_A_CNTL, 680 OTG_V_SYNC_A_POL, &falling_edge); 681 682 if (falling_edge) 683 REG_SET_3(OTG_TRIGA_CNTL, 0, 684 /* vsync signal from selected OTG pipe based 685 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 686 */ 687 OTG_TRIGA_SOURCE_SELECT, 20, 688 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 689 /* always detect falling edge */ 690 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 691 else 692 REG_SET_3(OTG_TRIGA_CNTL, 0, 693 /* vsync signal from selected OTG pipe based 694 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 695 */ 696 OTG_TRIGA_SOURCE_SELECT, 20, 697 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 698 /* always detect rising edge */ 699 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 700 701 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 702 /* force H count to H_TOTAL and V count to V_TOTAL in 703 * progressive mode and V_TOTAL-1 in interlaced mode 704 */ 705 OTG_FORCE_COUNT_NOW_MODE, 2); 706 } 707 708 void optc1_enable_crtc_reset( 709 struct timing_generator *optc, 710 int source_tg_inst, 711 struct crtc_trigger_info *crtc_tp) 712 { 713 struct optc *optc1 = DCN10TG_FROM_TG(optc); 714 uint32_t falling_edge = 0; 715 uint32_t rising_edge = 0; 716 717 switch (crtc_tp->event) { 718 719 case CRTC_EVENT_VSYNC_RISING: 720 rising_edge = 1; 721 break; 722 723 case CRTC_EVENT_VSYNC_FALLING: 724 falling_edge = 1; 725 break; 726 } 727 728 REG_SET_4(OTG_TRIGA_CNTL, 0, 729 /* vsync signal from selected OTG pipe based 730 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 731 */ 732 OTG_TRIGA_SOURCE_SELECT, 20, 733 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 734 /* always detect falling edge */ 735 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 736 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 737 738 switch (crtc_tp->delay) { 739 case TRIGGER_DELAY_NEXT_LINE: 740 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 741 OTG_AUTO_FORCE_VSYNC_MODE, 1); 742 break; 743 case TRIGGER_DELAY_NEXT_PIXEL: 744 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 745 /* force H count to H_TOTAL and V count to V_TOTAL in 746 * progressive mode and V_TOTAL-1 in interlaced mode 747 */ 748 OTG_FORCE_COUNT_NOW_MODE, 2); 749 break; 750 } 751 } 752 753 void optc1_wait_for_state(struct timing_generator *optc, 754 enum crtc_state state) 755 { 756 struct optc *optc1 = DCN10TG_FROM_TG(optc); 757 758 switch (state) { 759 case CRTC_STATE_VBLANK: 760 REG_WAIT(OTG_STATUS, 761 OTG_V_BLANK, 1, 762 1, 100000); /* 1 vupdate at 10hz */ 763 break; 764 765 case CRTC_STATE_VACTIVE: 766 REG_WAIT(OTG_STATUS, 767 OTG_V_ACTIVE_DISP, 1, 768 1, 100000); /* 1 vupdate at 10hz */ 769 break; 770 771 default: 772 break; 773 } 774 } 775 776 void optc1_set_early_control( 777 struct timing_generator *optc, 778 uint32_t early_cntl) 779 { 780 /* asic design change, do not need this control 781 * empty for share caller logic 782 */ 783 } 784 785 786 void optc1_set_static_screen_control( 787 struct timing_generator *optc, 788 uint32_t value) 789 { 790 struct optc *optc1 = DCN10TG_FROM_TG(optc); 791 792 /* Bit 8 is no longer applicable in RV for PSR case, 793 * set bit 8 to 0 if given 794 */ 795 if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 796 != 0) 797 value = value & 798 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 799 800 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 801 OTG_STATIC_SCREEN_EVENT_MASK, value, 802 OTG_STATIC_SCREEN_FRAME_COUNT, 2); 803 } 804 805 806 /** 807 ***************************************************************************** 808 * Function: set_drr 809 * 810 * @brief 811 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 812 * 813 ***************************************************************************** 814 */ 815 void optc1_set_drr( 816 struct timing_generator *optc, 817 const struct drr_params *params) 818 { 819 struct optc *optc1 = DCN10TG_FROM_TG(optc); 820 821 if (params != NULL && 822 params->vertical_total_max > 0 && 823 params->vertical_total_min > 0) { 824 825 REG_SET(OTG_V_TOTAL_MAX, 0, 826 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 827 828 REG_SET(OTG_V_TOTAL_MIN, 0, 829 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 830 831 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 832 OTG_V_TOTAL_MIN_SEL, 1, 833 OTG_V_TOTAL_MAX_SEL, 1, 834 OTG_FORCE_LOCK_ON_EVENT, 0, 835 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 836 OTG_SET_V_TOTAL_MIN_MASK, 0); 837 } else { 838 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 839 OTG_SET_V_TOTAL_MIN_MASK, 0, 840 OTG_V_TOTAL_MIN_SEL, 0, 841 OTG_V_TOTAL_MAX_SEL, 0, 842 OTG_FORCE_LOCK_ON_EVENT, 0); 843 844 REG_SET(OTG_V_TOTAL_MIN, 0, 845 OTG_V_TOTAL_MIN, 0); 846 847 REG_SET(OTG_V_TOTAL_MAX, 0, 848 OTG_V_TOTAL_MAX, 0); 849 } 850 } 851 852 static void optc1_set_test_pattern( 853 struct timing_generator *optc, 854 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 855 * because this is not DP-specific (which is probably somewhere in DP 856 * encoder) */ 857 enum controller_dp_test_pattern test_pattern, 858 enum dc_color_depth color_depth) 859 { 860 struct optc *optc1 = DCN10TG_FROM_TG(optc); 861 enum test_pattern_color_format bit_depth; 862 enum test_pattern_dyn_range dyn_range; 863 enum test_pattern_mode mode; 864 uint32_t pattern_mask; 865 uint32_t pattern_data; 866 /* color ramp generator mixes 16-bits color */ 867 uint32_t src_bpc = 16; 868 /* requested bpc */ 869 uint32_t dst_bpc; 870 uint32_t index; 871 /* RGB values of the color bars. 872 * Produce two RGB colors: RGB0 - white (all Fs) 873 * and RGB1 - black (all 0s) 874 * (three RGB components for two colors) 875 */ 876 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 877 0x0000, 0x0000}; 878 /* dest color (converted to the specified color format) */ 879 uint16_t dst_color[6]; 880 uint32_t inc_base; 881 882 /* translate to bit depth */ 883 switch (color_depth) { 884 case COLOR_DEPTH_666: 885 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 886 break; 887 case COLOR_DEPTH_888: 888 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 889 break; 890 case COLOR_DEPTH_101010: 891 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 892 break; 893 case COLOR_DEPTH_121212: 894 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 895 break; 896 default: 897 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 898 break; 899 } 900 901 switch (test_pattern) { 902 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 903 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 904 { 905 dyn_range = (test_pattern == 906 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 907 TEST_PATTERN_DYN_RANGE_CEA : 908 TEST_PATTERN_DYN_RANGE_VESA); 909 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 910 911 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 912 OTG_TEST_PATTERN_VRES, 6, 913 OTG_TEST_PATTERN_HRES, 6); 914 915 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 916 OTG_TEST_PATTERN_EN, 1, 917 OTG_TEST_PATTERN_MODE, mode, 918 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 919 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 920 } 921 break; 922 923 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 924 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 925 { 926 mode = (test_pattern == 927 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 928 TEST_PATTERN_MODE_VERTICALBARS : 929 TEST_PATTERN_MODE_HORIZONTALBARS); 930 931 switch (bit_depth) { 932 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 933 dst_bpc = 6; 934 break; 935 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 936 dst_bpc = 8; 937 break; 938 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 939 dst_bpc = 10; 940 break; 941 default: 942 dst_bpc = 8; 943 break; 944 } 945 946 /* adjust color to the required colorFormat */ 947 for (index = 0; index < 6; index++) { 948 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 949 * (srcBpc - dstBpc); 950 */ 951 dst_color[index] = 952 src_color[index] >> (src_bpc - dst_bpc); 953 /* CRTC_TEST_PATTERN_DATA has 16 bits, 954 * lowest 6 are hardwired to ZERO 955 * color bits should be left aligned aligned to MSB 956 * XXXXXXXXXX000000 for 10 bit, 957 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 958 */ 959 dst_color[index] <<= (16 - dst_bpc); 960 } 961 962 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 963 964 /* We have to write the mask before data, similar to pipeline. 965 * For example, for 8 bpc, if we want RGB0 to be magenta, 966 * and RGB1 to be cyan, 967 * we need to make 7 writes: 968 * MASK DATA 969 * 000001 00000000 00000000 set mask to R0 970 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 971 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 972 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 973 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 974 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 975 * 100000 11111111 00000000 B1 255, 0xFF00 976 * 977 * we will make a loop of 6 in which we prepare the mask, 978 * then write, then prepare the color for next write. 979 * first iteration will write mask only, 980 * but each next iteration color prepared in 981 * previous iteration will be written within new mask, 982 * the last component will written separately, 983 * mask is not changing between 6th and 7th write 984 * and color will be prepared by last iteration 985 */ 986 987 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 988 * is B1, G1, R1, B0, G0, R0 989 */ 990 pattern_data = 0; 991 for (index = 0; index < 6; index++) { 992 /* prepare color mask, first write PATTERN_DATA 993 * will have all zeros 994 */ 995 pattern_mask = (1 << index); 996 997 /* write color component */ 998 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 999 OTG_TEST_PATTERN_MASK, pattern_mask, 1000 OTG_TEST_PATTERN_DATA, pattern_data); 1001 1002 /* prepare next color component, 1003 * will be written in the next iteration 1004 */ 1005 pattern_data = dst_color[index]; 1006 } 1007 /* write last color component, 1008 * it's been already prepared in the loop 1009 */ 1010 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1011 OTG_TEST_PATTERN_MASK, pattern_mask, 1012 OTG_TEST_PATTERN_DATA, pattern_data); 1013 1014 /* enable test pattern */ 1015 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1016 OTG_TEST_PATTERN_EN, 1, 1017 OTG_TEST_PATTERN_MODE, mode, 1018 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1019 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1020 } 1021 break; 1022 1023 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1024 { 1025 mode = (bit_depth == 1026 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1027 TEST_PATTERN_MODE_DUALRAMP_RGB : 1028 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1029 1030 switch (bit_depth) { 1031 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1032 dst_bpc = 6; 1033 break; 1034 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1035 dst_bpc = 8; 1036 break; 1037 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1038 dst_bpc = 10; 1039 break; 1040 default: 1041 dst_bpc = 8; 1042 break; 1043 } 1044 1045 /* increment for the first ramp for one color gradation 1046 * 1 gradation for 6-bit color is 2^10 1047 * gradations in 16-bit color 1048 */ 1049 inc_base = (src_bpc - dst_bpc); 1050 1051 switch (bit_depth) { 1052 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1053 { 1054 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1055 OTG_TEST_PATTERN_INC0, inc_base, 1056 OTG_TEST_PATTERN_INC1, 0, 1057 OTG_TEST_PATTERN_HRES, 6, 1058 OTG_TEST_PATTERN_VRES, 6, 1059 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1060 } 1061 break; 1062 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1063 { 1064 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1065 OTG_TEST_PATTERN_INC0, inc_base, 1066 OTG_TEST_PATTERN_INC1, 0, 1067 OTG_TEST_PATTERN_HRES, 8, 1068 OTG_TEST_PATTERN_VRES, 6, 1069 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1070 } 1071 break; 1072 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1073 { 1074 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1075 OTG_TEST_PATTERN_INC0, inc_base, 1076 OTG_TEST_PATTERN_INC1, inc_base + 2, 1077 OTG_TEST_PATTERN_HRES, 8, 1078 OTG_TEST_PATTERN_VRES, 5, 1079 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1080 } 1081 break; 1082 default: 1083 break; 1084 } 1085 1086 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1087 1088 /* enable test pattern */ 1089 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1090 1091 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1092 OTG_TEST_PATTERN_EN, 1, 1093 OTG_TEST_PATTERN_MODE, mode, 1094 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1095 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1096 } 1097 break; 1098 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1099 { 1100 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1101 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1102 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1103 } 1104 break; 1105 default: 1106 break; 1107 1108 } 1109 } 1110 1111 void optc1_get_crtc_scanoutpos( 1112 struct timing_generator *optc, 1113 uint32_t *v_blank_start, 1114 uint32_t *v_blank_end, 1115 uint32_t *h_position, 1116 uint32_t *v_position) 1117 { 1118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1119 struct crtc_position position; 1120 1121 REG_GET_2(OTG_V_BLANK_START_END, 1122 OTG_V_BLANK_START, v_blank_start, 1123 OTG_V_BLANK_END, v_blank_end); 1124 1125 optc1_get_position(optc, &position); 1126 1127 *h_position = position.horizontal_count; 1128 *v_position = position.vertical_count; 1129 } 1130 1131 static void optc1_enable_stereo(struct timing_generator *optc, 1132 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1133 { 1134 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1135 1136 if (flags) { 1137 uint32_t stereo_en; 1138 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1139 1140 if (flags->PROGRAM_STEREO) 1141 REG_UPDATE_3(OTG_STEREO_CONTROL, 1142 OTG_STEREO_EN, stereo_en, 1143 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1144 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0); 1145 1146 if (flags->PROGRAM_POLARITY) 1147 REG_UPDATE(OTG_STEREO_CONTROL, 1148 OTG_STEREO_EYE_FLAG_POLARITY, 1149 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1150 1151 if (flags->DISABLE_STEREO_DP_SYNC) 1152 REG_UPDATE(OTG_STEREO_CONTROL, 1153 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1154 1155 if (flags->PROGRAM_STEREO) 1156 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1157 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1158 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1159 1160 } 1161 } 1162 1163 void optc1_program_stereo(struct timing_generator *optc, 1164 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1165 { 1166 if (flags->PROGRAM_STEREO) 1167 optc1_enable_stereo(optc, timing, flags); 1168 else 1169 optc1_disable_stereo(optc); 1170 } 1171 1172 1173 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1174 { 1175 bool ret = false; 1176 uint32_t left_eye = 0; 1177 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1178 1179 REG_GET(OTG_STEREO_STATUS, 1180 OTG_STEREO_CURRENT_EYE, &left_eye); 1181 if (left_eye == 1) 1182 ret = true; 1183 else 1184 ret = false; 1185 1186 return ret; 1187 } 1188 1189 void optc1_read_otg_state(struct optc *optc1, 1190 struct dcn_otg_state *s) 1191 { 1192 REG_GET(OTG_CONTROL, 1193 OTG_MASTER_EN, &s->otg_enabled); 1194 1195 REG_GET_2(OTG_V_BLANK_START_END, 1196 OTG_V_BLANK_START, &s->v_blank_start, 1197 OTG_V_BLANK_END, &s->v_blank_end); 1198 1199 REG_GET(OTG_V_SYNC_A_CNTL, 1200 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1201 1202 REG_GET(OTG_V_TOTAL, 1203 OTG_V_TOTAL, &s->v_total); 1204 1205 REG_GET(OTG_V_TOTAL_MAX, 1206 OTG_V_TOTAL_MAX, &s->v_total_max); 1207 1208 REG_GET(OTG_V_TOTAL_MIN, 1209 OTG_V_TOTAL_MIN, &s->v_total_min); 1210 1211 REG_GET(OTG_V_TOTAL_CONTROL, 1212 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1213 1214 REG_GET(OTG_V_TOTAL_CONTROL, 1215 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1216 1217 REG_GET_2(OTG_V_SYNC_A, 1218 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1219 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1220 1221 REG_GET_2(OTG_H_BLANK_START_END, 1222 OTG_H_BLANK_START, &s->h_blank_start, 1223 OTG_H_BLANK_END, &s->h_blank_end); 1224 1225 REG_GET_2(OTG_H_SYNC_A, 1226 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1227 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1228 1229 REG_GET(OTG_H_SYNC_A_CNTL, 1230 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1231 1232 REG_GET(OTG_H_TOTAL, 1233 OTG_H_TOTAL, &s->h_total); 1234 1235 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1236 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1237 } 1238 1239 bool optc1_get_otg_active_size(struct timing_generator *optc, 1240 uint32_t *otg_active_width, 1241 uint32_t *otg_active_height) 1242 { 1243 uint32_t otg_enabled; 1244 uint32_t v_blank_start; 1245 uint32_t v_blank_end; 1246 uint32_t h_blank_start; 1247 uint32_t h_blank_end; 1248 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1249 1250 1251 REG_GET(OTG_CONTROL, 1252 OTG_MASTER_EN, &otg_enabled); 1253 1254 if (otg_enabled == 0) 1255 return false; 1256 1257 REG_GET_2(OTG_V_BLANK_START_END, 1258 OTG_V_BLANK_START, &v_blank_start, 1259 OTG_V_BLANK_END, &v_blank_end); 1260 1261 REG_GET_2(OTG_H_BLANK_START_END, 1262 OTG_H_BLANK_START, &h_blank_start, 1263 OTG_H_BLANK_END, &h_blank_end); 1264 1265 *otg_active_width = v_blank_start - v_blank_end; 1266 *otg_active_height = h_blank_start - h_blank_end; 1267 return true; 1268 } 1269 1270 void optc1_clear_optc_underflow(struct timing_generator *optc) 1271 { 1272 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1273 1274 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1275 } 1276 1277 void optc1_tg_init(struct timing_generator *optc) 1278 { 1279 optc1_set_blank_data_double_buffer(optc, true); 1280 optc1_clear_optc_underflow(optc); 1281 } 1282 1283 bool optc1_is_tg_enabled(struct timing_generator *optc) 1284 { 1285 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1286 uint32_t otg_enabled = 0; 1287 1288 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1289 1290 return (otg_enabled != 0); 1291 1292 } 1293 1294 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1295 { 1296 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1297 uint32_t underflow_occurred = 0; 1298 1299 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1300 OPTC_UNDERFLOW_OCCURRED_STATUS, 1301 &underflow_occurred); 1302 1303 return (underflow_occurred == 1); 1304 } 1305 1306 bool optc1_configure_crc(struct timing_generator *optc, 1307 const struct crc_params *params) 1308 { 1309 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1310 1311 /* Cannot configure crc on a CRTC that is disabled */ 1312 if (!optc1_is_tg_enabled(optc)) 1313 return false; 1314 1315 REG_WRITE(OTG_CRC_CNTL, 0); 1316 1317 if (!params->enable) 1318 return true; 1319 1320 /* Program frame boundaries */ 1321 /* Window A x axis start and end. */ 1322 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1323 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1324 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1325 1326 /* Window A y axis start and end. */ 1327 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1328 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1329 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1330 1331 /* Window B x axis start and end. */ 1332 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1333 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1334 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1335 1336 /* Window B y axis start and end. */ 1337 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1338 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1339 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1340 1341 /* Set crc mode and selection, and enable. Only using CRC0*/ 1342 REG_UPDATE_3(OTG_CRC_CNTL, 1343 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1344 OTG_CRC0_SELECT, params->selection, 1345 OTG_CRC_EN, 1); 1346 1347 return true; 1348 } 1349 1350 bool optc1_get_crc(struct timing_generator *optc, 1351 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1352 { 1353 uint32_t field = 0; 1354 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1355 1356 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1357 1358 /* Early return if CRC is not enabled for this CRTC */ 1359 if (!field) 1360 return false; 1361 1362 REG_GET_2(OTG_CRC0_DATA_RG, 1363 CRC0_R_CR, r_cr, 1364 CRC0_G_Y, g_y); 1365 1366 REG_GET(OTG_CRC0_DATA_B, 1367 CRC0_B_CB, b_cb); 1368 1369 return true; 1370 } 1371 1372 static const struct timing_generator_funcs dcn10_tg_funcs = { 1373 .validate_timing = optc1_validate_timing, 1374 .program_timing = optc1_program_timing, 1375 .program_vline_interrupt = optc1_program_vline_interrupt, 1376 .program_global_sync = optc1_program_global_sync, 1377 .enable_crtc = optc1_enable_crtc, 1378 .disable_crtc = optc1_disable_crtc, 1379 /* used by enable_timing_synchronization. Not need for FPGA */ 1380 .is_counter_moving = optc1_is_counter_moving, 1381 .get_position = optc1_get_position, 1382 .get_frame_count = optc1_get_vblank_counter, 1383 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1384 .get_otg_active_size = optc1_get_otg_active_size, 1385 .set_early_control = optc1_set_early_control, 1386 /* used by enable_timing_synchronization. Not need for FPGA */ 1387 .wait_for_state = optc1_wait_for_state, 1388 .set_blank = optc1_set_blank, 1389 .is_blanked = optc1_is_blanked, 1390 .set_blank_color = optc1_program_blank_color, 1391 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1392 .enable_reset_trigger = optc1_enable_reset_trigger, 1393 .enable_crtc_reset = optc1_enable_crtc_reset, 1394 .disable_reset_trigger = optc1_disable_reset_trigger, 1395 .lock = optc1_lock, 1396 .unlock = optc1_unlock, 1397 .enable_optc_clock = optc1_enable_optc_clock, 1398 .set_drr = optc1_set_drr, 1399 .set_static_screen_control = optc1_set_static_screen_control, 1400 .set_test_pattern = optc1_set_test_pattern, 1401 .program_stereo = optc1_program_stereo, 1402 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1403 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1404 .tg_init = optc1_tg_init, 1405 .is_tg_enabled = optc1_is_tg_enabled, 1406 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1407 .clear_optc_underflow = optc1_clear_optc_underflow, 1408 .get_crc = optc1_get_crc, 1409 .configure_crc = optc1_configure_crc, 1410 }; 1411 1412 void dcn10_timing_generator_init(struct optc *optc1) 1413 { 1414 optc1->base.funcs = &dcn10_tg_funcs; 1415 1416 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1417 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1418 1419 optc1->min_h_blank = 32; 1420 optc1->min_v_blank = 3; 1421 optc1->min_v_blank_interlace = 5; 1422 optc1->min_h_sync_width = 8; 1423 optc1->min_v_sync_width = 1; 1424 } 1425