1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 optc1->orginal_patched_timing = patched_crtc_timing; 169 170 /* Load horizontal timing */ 171 172 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 173 REG_SET(OTG_H_TOTAL, 0, 174 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 175 176 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 177 REG_UPDATE_2(OTG_H_SYNC_A, 178 OTG_H_SYNC_A_START, 0, 179 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 180 181 /* blank_start = line end - front porch */ 182 asic_blank_start = patched_crtc_timing.h_total - 183 patched_crtc_timing.h_front_porch; 184 185 /* blank_end = blank_start - active */ 186 asic_blank_end = asic_blank_start - 187 patched_crtc_timing.h_border_right - 188 patched_crtc_timing.h_addressable - 189 patched_crtc_timing.h_border_left; 190 191 REG_UPDATE_2(OTG_H_BLANK_START_END, 192 OTG_H_BLANK_START, asic_blank_start, 193 OTG_H_BLANK_END, asic_blank_end); 194 195 /* h_sync polarity */ 196 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 197 0 : 1; 198 199 REG_UPDATE(OTG_H_SYNC_A_CNTL, 200 OTG_H_SYNC_A_POL, h_sync_polarity); 201 202 v_total = patched_crtc_timing.v_total - 1; 203 204 REG_SET(OTG_V_TOTAL, 0, 205 OTG_V_TOTAL, v_total); 206 207 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 208 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 209 */ 210 optc->funcs->set_vtotal_min_max(optc, v_total, v_total); 211 212 /* v_sync_start = 0, v_sync_end = v_sync_width */ 213 v_sync_end = patched_crtc_timing.v_sync_width; 214 215 REG_UPDATE_2(OTG_V_SYNC_A, 216 OTG_V_SYNC_A_START, 0, 217 OTG_V_SYNC_A_END, v_sync_end); 218 219 /* blank_start = frame end - front porch */ 220 asic_blank_start = patched_crtc_timing.v_total - 221 patched_crtc_timing.v_front_porch; 222 223 /* blank_end = blank_start - active */ 224 asic_blank_end = asic_blank_start - 225 patched_crtc_timing.v_border_bottom - 226 patched_crtc_timing.v_addressable - 227 patched_crtc_timing.v_border_top; 228 229 REG_UPDATE_2(OTG_V_BLANK_START_END, 230 OTG_V_BLANK_START, asic_blank_start, 231 OTG_V_BLANK_END, asic_blank_end); 232 233 /* v_sync polarity */ 234 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 235 0 : 1; 236 237 REG_UPDATE(OTG_V_SYNC_A_CNTL, 238 OTG_V_SYNC_A_POL, v_sync_polarity); 239 240 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 241 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 242 optc1->signal == SIGNAL_TYPE_EDP) { 243 start_point = 1; 244 if (patched_crtc_timing.flags.INTERLACE == 1) 245 field_num = 1; 246 } 247 248 /* Interlace */ 249 if (REG(OTG_INTERLACE_CONTROL)) { 250 if (patched_crtc_timing.flags.INTERLACE == 1) 251 REG_UPDATE(OTG_INTERLACE_CONTROL, 252 OTG_INTERLACE_ENABLE, 1); 253 else 254 REG_UPDATE(OTG_INTERLACE_CONTROL, 255 OTG_INTERLACE_ENABLE, 0); 256 } 257 258 /* VTG enable set to 0 first VInit */ 259 REG_UPDATE(CONTROL, 260 VTG0_ENABLE, 0); 261 262 /* original code is using VTG offset to address OTG reg, seems wrong */ 263 REG_UPDATE_2(OTG_CONTROL, 264 OTG_START_POINT_CNTL, start_point, 265 OTG_FIELD_NUMBER_CNTL, field_num); 266 267 optc->funcs->program_global_sync(optc, 268 vready_offset, 269 vstartup_start, 270 vupdate_offset, 271 vupdate_width); 272 273 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true); 274 275 /* TODO 276 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 277 * program_horz_count_by_2 278 * for DVI 30bpp mode, 0 otherwise 279 * program_horz_count_by_2(optc, &patched_crtc_timing); 280 */ 281 282 /* Enable stereo - only when we need to pack 3D frame. Other types 283 * of stereo handled in explicit call 284 */ 285 286 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) 287 h_div = H_TIMING_DIV_BY2; 288 289 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { 290 uint32_t data_fmt = 0; 291 292 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 293 data_fmt = 1; 294 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 295 data_fmt = 2; 296 297 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 298 } 299 300 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { 301 if (optc1->opp_count == 4) 302 h_div = H_TIMING_DIV_BY4; 303 304 REG_UPDATE(OTG_H_TIMING_CNTL, 305 OTG_H_TIMING_DIV_MODE, h_div); 306 } else { 307 REG_UPDATE(OTG_H_TIMING_CNTL, 308 OTG_H_TIMING_DIV_BY2, h_div); 309 } 310 } 311 312 /** 313 * optc1_set_vtg_params - Set Vertical Timing Generator (VTG) parameters 314 * 315 * @optc: timing_generator struct used to extract the optc parameters 316 * @dc_crtc_timing: Timing parameters configured 317 * @program_fp2: Boolean value indicating if FP2 will be programmed or not 318 * 319 * OTG is responsible for generating the global sync signals, including 320 * vertical timing information for each HUBP in the dcfclk domain. Each VTG is 321 * associated with one OTG that provides HUBP with vertical timing information 322 * (i.e., there is 1:1 correspondence between OTG and VTG). This function is 323 * responsible for setting the OTG parameters to the VTG during the pipe 324 * programming. 325 */ 326 void optc1_set_vtg_params(struct timing_generator *optc, 327 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2) 328 { 329 struct dc_crtc_timing patched_crtc_timing; 330 uint32_t asic_blank_end; 331 uint32_t v_init; 332 uint32_t v_fp2 = 0; 333 int32_t vertical_line_start; 334 335 struct optc *optc1 = DCN10TG_FROM_TG(optc); 336 337 patched_crtc_timing = *dc_crtc_timing; 338 apply_front_porch_workaround(&patched_crtc_timing); 339 340 /* VCOUNT_INIT is the start of blank */ 341 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 342 343 /* end of blank = v_init - active */ 344 asic_blank_end = v_init - 345 patched_crtc_timing.v_border_bottom - 346 patched_crtc_timing.v_addressable - 347 patched_crtc_timing.v_border_top; 348 349 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 350 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 351 if (vertical_line_start < 0) 352 v_fp2 = -vertical_line_start; 353 354 /* Interlace */ 355 if (REG(OTG_INTERLACE_CONTROL)) { 356 if (patched_crtc_timing.flags.INTERLACE == 1) { 357 v_init = v_init / 2; 358 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 359 v_fp2 = v_fp2 / 2; 360 } 361 } 362 363 if (program_fp2) 364 REG_UPDATE_2(CONTROL, 365 VTG0_FP2, v_fp2, 366 VTG0_VCOUNT_INIT, v_init); 367 else 368 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); 369 } 370 371 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 372 { 373 struct optc *optc1 = DCN10TG_FROM_TG(optc); 374 375 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 376 377 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 378 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 379 } 380 381 /** 382 * optc1_set_timing_double_buffer() - DRR double buffering control 383 * 384 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 385 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 386 * 387 * Options: any time, start of frame, dp start of frame (range timing) 388 */ 389 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 390 { 391 struct optc *optc1 = DCN10TG_FROM_TG(optc); 392 uint32_t mode = enable ? 2 : 0; 393 394 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 395 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode); 396 } 397 398 /** 399 * unblank_crtc 400 * Call ASIC Control Object to UnBlank CRTC. 401 */ 402 static void optc1_unblank_crtc(struct timing_generator *optc) 403 { 404 struct optc *optc1 = DCN10TG_FROM_TG(optc); 405 406 REG_UPDATE_2(OTG_BLANK_CONTROL, 407 OTG_BLANK_DATA_EN, 0, 408 OTG_BLANK_DE_MODE, 0); 409 410 /* W/A for automated testing 411 * Automated testing will fail underflow test as there 412 * sporadic underflows which occur during the optc blank 413 * sequence. As a w/a, clear underflow on unblank. 414 * This prevents the failure, but will not mask actual 415 * underflow that affect real use cases. 416 */ 417 optc1_clear_optc_underflow(optc); 418 } 419 420 /** 421 * blank_crtc 422 * Call ASIC Control Object to Blank CRTC. 423 */ 424 425 static void optc1_blank_crtc(struct timing_generator *optc) 426 { 427 struct optc *optc1 = DCN10TG_FROM_TG(optc); 428 429 REG_UPDATE_2(OTG_BLANK_CONTROL, 430 OTG_BLANK_DATA_EN, 1, 431 OTG_BLANK_DE_MODE, 0); 432 433 optc1_set_blank_data_double_buffer(optc, false); 434 } 435 436 void optc1_set_blank(struct timing_generator *optc, 437 bool enable_blanking) 438 { 439 if (enable_blanking) 440 optc1_blank_crtc(optc); 441 else 442 optc1_unblank_crtc(optc); 443 } 444 445 bool optc1_is_blanked(struct timing_generator *optc) 446 { 447 struct optc *optc1 = DCN10TG_FROM_TG(optc); 448 uint32_t blank_en; 449 uint32_t blank_state; 450 451 REG_GET_2(OTG_BLANK_CONTROL, 452 OTG_BLANK_DATA_EN, &blank_en, 453 OTG_CURRENT_BLANK_STATE, &blank_state); 454 455 return blank_en && blank_state; 456 } 457 458 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 459 { 460 struct optc *optc1 = DCN10TG_FROM_TG(optc); 461 462 if (enable) { 463 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 464 OPTC_INPUT_CLK_EN, 1, 465 OPTC_INPUT_CLK_GATE_DIS, 1); 466 467 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 468 OPTC_INPUT_CLK_ON, 1, 469 1, 1000); 470 471 /* Enable clock */ 472 REG_UPDATE_2(OTG_CLOCK_CONTROL, 473 OTG_CLOCK_EN, 1, 474 OTG_CLOCK_GATE_DIS, 1); 475 REG_WAIT(OTG_CLOCK_CONTROL, 476 OTG_CLOCK_ON, 1, 477 1, 1000); 478 } else { 479 480 //last chance to clear underflow, otherwise, it will always there due to clock is off. 481 if (optc->funcs->is_optc_underflow_occurred(optc) == true) 482 optc->funcs->clear_optc_underflow(optc); 483 484 REG_UPDATE_2(OTG_CLOCK_CONTROL, 485 OTG_CLOCK_GATE_DIS, 0, 486 OTG_CLOCK_EN, 0); 487 488 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 489 OPTC_INPUT_CLK_GATE_DIS, 0, 490 OPTC_INPUT_CLK_EN, 0); 491 } 492 } 493 494 /** 495 * Enable CRTC 496 * Enable CRTC - call ASIC Control Object to enable Timing generator. 497 */ 498 static bool optc1_enable_crtc(struct timing_generator *optc) 499 { 500 /* TODO FPGA wait for answer 501 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 502 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 503 */ 504 struct optc *optc1 = DCN10TG_FROM_TG(optc); 505 506 /* opp instance for OTG. For DCN1.0, ODM is remoed. 507 * OPP and OPTC should 1:1 mapping 508 */ 509 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 510 OPTC_SRC_SEL, optc->inst); 511 512 /* VTG enable first is for HW workaround */ 513 REG_UPDATE(CONTROL, 514 VTG0_ENABLE, 1); 515 516 REG_SEQ_START(); 517 518 /* Enable CRTC */ 519 REG_UPDATE_2(OTG_CONTROL, 520 OTG_DISABLE_POINT_CNTL, 3, 521 OTG_MASTER_EN, 1); 522 523 REG_SEQ_SUBMIT(); 524 REG_SEQ_WAIT_DONE(); 525 526 return true; 527 } 528 529 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 530 bool optc1_disable_crtc(struct timing_generator *optc) 531 { 532 struct optc *optc1 = DCN10TG_FROM_TG(optc); 533 534 /* disable otg request until end of the first line 535 * in the vertical blank region 536 */ 537 REG_UPDATE_2(OTG_CONTROL, 538 OTG_DISABLE_POINT_CNTL, 3, 539 OTG_MASTER_EN, 0); 540 541 REG_UPDATE(CONTROL, 542 VTG0_ENABLE, 0); 543 544 /* CRTC disabled, so disable clock. */ 545 REG_WAIT(OTG_CLOCK_CONTROL, 546 OTG_BUSY, 0, 547 1, 100000); 548 549 return true; 550 } 551 552 553 void optc1_program_blank_color( 554 struct timing_generator *optc, 555 const struct tg_color *black_color) 556 { 557 struct optc *optc1 = DCN10TG_FROM_TG(optc); 558 559 REG_SET_3(OTG_BLACK_COLOR, 0, 560 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 561 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 562 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 563 } 564 565 bool optc1_validate_timing( 566 struct timing_generator *optc, 567 const struct dc_crtc_timing *timing) 568 { 569 uint32_t v_blank; 570 uint32_t h_blank; 571 uint32_t min_v_blank; 572 struct optc *optc1 = DCN10TG_FROM_TG(optc); 573 574 ASSERT(timing != NULL); 575 576 v_blank = (timing->v_total - timing->v_addressable - 577 timing->v_border_top - timing->v_border_bottom); 578 579 h_blank = (timing->h_total - timing->h_addressable - 580 timing->h_border_right - 581 timing->h_border_left); 582 583 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 584 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 585 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 586 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 587 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 588 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 589 return false; 590 591 /* Temporarily blocking interlacing mode until it's supported */ 592 if (timing->flags.INTERLACE == 1) 593 return false; 594 595 /* Check maximum number of pixels supported by Timing Generator 596 * (Currently will never fail, in order to fail needs display which 597 * needs more than 8192 horizontal and 598 * more than 8192 vertical total pixels) 599 */ 600 if (timing->h_total > optc1->max_h_total || 601 timing->v_total > optc1->max_v_total) 602 return false; 603 604 605 if (h_blank < optc1->min_h_blank) 606 return false; 607 608 if (timing->h_sync_width < optc1->min_h_sync_width || 609 timing->v_sync_width < optc1->min_v_sync_width) 610 return false; 611 612 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 613 614 if (v_blank < min_v_blank) 615 return false; 616 617 return true; 618 619 } 620 621 /* 622 * get_vblank_counter 623 * 624 * @brief 625 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 626 * holds the counter of frames. 627 * 628 * @param 629 * struct timing_generator *optc - [in] timing generator which controls the 630 * desired CRTC 631 * 632 * @return 633 * Counter of frames, which should equal to number of vblanks. 634 */ 635 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 636 { 637 struct optc *optc1 = DCN10TG_FROM_TG(optc); 638 uint32_t frame_count; 639 640 REG_GET(OTG_STATUS_FRAME_COUNT, 641 OTG_FRAME_COUNT, &frame_count); 642 643 return frame_count; 644 } 645 646 void optc1_lock(struct timing_generator *optc) 647 { 648 struct optc *optc1 = DCN10TG_FROM_TG(optc); 649 650 REG_SET(OTG_GLOBAL_CONTROL0, 0, 651 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 652 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 653 OTG_MASTER_UPDATE_LOCK, 1); 654 655 /* Should be fast, status does not update on maximus */ 656 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 657 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 658 UPDATE_LOCK_STATUS, 1, 659 1, 10); 660 } 661 662 void optc1_unlock(struct timing_generator *optc) 663 { 664 struct optc *optc1 = DCN10TG_FROM_TG(optc); 665 666 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 667 OTG_MASTER_UPDATE_LOCK, 0); 668 } 669 670 void optc1_get_position(struct timing_generator *optc, 671 struct crtc_position *position) 672 { 673 struct optc *optc1 = DCN10TG_FROM_TG(optc); 674 675 REG_GET_2(OTG_STATUS_POSITION, 676 OTG_HORZ_COUNT, &position->horizontal_count, 677 OTG_VERT_COUNT, &position->vertical_count); 678 679 REG_GET(OTG_NOM_VERT_POSITION, 680 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 681 } 682 683 bool optc1_is_counter_moving(struct timing_generator *optc) 684 { 685 struct crtc_position position1, position2; 686 687 optc->funcs->get_position(optc, &position1); 688 optc->funcs->get_position(optc, &position2); 689 690 if (position1.horizontal_count == position2.horizontal_count && 691 position1.vertical_count == position2.vertical_count) 692 return false; 693 else 694 return true; 695 } 696 697 bool optc1_did_triggered_reset_occur( 698 struct timing_generator *optc) 699 { 700 struct optc *optc1 = DCN10TG_FROM_TG(optc); 701 uint32_t occurred_force, occurred_vsync; 702 703 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 704 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 705 706 REG_GET(OTG_VERT_SYNC_CONTROL, 707 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 708 709 return occurred_vsync != 0 || occurred_force != 0; 710 } 711 712 void optc1_disable_reset_trigger(struct timing_generator *optc) 713 { 714 struct optc *optc1 = DCN10TG_FROM_TG(optc); 715 716 REG_WRITE(OTG_TRIGA_CNTL, 0); 717 718 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 719 OTG_FORCE_COUNT_NOW_CLEAR, 1); 720 721 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 722 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 723 } 724 725 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 726 { 727 struct optc *optc1 = DCN10TG_FROM_TG(optc); 728 uint32_t falling_edge; 729 730 REG_GET(OTG_V_SYNC_A_CNTL, 731 OTG_V_SYNC_A_POL, &falling_edge); 732 733 if (falling_edge) 734 REG_SET_3(OTG_TRIGA_CNTL, 0, 735 /* vsync signal from selected OTG pipe based 736 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 737 */ 738 OTG_TRIGA_SOURCE_SELECT, 20, 739 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 740 /* always detect falling edge */ 741 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 742 else 743 REG_SET_3(OTG_TRIGA_CNTL, 0, 744 /* vsync signal from selected OTG pipe based 745 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 746 */ 747 OTG_TRIGA_SOURCE_SELECT, 20, 748 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 749 /* always detect rising edge */ 750 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 751 752 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 753 /* force H count to H_TOTAL and V count to V_TOTAL in 754 * progressive mode and V_TOTAL-1 in interlaced mode 755 */ 756 OTG_FORCE_COUNT_NOW_MODE, 2); 757 } 758 759 void optc1_enable_crtc_reset( 760 struct timing_generator *optc, 761 int source_tg_inst, 762 struct crtc_trigger_info *crtc_tp) 763 { 764 struct optc *optc1 = DCN10TG_FROM_TG(optc); 765 uint32_t falling_edge = 0; 766 uint32_t rising_edge = 0; 767 768 switch (crtc_tp->event) { 769 770 case CRTC_EVENT_VSYNC_RISING: 771 rising_edge = 1; 772 break; 773 774 case CRTC_EVENT_VSYNC_FALLING: 775 falling_edge = 1; 776 break; 777 } 778 779 REG_SET_4(OTG_TRIGA_CNTL, 0, 780 /* vsync signal from selected OTG pipe based 781 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 782 */ 783 OTG_TRIGA_SOURCE_SELECT, 20, 784 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 785 /* always detect falling edge */ 786 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 787 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 788 789 switch (crtc_tp->delay) { 790 case TRIGGER_DELAY_NEXT_LINE: 791 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 792 OTG_AUTO_FORCE_VSYNC_MODE, 1); 793 break; 794 case TRIGGER_DELAY_NEXT_PIXEL: 795 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 796 /* force H count to H_TOTAL and V count to V_TOTAL in 797 * progressive mode and V_TOTAL-1 in interlaced mode 798 */ 799 OTG_FORCE_COUNT_NOW_MODE, 2); 800 break; 801 } 802 } 803 804 void optc1_wait_for_state(struct timing_generator *optc, 805 enum crtc_state state) 806 { 807 struct optc *optc1 = DCN10TG_FROM_TG(optc); 808 809 switch (state) { 810 case CRTC_STATE_VBLANK: 811 REG_WAIT(OTG_STATUS, 812 OTG_V_BLANK, 1, 813 1, 100000); /* 1 vupdate at 10hz */ 814 break; 815 816 case CRTC_STATE_VACTIVE: 817 REG_WAIT(OTG_STATUS, 818 OTG_V_ACTIVE_DISP, 1, 819 1, 100000); /* 1 vupdate at 10hz */ 820 break; 821 822 default: 823 break; 824 } 825 } 826 827 void optc1_set_early_control( 828 struct timing_generator *optc, 829 uint32_t early_cntl) 830 { 831 /* asic design change, do not need this control 832 * empty for share caller logic 833 */ 834 } 835 836 837 void optc1_set_static_screen_control( 838 struct timing_generator *optc, 839 uint32_t event_triggers, 840 uint32_t num_frames) 841 { 842 struct optc *optc1 = DCN10TG_FROM_TG(optc); 843 844 // By register spec, it only takes 8 bit value 845 if (num_frames > 0xFF) 846 num_frames = 0xFF; 847 848 /* Bit 8 is no longer applicable in RV for PSR case, 849 * set bit 8 to 0 if given 850 */ 851 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 852 != 0) 853 event_triggers = event_triggers & 854 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 855 856 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 857 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 858 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 859 } 860 861 static void optc1_setup_manual_trigger(struct timing_generator *optc) 862 { 863 struct optc *optc1 = DCN10TG_FROM_TG(optc); 864 865 REG_SET(OTG_GLOBAL_CONTROL2, 0, 866 MANUAL_FLOW_CONTROL_SEL, optc->inst); 867 868 REG_SET_8(OTG_TRIGA_CNTL, 0, 869 OTG_TRIGA_SOURCE_SELECT, 22, 870 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 871 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 872 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 873 OTG_TRIGA_POLARITY_SELECT, 0, 874 OTG_TRIGA_FREQUENCY_SELECT, 0, 875 OTG_TRIGA_DELAY, 0, 876 OTG_TRIGA_CLEAR, 1); 877 } 878 879 static void optc1_program_manual_trigger(struct timing_generator *optc) 880 { 881 struct optc *optc1 = DCN10TG_FROM_TG(optc); 882 883 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 884 MANUAL_FLOW_CONTROL, 1); 885 886 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 887 MANUAL_FLOW_CONTROL, 0); 888 } 889 890 891 /** 892 ***************************************************************************** 893 * Function: set_drr 894 * 895 * @brief 896 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 897 * 898 ***************************************************************************** 899 */ 900 void optc1_set_drr( 901 struct timing_generator *optc, 902 const struct drr_params *params) 903 { 904 struct optc *optc1 = DCN10TG_FROM_TG(optc); 905 906 if (params != NULL && 907 params->vertical_total_max > 0 && 908 params->vertical_total_min > 0) { 909 910 if (params->vertical_total_mid != 0) { 911 912 REG_SET(OTG_V_TOTAL_MID, 0, 913 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 914 915 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 916 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 917 OTG_VTOTAL_MID_FRAME_NUM, 918 (uint8_t)params->vertical_total_mid_frame_num); 919 920 } 921 922 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1); 923 924 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 925 OTG_V_TOTAL_MIN_SEL, 1, 926 OTG_V_TOTAL_MAX_SEL, 1, 927 OTG_FORCE_LOCK_ON_EVENT, 0, 928 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 929 OTG_SET_V_TOTAL_MIN_MASK, 0); 930 931 // Setup manual flow control for EOF via TRIG_A 932 optc->funcs->setup_manual_trigger(optc); 933 934 } else { 935 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 936 OTG_SET_V_TOTAL_MIN_MASK, 0, 937 OTG_V_TOTAL_MIN_SEL, 0, 938 OTG_V_TOTAL_MAX_SEL, 0, 939 OTG_FORCE_LOCK_ON_EVENT, 0); 940 941 optc->funcs->set_vtotal_min_max(optc, 0, 0); 942 } 943 } 944 945 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max) 946 { 947 struct optc *optc1 = DCN10TG_FROM_TG(optc); 948 949 REG_SET(OTG_V_TOTAL_MAX, 0, 950 OTG_V_TOTAL_MAX, vtotal_max); 951 952 REG_SET(OTG_V_TOTAL_MIN, 0, 953 OTG_V_TOTAL_MIN, vtotal_min); 954 } 955 956 static void optc1_set_test_pattern( 957 struct timing_generator *optc, 958 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 959 * because this is not DP-specific (which is probably somewhere in DP 960 * encoder) */ 961 enum controller_dp_test_pattern test_pattern, 962 enum dc_color_depth color_depth) 963 { 964 struct optc *optc1 = DCN10TG_FROM_TG(optc); 965 enum test_pattern_color_format bit_depth; 966 enum test_pattern_dyn_range dyn_range; 967 enum test_pattern_mode mode; 968 uint32_t pattern_mask; 969 uint32_t pattern_data; 970 /* color ramp generator mixes 16-bits color */ 971 uint32_t src_bpc = 16; 972 /* requested bpc */ 973 uint32_t dst_bpc; 974 uint32_t index; 975 /* RGB values of the color bars. 976 * Produce two RGB colors: RGB0 - white (all Fs) 977 * and RGB1 - black (all 0s) 978 * (three RGB components for two colors) 979 */ 980 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 981 0x0000, 0x0000}; 982 /* dest color (converted to the specified color format) */ 983 uint16_t dst_color[6]; 984 uint32_t inc_base; 985 986 /* translate to bit depth */ 987 switch (color_depth) { 988 case COLOR_DEPTH_666: 989 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 990 break; 991 case COLOR_DEPTH_888: 992 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 993 break; 994 case COLOR_DEPTH_101010: 995 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 996 break; 997 case COLOR_DEPTH_121212: 998 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 999 break; 1000 default: 1001 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1002 break; 1003 } 1004 1005 switch (test_pattern) { 1006 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 1007 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 1008 { 1009 dyn_range = (test_pattern == 1010 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 1011 TEST_PATTERN_DYN_RANGE_CEA : 1012 TEST_PATTERN_DYN_RANGE_VESA); 1013 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 1014 1015 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 1016 OTG_TEST_PATTERN_VRES, 6, 1017 OTG_TEST_PATTERN_HRES, 6); 1018 1019 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1020 OTG_TEST_PATTERN_EN, 1, 1021 OTG_TEST_PATTERN_MODE, mode, 1022 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 1023 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1024 } 1025 break; 1026 1027 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 1028 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 1029 { 1030 mode = (test_pattern == 1031 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 1032 TEST_PATTERN_MODE_VERTICALBARS : 1033 TEST_PATTERN_MODE_HORIZONTALBARS); 1034 1035 switch (bit_depth) { 1036 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1037 dst_bpc = 6; 1038 break; 1039 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1040 dst_bpc = 8; 1041 break; 1042 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1043 dst_bpc = 10; 1044 break; 1045 default: 1046 dst_bpc = 8; 1047 break; 1048 } 1049 1050 /* adjust color to the required colorFormat */ 1051 for (index = 0; index < 6; index++) { 1052 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1053 * (srcBpc - dstBpc); 1054 */ 1055 dst_color[index] = 1056 src_color[index] >> (src_bpc - dst_bpc); 1057 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1058 * lowest 6 are hardwired to ZERO 1059 * color bits should be left aligned to MSB 1060 * XXXXXXXXXX000000 for 10 bit, 1061 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1062 */ 1063 dst_color[index] <<= (16 - dst_bpc); 1064 } 1065 1066 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1067 1068 /* We have to write the mask before data, similar to pipeline. 1069 * For example, for 8 bpc, if we want RGB0 to be magenta, 1070 * and RGB1 to be cyan, 1071 * we need to make 7 writes: 1072 * MASK DATA 1073 * 000001 00000000 00000000 set mask to R0 1074 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1075 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1076 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1077 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1078 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1079 * 100000 11111111 00000000 B1 255, 0xFF00 1080 * 1081 * we will make a loop of 6 in which we prepare the mask, 1082 * then write, then prepare the color for next write. 1083 * first iteration will write mask only, 1084 * but each next iteration color prepared in 1085 * previous iteration will be written within new mask, 1086 * the last component will written separately, 1087 * mask is not changing between 6th and 7th write 1088 * and color will be prepared by last iteration 1089 */ 1090 1091 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1092 * is B1, G1, R1, B0, G0, R0 1093 */ 1094 pattern_data = 0; 1095 for (index = 0; index < 6; index++) { 1096 /* prepare color mask, first write PATTERN_DATA 1097 * will have all zeros 1098 */ 1099 pattern_mask = (1 << index); 1100 1101 /* write color component */ 1102 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1103 OTG_TEST_PATTERN_MASK, pattern_mask, 1104 OTG_TEST_PATTERN_DATA, pattern_data); 1105 1106 /* prepare next color component, 1107 * will be written in the next iteration 1108 */ 1109 pattern_data = dst_color[index]; 1110 } 1111 /* write last color component, 1112 * it's been already prepared in the loop 1113 */ 1114 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1115 OTG_TEST_PATTERN_MASK, pattern_mask, 1116 OTG_TEST_PATTERN_DATA, pattern_data); 1117 1118 /* enable test pattern */ 1119 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1120 OTG_TEST_PATTERN_EN, 1, 1121 OTG_TEST_PATTERN_MODE, mode, 1122 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1123 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1124 } 1125 break; 1126 1127 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1128 { 1129 mode = (bit_depth == 1130 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1131 TEST_PATTERN_MODE_DUALRAMP_RGB : 1132 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1133 1134 switch (bit_depth) { 1135 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1136 dst_bpc = 6; 1137 break; 1138 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1139 dst_bpc = 8; 1140 break; 1141 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1142 dst_bpc = 10; 1143 break; 1144 default: 1145 dst_bpc = 8; 1146 break; 1147 } 1148 1149 /* increment for the first ramp for one color gradation 1150 * 1 gradation for 6-bit color is 2^10 1151 * gradations in 16-bit color 1152 */ 1153 inc_base = (src_bpc - dst_bpc); 1154 1155 switch (bit_depth) { 1156 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1157 { 1158 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1159 OTG_TEST_PATTERN_INC0, inc_base, 1160 OTG_TEST_PATTERN_INC1, 0, 1161 OTG_TEST_PATTERN_HRES, 6, 1162 OTG_TEST_PATTERN_VRES, 6, 1163 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1164 } 1165 break; 1166 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1167 { 1168 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1169 OTG_TEST_PATTERN_INC0, inc_base, 1170 OTG_TEST_PATTERN_INC1, 0, 1171 OTG_TEST_PATTERN_HRES, 8, 1172 OTG_TEST_PATTERN_VRES, 6, 1173 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1174 } 1175 break; 1176 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1177 { 1178 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1179 OTG_TEST_PATTERN_INC0, inc_base, 1180 OTG_TEST_PATTERN_INC1, inc_base + 2, 1181 OTG_TEST_PATTERN_HRES, 8, 1182 OTG_TEST_PATTERN_VRES, 5, 1183 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1184 } 1185 break; 1186 default: 1187 break; 1188 } 1189 1190 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1191 1192 /* enable test pattern */ 1193 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1194 1195 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1196 OTG_TEST_PATTERN_EN, 1, 1197 OTG_TEST_PATTERN_MODE, mode, 1198 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1199 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1200 } 1201 break; 1202 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1203 { 1204 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1205 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1206 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1207 } 1208 break; 1209 default: 1210 break; 1211 1212 } 1213 } 1214 1215 void optc1_get_crtc_scanoutpos( 1216 struct timing_generator *optc, 1217 uint32_t *v_blank_start, 1218 uint32_t *v_blank_end, 1219 uint32_t *h_position, 1220 uint32_t *v_position) 1221 { 1222 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1223 struct crtc_position position; 1224 1225 REG_GET_2(OTG_V_BLANK_START_END, 1226 OTG_V_BLANK_START, v_blank_start, 1227 OTG_V_BLANK_END, v_blank_end); 1228 1229 optc1_get_position(optc, &position); 1230 1231 *h_position = position.horizontal_count; 1232 *v_position = position.vertical_count; 1233 } 1234 1235 static void optc1_enable_stereo(struct timing_generator *optc, 1236 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1237 { 1238 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1239 1240 if (flags) { 1241 uint32_t stereo_en; 1242 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1243 1244 if (flags->PROGRAM_STEREO) 1245 REG_UPDATE_3(OTG_STEREO_CONTROL, 1246 OTG_STEREO_EN, stereo_en, 1247 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1248 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1249 1250 if (flags->PROGRAM_POLARITY) 1251 REG_UPDATE(OTG_STEREO_CONTROL, 1252 OTG_STEREO_EYE_FLAG_POLARITY, 1253 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1254 1255 if (flags->DISABLE_STEREO_DP_SYNC) 1256 REG_UPDATE(OTG_STEREO_CONTROL, 1257 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1258 1259 if (flags->PROGRAM_STEREO) 1260 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1261 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1262 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1263 1264 } 1265 } 1266 1267 void optc1_program_stereo(struct timing_generator *optc, 1268 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1269 { 1270 if (flags->PROGRAM_STEREO) 1271 optc1_enable_stereo(optc, timing, flags); 1272 else 1273 optc1_disable_stereo(optc); 1274 } 1275 1276 1277 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1278 { 1279 bool ret = false; 1280 uint32_t left_eye = 0; 1281 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1282 1283 REG_GET(OTG_STEREO_STATUS, 1284 OTG_STEREO_CURRENT_EYE, &left_eye); 1285 if (left_eye == 1) 1286 ret = true; 1287 else 1288 ret = false; 1289 1290 return ret; 1291 } 1292 1293 bool optc1_get_hw_timing(struct timing_generator *tg, 1294 struct dc_crtc_timing *hw_crtc_timing) 1295 { 1296 struct dcn_otg_state s = {0}; 1297 1298 if (tg == NULL || hw_crtc_timing == NULL) 1299 return false; 1300 1301 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1302 1303 hw_crtc_timing->h_total = s.h_total + 1; 1304 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1305 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1306 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1307 1308 hw_crtc_timing->v_total = s.v_total + 1; 1309 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1310 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1311 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1312 1313 return true; 1314 } 1315 1316 1317 void optc1_read_otg_state(struct optc *optc1, 1318 struct dcn_otg_state *s) 1319 { 1320 REG_GET(OTG_CONTROL, 1321 OTG_MASTER_EN, &s->otg_enabled); 1322 1323 REG_GET_2(OTG_V_BLANK_START_END, 1324 OTG_V_BLANK_START, &s->v_blank_start, 1325 OTG_V_BLANK_END, &s->v_blank_end); 1326 1327 REG_GET(OTG_V_SYNC_A_CNTL, 1328 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1329 1330 REG_GET(OTG_V_TOTAL, 1331 OTG_V_TOTAL, &s->v_total); 1332 1333 REG_GET(OTG_V_TOTAL_MAX, 1334 OTG_V_TOTAL_MAX, &s->v_total_max); 1335 1336 REG_GET(OTG_V_TOTAL_MIN, 1337 OTG_V_TOTAL_MIN, &s->v_total_min); 1338 1339 REG_GET(OTG_V_TOTAL_CONTROL, 1340 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1341 1342 REG_GET(OTG_V_TOTAL_CONTROL, 1343 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1344 1345 REG_GET_2(OTG_V_SYNC_A, 1346 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1347 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1348 1349 REG_GET_2(OTG_H_BLANK_START_END, 1350 OTG_H_BLANK_START, &s->h_blank_start, 1351 OTG_H_BLANK_END, &s->h_blank_end); 1352 1353 REG_GET_2(OTG_H_SYNC_A, 1354 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1355 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1356 1357 REG_GET(OTG_H_SYNC_A_CNTL, 1358 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1359 1360 REG_GET(OTG_H_TOTAL, 1361 OTG_H_TOTAL, &s->h_total); 1362 1363 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1364 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1365 1366 REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL, 1367 OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &s->vertical_interrupt1_en); 1368 1369 REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION, 1370 OTG_VERTICAL_INTERRUPT1_LINE_START, &s->vertical_interrupt1_line); 1371 1372 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 1373 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en); 1374 1375 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION, 1376 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line); 1377 } 1378 1379 bool optc1_get_otg_active_size(struct timing_generator *optc, 1380 uint32_t *otg_active_width, 1381 uint32_t *otg_active_height) 1382 { 1383 uint32_t otg_enabled; 1384 uint32_t v_blank_start; 1385 uint32_t v_blank_end; 1386 uint32_t h_blank_start; 1387 uint32_t h_blank_end; 1388 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1389 1390 1391 REG_GET(OTG_CONTROL, 1392 OTG_MASTER_EN, &otg_enabled); 1393 1394 if (otg_enabled == 0) 1395 return false; 1396 1397 REG_GET_2(OTG_V_BLANK_START_END, 1398 OTG_V_BLANK_START, &v_blank_start, 1399 OTG_V_BLANK_END, &v_blank_end); 1400 1401 REG_GET_2(OTG_H_BLANK_START_END, 1402 OTG_H_BLANK_START, &h_blank_start, 1403 OTG_H_BLANK_END, &h_blank_end); 1404 1405 *otg_active_width = v_blank_start - v_blank_end; 1406 *otg_active_height = h_blank_start - h_blank_end; 1407 return true; 1408 } 1409 1410 void optc1_clear_optc_underflow(struct timing_generator *optc) 1411 { 1412 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1413 1414 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1415 } 1416 1417 void optc1_tg_init(struct timing_generator *optc) 1418 { 1419 optc1_set_blank_data_double_buffer(optc, true); 1420 optc1_set_timing_double_buffer(optc, true); 1421 optc1_clear_optc_underflow(optc); 1422 } 1423 1424 bool optc1_is_tg_enabled(struct timing_generator *optc) 1425 { 1426 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1427 uint32_t otg_enabled = 0; 1428 1429 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1430 1431 return (otg_enabled != 0); 1432 1433 } 1434 1435 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1436 { 1437 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1438 uint32_t underflow_occurred = 0; 1439 1440 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1441 OPTC_UNDERFLOW_OCCURRED_STATUS, 1442 &underflow_occurred); 1443 1444 return (underflow_occurred == 1); 1445 } 1446 1447 bool optc1_configure_crc(struct timing_generator *optc, 1448 const struct crc_params *params) 1449 { 1450 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1451 1452 /* Cannot configure crc on a CRTC that is disabled */ 1453 if (!optc1_is_tg_enabled(optc)) 1454 return false; 1455 1456 REG_WRITE(OTG_CRC_CNTL, 0); 1457 1458 if (!params->enable) 1459 return true; 1460 1461 /* Program frame boundaries */ 1462 /* Window A x axis start and end. */ 1463 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1464 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1465 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1466 1467 /* Window A y axis start and end. */ 1468 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1469 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1470 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1471 1472 /* Window B x axis start and end. */ 1473 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1474 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1475 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1476 1477 /* Window B y axis start and end. */ 1478 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1479 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1480 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1481 1482 /* Set crc mode and selection, and enable. Only using CRC0*/ 1483 REG_UPDATE_3(OTG_CRC_CNTL, 1484 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1485 OTG_CRC0_SELECT, params->selection, 1486 OTG_CRC_EN, 1); 1487 1488 return true; 1489 } 1490 1491 /** 1492 * optc1_get_crc - Capture CRC result per component 1493 * 1494 * @optc: timing_generator instance. 1495 * @r_cr: 16-bit primary CRC signature for red data. 1496 * @g_y: 16-bit primary CRC signature for green data. 1497 * @b_cb: 16-bit primary CRC signature for blue data. 1498 * 1499 * This function reads the CRC signature from the OPTC registers. Notice that 1500 * we have three registers to keep the CRC result per color component (RGB). 1501 * 1502 * Returns: 1503 * If CRC is disabled, return false; otherwise, return true, and the CRC 1504 * results in the parameters. 1505 */ 1506 bool optc1_get_crc(struct timing_generator *optc, 1507 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1508 { 1509 uint32_t field = 0; 1510 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1511 1512 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1513 1514 /* Early return if CRC is not enabled for this CRTC */ 1515 if (!field) 1516 return false; 1517 1518 /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */ 1519 REG_GET_2(OTG_CRC0_DATA_RG, 1520 CRC0_R_CR, r_cr, 1521 CRC0_G_Y, g_y); 1522 1523 /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */ 1524 REG_GET(OTG_CRC0_DATA_B, 1525 CRC0_B_CB, b_cb); 1526 1527 return true; 1528 } 1529 1530 static const struct timing_generator_funcs dcn10_tg_funcs = { 1531 .validate_timing = optc1_validate_timing, 1532 .program_timing = optc1_program_timing, 1533 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1534 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1535 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1536 .program_global_sync = optc1_program_global_sync, 1537 .enable_crtc = optc1_enable_crtc, 1538 .disable_crtc = optc1_disable_crtc, 1539 /* used by enable_timing_synchronization. Not need for FPGA */ 1540 .is_counter_moving = optc1_is_counter_moving, 1541 .get_position = optc1_get_position, 1542 .get_frame_count = optc1_get_vblank_counter, 1543 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1544 .get_otg_active_size = optc1_get_otg_active_size, 1545 .set_early_control = optc1_set_early_control, 1546 /* used by enable_timing_synchronization. Not need for FPGA */ 1547 .wait_for_state = optc1_wait_for_state, 1548 .set_blank = optc1_set_blank, 1549 .is_blanked = optc1_is_blanked, 1550 .set_blank_color = optc1_program_blank_color, 1551 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1552 .enable_reset_trigger = optc1_enable_reset_trigger, 1553 .enable_crtc_reset = optc1_enable_crtc_reset, 1554 .disable_reset_trigger = optc1_disable_reset_trigger, 1555 .lock = optc1_lock, 1556 .unlock = optc1_unlock, 1557 .enable_optc_clock = optc1_enable_optc_clock, 1558 .set_drr = optc1_set_drr, 1559 .get_last_used_drr_vtotal = NULL, 1560 .set_vtotal_min_max = optc1_set_vtotal_min_max, 1561 .set_static_screen_control = optc1_set_static_screen_control, 1562 .set_test_pattern = optc1_set_test_pattern, 1563 .program_stereo = optc1_program_stereo, 1564 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1565 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1566 .tg_init = optc1_tg_init, 1567 .is_tg_enabled = optc1_is_tg_enabled, 1568 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1569 .clear_optc_underflow = optc1_clear_optc_underflow, 1570 .get_crc = optc1_get_crc, 1571 .configure_crc = optc1_configure_crc, 1572 .set_vtg_params = optc1_set_vtg_params, 1573 .program_manual_trigger = optc1_program_manual_trigger, 1574 .setup_manual_trigger = optc1_setup_manual_trigger, 1575 .get_hw_timing = optc1_get_hw_timing, 1576 }; 1577 1578 void dcn10_timing_generator_init(struct optc *optc1) 1579 { 1580 optc1->base.funcs = &dcn10_tg_funcs; 1581 1582 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1583 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1584 1585 optc1->min_h_blank = 32; 1586 optc1->min_v_blank = 3; 1587 optc1->min_v_blank_interlace = 5; 1588 optc1->min_h_sync_width = 4; 1589 optc1->min_v_sync_width = 1; 1590 } 1591 1592 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1593 * 1594 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1595 * containter rate. 1596 * 1597 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1598 * halved to maintain the correct pixel rate. 1599 * 1600 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1601 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1602 * 1603 */ 1604 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1605 { 1606 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1607 1608 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1609 && !timing->dsc_cfg.ycbcr422_simple); 1610 return two_pix; 1611 } 1612 1613