1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 50 { 51 if (timing->flags.INTERLACE == 1) { 52 if (timing->v_front_porch < 2) 53 timing->v_front_porch = 2; 54 } else { 55 if (timing->v_front_porch < 1) 56 timing->v_front_porch = 1; 57 } 58 } 59 60 void optc1_program_global_sync( 61 struct timing_generator *optc, 62 int vready_offset, 63 int vstartup_start, 64 int vupdate_offset, 65 int vupdate_width) 66 { 67 struct optc *optc1 = DCN10TG_FROM_TG(optc); 68 69 optc1->vready_offset = vready_offset; 70 optc1->vstartup_start = vstartup_start; 71 optc1->vupdate_offset = vupdate_offset; 72 optc1->vupdate_width = vupdate_width; 73 74 if (optc1->vstartup_start == 0) { 75 BREAK_TO_DEBUGGER(); 76 return; 77 } 78 79 REG_SET(OTG_VSTARTUP_PARAM, 0, 80 VSTARTUP_START, optc1->vstartup_start); 81 82 REG_SET_2(OTG_VUPDATE_PARAM, 0, 83 VUPDATE_OFFSET, optc1->vupdate_offset, 84 VUPDATE_WIDTH, optc1->vupdate_width); 85 86 REG_SET(OTG_VREADY_PARAM, 0, 87 VREADY_OFFSET, optc1->vready_offset); 88 } 89 90 static void optc1_disable_stereo(struct timing_generator *optc) 91 { 92 struct optc *optc1 = DCN10TG_FROM_TG(optc); 93 94 REG_SET(OTG_STEREO_CONTROL, 0, 95 OTG_STEREO_EN, 0); 96 97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 98 OTG_3D_STRUCTURE_EN, 0, 99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 100 } 101 102 void optc1_setup_vertical_interrupt0( 103 struct timing_generator *optc, 104 uint32_t start_line, 105 uint32_t end_line) 106 { 107 struct optc *optc1 = DCN10TG_FROM_TG(optc); 108 109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 112 } 113 114 void optc1_setup_vertical_interrupt1( 115 struct timing_generator *optc, 116 uint32_t start_line) 117 { 118 struct optc *optc1 = DCN10TG_FROM_TG(optc); 119 120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 122 } 123 124 void optc1_setup_vertical_interrupt2( 125 struct timing_generator *optc, 126 uint32_t start_line) 127 { 128 struct optc *optc1 = DCN10TG_FROM_TG(optc); 129 130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 132 } 133 134 /** 135 * program_timing_generator used by mode timing set 136 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 137 * Including SYNC. Call BIOS command table to program Timings. 138 */ 139 void optc1_program_timing( 140 struct timing_generator *optc, 141 const struct dc_crtc_timing *dc_crtc_timing, 142 int vready_offset, 143 int vstartup_start, 144 int vupdate_offset, 145 int vupdate_width, 146 const enum signal_type signal, 147 bool use_vbios) 148 { 149 struct dc_crtc_timing patched_crtc_timing; 150 uint32_t asic_blank_end; 151 uint32_t asic_blank_start; 152 uint32_t v_total; 153 uint32_t v_sync_end; 154 uint32_t h_sync_polarity, v_sync_polarity; 155 uint32_t start_point = 0; 156 uint32_t field_num = 0; 157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 158 159 struct optc *optc1 = DCN10TG_FROM_TG(optc); 160 161 optc1->signal = signal; 162 optc1->vready_offset = vready_offset; 163 optc1->vstartup_start = vstartup_start; 164 optc1->vupdate_offset = vupdate_offset; 165 optc1->vupdate_width = vupdate_width; 166 patched_crtc_timing = *dc_crtc_timing; 167 apply_front_porch_workaround(&patched_crtc_timing); 168 optc1->orginal_patched_timing = patched_crtc_timing; 169 170 /* Load horizontal timing */ 171 172 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 173 REG_SET(OTG_H_TOTAL, 0, 174 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 175 176 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 177 REG_UPDATE_2(OTG_H_SYNC_A, 178 OTG_H_SYNC_A_START, 0, 179 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 180 181 /* blank_start = line end - front porch */ 182 asic_blank_start = patched_crtc_timing.h_total - 183 patched_crtc_timing.h_front_porch; 184 185 /* blank_end = blank_start - active */ 186 asic_blank_end = asic_blank_start - 187 patched_crtc_timing.h_border_right - 188 patched_crtc_timing.h_addressable - 189 patched_crtc_timing.h_border_left; 190 191 REG_UPDATE_2(OTG_H_BLANK_START_END, 192 OTG_H_BLANK_START, asic_blank_start, 193 OTG_H_BLANK_END, asic_blank_end); 194 195 /* h_sync polarity */ 196 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 197 0 : 1; 198 199 REG_UPDATE(OTG_H_SYNC_A_CNTL, 200 OTG_H_SYNC_A_POL, h_sync_polarity); 201 202 v_total = patched_crtc_timing.v_total - 1; 203 204 REG_SET(OTG_V_TOTAL, 0, 205 OTG_V_TOTAL, v_total); 206 207 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 208 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 209 */ 210 REG_SET(OTG_V_TOTAL_MAX, 0, 211 OTG_V_TOTAL_MAX, v_total); 212 REG_SET(OTG_V_TOTAL_MIN, 0, 213 OTG_V_TOTAL_MIN, v_total); 214 215 /* v_sync_start = 0, v_sync_end = v_sync_width */ 216 v_sync_end = patched_crtc_timing.v_sync_width; 217 218 REG_UPDATE_2(OTG_V_SYNC_A, 219 OTG_V_SYNC_A_START, 0, 220 OTG_V_SYNC_A_END, v_sync_end); 221 222 /* blank_start = frame end - front porch */ 223 asic_blank_start = patched_crtc_timing.v_total - 224 patched_crtc_timing.v_front_porch; 225 226 /* blank_end = blank_start - active */ 227 asic_blank_end = asic_blank_start - 228 patched_crtc_timing.v_border_bottom - 229 patched_crtc_timing.v_addressable - 230 patched_crtc_timing.v_border_top; 231 232 REG_UPDATE_2(OTG_V_BLANK_START_END, 233 OTG_V_BLANK_START, asic_blank_start, 234 OTG_V_BLANK_END, asic_blank_end); 235 236 /* v_sync polarity */ 237 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 238 0 : 1; 239 240 REG_UPDATE(OTG_V_SYNC_A_CNTL, 241 OTG_V_SYNC_A_POL, v_sync_polarity); 242 243 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT || 244 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 245 optc1->signal == SIGNAL_TYPE_EDP) { 246 start_point = 1; 247 if (patched_crtc_timing.flags.INTERLACE == 1) 248 field_num = 1; 249 } 250 251 /* Interlace */ 252 if (REG(OTG_INTERLACE_CONTROL)) { 253 if (patched_crtc_timing.flags.INTERLACE == 1) 254 REG_UPDATE(OTG_INTERLACE_CONTROL, 255 OTG_INTERLACE_ENABLE, 1); 256 else 257 REG_UPDATE(OTG_INTERLACE_CONTROL, 258 OTG_INTERLACE_ENABLE, 0); 259 } 260 261 /* VTG enable set to 0 first VInit */ 262 REG_UPDATE(CONTROL, 263 VTG0_ENABLE, 0); 264 265 /* original code is using VTG offset to address OTG reg, seems wrong */ 266 REG_UPDATE_2(OTG_CONTROL, 267 OTG_START_POINT_CNTL, start_point, 268 OTG_FIELD_NUMBER_CNTL, field_num); 269 270 optc->funcs->program_global_sync(optc, 271 vready_offset, 272 vstartup_start, 273 vupdate_offset, 274 vupdate_width); 275 276 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true); 277 278 /* TODO 279 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 280 * program_horz_count_by_2 281 * for DVI 30bpp mode, 0 otherwise 282 * program_horz_count_by_2(optc, &patched_crtc_timing); 283 */ 284 285 /* Enable stereo - only when we need to pack 3D frame. Other types 286 * of stereo handled in explicit call 287 */ 288 289 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) 290 h_div = H_TIMING_DIV_BY2; 291 292 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { 293 uint32_t data_fmt = 0; 294 295 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 296 data_fmt = 1; 297 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 298 data_fmt = 2; 299 300 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 301 } 302 303 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { 304 if (optc1->opp_count == 4) 305 h_div = H_TIMING_DIV_BY4; 306 307 REG_UPDATE(OTG_H_TIMING_CNTL, 308 OTG_H_TIMING_DIV_MODE, h_div); 309 } else { 310 REG_UPDATE(OTG_H_TIMING_CNTL, 311 OTG_H_TIMING_DIV_BY2, h_div); 312 } 313 } 314 315 void optc1_set_vtg_params(struct timing_generator *optc, 316 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2) 317 { 318 struct dc_crtc_timing patched_crtc_timing; 319 uint32_t asic_blank_end; 320 uint32_t v_init; 321 uint32_t v_fp2 = 0; 322 int32_t vertical_line_start; 323 324 struct optc *optc1 = DCN10TG_FROM_TG(optc); 325 326 patched_crtc_timing = *dc_crtc_timing; 327 apply_front_porch_workaround(&patched_crtc_timing); 328 329 /* VCOUNT_INIT is the start of blank */ 330 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; 331 332 /* end of blank = v_init - active */ 333 asic_blank_end = v_init - 334 patched_crtc_timing.v_border_bottom - 335 patched_crtc_timing.v_addressable - 336 patched_crtc_timing.v_border_top; 337 338 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */ 339 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; 340 if (vertical_line_start < 0) 341 v_fp2 = -vertical_line_start; 342 343 /* Interlace */ 344 if (REG(OTG_INTERLACE_CONTROL)) { 345 if (patched_crtc_timing.flags.INTERLACE == 1) { 346 v_init = v_init / 2; 347 if ((optc1->vstartup_start/2)*2 > asic_blank_end) 348 v_fp2 = v_fp2 / 2; 349 } 350 } 351 352 if (program_fp2) 353 REG_UPDATE_2(CONTROL, 354 VTG0_FP2, v_fp2, 355 VTG0_VCOUNT_INIT, v_init); 356 else 357 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init); 358 } 359 360 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 361 { 362 struct optc *optc1 = DCN10TG_FROM_TG(optc); 363 364 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 365 366 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 367 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 368 } 369 370 /** 371 * optc1_set_timing_double_buffer() - DRR double buffering control 372 * 373 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 374 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 375 * 376 * Options: any time, start of frame, dp start of frame (range timing) 377 */ 378 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) 379 { 380 struct optc *optc1 = DCN10TG_FROM_TG(optc); 381 uint32_t mode = enable ? 2 : 0; 382 383 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 384 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode); 385 } 386 387 /** 388 * unblank_crtc 389 * Call ASIC Control Object to UnBlank CRTC. 390 */ 391 static void optc1_unblank_crtc(struct timing_generator *optc) 392 { 393 struct optc *optc1 = DCN10TG_FROM_TG(optc); 394 395 REG_UPDATE_2(OTG_BLANK_CONTROL, 396 OTG_BLANK_DATA_EN, 0, 397 OTG_BLANK_DE_MODE, 0); 398 399 /* W/A for automated testing 400 * Automated testing will fail underflow test as there 401 * sporadic underflows which occur during the optc blank 402 * sequence. As a w/a, clear underflow on unblank. 403 * This prevents the failure, but will not mask actual 404 * underflow that affect real use cases. 405 */ 406 optc1_clear_optc_underflow(optc); 407 } 408 409 /** 410 * blank_crtc 411 * Call ASIC Control Object to Blank CRTC. 412 */ 413 414 static void optc1_blank_crtc(struct timing_generator *optc) 415 { 416 struct optc *optc1 = DCN10TG_FROM_TG(optc); 417 418 REG_UPDATE_2(OTG_BLANK_CONTROL, 419 OTG_BLANK_DATA_EN, 1, 420 OTG_BLANK_DE_MODE, 0); 421 422 optc1_set_blank_data_double_buffer(optc, false); 423 } 424 425 void optc1_set_blank(struct timing_generator *optc, 426 bool enable_blanking) 427 { 428 if (enable_blanking) 429 optc1_blank_crtc(optc); 430 else 431 optc1_unblank_crtc(optc); 432 } 433 434 bool optc1_is_blanked(struct timing_generator *optc) 435 { 436 struct optc *optc1 = DCN10TG_FROM_TG(optc); 437 uint32_t blank_en; 438 uint32_t blank_state; 439 440 REG_GET_2(OTG_BLANK_CONTROL, 441 OTG_BLANK_DATA_EN, &blank_en, 442 OTG_CURRENT_BLANK_STATE, &blank_state); 443 444 return blank_en && blank_state; 445 } 446 447 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 448 { 449 struct optc *optc1 = DCN10TG_FROM_TG(optc); 450 451 if (enable) { 452 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 453 OPTC_INPUT_CLK_EN, 1, 454 OPTC_INPUT_CLK_GATE_DIS, 1); 455 456 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 457 OPTC_INPUT_CLK_ON, 1, 458 1, 1000); 459 460 /* Enable clock */ 461 REG_UPDATE_2(OTG_CLOCK_CONTROL, 462 OTG_CLOCK_EN, 1, 463 OTG_CLOCK_GATE_DIS, 1); 464 REG_WAIT(OTG_CLOCK_CONTROL, 465 OTG_CLOCK_ON, 1, 466 1, 1000); 467 } else { 468 REG_UPDATE_2(OTG_CLOCK_CONTROL, 469 OTG_CLOCK_GATE_DIS, 0, 470 OTG_CLOCK_EN, 0); 471 472 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 473 OPTC_INPUT_CLK_GATE_DIS, 0, 474 OPTC_INPUT_CLK_EN, 0); 475 } 476 } 477 478 /** 479 * Enable CRTC 480 * Enable CRTC - call ASIC Control Object to enable Timing generator. 481 */ 482 static bool optc1_enable_crtc(struct timing_generator *optc) 483 { 484 /* TODO FPGA wait for answer 485 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 486 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 487 */ 488 struct optc *optc1 = DCN10TG_FROM_TG(optc); 489 490 /* opp instance for OTG. For DCN1.0, ODM is remoed. 491 * OPP and OPTC should 1:1 mapping 492 */ 493 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 494 OPTC_SRC_SEL, optc->inst); 495 496 /* VTG enable first is for HW workaround */ 497 REG_UPDATE(CONTROL, 498 VTG0_ENABLE, 1); 499 500 REG_SEQ_START(); 501 502 /* Enable CRTC */ 503 REG_UPDATE_2(OTG_CONTROL, 504 OTG_DISABLE_POINT_CNTL, 3, 505 OTG_MASTER_EN, 1); 506 507 REG_SEQ_SUBMIT(); 508 REG_SEQ_WAIT_DONE(); 509 510 return true; 511 } 512 513 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 514 bool optc1_disable_crtc(struct timing_generator *optc) 515 { 516 struct optc *optc1 = DCN10TG_FROM_TG(optc); 517 518 /* disable otg request until end of the first line 519 * in the vertical blank region 520 */ 521 REG_UPDATE_2(OTG_CONTROL, 522 OTG_DISABLE_POINT_CNTL, 3, 523 OTG_MASTER_EN, 0); 524 525 REG_UPDATE(CONTROL, 526 VTG0_ENABLE, 0); 527 528 /* CRTC disabled, so disable clock. */ 529 REG_WAIT(OTG_CLOCK_CONTROL, 530 OTG_BUSY, 0, 531 1, 100000); 532 533 return true; 534 } 535 536 537 void optc1_program_blank_color( 538 struct timing_generator *optc, 539 const struct tg_color *black_color) 540 { 541 struct optc *optc1 = DCN10TG_FROM_TG(optc); 542 543 REG_SET_3(OTG_BLACK_COLOR, 0, 544 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 545 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 546 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 547 } 548 549 bool optc1_validate_timing( 550 struct timing_generator *optc, 551 const struct dc_crtc_timing *timing) 552 { 553 uint32_t v_blank; 554 uint32_t h_blank; 555 uint32_t min_v_blank; 556 struct optc *optc1 = DCN10TG_FROM_TG(optc); 557 558 ASSERT(timing != NULL); 559 560 v_blank = (timing->v_total - timing->v_addressable - 561 timing->v_border_top - timing->v_border_bottom); 562 563 h_blank = (timing->h_total - timing->h_addressable - 564 timing->h_border_right - 565 timing->h_border_left); 566 567 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 568 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 569 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 570 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 571 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 572 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 573 return false; 574 575 /* Temporarily blocking interlacing mode until it's supported */ 576 if (timing->flags.INTERLACE == 1) 577 return false; 578 579 /* Check maximum number of pixels supported by Timing Generator 580 * (Currently will never fail, in order to fail needs display which 581 * needs more than 8192 horizontal and 582 * more than 8192 vertical total pixels) 583 */ 584 if (timing->h_total > optc1->max_h_total || 585 timing->v_total > optc1->max_v_total) 586 return false; 587 588 589 if (h_blank < optc1->min_h_blank) 590 return false; 591 592 if (timing->h_sync_width < optc1->min_h_sync_width || 593 timing->v_sync_width < optc1->min_v_sync_width) 594 return false; 595 596 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 597 598 if (v_blank < min_v_blank) 599 return false; 600 601 return true; 602 603 } 604 605 /* 606 * get_vblank_counter 607 * 608 * @brief 609 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 610 * holds the counter of frames. 611 * 612 * @param 613 * struct timing_generator *optc - [in] timing generator which controls the 614 * desired CRTC 615 * 616 * @return 617 * Counter of frames, which should equal to number of vblanks. 618 */ 619 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 620 { 621 struct optc *optc1 = DCN10TG_FROM_TG(optc); 622 uint32_t frame_count; 623 624 REG_GET(OTG_STATUS_FRAME_COUNT, 625 OTG_FRAME_COUNT, &frame_count); 626 627 return frame_count; 628 } 629 630 void optc1_lock(struct timing_generator *optc) 631 { 632 struct optc *optc1 = DCN10TG_FROM_TG(optc); 633 uint32_t regval = 0; 634 635 regval = REG_READ(OTG_CONTROL); 636 637 /* otg is not running, do not need to be locked */ 638 if ((regval & 0x1) == 0x0) 639 return; 640 641 REG_SET(OTG_GLOBAL_CONTROL0, 0, 642 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 643 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 644 OTG_MASTER_UPDATE_LOCK, 1); 645 646 /* Should be fast, status does not update on maximus */ 647 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) { 648 649 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 650 UPDATE_LOCK_STATUS, 1, 651 1, 10); 652 } 653 } 654 655 void optc1_unlock(struct timing_generator *optc) 656 { 657 struct optc *optc1 = DCN10TG_FROM_TG(optc); 658 659 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 660 OTG_MASTER_UPDATE_LOCK, 0); 661 } 662 663 bool optc1_is_locked(struct timing_generator *optc) 664 { 665 struct optc *optc1 = DCN10TG_FROM_TG(optc); 666 uint32_t locked; 667 668 REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &locked); 669 670 return (locked == 1); 671 } 672 673 void optc1_get_position(struct timing_generator *optc, 674 struct crtc_position *position) 675 { 676 struct optc *optc1 = DCN10TG_FROM_TG(optc); 677 678 REG_GET_2(OTG_STATUS_POSITION, 679 OTG_HORZ_COUNT, &position->horizontal_count, 680 OTG_VERT_COUNT, &position->vertical_count); 681 682 REG_GET(OTG_NOM_VERT_POSITION, 683 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 684 } 685 686 bool optc1_is_counter_moving(struct timing_generator *optc) 687 { 688 struct crtc_position position1, position2; 689 690 optc->funcs->get_position(optc, &position1); 691 optc->funcs->get_position(optc, &position2); 692 693 if (position1.horizontal_count == position2.horizontal_count && 694 position1.vertical_count == position2.vertical_count) 695 return false; 696 else 697 return true; 698 } 699 700 bool optc1_did_triggered_reset_occur( 701 struct timing_generator *optc) 702 { 703 struct optc *optc1 = DCN10TG_FROM_TG(optc); 704 uint32_t occurred_force, occurred_vsync; 705 706 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 707 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 708 709 REG_GET(OTG_VERT_SYNC_CONTROL, 710 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 711 712 return occurred_vsync != 0 || occurred_force != 0; 713 } 714 715 void optc1_disable_reset_trigger(struct timing_generator *optc) 716 { 717 struct optc *optc1 = DCN10TG_FROM_TG(optc); 718 719 REG_WRITE(OTG_TRIGA_CNTL, 0); 720 721 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 722 OTG_FORCE_COUNT_NOW_CLEAR, 1); 723 724 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 725 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 726 } 727 728 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 729 { 730 struct optc *optc1 = DCN10TG_FROM_TG(optc); 731 uint32_t falling_edge; 732 733 REG_GET(OTG_V_SYNC_A_CNTL, 734 OTG_V_SYNC_A_POL, &falling_edge); 735 736 if (falling_edge) 737 REG_SET_3(OTG_TRIGA_CNTL, 0, 738 /* vsync signal from selected OTG pipe based 739 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 740 */ 741 OTG_TRIGA_SOURCE_SELECT, 20, 742 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 743 /* always detect falling edge */ 744 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 745 else 746 REG_SET_3(OTG_TRIGA_CNTL, 0, 747 /* vsync signal from selected OTG pipe based 748 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 749 */ 750 OTG_TRIGA_SOURCE_SELECT, 20, 751 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 752 /* always detect rising edge */ 753 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 754 755 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 756 /* force H count to H_TOTAL and V count to V_TOTAL in 757 * progressive mode and V_TOTAL-1 in interlaced mode 758 */ 759 OTG_FORCE_COUNT_NOW_MODE, 2); 760 } 761 762 void optc1_enable_crtc_reset( 763 struct timing_generator *optc, 764 int source_tg_inst, 765 struct crtc_trigger_info *crtc_tp) 766 { 767 struct optc *optc1 = DCN10TG_FROM_TG(optc); 768 uint32_t falling_edge = 0; 769 uint32_t rising_edge = 0; 770 771 switch (crtc_tp->event) { 772 773 case CRTC_EVENT_VSYNC_RISING: 774 rising_edge = 1; 775 break; 776 777 case CRTC_EVENT_VSYNC_FALLING: 778 falling_edge = 1; 779 break; 780 } 781 782 REG_SET_4(OTG_TRIGA_CNTL, 0, 783 /* vsync signal from selected OTG pipe based 784 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 785 */ 786 OTG_TRIGA_SOURCE_SELECT, 20, 787 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 788 /* always detect falling edge */ 789 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 790 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 791 792 switch (crtc_tp->delay) { 793 case TRIGGER_DELAY_NEXT_LINE: 794 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 795 OTG_AUTO_FORCE_VSYNC_MODE, 1); 796 break; 797 case TRIGGER_DELAY_NEXT_PIXEL: 798 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 799 /* force H count to H_TOTAL and V count to V_TOTAL in 800 * progressive mode and V_TOTAL-1 in interlaced mode 801 */ 802 OTG_FORCE_COUNT_NOW_MODE, 2); 803 break; 804 } 805 } 806 807 void optc1_wait_for_state(struct timing_generator *optc, 808 enum crtc_state state) 809 { 810 struct optc *optc1 = DCN10TG_FROM_TG(optc); 811 812 switch (state) { 813 case CRTC_STATE_VBLANK: 814 REG_WAIT(OTG_STATUS, 815 OTG_V_BLANK, 1, 816 1, 100000); /* 1 vupdate at 10hz */ 817 break; 818 819 case CRTC_STATE_VACTIVE: 820 REG_WAIT(OTG_STATUS, 821 OTG_V_ACTIVE_DISP, 1, 822 1, 100000); /* 1 vupdate at 10hz */ 823 break; 824 825 default: 826 break; 827 } 828 } 829 830 void optc1_set_early_control( 831 struct timing_generator *optc, 832 uint32_t early_cntl) 833 { 834 /* asic design change, do not need this control 835 * empty for share caller logic 836 */ 837 } 838 839 840 void optc1_set_static_screen_control( 841 struct timing_generator *optc, 842 uint32_t event_triggers, 843 uint32_t num_frames) 844 { 845 struct optc *optc1 = DCN10TG_FROM_TG(optc); 846 847 // By register spec, it only takes 8 bit value 848 if (num_frames > 0xFF) 849 num_frames = 0xFF; 850 851 /* Bit 8 is no longer applicable in RV for PSR case, 852 * set bit 8 to 0 if given 853 */ 854 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 855 != 0) 856 event_triggers = event_triggers & 857 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 858 859 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 860 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers, 861 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames); 862 } 863 864 static void optc1_setup_manual_trigger(struct timing_generator *optc) 865 { 866 struct optc *optc1 = DCN10TG_FROM_TG(optc); 867 868 REG_SET(OTG_GLOBAL_CONTROL2, 0, 869 MANUAL_FLOW_CONTROL_SEL, optc->inst); 870 871 REG_SET_8(OTG_TRIGA_CNTL, 0, 872 OTG_TRIGA_SOURCE_SELECT, 22, 873 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, 874 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, 875 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, 876 OTG_TRIGA_POLARITY_SELECT, 0, 877 OTG_TRIGA_FREQUENCY_SELECT, 0, 878 OTG_TRIGA_DELAY, 0, 879 OTG_TRIGA_CLEAR, 1); 880 } 881 882 static void optc1_program_manual_trigger(struct timing_generator *optc) 883 { 884 struct optc *optc1 = DCN10TG_FROM_TG(optc); 885 886 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 887 MANUAL_FLOW_CONTROL, 1); 888 889 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, 890 MANUAL_FLOW_CONTROL, 0); 891 } 892 893 894 /** 895 ***************************************************************************** 896 * Function: set_drr 897 * 898 * @brief 899 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 900 * 901 ***************************************************************************** 902 */ 903 void optc1_set_drr( 904 struct timing_generator *optc, 905 const struct drr_params *params) 906 { 907 struct optc *optc1 = DCN10TG_FROM_TG(optc); 908 909 if (params != NULL && 910 params->vertical_total_max > 0 && 911 params->vertical_total_min > 0) { 912 913 if (params->vertical_total_mid != 0) { 914 915 REG_SET(OTG_V_TOTAL_MID, 0, 916 OTG_V_TOTAL_MID, params->vertical_total_mid - 1); 917 918 REG_UPDATE_2(OTG_V_TOTAL_CONTROL, 919 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1, 920 OTG_VTOTAL_MID_FRAME_NUM, 921 (uint8_t)params->vertical_total_mid_frame_num); 922 923 } 924 925 REG_SET(OTG_V_TOTAL_MAX, 0, 926 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 927 928 REG_SET(OTG_V_TOTAL_MIN, 0, 929 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 930 931 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 932 OTG_V_TOTAL_MIN_SEL, 1, 933 OTG_V_TOTAL_MAX_SEL, 1, 934 OTG_FORCE_LOCK_ON_EVENT, 0, 935 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 936 OTG_SET_V_TOTAL_MIN_MASK, 0); 937 938 // Setup manual flow control for EOF via TRIG_A 939 optc->funcs->setup_manual_trigger(optc); 940 941 } else { 942 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 943 OTG_SET_V_TOTAL_MIN_MASK, 0, 944 OTG_V_TOTAL_MIN_SEL, 0, 945 OTG_V_TOTAL_MAX_SEL, 0, 946 OTG_FORCE_LOCK_ON_EVENT, 0); 947 948 REG_SET(OTG_V_TOTAL_MIN, 0, 949 OTG_V_TOTAL_MIN, 0); 950 951 REG_SET(OTG_V_TOTAL_MAX, 0, 952 OTG_V_TOTAL_MAX, 0); 953 } 954 } 955 956 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max) 957 { 958 struct optc *optc1 = DCN10TG_FROM_TG(optc); 959 960 REG_SET(OTG_V_TOTAL_MAX, 0, 961 OTG_V_TOTAL_MAX, vtotal_max); 962 963 REG_SET(OTG_V_TOTAL_MIN, 0, 964 OTG_V_TOTAL_MIN, vtotal_min); 965 } 966 967 static void optc1_set_test_pattern( 968 struct timing_generator *optc, 969 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 970 * because this is not DP-specific (which is probably somewhere in DP 971 * encoder) */ 972 enum controller_dp_test_pattern test_pattern, 973 enum dc_color_depth color_depth) 974 { 975 struct optc *optc1 = DCN10TG_FROM_TG(optc); 976 enum test_pattern_color_format bit_depth; 977 enum test_pattern_dyn_range dyn_range; 978 enum test_pattern_mode mode; 979 uint32_t pattern_mask; 980 uint32_t pattern_data; 981 /* color ramp generator mixes 16-bits color */ 982 uint32_t src_bpc = 16; 983 /* requested bpc */ 984 uint32_t dst_bpc; 985 uint32_t index; 986 /* RGB values of the color bars. 987 * Produce two RGB colors: RGB0 - white (all Fs) 988 * and RGB1 - black (all 0s) 989 * (three RGB components for two colors) 990 */ 991 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 992 0x0000, 0x0000}; 993 /* dest color (converted to the specified color format) */ 994 uint16_t dst_color[6]; 995 uint32_t inc_base; 996 997 /* translate to bit depth */ 998 switch (color_depth) { 999 case COLOR_DEPTH_666: 1000 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 1001 break; 1002 case COLOR_DEPTH_888: 1003 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1004 break; 1005 case COLOR_DEPTH_101010: 1006 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 1007 break; 1008 case COLOR_DEPTH_121212: 1009 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 1010 break; 1011 default: 1012 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 1013 break; 1014 } 1015 1016 switch (test_pattern) { 1017 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 1018 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 1019 { 1020 dyn_range = (test_pattern == 1021 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 1022 TEST_PATTERN_DYN_RANGE_CEA : 1023 TEST_PATTERN_DYN_RANGE_VESA); 1024 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 1025 1026 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 1027 OTG_TEST_PATTERN_VRES, 6, 1028 OTG_TEST_PATTERN_HRES, 6); 1029 1030 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1031 OTG_TEST_PATTERN_EN, 1, 1032 OTG_TEST_PATTERN_MODE, mode, 1033 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 1034 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1035 } 1036 break; 1037 1038 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 1039 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 1040 { 1041 mode = (test_pattern == 1042 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 1043 TEST_PATTERN_MODE_VERTICALBARS : 1044 TEST_PATTERN_MODE_HORIZONTALBARS); 1045 1046 switch (bit_depth) { 1047 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1048 dst_bpc = 6; 1049 break; 1050 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1051 dst_bpc = 8; 1052 break; 1053 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1054 dst_bpc = 10; 1055 break; 1056 default: 1057 dst_bpc = 8; 1058 break; 1059 } 1060 1061 /* adjust color to the required colorFormat */ 1062 for (index = 0; index < 6; index++) { 1063 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 1064 * (srcBpc - dstBpc); 1065 */ 1066 dst_color[index] = 1067 src_color[index] >> (src_bpc - dst_bpc); 1068 /* CRTC_TEST_PATTERN_DATA has 16 bits, 1069 * lowest 6 are hardwired to ZERO 1070 * color bits should be left aligned aligned to MSB 1071 * XXXXXXXXXX000000 for 10 bit, 1072 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 1073 */ 1074 dst_color[index] <<= (16 - dst_bpc); 1075 } 1076 1077 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1078 1079 /* We have to write the mask before data, similar to pipeline. 1080 * For example, for 8 bpc, if we want RGB0 to be magenta, 1081 * and RGB1 to be cyan, 1082 * we need to make 7 writes: 1083 * MASK DATA 1084 * 000001 00000000 00000000 set mask to R0 1085 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 1086 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 1087 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 1088 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 1089 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 1090 * 100000 11111111 00000000 B1 255, 0xFF00 1091 * 1092 * we will make a loop of 6 in which we prepare the mask, 1093 * then write, then prepare the color for next write. 1094 * first iteration will write mask only, 1095 * but each next iteration color prepared in 1096 * previous iteration will be written within new mask, 1097 * the last component will written separately, 1098 * mask is not changing between 6th and 7th write 1099 * and color will be prepared by last iteration 1100 */ 1101 1102 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 1103 * is B1, G1, R1, B0, G0, R0 1104 */ 1105 pattern_data = 0; 1106 for (index = 0; index < 6; index++) { 1107 /* prepare color mask, first write PATTERN_DATA 1108 * will have all zeros 1109 */ 1110 pattern_mask = (1 << index); 1111 1112 /* write color component */ 1113 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1114 OTG_TEST_PATTERN_MASK, pattern_mask, 1115 OTG_TEST_PATTERN_DATA, pattern_data); 1116 1117 /* prepare next color component, 1118 * will be written in the next iteration 1119 */ 1120 pattern_data = dst_color[index]; 1121 } 1122 /* write last color component, 1123 * it's been already prepared in the loop 1124 */ 1125 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 1126 OTG_TEST_PATTERN_MASK, pattern_mask, 1127 OTG_TEST_PATTERN_DATA, pattern_data); 1128 1129 /* enable test pattern */ 1130 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 1131 OTG_TEST_PATTERN_EN, 1, 1132 OTG_TEST_PATTERN_MODE, mode, 1133 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1134 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1135 } 1136 break; 1137 1138 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 1139 { 1140 mode = (bit_depth == 1141 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 1142 TEST_PATTERN_MODE_DUALRAMP_RGB : 1143 TEST_PATTERN_MODE_SINGLERAMP_RGB); 1144 1145 switch (bit_depth) { 1146 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1147 dst_bpc = 6; 1148 break; 1149 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1150 dst_bpc = 8; 1151 break; 1152 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1153 dst_bpc = 10; 1154 break; 1155 default: 1156 dst_bpc = 8; 1157 break; 1158 } 1159 1160 /* increment for the first ramp for one color gradation 1161 * 1 gradation for 6-bit color is 2^10 1162 * gradations in 16-bit color 1163 */ 1164 inc_base = (src_bpc - dst_bpc); 1165 1166 switch (bit_depth) { 1167 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1168 { 1169 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1170 OTG_TEST_PATTERN_INC0, inc_base, 1171 OTG_TEST_PATTERN_INC1, 0, 1172 OTG_TEST_PATTERN_HRES, 6, 1173 OTG_TEST_PATTERN_VRES, 6, 1174 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1175 } 1176 break; 1177 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1178 { 1179 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1180 OTG_TEST_PATTERN_INC0, inc_base, 1181 OTG_TEST_PATTERN_INC1, 0, 1182 OTG_TEST_PATTERN_HRES, 8, 1183 OTG_TEST_PATTERN_VRES, 6, 1184 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1185 } 1186 break; 1187 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1188 { 1189 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1190 OTG_TEST_PATTERN_INC0, inc_base, 1191 OTG_TEST_PATTERN_INC1, inc_base + 2, 1192 OTG_TEST_PATTERN_HRES, 8, 1193 OTG_TEST_PATTERN_VRES, 5, 1194 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1195 } 1196 break; 1197 default: 1198 break; 1199 } 1200 1201 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1202 1203 /* enable test pattern */ 1204 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1205 1206 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1207 OTG_TEST_PATTERN_EN, 1, 1208 OTG_TEST_PATTERN_MODE, mode, 1209 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1210 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1211 } 1212 break; 1213 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1214 { 1215 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1216 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1217 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1218 } 1219 break; 1220 default: 1221 break; 1222 1223 } 1224 } 1225 1226 void optc1_get_crtc_scanoutpos( 1227 struct timing_generator *optc, 1228 uint32_t *v_blank_start, 1229 uint32_t *v_blank_end, 1230 uint32_t *h_position, 1231 uint32_t *v_position) 1232 { 1233 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1234 struct crtc_position position; 1235 1236 REG_GET_2(OTG_V_BLANK_START_END, 1237 OTG_V_BLANK_START, v_blank_start, 1238 OTG_V_BLANK_END, v_blank_end); 1239 1240 optc1_get_position(optc, &position); 1241 1242 *h_position = position.horizontal_count; 1243 *v_position = position.vertical_count; 1244 } 1245 1246 static void optc1_enable_stereo(struct timing_generator *optc, 1247 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1248 { 1249 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1250 1251 if (flags) { 1252 uint32_t stereo_en; 1253 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1254 1255 if (flags->PROGRAM_STEREO) 1256 REG_UPDATE_3(OTG_STEREO_CONTROL, 1257 OTG_STEREO_EN, stereo_en, 1258 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1259 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1260 1261 if (flags->PROGRAM_POLARITY) 1262 REG_UPDATE(OTG_STEREO_CONTROL, 1263 OTG_STEREO_EYE_FLAG_POLARITY, 1264 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1265 1266 if (flags->DISABLE_STEREO_DP_SYNC) 1267 REG_UPDATE(OTG_STEREO_CONTROL, 1268 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1269 1270 if (flags->PROGRAM_STEREO) 1271 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1272 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1273 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1274 1275 } 1276 } 1277 1278 void optc1_program_stereo(struct timing_generator *optc, 1279 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1280 { 1281 if (flags->PROGRAM_STEREO) 1282 optc1_enable_stereo(optc, timing, flags); 1283 else 1284 optc1_disable_stereo(optc); 1285 } 1286 1287 1288 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1289 { 1290 bool ret = false; 1291 uint32_t left_eye = 0; 1292 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1293 1294 REG_GET(OTG_STEREO_STATUS, 1295 OTG_STEREO_CURRENT_EYE, &left_eye); 1296 if (left_eye == 1) 1297 ret = true; 1298 else 1299 ret = false; 1300 1301 return ret; 1302 } 1303 1304 bool optc1_get_hw_timing(struct timing_generator *tg, 1305 struct dc_crtc_timing *hw_crtc_timing) 1306 { 1307 struct dcn_otg_state s = {0}; 1308 1309 if (tg == NULL || hw_crtc_timing == NULL) 1310 return false; 1311 1312 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1313 1314 hw_crtc_timing->h_total = s.h_total + 1; 1315 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1316 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start; 1317 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1318 1319 hw_crtc_timing->v_total = s.v_total + 1; 1320 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1321 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start; 1322 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1323 1324 return true; 1325 } 1326 1327 1328 void optc1_read_otg_state(struct optc *optc1, 1329 struct dcn_otg_state *s) 1330 { 1331 REG_GET(OTG_CONTROL, 1332 OTG_MASTER_EN, &s->otg_enabled); 1333 1334 REG_GET_2(OTG_V_BLANK_START_END, 1335 OTG_V_BLANK_START, &s->v_blank_start, 1336 OTG_V_BLANK_END, &s->v_blank_end); 1337 1338 REG_GET(OTG_V_SYNC_A_CNTL, 1339 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1340 1341 REG_GET(OTG_V_TOTAL, 1342 OTG_V_TOTAL, &s->v_total); 1343 1344 REG_GET(OTG_V_TOTAL_MAX, 1345 OTG_V_TOTAL_MAX, &s->v_total_max); 1346 1347 REG_GET(OTG_V_TOTAL_MIN, 1348 OTG_V_TOTAL_MIN, &s->v_total_min); 1349 1350 REG_GET(OTG_V_TOTAL_CONTROL, 1351 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1352 1353 REG_GET(OTG_V_TOTAL_CONTROL, 1354 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1355 1356 REG_GET_2(OTG_V_SYNC_A, 1357 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1358 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1359 1360 REG_GET_2(OTG_H_BLANK_START_END, 1361 OTG_H_BLANK_START, &s->h_blank_start, 1362 OTG_H_BLANK_END, &s->h_blank_end); 1363 1364 REG_GET_2(OTG_H_SYNC_A, 1365 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1366 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1367 1368 REG_GET(OTG_H_SYNC_A_CNTL, 1369 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1370 1371 REG_GET(OTG_H_TOTAL, 1372 OTG_H_TOTAL, &s->h_total); 1373 1374 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1375 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1376 1377 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL, 1378 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en); 1379 1380 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION, 1381 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line); 1382 } 1383 1384 bool optc1_get_otg_active_size(struct timing_generator *optc, 1385 uint32_t *otg_active_width, 1386 uint32_t *otg_active_height) 1387 { 1388 uint32_t otg_enabled; 1389 uint32_t v_blank_start; 1390 uint32_t v_blank_end; 1391 uint32_t h_blank_start; 1392 uint32_t h_blank_end; 1393 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1394 1395 1396 REG_GET(OTG_CONTROL, 1397 OTG_MASTER_EN, &otg_enabled); 1398 1399 if (otg_enabled == 0) 1400 return false; 1401 1402 REG_GET_2(OTG_V_BLANK_START_END, 1403 OTG_V_BLANK_START, &v_blank_start, 1404 OTG_V_BLANK_END, &v_blank_end); 1405 1406 REG_GET_2(OTG_H_BLANK_START_END, 1407 OTG_H_BLANK_START, &h_blank_start, 1408 OTG_H_BLANK_END, &h_blank_end); 1409 1410 *otg_active_width = v_blank_start - v_blank_end; 1411 *otg_active_height = h_blank_start - h_blank_end; 1412 return true; 1413 } 1414 1415 void optc1_clear_optc_underflow(struct timing_generator *optc) 1416 { 1417 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1418 1419 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1420 } 1421 1422 void optc1_tg_init(struct timing_generator *optc) 1423 { 1424 optc1_set_blank_data_double_buffer(optc, true); 1425 optc1_set_timing_double_buffer(optc, true); 1426 optc1_clear_optc_underflow(optc); 1427 } 1428 1429 bool optc1_is_tg_enabled(struct timing_generator *optc) 1430 { 1431 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1432 uint32_t otg_enabled = 0; 1433 1434 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1435 1436 return (otg_enabled != 0); 1437 1438 } 1439 1440 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1441 { 1442 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1443 uint32_t underflow_occurred = 0; 1444 1445 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1446 OPTC_UNDERFLOW_OCCURRED_STATUS, 1447 &underflow_occurred); 1448 1449 return (underflow_occurred == 1); 1450 } 1451 1452 bool optc1_configure_crc(struct timing_generator *optc, 1453 const struct crc_params *params) 1454 { 1455 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1456 1457 /* Cannot configure crc on a CRTC that is disabled */ 1458 if (!optc1_is_tg_enabled(optc)) 1459 return false; 1460 1461 REG_WRITE(OTG_CRC_CNTL, 0); 1462 1463 if (!params->enable) 1464 return true; 1465 1466 /* Program frame boundaries */ 1467 /* Window A x axis start and end. */ 1468 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1469 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1470 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1471 1472 /* Window A y axis start and end. */ 1473 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1474 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1475 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1476 1477 /* Window B x axis start and end. */ 1478 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1479 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1480 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1481 1482 /* Window B y axis start and end. */ 1483 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1484 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1485 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1486 1487 /* Set crc mode and selection, and enable. Only using CRC0*/ 1488 REG_UPDATE_3(OTG_CRC_CNTL, 1489 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1490 OTG_CRC0_SELECT, params->selection, 1491 OTG_CRC_EN, 1); 1492 1493 return true; 1494 } 1495 1496 bool optc1_get_crc(struct timing_generator *optc, 1497 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1498 { 1499 uint32_t field = 0; 1500 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1501 1502 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1503 1504 /* Early return if CRC is not enabled for this CRTC */ 1505 if (!field) 1506 return false; 1507 1508 REG_GET_2(OTG_CRC0_DATA_RG, 1509 CRC0_R_CR, r_cr, 1510 CRC0_G_Y, g_y); 1511 1512 REG_GET(OTG_CRC0_DATA_B, 1513 CRC0_B_CB, b_cb); 1514 1515 return true; 1516 } 1517 1518 static const struct timing_generator_funcs dcn10_tg_funcs = { 1519 .validate_timing = optc1_validate_timing, 1520 .program_timing = optc1_program_timing, 1521 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1522 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1523 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1524 .program_global_sync = optc1_program_global_sync, 1525 .enable_crtc = optc1_enable_crtc, 1526 .disable_crtc = optc1_disable_crtc, 1527 /* used by enable_timing_synchronization. Not need for FPGA */ 1528 .is_counter_moving = optc1_is_counter_moving, 1529 .get_position = optc1_get_position, 1530 .get_frame_count = optc1_get_vblank_counter, 1531 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1532 .get_otg_active_size = optc1_get_otg_active_size, 1533 .set_early_control = optc1_set_early_control, 1534 /* used by enable_timing_synchronization. Not need for FPGA */ 1535 .wait_for_state = optc1_wait_for_state, 1536 .set_blank = optc1_set_blank, 1537 .is_blanked = optc1_is_blanked, 1538 .set_blank_color = optc1_program_blank_color, 1539 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1540 .enable_reset_trigger = optc1_enable_reset_trigger, 1541 .enable_crtc_reset = optc1_enable_crtc_reset, 1542 .disable_reset_trigger = optc1_disable_reset_trigger, 1543 .lock = optc1_lock, 1544 .is_locked = optc1_is_locked, 1545 .unlock = optc1_unlock, 1546 .enable_optc_clock = optc1_enable_optc_clock, 1547 .set_drr = optc1_set_drr, 1548 .get_last_used_drr_vtotal = NULL, 1549 .set_static_screen_control = optc1_set_static_screen_control, 1550 .set_test_pattern = optc1_set_test_pattern, 1551 .program_stereo = optc1_program_stereo, 1552 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1553 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1554 .tg_init = optc1_tg_init, 1555 .is_tg_enabled = optc1_is_tg_enabled, 1556 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1557 .clear_optc_underflow = optc1_clear_optc_underflow, 1558 .get_crc = optc1_get_crc, 1559 .configure_crc = optc1_configure_crc, 1560 .set_vtg_params = optc1_set_vtg_params, 1561 .program_manual_trigger = optc1_program_manual_trigger, 1562 .setup_manual_trigger = optc1_setup_manual_trigger, 1563 .get_hw_timing = optc1_get_hw_timing, 1564 }; 1565 1566 void dcn10_timing_generator_init(struct optc *optc1) 1567 { 1568 optc1->base.funcs = &dcn10_tg_funcs; 1569 1570 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1571 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1572 1573 optc1->min_h_blank = 32; 1574 optc1->min_v_blank = 3; 1575 optc1->min_v_blank_interlace = 5; 1576 optc1->min_h_sync_width = 4; 1577 optc1->min_v_sync_width = 1; 1578 } 1579 1580 /* "Containter" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this: 1581 * 1582 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as 1583 * containter rate. 1584 * 1585 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be 1586 * halved to maintain the correct pixel rate. 1587 * 1588 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied 1589 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well. 1590 * 1591 */ 1592 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1593 { 1594 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1595 1596 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 1597 && !timing->dsc_cfg.ycbcr422_simple); 1598 return two_pix; 1599 } 1600 1601