1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 #include "dcn10_optc.h" 29 #include "dc.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 42 43 /** 44 * apply_front_porch_workaround TODO FPGA still need? 45 * 46 * This is a workaround for a bug that has existed since R5xx and has not been 47 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 48 */ 49 static void optc1_apply_front_porch_workaround( 50 struct timing_generator *optc, 51 struct dc_crtc_timing *timing) 52 { 53 if (timing->flags.INTERLACE == 1) { 54 if (timing->v_front_porch < 2) 55 timing->v_front_porch = 2; 56 } else { 57 if (timing->v_front_porch < 1) 58 timing->v_front_porch = 1; 59 } 60 } 61 62 void optc1_program_global_sync( 63 struct timing_generator *optc) 64 { 65 struct optc *optc1 = DCN10TG_FROM_TG(optc); 66 67 if (optc->dlg_otg_param.vstartup_start == 0) { 68 BREAK_TO_DEBUGGER(); 69 return; 70 } 71 72 REG_SET(OTG_VSTARTUP_PARAM, 0, 73 VSTARTUP_START, optc->dlg_otg_param.vstartup_start); 74 75 REG_SET_2(OTG_VUPDATE_PARAM, 0, 76 VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset, 77 VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width); 78 79 REG_SET(OTG_VREADY_PARAM, 0, 80 VREADY_OFFSET, optc->dlg_otg_param.vready_offset); 81 } 82 83 static void optc1_disable_stereo(struct timing_generator *optc) 84 { 85 struct optc *optc1 = DCN10TG_FROM_TG(optc); 86 87 REG_SET(OTG_STEREO_CONTROL, 0, 88 OTG_STEREO_EN, 0); 89 90 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, 91 OTG_3D_STRUCTURE_EN, 0, 92 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); 93 } 94 95 void optc1_setup_vertical_interrupt0( 96 struct timing_generator *optc, 97 uint32_t start_line, 98 uint32_t end_line) 99 { 100 struct optc *optc1 = DCN10TG_FROM_TG(optc); 101 102 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, 103 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line, 104 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line); 105 } 106 107 void optc1_setup_vertical_interrupt1( 108 struct timing_generator *optc, 109 uint32_t start_line) 110 { 111 struct optc *optc1 = DCN10TG_FROM_TG(optc); 112 113 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, 114 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line); 115 } 116 117 void optc1_setup_vertical_interrupt2( 118 struct timing_generator *optc, 119 uint32_t start_line) 120 { 121 struct optc *optc1 = DCN10TG_FROM_TG(optc); 122 123 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, 124 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line); 125 } 126 127 /** 128 * program_timing_generator used by mode timing set 129 * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 130 * Including SYNC. Call BIOS command table to program Timings. 131 */ 132 void optc1_program_timing( 133 struct timing_generator *optc, 134 const struct dc_crtc_timing *dc_crtc_timing, 135 bool use_vbios) 136 { 137 struct dc_crtc_timing patched_crtc_timing; 138 uint32_t vesa_sync_start; 139 uint32_t asic_blank_end; 140 uint32_t asic_blank_start; 141 uint32_t v_total; 142 uint32_t v_sync_end; 143 uint32_t v_init, v_fp2; 144 uint32_t h_sync_polarity, v_sync_polarity; 145 uint32_t start_point = 0; 146 uint32_t field_num = 0; 147 uint32_t h_div_2; 148 int32_t vertical_line_start; 149 150 struct optc *optc1 = DCN10TG_FROM_TG(optc); 151 152 patched_crtc_timing = *dc_crtc_timing; 153 optc1_apply_front_porch_workaround(optc, &patched_crtc_timing); 154 155 /* Load horizontal timing */ 156 157 /* CRTC_H_TOTAL = vesa.h_total - 1 */ 158 REG_SET(OTG_H_TOTAL, 0, 159 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); 160 161 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */ 162 REG_UPDATE_2(OTG_H_SYNC_A, 163 OTG_H_SYNC_A_START, 0, 164 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); 165 166 /* asic_h_blank_end = HsyncWidth + HbackPorch = 167 * vesa. usHorizontalTotal - vesa. usHorizontalSyncStart - 168 * vesa.h_left_border 169 */ 170 vesa_sync_start = patched_crtc_timing.h_addressable + 171 patched_crtc_timing.h_border_right + 172 patched_crtc_timing.h_front_porch; 173 174 asic_blank_end = patched_crtc_timing.h_total - 175 vesa_sync_start - 176 patched_crtc_timing.h_border_left; 177 178 /* h_blank_start = v_blank_end + v_active */ 179 asic_blank_start = asic_blank_end + 180 patched_crtc_timing.h_border_left + 181 patched_crtc_timing.h_addressable + 182 patched_crtc_timing.h_border_right; 183 184 REG_UPDATE_2(OTG_H_BLANK_START_END, 185 OTG_H_BLANK_START, asic_blank_start, 186 OTG_H_BLANK_END, asic_blank_end); 187 188 /* h_sync polarity */ 189 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ? 190 0 : 1; 191 192 REG_UPDATE(OTG_H_SYNC_A_CNTL, 193 OTG_H_SYNC_A_POL, h_sync_polarity); 194 195 v_total = patched_crtc_timing.v_total - 1; 196 197 REG_SET(OTG_V_TOTAL, 0, 198 OTG_V_TOTAL, v_total); 199 200 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and 201 * OTG_V_TOTAL_MIN are equal to V_TOTAL. 202 */ 203 REG_SET(OTG_V_TOTAL_MAX, 0, 204 OTG_V_TOTAL_MAX, v_total); 205 REG_SET(OTG_V_TOTAL_MIN, 0, 206 OTG_V_TOTAL_MIN, v_total); 207 208 /* v_sync_start = 0, v_sync_end = v_sync_width */ 209 v_sync_end = patched_crtc_timing.v_sync_width; 210 211 REG_UPDATE_2(OTG_V_SYNC_A, 212 OTG_V_SYNC_A_START, 0, 213 OTG_V_SYNC_A_END, v_sync_end); 214 215 vesa_sync_start = patched_crtc_timing.v_addressable + 216 patched_crtc_timing.v_border_bottom + 217 patched_crtc_timing.v_front_porch; 218 219 asic_blank_end = (patched_crtc_timing.v_total - 220 vesa_sync_start - 221 patched_crtc_timing.v_border_top); 222 223 /* v_blank_start = v_blank_end + v_active */ 224 asic_blank_start = asic_blank_end + 225 (patched_crtc_timing.v_border_top + 226 patched_crtc_timing.v_addressable + 227 patched_crtc_timing.v_border_bottom); 228 229 vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1; 230 v_fp2 = 0; 231 if (vertical_line_start < 0) 232 v_fp2 = -vertical_line_start; 233 234 REG_UPDATE_2(OTG_V_BLANK_START_END, 235 OTG_V_BLANK_START, asic_blank_start, 236 OTG_V_BLANK_END, asic_blank_end); 237 238 /* v_sync polarity */ 239 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ? 240 0 : 1; 241 242 REG_UPDATE(OTG_V_SYNC_A_CNTL, 243 OTG_V_SYNC_A_POL, v_sync_polarity); 244 245 v_init = asic_blank_start; 246 if (optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT || 247 optc->dlg_otg_param.signal == SIGNAL_TYPE_DISPLAY_PORT_MST || 248 optc->dlg_otg_param.signal == SIGNAL_TYPE_EDP) { 249 start_point = 1; 250 if (patched_crtc_timing.flags.INTERLACE == 1) 251 field_num = 1; 252 } 253 254 /* Interlace */ 255 if (REG(OTG_INTERLACE_CONTROL)) { 256 if (patched_crtc_timing.flags.INTERLACE == 1) { 257 REG_UPDATE(OTG_INTERLACE_CONTROL, 258 OTG_INTERLACE_ENABLE, 1); 259 v_init = v_init / 2; 260 if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end) 261 v_fp2 = v_fp2 / 2; 262 } else 263 REG_UPDATE(OTG_INTERLACE_CONTROL, 264 OTG_INTERLACE_ENABLE, 0); 265 } 266 267 /* VTG enable set to 0 first VInit */ 268 REG_UPDATE(CONTROL, 269 VTG0_ENABLE, 0); 270 271 REG_UPDATE_2(CONTROL, 272 VTG0_FP2, v_fp2, 273 VTG0_VCOUNT_INIT, v_init); 274 275 /* original code is using VTG offset to address OTG reg, seems wrong */ 276 REG_UPDATE_2(OTG_CONTROL, 277 OTG_START_POINT_CNTL, start_point, 278 OTG_FIELD_NUMBER_CNTL, field_num); 279 280 optc1_program_global_sync(optc); 281 282 /* TODO 283 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1 284 * program_horz_count_by_2 285 * for DVI 30bpp mode, 0 otherwise 286 * program_horz_count_by_2(optc, &patched_crtc_timing); 287 */ 288 289 /* Enable stereo - only when we need to pack 3D frame. Other types 290 * of stereo handled in explicit call 291 */ 292 293 h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing); 294 REG_UPDATE(OTG_H_TIMING_CNTL, 295 OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf); 296 297 } 298 299 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable) 300 { 301 struct optc *optc1 = DCN10TG_FROM_TG(optc); 302 303 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0; 304 305 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 306 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable); 307 } 308 309 /** 310 * unblank_crtc 311 * Call ASIC Control Object to UnBlank CRTC. 312 */ 313 static void optc1_unblank_crtc(struct timing_generator *optc) 314 { 315 struct optc *optc1 = DCN10TG_FROM_TG(optc); 316 317 REG_UPDATE_2(OTG_BLANK_CONTROL, 318 OTG_BLANK_DATA_EN, 0, 319 OTG_BLANK_DE_MODE, 0); 320 321 /* W/A for automated testing 322 * Automated testing will fail underflow test as there 323 * sporadic underflows which occur during the optc blank 324 * sequence. As a w/a, clear underflow on unblank. 325 * This prevents the failure, but will not mask actual 326 * underflow that affect real use cases. 327 */ 328 optc1_clear_optc_underflow(optc); 329 } 330 331 /** 332 * blank_crtc 333 * Call ASIC Control Object to Blank CRTC. 334 */ 335 336 static void optc1_blank_crtc(struct timing_generator *optc) 337 { 338 struct optc *optc1 = DCN10TG_FROM_TG(optc); 339 340 REG_UPDATE_2(OTG_BLANK_CONTROL, 341 OTG_BLANK_DATA_EN, 1, 342 OTG_BLANK_DE_MODE, 0); 343 344 optc1_set_blank_data_double_buffer(optc, false); 345 } 346 347 void optc1_set_blank(struct timing_generator *optc, 348 bool enable_blanking) 349 { 350 if (enable_blanking) 351 optc1_blank_crtc(optc); 352 else 353 optc1_unblank_crtc(optc); 354 } 355 356 bool optc1_is_blanked(struct timing_generator *optc) 357 { 358 struct optc *optc1 = DCN10TG_FROM_TG(optc); 359 uint32_t blank_en; 360 uint32_t blank_state; 361 362 REG_GET_2(OTG_BLANK_CONTROL, 363 OTG_BLANK_DATA_EN, &blank_en, 364 OTG_CURRENT_BLANK_STATE, &blank_state); 365 366 return blank_en && blank_state; 367 } 368 369 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable) 370 { 371 struct optc *optc1 = DCN10TG_FROM_TG(optc); 372 373 if (enable) { 374 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 375 OPTC_INPUT_CLK_EN, 1, 376 OPTC_INPUT_CLK_GATE_DIS, 1); 377 378 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, 379 OPTC_INPUT_CLK_ON, 1, 380 1, 1000); 381 382 /* Enable clock */ 383 REG_UPDATE_2(OTG_CLOCK_CONTROL, 384 OTG_CLOCK_EN, 1, 385 OTG_CLOCK_GATE_DIS, 1); 386 REG_WAIT(OTG_CLOCK_CONTROL, 387 OTG_CLOCK_ON, 1, 388 1, 1000); 389 } else { 390 REG_UPDATE_2(OTG_CLOCK_CONTROL, 391 OTG_CLOCK_GATE_DIS, 0, 392 OTG_CLOCK_EN, 0); 393 394 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL, 395 OPTC_INPUT_CLK_GATE_DIS, 0, 396 OPTC_INPUT_CLK_EN, 0); 397 } 398 } 399 400 /** 401 * Enable CRTC 402 * Enable CRTC - call ASIC Control Object to enable Timing generator. 403 */ 404 static bool optc1_enable_crtc(struct timing_generator *optc) 405 { 406 /* TODO FPGA wait for answer 407 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE 408 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK 409 */ 410 struct optc *optc1 = DCN10TG_FROM_TG(optc); 411 412 /* opp instance for OTG. For DCN1.0, ODM is remoed. 413 * OPP and OPTC should 1:1 mapping 414 */ 415 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, 416 OPTC_SRC_SEL, optc->inst); 417 418 /* VTG enable first is for HW workaround */ 419 REG_UPDATE(CONTROL, 420 VTG0_ENABLE, 1); 421 422 /* Enable CRTC */ 423 REG_UPDATE_2(OTG_CONTROL, 424 OTG_DISABLE_POINT_CNTL, 3, 425 OTG_MASTER_EN, 1); 426 427 return true; 428 } 429 430 /* disable_crtc - call ASIC Control Object to disable Timing generator. */ 431 bool optc1_disable_crtc(struct timing_generator *optc) 432 { 433 struct optc *optc1 = DCN10TG_FROM_TG(optc); 434 435 /* disable otg request until end of the first line 436 * in the vertical blank region 437 */ 438 REG_UPDATE_2(OTG_CONTROL, 439 OTG_DISABLE_POINT_CNTL, 3, 440 OTG_MASTER_EN, 0); 441 442 REG_UPDATE(CONTROL, 443 VTG0_ENABLE, 0); 444 445 /* CRTC disabled, so disable clock. */ 446 REG_WAIT(OTG_CLOCK_CONTROL, 447 OTG_BUSY, 0, 448 1, 100000); 449 450 return true; 451 } 452 453 454 void optc1_program_blank_color( 455 struct timing_generator *optc, 456 const struct tg_color *black_color) 457 { 458 struct optc *optc1 = DCN10TG_FROM_TG(optc); 459 460 REG_SET_3(OTG_BLACK_COLOR, 0, 461 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb, 462 OTG_BLACK_COLOR_G_Y, black_color->color_g_y, 463 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr); 464 } 465 466 bool optc1_validate_timing( 467 struct timing_generator *optc, 468 const struct dc_crtc_timing *timing) 469 { 470 uint32_t v_blank; 471 uint32_t h_blank; 472 uint32_t min_v_blank; 473 struct optc *optc1 = DCN10TG_FROM_TG(optc); 474 475 ASSERT(timing != NULL); 476 477 v_blank = (timing->v_total - timing->v_addressable - 478 timing->v_border_top - timing->v_border_bottom); 479 480 h_blank = (timing->h_total - timing->h_addressable - 481 timing->h_border_right - 482 timing->h_border_left); 483 484 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && 485 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING && 486 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM && 487 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE && 488 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE && 489 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA) 490 return false; 491 492 /* Temporarily blocking interlacing mode until it's supported */ 493 if (timing->flags.INTERLACE == 1) 494 return false; 495 496 /* Check maximum number of pixels supported by Timing Generator 497 * (Currently will never fail, in order to fail needs display which 498 * needs more than 8192 horizontal and 499 * more than 8192 vertical total pixels) 500 */ 501 if (timing->h_total > optc1->max_h_total || 502 timing->v_total > optc1->max_v_total) 503 return false; 504 505 506 if (h_blank < optc1->min_h_blank) 507 return false; 508 509 if (timing->h_sync_width < optc1->min_h_sync_width || 510 timing->v_sync_width < optc1->min_v_sync_width) 511 return false; 512 513 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank; 514 515 if (v_blank < min_v_blank) 516 return false; 517 518 return true; 519 520 } 521 522 /* 523 * get_vblank_counter 524 * 525 * @brief 526 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which 527 * holds the counter of frames. 528 * 529 * @param 530 * struct timing_generator *optc - [in] timing generator which controls the 531 * desired CRTC 532 * 533 * @return 534 * Counter of frames, which should equal to number of vblanks. 535 */ 536 uint32_t optc1_get_vblank_counter(struct timing_generator *optc) 537 { 538 struct optc *optc1 = DCN10TG_FROM_TG(optc); 539 uint32_t frame_count; 540 541 REG_GET(OTG_STATUS_FRAME_COUNT, 542 OTG_FRAME_COUNT, &frame_count); 543 544 return frame_count; 545 } 546 547 void optc1_lock(struct timing_generator *optc) 548 { 549 struct optc *optc1 = DCN10TG_FROM_TG(optc); 550 551 REG_SET(OTG_GLOBAL_CONTROL0, 0, 552 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 553 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 554 OTG_MASTER_UPDATE_LOCK, 1); 555 556 /* Should be fast, status does not update on maximus */ 557 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 558 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 559 UPDATE_LOCK_STATUS, 1, 560 1, 10); 561 } 562 563 void optc1_unlock(struct timing_generator *optc) 564 { 565 struct optc *optc1 = DCN10TG_FROM_TG(optc); 566 567 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 568 OTG_MASTER_UPDATE_LOCK, 0); 569 } 570 571 void optc1_get_position(struct timing_generator *optc, 572 struct crtc_position *position) 573 { 574 struct optc *optc1 = DCN10TG_FROM_TG(optc); 575 576 REG_GET_2(OTG_STATUS_POSITION, 577 OTG_HORZ_COUNT, &position->horizontal_count, 578 OTG_VERT_COUNT, &position->vertical_count); 579 580 REG_GET(OTG_NOM_VERT_POSITION, 581 OTG_VERT_COUNT_NOM, &position->nominal_vcount); 582 } 583 584 bool optc1_is_counter_moving(struct timing_generator *optc) 585 { 586 struct crtc_position position1, position2; 587 588 optc->funcs->get_position(optc, &position1); 589 optc->funcs->get_position(optc, &position2); 590 591 if (position1.horizontal_count == position2.horizontal_count && 592 position1.vertical_count == position2.vertical_count) 593 return false; 594 else 595 return true; 596 } 597 598 bool optc1_did_triggered_reset_occur( 599 struct timing_generator *optc) 600 { 601 struct optc *optc1 = DCN10TG_FROM_TG(optc); 602 uint32_t occurred_force, occurred_vsync; 603 604 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, 605 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force); 606 607 REG_GET(OTG_VERT_SYNC_CONTROL, 608 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync); 609 610 return occurred_vsync != 0 || occurred_force != 0; 611 } 612 613 void optc1_disable_reset_trigger(struct timing_generator *optc) 614 { 615 struct optc *optc1 = DCN10TG_FROM_TG(optc); 616 617 REG_WRITE(OTG_TRIGA_CNTL, 0); 618 619 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 620 OTG_FORCE_COUNT_NOW_CLEAR, 1); 621 622 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 623 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1); 624 } 625 626 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst) 627 { 628 struct optc *optc1 = DCN10TG_FROM_TG(optc); 629 uint32_t falling_edge; 630 631 REG_GET(OTG_V_SYNC_A_CNTL, 632 OTG_V_SYNC_A_POL, &falling_edge); 633 634 if (falling_edge) 635 REG_SET_3(OTG_TRIGA_CNTL, 0, 636 /* vsync signal from selected OTG pipe based 637 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 638 */ 639 OTG_TRIGA_SOURCE_SELECT, 20, 640 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 641 /* always detect falling edge */ 642 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1); 643 else 644 REG_SET_3(OTG_TRIGA_CNTL, 0, 645 /* vsync signal from selected OTG pipe based 646 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 647 */ 648 OTG_TRIGA_SOURCE_SELECT, 20, 649 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 650 /* always detect rising edge */ 651 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1); 652 653 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 654 /* force H count to H_TOTAL and V count to V_TOTAL in 655 * progressive mode and V_TOTAL-1 in interlaced mode 656 */ 657 OTG_FORCE_COUNT_NOW_MODE, 2); 658 } 659 660 void optc1_enable_crtc_reset( 661 struct timing_generator *optc, 662 int source_tg_inst, 663 struct crtc_trigger_info *crtc_tp) 664 { 665 struct optc *optc1 = DCN10TG_FROM_TG(optc); 666 uint32_t falling_edge = 0; 667 uint32_t rising_edge = 0; 668 669 switch (crtc_tp->event) { 670 671 case CRTC_EVENT_VSYNC_RISING: 672 rising_edge = 1; 673 break; 674 675 case CRTC_EVENT_VSYNC_FALLING: 676 falling_edge = 1; 677 break; 678 } 679 680 REG_SET_4(OTG_TRIGA_CNTL, 0, 681 /* vsync signal from selected OTG pipe based 682 * on OTG_TRIG_SOURCE_PIPE_SELECT setting 683 */ 684 OTG_TRIGA_SOURCE_SELECT, 20, 685 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst, 686 /* always detect falling edge */ 687 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge, 688 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge); 689 690 switch (crtc_tp->delay) { 691 case TRIGGER_DELAY_NEXT_LINE: 692 REG_SET(OTG_VERT_SYNC_CONTROL, 0, 693 OTG_AUTO_FORCE_VSYNC_MODE, 1); 694 break; 695 case TRIGGER_DELAY_NEXT_PIXEL: 696 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0, 697 /* force H count to H_TOTAL and V count to V_TOTAL in 698 * progressive mode and V_TOTAL-1 in interlaced mode 699 */ 700 OTG_FORCE_COUNT_NOW_MODE, 2); 701 break; 702 } 703 } 704 705 void optc1_wait_for_state(struct timing_generator *optc, 706 enum crtc_state state) 707 { 708 struct optc *optc1 = DCN10TG_FROM_TG(optc); 709 710 switch (state) { 711 case CRTC_STATE_VBLANK: 712 REG_WAIT(OTG_STATUS, 713 OTG_V_BLANK, 1, 714 1, 100000); /* 1 vupdate at 10hz */ 715 break; 716 717 case CRTC_STATE_VACTIVE: 718 REG_WAIT(OTG_STATUS, 719 OTG_V_ACTIVE_DISP, 1, 720 1, 100000); /* 1 vupdate at 10hz */ 721 break; 722 723 default: 724 break; 725 } 726 } 727 728 void optc1_set_early_control( 729 struct timing_generator *optc, 730 uint32_t early_cntl) 731 { 732 /* asic design change, do not need this control 733 * empty for share caller logic 734 */ 735 } 736 737 738 void optc1_set_static_screen_control( 739 struct timing_generator *optc, 740 uint32_t value) 741 { 742 struct optc *optc1 = DCN10TG_FROM_TG(optc); 743 744 /* Bit 8 is no longer applicable in RV for PSR case, 745 * set bit 8 to 0 if given 746 */ 747 if ((value & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN) 748 != 0) 749 value = value & 750 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN; 751 752 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, 753 OTG_STATIC_SCREEN_EVENT_MASK, value, 754 OTG_STATIC_SCREEN_FRAME_COUNT, 2); 755 } 756 757 758 /** 759 ***************************************************************************** 760 * Function: set_drr 761 * 762 * @brief 763 * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 764 * 765 ***************************************************************************** 766 */ 767 void optc1_set_drr( 768 struct timing_generator *optc, 769 const struct drr_params *params) 770 { 771 struct optc *optc1 = DCN10TG_FROM_TG(optc); 772 773 if (params != NULL && 774 params->vertical_total_max > 0 && 775 params->vertical_total_min > 0) { 776 777 REG_SET(OTG_V_TOTAL_MAX, 0, 778 OTG_V_TOTAL_MAX, params->vertical_total_max - 1); 779 780 REG_SET(OTG_V_TOTAL_MIN, 0, 781 OTG_V_TOTAL_MIN, params->vertical_total_min - 1); 782 783 REG_UPDATE_5(OTG_V_TOTAL_CONTROL, 784 OTG_V_TOTAL_MIN_SEL, 1, 785 OTG_V_TOTAL_MAX_SEL, 1, 786 OTG_FORCE_LOCK_ON_EVENT, 0, 787 OTG_SET_V_TOTAL_MIN_MASK_EN, 0, 788 OTG_SET_V_TOTAL_MIN_MASK, 0); 789 } else { 790 REG_UPDATE_4(OTG_V_TOTAL_CONTROL, 791 OTG_SET_V_TOTAL_MIN_MASK, 0, 792 OTG_V_TOTAL_MIN_SEL, 0, 793 OTG_V_TOTAL_MAX_SEL, 0, 794 OTG_FORCE_LOCK_ON_EVENT, 0); 795 796 REG_SET(OTG_V_TOTAL_MIN, 0, 797 OTG_V_TOTAL_MIN, 0); 798 799 REG_SET(OTG_V_TOTAL_MAX, 0, 800 OTG_V_TOTAL_MAX, 0); 801 } 802 } 803 804 static void optc1_set_test_pattern( 805 struct timing_generator *optc, 806 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode' 807 * because this is not DP-specific (which is probably somewhere in DP 808 * encoder) */ 809 enum controller_dp_test_pattern test_pattern, 810 enum dc_color_depth color_depth) 811 { 812 struct optc *optc1 = DCN10TG_FROM_TG(optc); 813 enum test_pattern_color_format bit_depth; 814 enum test_pattern_dyn_range dyn_range; 815 enum test_pattern_mode mode; 816 uint32_t pattern_mask; 817 uint32_t pattern_data; 818 /* color ramp generator mixes 16-bits color */ 819 uint32_t src_bpc = 16; 820 /* requested bpc */ 821 uint32_t dst_bpc; 822 uint32_t index; 823 /* RGB values of the color bars. 824 * Produce two RGB colors: RGB0 - white (all Fs) 825 * and RGB1 - black (all 0s) 826 * (three RGB components for two colors) 827 */ 828 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000, 829 0x0000, 0x0000}; 830 /* dest color (converted to the specified color format) */ 831 uint16_t dst_color[6]; 832 uint32_t inc_base; 833 834 /* translate to bit depth */ 835 switch (color_depth) { 836 case COLOR_DEPTH_666: 837 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6; 838 break; 839 case COLOR_DEPTH_888: 840 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 841 break; 842 case COLOR_DEPTH_101010: 843 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10; 844 break; 845 case COLOR_DEPTH_121212: 846 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12; 847 break; 848 default: 849 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8; 850 break; 851 } 852 853 switch (test_pattern) { 854 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES: 855 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA: 856 { 857 dyn_range = (test_pattern == 858 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ? 859 TEST_PATTERN_DYN_RANGE_CEA : 860 TEST_PATTERN_DYN_RANGE_VESA); 861 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB; 862 863 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS, 864 OTG_TEST_PATTERN_VRES, 6, 865 OTG_TEST_PATTERN_HRES, 6); 866 867 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 868 OTG_TEST_PATTERN_EN, 1, 869 OTG_TEST_PATTERN_MODE, mode, 870 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range, 871 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 872 } 873 break; 874 875 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS: 876 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS: 877 { 878 mode = (test_pattern == 879 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ? 880 TEST_PATTERN_MODE_VERTICALBARS : 881 TEST_PATTERN_MODE_HORIZONTALBARS); 882 883 switch (bit_depth) { 884 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 885 dst_bpc = 6; 886 break; 887 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 888 dst_bpc = 8; 889 break; 890 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 891 dst_bpc = 10; 892 break; 893 default: 894 dst_bpc = 8; 895 break; 896 } 897 898 /* adjust color to the required colorFormat */ 899 for (index = 0; index < 6; index++) { 900 /* dst = 2^dstBpc * src / 2^srcBpc = src >> 901 * (srcBpc - dstBpc); 902 */ 903 dst_color[index] = 904 src_color[index] >> (src_bpc - dst_bpc); 905 /* CRTC_TEST_PATTERN_DATA has 16 bits, 906 * lowest 6 are hardwired to ZERO 907 * color bits should be left aligned aligned to MSB 908 * XXXXXXXXXX000000 for 10 bit, 909 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6 910 */ 911 dst_color[index] <<= (16 - dst_bpc); 912 } 913 914 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 915 916 /* We have to write the mask before data, similar to pipeline. 917 * For example, for 8 bpc, if we want RGB0 to be magenta, 918 * and RGB1 to be cyan, 919 * we need to make 7 writes: 920 * MASK DATA 921 * 000001 00000000 00000000 set mask to R0 922 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0 923 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0 924 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1 925 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1 926 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1 927 * 100000 11111111 00000000 B1 255, 0xFF00 928 * 929 * we will make a loop of 6 in which we prepare the mask, 930 * then write, then prepare the color for next write. 931 * first iteration will write mask only, 932 * but each next iteration color prepared in 933 * previous iteration will be written within new mask, 934 * the last component will written separately, 935 * mask is not changing between 6th and 7th write 936 * and color will be prepared by last iteration 937 */ 938 939 /* write color, color values mask in CRTC_TEST_PATTERN_MASK 940 * is B1, G1, R1, B0, G0, R0 941 */ 942 pattern_data = 0; 943 for (index = 0; index < 6; index++) { 944 /* prepare color mask, first write PATTERN_DATA 945 * will have all zeros 946 */ 947 pattern_mask = (1 << index); 948 949 /* write color component */ 950 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 951 OTG_TEST_PATTERN_MASK, pattern_mask, 952 OTG_TEST_PATTERN_DATA, pattern_data); 953 954 /* prepare next color component, 955 * will be written in the next iteration 956 */ 957 pattern_data = dst_color[index]; 958 } 959 /* write last color component, 960 * it's been already prepared in the loop 961 */ 962 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, 963 OTG_TEST_PATTERN_MASK, pattern_mask, 964 OTG_TEST_PATTERN_DATA, pattern_data); 965 966 /* enable test pattern */ 967 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL, 968 OTG_TEST_PATTERN_EN, 1, 969 OTG_TEST_PATTERN_MODE, mode, 970 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 971 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 972 } 973 break; 974 975 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP: 976 { 977 mode = (bit_depth == 978 TEST_PATTERN_COLOR_FORMAT_BPC_10 ? 979 TEST_PATTERN_MODE_DUALRAMP_RGB : 980 TEST_PATTERN_MODE_SINGLERAMP_RGB); 981 982 switch (bit_depth) { 983 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 984 dst_bpc = 6; 985 break; 986 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 987 dst_bpc = 8; 988 break; 989 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 990 dst_bpc = 10; 991 break; 992 default: 993 dst_bpc = 8; 994 break; 995 } 996 997 /* increment for the first ramp for one color gradation 998 * 1 gradation for 6-bit color is 2^10 999 * gradations in 16-bit color 1000 */ 1001 inc_base = (src_bpc - dst_bpc); 1002 1003 switch (bit_depth) { 1004 case TEST_PATTERN_COLOR_FORMAT_BPC_6: 1005 { 1006 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1007 OTG_TEST_PATTERN_INC0, inc_base, 1008 OTG_TEST_PATTERN_INC1, 0, 1009 OTG_TEST_PATTERN_HRES, 6, 1010 OTG_TEST_PATTERN_VRES, 6, 1011 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1012 } 1013 break; 1014 case TEST_PATTERN_COLOR_FORMAT_BPC_8: 1015 { 1016 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1017 OTG_TEST_PATTERN_INC0, inc_base, 1018 OTG_TEST_PATTERN_INC1, 0, 1019 OTG_TEST_PATTERN_HRES, 8, 1020 OTG_TEST_PATTERN_VRES, 6, 1021 OTG_TEST_PATTERN_RAMP0_OFFSET, 0); 1022 } 1023 break; 1024 case TEST_PATTERN_COLOR_FORMAT_BPC_10: 1025 { 1026 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS, 1027 OTG_TEST_PATTERN_INC0, inc_base, 1028 OTG_TEST_PATTERN_INC1, inc_base + 2, 1029 OTG_TEST_PATTERN_HRES, 8, 1030 OTG_TEST_PATTERN_VRES, 5, 1031 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6); 1032 } 1033 break; 1034 default: 1035 break; 1036 } 1037 1038 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1039 1040 /* enable test pattern */ 1041 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1042 1043 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0, 1044 OTG_TEST_PATTERN_EN, 1, 1045 OTG_TEST_PATTERN_MODE, mode, 1046 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0, 1047 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth); 1048 } 1049 break; 1050 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE: 1051 { 1052 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0); 1053 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0); 1054 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0); 1055 } 1056 break; 1057 default: 1058 break; 1059 1060 } 1061 } 1062 1063 void optc1_get_crtc_scanoutpos( 1064 struct timing_generator *optc, 1065 uint32_t *v_blank_start, 1066 uint32_t *v_blank_end, 1067 uint32_t *h_position, 1068 uint32_t *v_position) 1069 { 1070 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1071 struct crtc_position position; 1072 1073 REG_GET_2(OTG_V_BLANK_START_END, 1074 OTG_V_BLANK_START, v_blank_start, 1075 OTG_V_BLANK_END, v_blank_end); 1076 1077 optc1_get_position(optc, &position); 1078 1079 *h_position = position.horizontal_count; 1080 *v_position = position.vertical_count; 1081 } 1082 1083 static void optc1_enable_stereo(struct timing_generator *optc, 1084 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1085 { 1086 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1087 1088 if (flags) { 1089 uint32_t stereo_en; 1090 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; 1091 1092 if (flags->PROGRAM_STEREO) 1093 REG_UPDATE_3(OTG_STEREO_CONTROL, 1094 OTG_STEREO_EN, stereo_en, 1095 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0, 1096 OTG_STEREO_SYNC_OUTPUT_POLARITY, 0); 1097 1098 if (flags->PROGRAM_POLARITY) 1099 REG_UPDATE(OTG_STEREO_CONTROL, 1100 OTG_STEREO_EYE_FLAG_POLARITY, 1101 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1); 1102 1103 if (flags->DISABLE_STEREO_DP_SYNC) 1104 REG_UPDATE(OTG_STEREO_CONTROL, 1105 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1); 1106 1107 if (flags->PROGRAM_STEREO) 1108 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL, 1109 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED, 1110 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); 1111 1112 } 1113 } 1114 1115 void optc1_program_stereo(struct timing_generator *optc, 1116 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) 1117 { 1118 if (flags->PROGRAM_STEREO) 1119 optc1_enable_stereo(optc, timing, flags); 1120 else 1121 optc1_disable_stereo(optc); 1122 } 1123 1124 1125 bool optc1_is_stereo_left_eye(struct timing_generator *optc) 1126 { 1127 bool ret = false; 1128 uint32_t left_eye = 0; 1129 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1130 1131 REG_GET(OTG_STEREO_STATUS, 1132 OTG_STEREO_CURRENT_EYE, &left_eye); 1133 if (left_eye == 1) 1134 ret = true; 1135 else 1136 ret = false; 1137 1138 return ret; 1139 } 1140 1141 bool optc1_is_matching_timing(struct timing_generator *tg, 1142 const struct dc_crtc_timing *otg_timing) 1143 { 1144 struct dc_crtc_timing hw_crtc_timing = {0}; 1145 struct dcn_otg_state s = {0}; 1146 1147 if (tg == NULL || otg_timing == NULL) 1148 return false; 1149 1150 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); 1151 1152 hw_crtc_timing.h_total = s.h_total + 1; 1153 hw_crtc_timing.h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); 1154 hw_crtc_timing.h_front_porch = s.h_total + 1 - s.h_blank_start; 1155 hw_crtc_timing.h_sync_width = s.h_sync_a_end - s.h_sync_a_start; 1156 1157 hw_crtc_timing.v_total = s.v_total + 1; 1158 hw_crtc_timing.v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end); 1159 hw_crtc_timing.v_front_porch = s.v_total + 1 - s.v_blank_start; 1160 hw_crtc_timing.v_sync_width = s.v_sync_a_end - s.v_sync_a_start; 1161 1162 if (otg_timing->h_total != hw_crtc_timing.h_total) 1163 return false; 1164 1165 if (otg_timing->h_border_left != hw_crtc_timing.h_border_left) 1166 return false; 1167 1168 if (otg_timing->h_addressable != hw_crtc_timing.h_addressable) 1169 return false; 1170 1171 if (otg_timing->h_border_right != hw_crtc_timing.h_border_right) 1172 return false; 1173 1174 if (otg_timing->h_front_porch != hw_crtc_timing.h_front_porch) 1175 return false; 1176 1177 if (otg_timing->h_sync_width != hw_crtc_timing.h_sync_width) 1178 return false; 1179 1180 if (otg_timing->v_total != hw_crtc_timing.v_total) 1181 return false; 1182 1183 if (otg_timing->v_border_top != hw_crtc_timing.v_border_top) 1184 return false; 1185 1186 if (otg_timing->v_addressable != hw_crtc_timing.v_addressable) 1187 return false; 1188 1189 if (otg_timing->v_border_bottom != hw_crtc_timing.v_border_bottom) 1190 return false; 1191 1192 if (otg_timing->v_sync_width != hw_crtc_timing.v_sync_width) 1193 return false; 1194 1195 return true; 1196 } 1197 1198 1199 void optc1_read_otg_state(struct optc *optc1, 1200 struct dcn_otg_state *s) 1201 { 1202 REG_GET(OTG_CONTROL, 1203 OTG_MASTER_EN, &s->otg_enabled); 1204 1205 REG_GET_2(OTG_V_BLANK_START_END, 1206 OTG_V_BLANK_START, &s->v_blank_start, 1207 OTG_V_BLANK_END, &s->v_blank_end); 1208 1209 REG_GET(OTG_V_SYNC_A_CNTL, 1210 OTG_V_SYNC_A_POL, &s->v_sync_a_pol); 1211 1212 REG_GET(OTG_V_TOTAL, 1213 OTG_V_TOTAL, &s->v_total); 1214 1215 REG_GET(OTG_V_TOTAL_MAX, 1216 OTG_V_TOTAL_MAX, &s->v_total_max); 1217 1218 REG_GET(OTG_V_TOTAL_MIN, 1219 OTG_V_TOTAL_MIN, &s->v_total_min); 1220 1221 REG_GET(OTG_V_TOTAL_CONTROL, 1222 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel); 1223 1224 REG_GET(OTG_V_TOTAL_CONTROL, 1225 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel); 1226 1227 REG_GET_2(OTG_V_SYNC_A, 1228 OTG_V_SYNC_A_START, &s->v_sync_a_start, 1229 OTG_V_SYNC_A_END, &s->v_sync_a_end); 1230 1231 REG_GET_2(OTG_H_BLANK_START_END, 1232 OTG_H_BLANK_START, &s->h_blank_start, 1233 OTG_H_BLANK_END, &s->h_blank_end); 1234 1235 REG_GET_2(OTG_H_SYNC_A, 1236 OTG_H_SYNC_A_START, &s->h_sync_a_start, 1237 OTG_H_SYNC_A_END, &s->h_sync_a_end); 1238 1239 REG_GET(OTG_H_SYNC_A_CNTL, 1240 OTG_H_SYNC_A_POL, &s->h_sync_a_pol); 1241 1242 REG_GET(OTG_H_TOTAL, 1243 OTG_H_TOTAL, &s->h_total); 1244 1245 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1246 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status); 1247 } 1248 1249 bool optc1_get_otg_active_size(struct timing_generator *optc, 1250 uint32_t *otg_active_width, 1251 uint32_t *otg_active_height) 1252 { 1253 uint32_t otg_enabled; 1254 uint32_t v_blank_start; 1255 uint32_t v_blank_end; 1256 uint32_t h_blank_start; 1257 uint32_t h_blank_end; 1258 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1259 1260 1261 REG_GET(OTG_CONTROL, 1262 OTG_MASTER_EN, &otg_enabled); 1263 1264 if (otg_enabled == 0) 1265 return false; 1266 1267 REG_GET_2(OTG_V_BLANK_START_END, 1268 OTG_V_BLANK_START, &v_blank_start, 1269 OTG_V_BLANK_END, &v_blank_end); 1270 1271 REG_GET_2(OTG_H_BLANK_START_END, 1272 OTG_H_BLANK_START, &h_blank_start, 1273 OTG_H_BLANK_END, &h_blank_end); 1274 1275 *otg_active_width = v_blank_start - v_blank_end; 1276 *otg_active_height = h_blank_start - h_blank_end; 1277 return true; 1278 } 1279 1280 void optc1_clear_optc_underflow(struct timing_generator *optc) 1281 { 1282 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1283 1284 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); 1285 } 1286 1287 void optc1_tg_init(struct timing_generator *optc) 1288 { 1289 optc1_set_blank_data_double_buffer(optc, true); 1290 optc1_clear_optc_underflow(optc); 1291 } 1292 1293 bool optc1_is_tg_enabled(struct timing_generator *optc) 1294 { 1295 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1296 uint32_t otg_enabled = 0; 1297 1298 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled); 1299 1300 return (otg_enabled != 0); 1301 1302 } 1303 1304 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc) 1305 { 1306 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1307 uint32_t underflow_occurred = 0; 1308 1309 REG_GET(OPTC_INPUT_GLOBAL_CONTROL, 1310 OPTC_UNDERFLOW_OCCURRED_STATUS, 1311 &underflow_occurred); 1312 1313 return (underflow_occurred == 1); 1314 } 1315 1316 bool optc1_configure_crc(struct timing_generator *optc, 1317 const struct crc_params *params) 1318 { 1319 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1320 1321 /* Cannot configure crc on a CRTC that is disabled */ 1322 if (!optc1_is_tg_enabled(optc)) 1323 return false; 1324 1325 REG_WRITE(OTG_CRC_CNTL, 0); 1326 1327 if (!params->enable) 1328 return true; 1329 1330 /* Program frame boundaries */ 1331 /* Window A x axis start and end. */ 1332 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL, 1333 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start, 1334 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end); 1335 1336 /* Window A y axis start and end. */ 1337 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL, 1338 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start, 1339 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end); 1340 1341 /* Window B x axis start and end. */ 1342 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL, 1343 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start, 1344 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end); 1345 1346 /* Window B y axis start and end. */ 1347 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL, 1348 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start, 1349 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end); 1350 1351 /* Set crc mode and selection, and enable. Only using CRC0*/ 1352 REG_UPDATE_3(OTG_CRC_CNTL, 1353 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0, 1354 OTG_CRC0_SELECT, params->selection, 1355 OTG_CRC_EN, 1); 1356 1357 return true; 1358 } 1359 1360 bool optc1_get_crc(struct timing_generator *optc, 1361 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) 1362 { 1363 uint32_t field = 0; 1364 struct optc *optc1 = DCN10TG_FROM_TG(optc); 1365 1366 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); 1367 1368 /* Early return if CRC is not enabled for this CRTC */ 1369 if (!field) 1370 return false; 1371 1372 REG_GET_2(OTG_CRC0_DATA_RG, 1373 CRC0_R_CR, r_cr, 1374 CRC0_G_Y, g_y); 1375 1376 REG_GET(OTG_CRC0_DATA_B, 1377 CRC0_B_CB, b_cb); 1378 1379 return true; 1380 } 1381 1382 static const struct timing_generator_funcs dcn10_tg_funcs = { 1383 .validate_timing = optc1_validate_timing, 1384 .program_timing = optc1_program_timing, 1385 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 1386 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 1387 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 1388 .program_global_sync = optc1_program_global_sync, 1389 .enable_crtc = optc1_enable_crtc, 1390 .disable_crtc = optc1_disable_crtc, 1391 /* used by enable_timing_synchronization. Not need for FPGA */ 1392 .is_counter_moving = optc1_is_counter_moving, 1393 .get_position = optc1_get_position, 1394 .get_frame_count = optc1_get_vblank_counter, 1395 .get_scanoutpos = optc1_get_crtc_scanoutpos, 1396 .get_otg_active_size = optc1_get_otg_active_size, 1397 .is_matching_timing = optc1_is_matching_timing, 1398 .set_early_control = optc1_set_early_control, 1399 /* used by enable_timing_synchronization. Not need for FPGA */ 1400 .wait_for_state = optc1_wait_for_state, 1401 .set_blank = optc1_set_blank, 1402 .is_blanked = optc1_is_blanked, 1403 .set_blank_color = optc1_program_blank_color, 1404 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 1405 .enable_reset_trigger = optc1_enable_reset_trigger, 1406 .enable_crtc_reset = optc1_enable_crtc_reset, 1407 .disable_reset_trigger = optc1_disable_reset_trigger, 1408 .lock = optc1_lock, 1409 .unlock = optc1_unlock, 1410 .enable_optc_clock = optc1_enable_optc_clock, 1411 .set_drr = optc1_set_drr, 1412 .set_static_screen_control = optc1_set_static_screen_control, 1413 .set_test_pattern = optc1_set_test_pattern, 1414 .program_stereo = optc1_program_stereo, 1415 .is_stereo_left_eye = optc1_is_stereo_left_eye, 1416 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer, 1417 .tg_init = optc1_tg_init, 1418 .is_tg_enabled = optc1_is_tg_enabled, 1419 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 1420 .clear_optc_underflow = optc1_clear_optc_underflow, 1421 .get_crc = optc1_get_crc, 1422 .configure_crc = optc1_configure_crc, 1423 }; 1424 1425 void dcn10_timing_generator_init(struct optc *optc1) 1426 { 1427 optc1->base.funcs = &dcn10_tg_funcs; 1428 1429 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 1430 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 1431 1432 optc1->min_h_blank = 32; 1433 optc1->min_v_blank = 3; 1434 optc1->min_v_blank_interlace = 5; 1435 optc1->min_h_sync_width = 8; 1436 optc1->min_v_sync_width = 1; 1437 optc1->comb_opp_id = 0xf; 1438 } 1439 1440 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) 1441 { 1442 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; 1443 1444 return two_pix; 1445 } 1446 1447